#08 Logic Simulation
#08 Logic Simulation
#08 Logic Simulation
Objective
Learn how to simulate RTL and gate level design with VCS.
Introduction
VCS is used to compile input files and simulate design. For debug Discovery Visual Environment (DVE) is
used. VCS is a command line tool compiling input sources. Using DVE it is possible to drag-and-drop
signals in various views or use the menu options to view the signal source, trace drivers, compare
waveforms, and view schematics. Use DVE to quickly find bugs in RTL or gate, assertions, testbench and
coverage.
Laboratory tasks
1. First compile johnson.v RTL source and Johnson_test.v testbenches using VCS with the following
command:
% dve
2. Setup DVE
- From menu bar select Simulator > Setup,
- In “Simulator executable” press “Browse…” and select “simv” file in the current directory
toolbars
menus
frame
Pane targets
Status bar
Using Simulator Menu Commands Runs the simulation until a breakpoint is hit, the simulation finishes, or
for the duration specified in the set Continue Time dialog box or toolbar time entries.
When the simulation is running, this icon is activated. Click to stop the simulation.
Link the Driver panes to Source view in the same top level frame and Path Schematic view. The Link to
radio buttons, at the right top of the pane, shows the current linked windows. By linking a Source and
Schematic view, when the object is selected in the Drivers pane, the object will also be selected in the
linked views.
To view a comparison
1. Select one or two signals, signal groups, scopes, or buses from the Signal pane of the Wave view.
2. Right-click and select Compare.
DVE> exit