Unit 2 Microprocessor Course Material

UNIT – II
SYLLABUS - 8086 PROCESSOR
8086 Architecture-Maximum and Minimum Mode-Memory Banks-Memory Segmentation-Programming Model -Instruction

Set-Programming of 8086.
INTEL 8086
Features of 8086 Microprocessor:

 Intel 8086 was launched in 1978.
 It was the first 16-bit microprocessor.
 This microprocessor had major improvement over the execution speed of
8085.
 It is available as 40-pin Dual-Inline-Package (DIP).
 It is available in three versions:
a. 8086 (5 MHz)
b. 8086-2 (8 MHz)
c. 8086-1 (10 MHz)
 It consists of 29,000 transistors.
 It has a 16 line data bus and 20 line address bus.
 It could address up to 1 MB of memory.
 It has more than 20,000 instructions.
PIN DIAGRAM OF 8086
 AD0-AD15
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These lines are multiplexed bidirectional address/data bus. During T1, they carry
lower order 16-bit address. In the remaining clock cycles,they carry 16-bit data.
AD0-AD7 carry lower order byte of data. AD8-AD15 carry higher order byte of data.
 A19/S6, A18/S5, A17/S4, A16/S3 [Pin 35-38 (Unidirectional)]

These lines are multiplexed unidirectional address and status bus. During T1, they
carry higher order 4-bit address. In the remaining clock cycles, they carry status
signals.
 BHE / S7 [Pin 34 (Output)]

BHE stands for Bus High Enable. BHE signal is used to indicate the transfer of data
over higher order data bus (D8 – D15). 8-bit I/O devices use this signal. It is
multiplexed with status pin S7.
 RD (Read) [Pin 32 (Output)]

It is a read signal used for read operation. It is an output signal. It is an active low
signal.
 READY [ Pin 22 (Input)]

This is an acknowledgement signal from slower I/O devices or memory. It is an
active high signal. When high, it indicates that the device is ready to transfer data.
When low, then microprocessor is in wait state.
 RESET[Pin 21 (Input)]
It is a system reset. It is an active high signal. When high, microprocessor enters
into reset state and terminates the current activity. It must be active for atleast four
clock cycles to reset the microprocessor.
 INTR [Pin 18 (Input)]

It is an interrupt request signal. It is active high. It is level triggered
 NMI[Pin 17 (Input)]
It is a non-maskable interrupt signal. It is an active high. It is an edge
triggeredinterrupt.
 TEST[Pin 23 (Input)]
It is used to test the status of math coprocessor 8087. The BUSY pin of 8087
isconnected to this pin of 8086. If low, execution continues else microprocessor is in
wait state.
 CLK[Pin 19 (Input)]
This clock input provides the basic timing for processor operation. It is symmetric
square wave with 33% duty cycle. The range of frequency of different versions is 5
MHz, 8 MHz and 10 MHz.
 VCC and VSS[Pin 40 and Pin 20 (Input)]

VCC is power supply signal. +5V DC is supplied through this pin. VSS is ground
signal
 MN / MX[Pin 33 (Input)]
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8086 works in two modes: Minimum Mode, Maximum Mode. If MN/MX is high, it
worksin minimum mode. If MN/MX is low, it works in maximum mode. Pins 24 to 31
issue twodifferent sets of signals. One set of signals is issued when CPU operates
in minimum mode. Other set of signals isissued when CPU operates in maximum
mode.
PIN Description for Minimum Mode

 INTA [Pin 24 (Output)]
This is an interruptacknowledge signal. When microprocessorreceives INTR
signal, it acknowledges the interrupt by generating this signal. It is an active low
signal
 ALE [Pin 25 (Output)].

This is an Address LatchEnable signal. It indicates that valid address is
available on bus AD0 – AD15. It is an active high signal and remains high during
T1 state. It is connected to enable pin of latch 8282.
 DEN[Pin 26 (Output)]
This is a Data Enable signal. This signal is used toenable the transceiver 8286.
Transceiver is used to separate the data from the address/data bus. It is an
active low signal
 DT / R[Pin 27 (Output)]
This is a DataTransmit/Receive signal. It decides the direction ofdata flow
through the transceiver. When it is high, data is transmitted out. When it is low,
data is received in.
 M / IO[Pin 28 (Output)]
This signal is issued by the microprocessor to distinguish memory access from
I/O access. When it is high, memory is accessed. When it is low, I/O devices are
accessed.
 WR [Pin 29 (Output)]
It is a Write signal. It is used to write data inmemory or output device depending
on the status of M/IO signal. It is an active low signal
 HLDA[Pin 30 (Output)]
It is a Hold Acknowledge signal. It is issued after receiving the HOLD signal. It
is an active high signal
 HOLD[Pin 31 (Input)]
When DMA controller needs to use address/data bus, it sends a request to the
CPU through this pin. It is an active high signal. When microprocessor receives
HOLD signal, it issues HLDA signal to the DMA controller.
PIN Description for Maximum Mode
 QS1 and QS0 [Pin 24 and 25 (Output)]
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These pins provide the status of instruction queue.
QS1 QS0 STATUS

0 0 NO OPERATION
0 1 1st byte of opcode from queue
1 0 Empty queue
1 1 Subsequent byte from queue
 S0, S1, S2 [Pin 26, 27, 28 (Output)]

These status signals indicate the operation being done by the microprocessor.
This information is required by the Bus Controller 8288. Bus controller 8288
generates all memory and I/O control signals.
S0 S1 S2 STATUS
0 0 0 Interrupt Acknowledge
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive
 LOCK[Pin 29 (Output)]
This signal indicates that other processors should not ask CPU to relinquish the
system bus. When it goes low, all interrupts are masked and HOLD request is
not granted. This pin is activated by using LOCK prefix on any instruction.
 RQ/GT1 and RQ/GT0 [Pin 30 and 31 (Bi-directional)]

These are Request/Grant pins. Other processors request the CPU through
these lines to release the system bus. After receiving the request, CPU sends
acknowledge signal on the same lines. RQ/GT0 has higher priority than
RQ/GT1.
Architecture of 8086
The microprocessors functions as the CPU in the stored program model of the digital
computer. Its job is to generate all system timing signals and synchronize the
transfer of data between memory, I/O, and itself. The microprocessor also has a S/W
function. It must recognize, decode, and execute program instructions fetched from
the memory unit. This requires an Arithmetic-Logic Unit (ALU) within the CPU to
perform arithmetic and logical (AND, OR, NOT, compare, etc) functions.
The 8086 has pipelined architecture. The 8086 CPU is organized as two separate
processors, called the Bus Interface Unit (BIU) and the Execution Unit (EU).
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A : Address Bus
D :Databus
Q : Q Bus
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Fig : Architecture of 8086
Bus Interface Unit (BIU)
The function of BIU is to:
 Fetch the instruction or data from memory.
 Write the data to memory.
 Write the data to the port.
 Read data from the port.
Instruction Queue
1. To increase the execution speed, BIU fetches as many as six instruction bytes
ahead to time from memory.
2. All six bytes are then held in first in first out 6 byte register called instruction
queue.
3. Then all bytes have to be given to EU one by one.
4. This pre fetching operation of BIU may be in parallel with execution operation of
EU, which improves the speed execution of the instruction.
Execution Unit (EU)
The functions of execution unit are:
To tell BIU where to fetch the instructions or data from.
To decode the instructions.
To execute the instructions.
The EU contains the control circuitry to perform various internal operations. A

decoder in EU decodes the instruction fetched memory to generate different internal
or external control signals required to perform the operation. EU has 16-bit ALU,
which can perform arithmetic and logical operations on 8-bit as well as 16-bit.
General Purpose Registers of 8086
These registers can be used as 8-bit registers individually or can be used as 16-bit
in pair to have AX, BX, CX, and DX.
1. AX Register: AX register is also known as accumulator register that stores

operands for arithmetic operation like divided, rotate.
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2. BX Register: This register is mainly used as a base register. It holds the starting
base location of a memory region within a data segment.
3. CX Register: It is defined as a counter. It is primarily used in loop instruction to

store loop counter.
4. DX Register: DX register is used to contain I/O port address for I/O instruction.
Segment Registers :
Additional registers called segment registers generate memory address when

combined with other in the microprocessor. In 8086 microprocessor, memory is
divided into 4 segments as follow:
Fig.: Memory Segments of 8086
1. Code Segment (CS): The CS register is used for addressing a

memory location in the Code Segment of the memory, where the executable
program is stored.
2. Data Segment (DS): The DS contains most data used by
program. Data are accessed in the Data Segment by an offset address or the
content of other register that holds the offset address.
3. Stack Segment (SS): SS defined the area of memory used for
the stack
4. Extra Segment (ES): ES is additional data segment that is used
by some of the string to hold the destination data.
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Flag Registers of 8086
Flag register in EU is of 16-bit , is shown
Fig : Flag Register of 8086
Flag Register determines the current state of the processor. They are modified
automatically by CPU after mathematical operations, this allows to determine the
type of the result, and to determine conditions to transfer control to other parts of the
program. 8086 has 9 flags and they are divided into two categories:
1. Conditional Flags
2. Control Flags
Conditional Flags
Conditional flags represent result of last arithmetic or logical instruction executed.

Conditional flags are as follows:
Carry Flag (CF): This flag indicates an overflow condition for unsigned integer
arithmetic. It is also used in multiple-precision arithmetic.
 Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow

from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e.
carry given by D3 bit to D4 is AF flag. This is not a general-purpose flag, it is used
internally by the processor to perform Binary to BCD conversion.
Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-
bits of the result contains even number of 1’s, the Parity Flag is set and for odd
number of 1’s, the Parity Flag is reset.
Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it
is reset.
Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB
bit. If the result of operation is negative, sign flag is set.
Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An
OF indicates that the result has exceeded the capacity of machine.
Control Flags
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Control flags are set or reset deliberately to control the operations of the execution
unit. Control flags are as follows:
1. Trap Flag (TP):
a. It is used for single step control.
b. It allows user to execute one instruction of a program at a time for debugging.
c. When trap flag is set, program can be run in single step mode.
2. Interrupt Flag (IF):
a. It is an interrupt enable/disable flag.
b. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt
is disabled.
c. It can be set by executing instruction sit and can be cleared by executing CLI
instruction.
3. Direction Flag (DF):
a. It is used in string operation.
b. If it is set, string bytes are accessed from higher memory address to lower
memory address.
c. When it is reset, the string bytes are accessed from lower memory address to
higher memory address.
Addressing modes of 8086
I. Addressing modes for register and immediate data
1) Register Addressing mode

2) Immediate Addressing mode
II. Addressing modes for memory data
3) Register Indirect Addressing mode

4) Direct Addressing mode
5) Based Addressing mode
6) Indexed Addressing mode
7) Base Relative Addressing mode
8) Base Indexed Addressing mode
9) String Addressing Mode
III. Addrressing modes for I/O port
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10) Direct I/O port Addressing
11) Indirect I/O port Addressing
IV. Relative Addressing mode

12) Relative Addressing
V. Implied Addressing Mode

13) Implied Addressing
Register Addressing Mode

Data transfer using registers is called register addressing mode. Here operand value
is present in register. For example
MOV AL,BL;
MOV AX,BX;
Immediate Addressing mode

When data is stored in code segment instead of data segment immediate addressing
mode is used. Here operand value is present in the instruction. For example
MOV AX, 0A9FH;
Direct Addressing mode

When direct memory address is supplied as part of the instruction is called direct
addressing mode. Operand offset value with respect to data segment is given in
instruction. For example
MOV AX, [089DH];
ADD AX, [0ADH];
Register Indirect Addressing mode

Here operand offset is given in a cpu register. Register used are BX, SI(source
index), DI(destination index), or BP(base pointer). BP holds offset w.r.t Stack
segment, but SI,DI and BX refer to data segment. For example-
MOV [BX],AX;
ADD AX, [SI];
Based addressing Mode
In this mode EA is obtained by adding a displacement (signed 8 bit or unsigned 16

bit) value to the contents of BX or BP.The segment registers used are DS & SS.
When Memory is accessed,the 20 bit physical address is computed from BX and

DS.On the other hand,when the stack is accessed,the 20 bit physical address is
computed from BP and SS.
eg:- MOV AL,START[BX] or MOV AL,[BX+START]
Where START=02H(8 bit displacement),BX=2000H
Now the 20 bit Physical address is computed from DS and EA
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If [DS]=5004(16),then
2000H BX 5004
02H Displacement 2 0 0 2 EA
2002H EA 5 2 0 4 0 20 bit Physical Address
Here the source operand is in based Addressing Mode.EA is obtained by adding the
value of START and [BX].The 20 bit physical address is produced from DS and
EA.The 8 bit content of this memory location is moved to AL register.
Therefore the contents of the memory location 52042 is moved in to AL register.
Indexed Addressing mode
In this mode,the EA is calculated by adding the unsigned 16 bit or signed extended 8

bit displacement and the contents of SI or DI.
eg:- MOV BH,START[SI]
Moves the contents of the 20 bit address computed from the displacement START,SI
and DS into BH register.The 8 bit displacement is provided by the programmer using
the assembler pseudoindtruction such as EQU.For 16 bit displacement,the EU adds
this to SI to determine EA.On the other hand,for 8 bit displacement the EU sign
extends it to 16 bits and then adds to SI for determining EA.
Base Relative Addressing mode

Operand offset given by a sum of a value held either in BP, or BX and a constant
offset specified as an operand. For example
MOV AX,[BP+1];
JMP [BX+1];
Base Indexed Addressing mode

Here operand offset is given by sum of either BX or BP with either SI or DI. For
example
MOV AX, [BX+SI]
JMP [BP+DI]
String Addressing
This mode uses index registers.The string instructions automatically assume SI to

point to the first byte or word of the source operand and DI to point to the first byte or
word of the destination operand.
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The segment register for the source is DS and may be overridden.The segment
register for the destination must be ES and cannot be overridden.
The contents of SI and DI are automatically incremented by clearing DF (Direction

Flag) to 0 by CLD instruction or automatically decremented by setting DF to 1 by
STD instruction.
Direct Addressing Modes
Here the port number is a 8 bit immediate operand.This allows fixed access to ports
numbered 0 to 255.
eg:- OUT 05H,AL
outputs [AL] to 8 bit port 05H
Indirect Addressing Mode
The port number is taken from DX allowing 64K 8 bit ports or 32K 16 bit ports.
eg:- IN AX,DX
If [DX]=5040,Inputs the 8 bit content of port 5040 into AL and 5041 into AH.
Relative Addressing Mode
In this mode,the operand is specified as a signed 8 bit displacement,relative to

PC(Program Counter).
eg:- JNC START
then,if carry=0,PC is loaded with current PC contents plus the 8 bit signed value of
START,otherwise the next instruction is executed.
Implied Addressing Mode
Instructions using this mode have no operands.
eg:- CLC
this clears the carry flag to zero.
INSTRUCTION SET OF 8086
I. DATA TRANSFER INSTRUCTIONS
 MOV – MOV Destination, Source

The MOV instruction copies a word or byte of data from a specified source to
a specified destination. The destination can be a register or a memory
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location. The source can be a register, a memory location or an immediate
number. The source and destination cannot both be memory locations. They
must both be of the same type (bytes or words).MOV instruction does not
affect any flag.
MOV CX, 037AH Put immediate number 037AH to CX
MOV BL, [437AH] Copy byte in DS at offset 437AH to BL
MOV AX, BX Copy content of register BX to AX
MOV DL, [BX] Copy byte from memory at [BX] to DL
MOV DS, BX Copy word from BX to DS register
MOV RESULT [BP], AX Copy AX to two memory locations; AL to the first

location, AH to the second; EA of the first memory
location is sum of the displacement represented by
RESULTS and content of BP. Physical address =
EA + SS.
MOV ES: RESULTS [BP], AX Same as the above instruction, but physical
address = EA + ES, because of the segment
override prefix ES
 XCHG – XCHG Destination, Source
The XCHG instruction exchanges the content of a register with the content
of another register or with the content of memory location(s). It cannot
directly exchange the content of two memory locations. The source and
destination must both be of the same type (bytes or words). The segment
registers cannot be used in this instruction. This instruction does not affect
any flag.
XCHG AX, DX Exchange word in AX with word in DX
XCHG BL, CH Exchange byte in BL with byte in CH
XCHG AL, PRICES [BX] Exchange byte in AL with byte in memory at

EA = PRICE [BX] in DS.
 LEA – LEA Register, Source
This instruction determines the offset of the variable or memory location named as
the source and puts this offset in the indicated 16-bit register. LEA does not affect
any flag.
LEA BX, PRICES Load BX with offset of PRICE in DS
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LEA BP, SS: STACK_TOP Load BP with offset of STACK_TOP
in SS
LEA CX, [BX][DI] Load CX with EA = [BX] + [DI]
 LDS – LDS Register, Memory address of the first word
This instruction loads new values into the specified register and into the DS register
from four successive memory locations. The word from two memory locations is
copied into the specified register and the word from the next two memory locations is
copied into the DS registers. LDS does not affect any flag.
LDS BX, [4326] Copy content of memory at displacement 4326H in

DS to BL, content of 4327H to BH. Copy content
at displacement of 4328H and 4329H in DS to DS
register.
LDS SI, SPTR Copy content of memory at displacement SPTR

and SPTR + 1 in DS to SI register. Copy content
of memory at displacements SPTR + 2 and SPTR
+ 3 in DS to DS register. DS: SI now points at start
of the desired string.
 LES – LES Register, Memory address of the first word
This instruction loads new values into the specified register and into the ES register
from four successive memory locations. The word from the first two memory
locations is copied into the specified register, and the word from the next two
memory locations is copied into the ES register. LES does not affect any flag.
LES BX, [789AH] Copy content of memory at displacement 789AH in

DS to BL, content of 789BH to BH, content of
memory at displacement 789CH and 789DH in
DS is copied to ES register.
LES DI, [BX] Copy content of memory at offset [BX] and offset
[BX] + 1 in DS to DI register. Copy content of
memory at offset [BX] + 2 and [BX] + 3 to ES
register.
 PUSH – PUSH Source
The PUSH instruction decrements the stack pointer by 2 and copies a word from a
specified source to the location in the stack segment to which the stack pointer
points. The source of the word can be generalpurpose register, segment register, or
memory. The stack segment register and the stack pointer must be initialized before
this instruction can be used. PUSH can be used to save data on the stack so that it
will not destroyed by a procedure. This instruction does not affect any flag.
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 PUSH BX Decrement SP by 2, copy BX to stack.
 PUSH DS Decrement SP by 2, copy DS to stack.
 PUSH BL Illegal; must push a word
 PUSH TABLE [BX] Decrement SP by 2, and copy word from memory
in DS at EA = TABLE + [BX] to stack
 POP – POP Destination
The POP instruction copies a word from the stack location pointed to by the stack
pointer to a destination specified in the instruction. The destination can be a general-
purpose register, a segment register or a memory location. The data in the stack is
not changed. After the word is copied to the specified destination, the stack pointer is
automatically incremented by 2 to point to the next word on the stack. The POP
instruction does not affect any flag.
 POP DX Copy a word from top of stack to DX; increment

SP by 2
 POP DS Copy a word from top of stack to DS; increment
SP by 2
 POP TABLE [DX] Copy a word from top of stack to memory in DS
with EA = TABLE + [BX]; increment SP by 2.
 PUSHF (PUSH FLAG REGISTER TO STACK)
The PUSHF instruction decrements the stack pointer by 2 and copies a word in the
flag register to two memory locations in stack pointed to by the stack pointer. The
stack segment register is not affected. This instruction does to affect any flag.
 POPF (POP WORD FROM TOP OF STACK TO FLAG REGISTER)
The POPF instruction copies a word from two memory locations at the top of the
stack to the flag register and increments the stack pointer by 2. The stack segment
register and word on the stack are not affected. This instruction does to affect any
flag.
 INPUT-OUTPUT INSTRUCTIONS
 IN – IN Accumulator, Port
The IN instruction copies data from a port to the AL or AX register. If an 8-bit port is
read, the data will go to AL. If a 16-bit port is read, the data will go to AX.
The IN instruction has two possible formats, fixed port and variable port. For fixed
port type, the 8-bit address of a port is specified directly in the instruction. With this
form, any one of 256 possible ports can be addressed.
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 IN AL, OC8H Input a byte from port OC8H to AL
 IN AX, 34H Input a word from port 34H to AX
For the variable-port form of the IN instruction, the port address is loaded into the DX
register before the IN instruction. Since DX is a 16-bit register, the port address can
be any number between 0000H and FFFFH. Therefore, up to 65,536 ports are
addressable in this mode.
 MOV DX, 0FF78H Initialize DX to point to port

IN AL, DX Input a byte from 8-bit port 0FF78H to AL
IN AX, DX Input a word from 16-bit port 0FF78H to AX
The variable-port IN instruction has advantage that the port address can be
computed or dynamically determined in the program. Suppose, for example, that an
8086-based computer needs to input data from 10 terminals, each having its own
port address. Instead of having a separate procedure to input data from each port,
you can write one generalized input procedure and simply pass the address of the
desired port to the procedure in DX.
The IN instruction does not change any flag.
 OUT – OUT Port, Accumulator
The OUT instruction copies a byte from AL or a word from AX to the specified port.
The OUT instruction has two possible forms, fixed port and variable port.
For the fixed port form, the 8-bit port address is specified directly in the instruction.
With this form, any one of 256 possible ports can be addressed.
 OUT 3BH, AL Copy the content of AL to port 3BH

 OUT 2CH, AX Copy the content of AX to port 2CH
For variable port form of the OUT instruction, the content of AL or AX will be copied
to the port at an address contained in DX. Therefore, the DX register must be loaded
with the desired port address before this form of the OUT instruction is used.
 MOV DX, 0FFF8H Load desired port address in DX

OUT DX, AL Copy content of AL to port FFF8H
OUT DX, AX Copy content of AX to port FFF8H
The OUT instruction does not affect any flag.
II. ARITHMETIC INSTRUCTIONS
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ADD – ADD Destination, Source
ADC – ADC Destination, Source
These instructions add a number from some source to a number in some destination
and put the result in the specified destination. The ADC also adds the status of the
carry flag to the result. The source may be an immediate number, a register, or a
memory location. The destination may be a register or a memory location. The
source and the destination in an instruction cannot both be memory locations. The
source and the destination must be of the same type (bytes or words). If you want to
add a byte to a word, you must copy the byte to a word location and fill the upper
byte of the word with 0’s before adding. Flags affected: AF, CF, OF, SF, ZF.
ADD AL, 74H Add immediate number 74H to content of AL. Result in
AL
ADC CL, BL Add content of BL plus carry status to content of CL
ADD DX, BX Add content of BX to content of DX
ADD DX, [SI] Add word from memory at offset [SI] in DS to content of
DX
ADC AL, PRICES [BX] Add byte from effective address [BX] plus carry status to
content of AL
ADD AL, PRICES [BX] Add content of memory at effective address PRICES [BX]
to AL
SUB – SUB Destination, Source
SBB – SBB Destination, Source
These instructions subtract the number in some source from the number in some
destination and put the result in the destination. The SBB instruction also subtracts
the content of carry flag from the destination. The source may be an immediate
number, a register or memory location. The destination can also be a register or a
memory location. However, the source and the destination cannot both be memory
location. The source and the destination must both be of the same type (bytes or
words). If you want to subtract a byte from a word, you must first move the byte to a
word location such as a 16-bit register and fill the upper byte of the word with 0’s.
Flags affected: AF, CF, OF, PF, SF, ZF.
SUB CX, BX CX – BX; Result in CX
SBB CH, AL Subtract content of AL and content of CF from content of

CH. Result in CH
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SUB AX, 3427H Subtract immediate number 3427H from AX
SBB BX, [3427H] Subtract word at displacement 3427H in DS and content of CF

from BX
SUB PRICES [BX], 04H Subtract 04 from byte at effective address PRICES [BX],
if PRICES is declared with DB; Subtract 04 from word at
effective address PRICES [BX], if it is declared with DW.
SBB CX, TABLE [BX] Subtract word from effective address TABLE [BX] and
status of CF from CX.
SBB TABLE [BX], CX Subtract CX and status of CF from word in memory at

effective address TABLE[BX].
MUL – MUL Source
This instruction multiplies an unsigned byte in some source with an unsigned byte in
AL register or an unsigned word in some source with an unsigned word in AX
register. The source can be a register or a memory location. When a byte is
multiplied by the content of AL, the result (product) is put in AX. When a word is
multiplied by the content of AX, the result is put in DX and AX registers. If the most
significant byte of a 16-bit result or the most significant word of a 32-bit result is 0,
CF and OF will both be 0’s. AF, PF, SF and ZF are undefined after a MUL
instruction.
If you want to multiply a byte with a word, you must first move the byte to a word
location such as an extended register and fill the upper byte of the word with all 0’s.
You cannot use the CBW instruction for this, because the CBW instruction fills the
upper byte with copies of the most significant bit of the lower byte.
MUL BH Multiply AL with BH; result in AX
MUL CX Multiply AX with CX; result high word in DX, low word in AX
MUL BYTE PTR [BX] Multiply AL with byte in DS pointed to by [BX]
MUL FACTOR [BX] Multiply AL with byte at effective address FACTOR [BX],
if it is declared as type byte with DB. Multiply AX with word at
effective address FACTOR [BX], if it is declared as type word
with DW.
MOV AX, MCAND_16 Load 16-bit multiplicand into AX MOV CL, MPLIER_8
Load 8-bit multiplier into CL MOV CH, 00H Set upper byte of
CX to all 0’s MUL CX AX times CX; 32-bit result in DX and AX
IMUL – IMUL Source
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This instruction multiplies a signed byte from source with a signed byte in AL or a
signed word from some source with a signed word in AX. The source can be a
register or a memory location. When a byte from source is multiplied with content of
AL, the signed result (product) will be put in AX. When a word from source is
multiplied by AX, the result is put in DX and AX. If the magnitude of the product does
not require all the bits of the destination, the unused byte / word will be filled with
copies of the sign bit. If the upper byte of a 16-bit result or the upper word of a 32-bit
result contains only copies of the sign bit (all 0’s or all 1’s), then CF and the OF will
both be 0; If it contains a part of the product, CF and OF will both be 1. AF, PF, SF
and ZF are undefined after IMUL.
If you want to multiply a signed byte with a signed word, you must first move the byte
into a word location and fill the upper byte of the word with copies of the sign bit. If
you move the byte into AL, you can use the CBW instruction to do this.
IMUL BH Multiply signed byte in AL with signed byte in BH; result

in AX.
IMUL AX Multiply AX times AX; result in DX and AX
MOV CX, MULTIPLIER Load signed word in CX
MOV AL, MULTIPLICAND Load signed byte in AL
CBW Extend sign of AL into AH
IMUL CX Multiply CX with AX; Result in DX and AX
DIV – DIV Source
This instruction is used to divide an unsigned word by a byte or to divide an unsigned

double word (32 bits) by a word. When a word is divided by a byte, the word must be
in the AX register. The divisor can be in a register or a memory location. After the
division, AL will contain the 8-bit quotient, and AH will contain the 8-bit remainder.
When a double word is divided by a word, the most significant word of the double
word must be in DX, and the least significant word of the double word must be in AX.
After the division, AX will contain the 16-bit quotient and DX will contain the 16-bit
remainder. If an attempt is made to divide by 0 or if the quotient is too large to fit in
the destination (greater than FFH / FFFFH), the 8086 will generate a type 0 interrupt.
All flags are undefined after a DIV instruction.
If you want to divide a byte by a byte, you must first put the dividend byte in AL and
fill AH with all 0’s. Likewise, if you want to divide a word by another word, then put
the dividend word in AX and fill DX with all 0’s.
DIV BL Divide word in AX by byte in BL; Quotient in AL, remainder in

AH
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DIV CX Divide down word in DX and AX by word in CX; Quotient in AX,
and remainder in DX.
DIV SCALE [BX] AX / (byte at effective address SCALE [BX]) if SCALE [BX] is of
type byte; or (DX and AX) / (word at effective address
SCALE[BX] if SCALE[BX] is of type word
IDIV – IDIV Source
This instruction is used to divide a signed word by a signed byte, or to divide a

signed double word by a signed word.
When dividing a signed word by a signed byte, the word must be in the AX register.
The divisor can be in an 8-bit register or a memory location. After the division, AL will
contain the signed quotient, and AH will contain the signed remainder. The sign of
the remainder will be the same as the sign of the dividend. If an attempt is made to
divide by 0, the quotient is greater than 127 (7FH) or less than –127 (81H), the 8086
will automatically generate a type 0 interrupt.
When dividing a signed double word by a signed word, the most significant word of
the dividend (numerator) must be in the DX register, and the least significant word of
the dividend must be in the AX register. The divisor can be in any other 16-bit
register or memory location. After the division, AX will contain a signed 16-bit
quotient, and DX will contain a signed 16-bit remainder. The sign of the remainder
will be the same as the sign of the dividend. Again, if an attempt is made to divide by
0, the quotient is greater than +32,767 (7FFFH) or less than –32,767 (8001H), the
8086 will automatically generate a type 0 interrupt.
All flags are undefined after an IDIV.
If you want to divide a signed byte by a signed byte, you must first put the dividend
byte in AL and signextend AL into AH. The CBW instruction can be used for this
purpose. Likewise, if you want to divide a signed word by a signed word, you must
put the dividend word in AX and extend the sign of AX to all the bits of DX. The CWD
instruction can be used for this purpose.
IDIV BL Signed word in AX/signed byte in BL
IDIV BP Signed double word in DX and AX/signed word in BP
IDIV BYTE PTR [BX] AX / byte at offset [BX] in DS
INC – INC Destination
The INC instruction adds 1 to a specified register or to a memory location. AF, OF,
PF, SF, and ZF are updated, but CF is not affected. This means that if an 8-bit
destination containing FFH or a 16-bit destination containing FFFFH is incremented,
the result will be all 0’s with no carry.
20
INC BL Add 1 to contains of BL register
INC CX Add 1 to contains of CX register
INC BYTE PTR [BX] Increment byte in data segment at offset contained
in BX.
INC WORD PTR [BX] Increment the word at offset of [BX] and [BX + 1] in the
data segment.
INC TEMP Increment byte or word named TEMP in the data

segment. Increment byte if MAX_TEMP declared with
DB.Increment word if MAX_TEMP is declared with DW.
INC PRICES [BX] Increment element pointed to by [BX] in array PRICES.

Increment a word if PRICES is declared as an array of
words; Increment a byte if PRICES is declared as an
array of bytes.
DEC – DEC Destination
This instruction subtracts 1 from the destination word or byte. The destination can be
a register or a memory location. AF, OF, SF, PF, and ZF are updated, but CF is not
affected. This means that if an 8-bit destination containing 00H or a 16-bit destination
containing 0000H is decremented, the result will be FFH or FFFFH with no carry
(borrow).
DEC CL Subtract 1 from content of CL register
DEC BP Subtract 1 from content of BP register
DEC BYTE PTR [BX] Subtract 1 from byte at offset [BX] in DS.
DEC WORD PTR [BP] Subtract 1 from a word at offset [BP] in SS.
DEC COUNT Subtract 1 from byte or word named COUNT in DS.

Decrement a byte if COUNT is declared with a DB;
Decrement a word if COUNT is declared with a DW.
DAA (DECIMAL ADJUST AFTER BCD ADDITION)
This instruction is used to make sure the result of adding two packed BCD numbers
is adjusted to be a legal BCD number. The result of the addition must be in AL for
DAA to work correctly. If the lower nibble in AL after an addition is greater than 9 or
AF was set by the addition, then the DAA instruction will add 6 to the lower nibble in
AL. If the result in the upper nibble of AL in now greater than 9 or if the carry flag was
set by the addition or correction, then the DAA instruction will add 60H to AL.
Let AL = 59 BCD, and BL = 35 BCD
21
ADD AL, BL AL = 8EH; lower nibble > 9, add 06H to AL
DAA AL = 94 BCD, CF = 0
Let AL = 88 BCD, and BL = 49 BCD
ADD AL, BL AL = D1H; AF = 1, add 06H to AL
DAA AL = D7H; upper nibble > 9, add 60H to AL
AL = 37 BCD, CF = 1
The DAA instruction updates AF, CF, SF, PF, and ZF; but OF is undefined.
DAS (DECIMAL ADJUST AFTER BCD SUBTRACTION)
This instruction is used after subtracting one packed BCD number from another
packed BCD number, to make sure the result is correct packed BCD. The result of
the subtraction must be in AL for DAS to work correctly. If the lower nibble in AL after
a subtraction is greater than 9 or the AF was set by the subtraction, then the DAS
instruction will subtract 6 from the lower nibble AL. If the result in the upper nibble is
now greater than 9 or if the carry flag was set, the DAS instruction will subtract 60
from AL.
Let AL = 86 BCD, and BH = 57 BCD
SUB AL, BH AL = 2FH; lower nibble > 9, subtract 06H from AL
AL = 29 BCD, CF = 0
Let AL = 49 BCD, and BH = 72 BCD
SUB AL, BH AL = D7H; upper nibble > 9, subtract 60H from AL
DAS AL = 77 BCD, CF = 1 (borrow is needed)
The DAS instruction updates AF, CF, SF, PF, and ZF; but OF is undefined.
CBW (CONVERT SIGNED BYTE TO SIGNED WORD)
This instruction copies the sign bit of the byte in AL to all the bits in AH. AH is then
said to be the sign extension of AL. CBW does not affect any flag.
Let AX = 00000000 10011011 (–155 decimal)
CBW Convert signed byte in AL to signed word in AX

AX = 11111111 10011011 (–155 decimal)
CWD (CONVERT SIGNED WORD TO SIGNED DOUBLE WORD)
22
This instruction copies the sign bit of a word in AX to all the bits of the DX register. In
other words, it extends the sign of AX into all of DX. CWD affects no flags.
Let DX = 00000000 00000000, and AX = 11110000 11000111 (–3897 decimal)
CWD Convert signed word in AX to signed double word in

DX:AX DX = 11111111 11111111 AX =
11110000 11000111 (–3897 decimal)
AAA (ASCII ADJUST FOR ADDITION)
Numerical data coming into a computer from a terminal is usually in ASCII code. In
this code, the numbers 0 to 9 are represented by the ASCII codes 30H to 39H. The
8086 allows you to add the ASCII codes for two decimal digits without masking off
the “3” in the upper nibble of each. After the addition, the AAA instruction is used to
make sure the result is the correct unpacked BCD.
Let AL = 0011 0101 (ASCII 5), and BL = 0011 1001 (ASCII 9)
ADD AL, BL AL = 0110 1110 (6EH, which is incorrect BCD)
AAA AL = 0000 0100 (unpacked BCD 4) CF = 1 indicates

answer is 14 decimal.
The AAA instruction works only on the AL register. The AAA instruction updates AF
and CF; but OF, PF, SF and ZF are left undefined.
AAS (ASCII ADJUST FOR SUBTRACTION)
Numerical data coming into a computer from a terminal is usually in an ASCII code.
In this code the numbers 0 to 9 are represented by the ASCII codes 30H to 39H. The
8086 allows you to subtract the ASCII codes for two decimal digits without masking
the “3” in the upper nibble of each. The AAS instruction is then used to make sure
the result is the correct unpacked BCD.
Let AL = 00111001 (39H or ASCII 9), and BL = 00110101 (35H or ASCII 5)
SUB AL, BL AL = 00000100 (BCD 04), and CF = 0
AAS AL = 00000100 (BCD 04), and CF = 0 (no borrow

required)
Let AL = 00110101 (35H or ASCII 5), and BL = 00111001 (39H or ASCII 9)
SUB AL, BL AL = 11111100 (– 4 in 2’s complement form), and CF = 1
AAS AL = 00000100 (BCD 06), and CF = 1 (borrow required)
The AAS instruction works only on the AL register. It updates ZF and CF; but OF,
PF, SF, AF are left undefined.
23
AAM (BCD ADJUST AFTER MULTIPLY)
Before you can multiply two ASCII digits, you must first mask the upper 4 bit of each.
This leaves unpacked BCD (one BCD digit per byte) in each byte. After the two
unpacked BCD digits are multiplied, the AAM instruction is used to adjust the product
to two unpacked BCD digits in AX. AAM works only after the multiplication of two
unpacked BCD bytes, and it works only the operand in AL. AAM updates PF, SF and
ZF but AF; CF and OF are left undefined.
Let AL = 00000101 (unpacked BCD 5), and BH = 00001001 (unpacked BCD 9)
MUL BH AL x BH: AX = 00000000 00101101 = 002DH
AAM AX = 00000100 00000101 = 0405H (unpacked BCD for

45)
AAD (BCD-TO-BINARY CONVERT BEFORE DIVISION)
AAD converts two unpacked BCD digits in AH and AL to the equivalent binary
number in AL. This adjustment must be made before dividing the two unpacked BCD
digits in AX by an unpacked BCD byte. After the BCD division, AL will contain the
unpacked BCD quotient and AH will contain the unpacked BCD remainder. AAD
updates PF, SF and ZF; AF, CF and OF are left undefined.
Let AX = 0607 (unpacked BCD for 67 decimal), and CH = 09H
AAD AX = 0043 (43H = 67 decimal)
DIV CH AL = 07; AH = 04; Flags undefined after DIV
If an attempt is made to divide by 0, the 8086 will generate a type 0 interrupt.
III. LOGICAL INSTRUCTIONS
AND – AND Destination, Source
This instruction ANDs each bit in a source byte or word with the same numbered
bit in a destination byte or word. The result is put in the specified destination. The
content of the specified source is not changed.
The source can be an immediate number, the content of a register, or the content
of a memory location. The destination can be a register or a memory location.
The source and the destination cannot both be memory locations. CF and OF are
both 0 after AND. PF, SF, and ZF are updated by the AND instruction. AF is
undefined. PF has meaning only for an 8-bit operand.
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AND CX, [SI] AND word in DS at offset [SI] with word in CX register;
Result in CX register
AND BH, CL AND byte in CL with byte in BH; Result in BH
AND BX, 00FFH 00FFH Masks upper byte, leaves lower byte unchanged.
OR – OR Destination, Source
This instruction ORs each bit in a source byte or word with the same numbered
bit in a destination byte or word. The result is put in the specified destination. The
content of the specified source is not changed.
The source and destination cannot both be memory locations. CF and OF are
both 0 after OR. PF, SF, and ZF are updated by the OR instruction. AF is
undefined. PF has meaning only for an 8-bit operand.
OR AH, CL CL ORed with AH, result in AH, CL not changed
OR BP, SI SI ORed with BP, result in BP, SI not changed
OR SI, BP BP ORed with SI, result in SI, BP not changed
OR BL, 80H BL ORed with immediate number 80H; sets MSB of BL to

1
OR CX, TABLE [SI] CX ORed with word from effective address TABLE [SI];
Content of memory is not changed.
XOR – XOR Destination, Source
This instruction Exclusive-ORs each bit in a source byte or word with the same
numbered bit in a destination byte or word. The result is put in the specified
destination. The content of the specified source is not changed.
The source and destination cannot both be memory locations. CF and OF are
both 0 after XOR. PF, SF, and ZF are updated. PF has meaning only for an 8-bit
operand. AF is undefined.
XOR CL, BH Byte in BH exclusive-ORed with byte in CL. Result

in CL. BH not changed.
XOR BP, DI Word in DI exclusive-ORed with word in BP.

Result in BP. DI not changed.
25
XOR WORD PTR [BX], 00FFH Exclusive-OR immediate number 00FFH
with word at offset [BX] in the data segment.
Result in memory location [BX]
NOT – NOT Destination
The NOT instruction inverts each bit (forms the 1’s complement) of a byte or word
in the specified destination. The destination can be a register or a memory
location. This instruction does not affect any flag.
NOT BX Complement content or BX register
NOT BYTE PTR [BX] Complement memory byte at offset [BX] in

data segment.
NEG – NEG Destination
This instruction replaces the number in a destination with its 2’s complement. The
destination can be a register or a memory location. It gives the same result as the
invert each bit and add one algorithm. The NEG instruction updates AF, AF, PF,
ZF, and OF.
NEG AL Replace number in AL with its 2’s

complement
NEG BX Replace number in BX with its 2’s

complement
NEG BYTE PTR [BX] Replace byte at offset BX in DX with its 2’s
complement NEG WORD PTR [BP] Replace word at offset BP in
SS with its 2’s complement
CMP – CMP Destination, Source
This instruction compares a byte / word in the specified source with a byte / word
in the specified destination. The source can be an immediate number, a register,
or a memory location. The destination can be a register or a memory location.
However, the source and the destination cannot both be memory locations. The
comparison is actually done by subtracting the source byte or word from the
destination byte or word. The source and the destination are not changed, but the
flags are set to indicate the results of the comparison. AF, OF, SF, ZF, PF, and
CF are updated by the CMP instruction. For the instruction CMP CX, BX, the
values of CF, ZF, and SF will be as follows:
26
CF ZF SF
CX = BX 0 1 0 Result of subtraction is 0
CX > BX 0 0 0 No borrow required, so CF = 0
CX < BX 1 0 1 Subtraction requires borrow, so CF = 1
CMP AL, 01H Compare immediate number 01H with byte

in AL
CMP BH, CL Compare byte in CL with byte in BH
CMP CX, TEMP Compare word in DS at displacement

TEMP with word at CX CMP PRICES [BX], 49H Compare immediate
number 49H with byte at offset [BX] in array PRICES
TEST – TEST Destination, Source
This instruction ANDs the byte / word in the specified source with the byte / word
in the specified destination. Flags are updated, but neither operand is changed.
The test instruction is often used to set flags before a Conditional jump
instruction.
The source and the destination cannot both be memory locations. CF and OF are
both 0’s after TEST. PF, SF and ZF will be updated to show the results of the
destination. AF is be undefined.
TEST AL, BH AND BH with AL. No result stored; Update PF, SF,
ZF.
TEST CX, 0001H AND CX with immediate number 0001H; No result

stored; Update PF, SF, ZF
TEST BP, [BX][DI] AND word are offset [BX][DI] in DS with word in
BP. No result stored. Update PF, SF, and ZF
IV. ROTATE AND SHIFT INSTRUCTION
RCL – RCL Destination, Count
This instruction rotates all the bits in a specified word or byte some number of bit
positions to the left. The operation circular because the MSB of the operand is
rotated into the carry flag and the bit in the carry flag is rotated around into LSB of
the operand.
27
For multi-bit rotates, CF will contain the bit most recently rotated out of the MSB.
The destination can be a register or a memory location. If you want to rotate the
operand by one bit position, you can specify this by putting a 1 in the count
position of the instruction. To rotate by more than one bit position, load the
desired number into the CL register and put “CL” in the count position of the
instruction.
RCL affects only CF and OF. OF will be a 1 after a single bit RCL if the MSB was
changed by the rotate. OF is undefined after the multi-bit rotate.
 RCL DX, 1 Word in DX 1 bit left, MSB to CF, CF to LSB

 MOV CL, 4 Load the number of bit positions to rotate into CL
RCL SUM [BX], CL Rotate byte or word at effective address SUM [BX]
4 bits left Original bit 4 now in CF, original CF
now in bit 3.
RCR – RCR Destination, Count
This instruction rotates all the bits in a specified word or byte some number of bit
positions to the right. The operation circular because the LSB of the operand is
rotated into the carry flag and the bit in the carry flag is rotate around into MSB of
the operand.
For multi-bit rotate, CF will contain the bit most recently rotated out of the LSB.
The destination can be a register or a memory location. If you want to rotate the
operand by one bit position, you can specify this by putting a 1 in the count
position of the instruction. To rotate more than one bit position, load the desired
number into the CL register and put “CL” in the count position of the instruction.
RCR affects only CF and OF. OF will be a 1 after a single bit RCR if the MSB
was changed by the rotate. OF is undefined after the multi-bit rotate.
 RCR BX, 1 Word in BX right 1 bit, CF to MSB, LSB to

CF
 MOV CL, 4 Load CL for rotating 4 bit position
28
RCR BYTE PTR [BX], 4 Rotate the byte at offset [BX] in DS 4 bit
positions right CF = original bit 3, Bit 4 – original
CF.
ROL – ROL Destination, Count
This instruction rotates all the bits in a specified word or byte to the left some
number of bit positions. The data bit rotated out of MSB is circled back into the
LSB. It is also copied into CF. In the case of multiple-bit rotate, CF will contain a
copy of the bit most recently moved out of the MSB.
The destination can be a register or a memory location. If you to want rotate the
operand by one bit position, you can specify this by putting 1 in the count position in
the instruction. To rotate more than one bit position, load the desired number into the
CL register and put “CL” in the count position of the instruction.
ROL affects only CF and OF. OF will be a 1 after a single bit ROL if the MSB was
changed by the rotate.
 ROL AX, 1 Rotate the word in AX 1 bit position left, MSB to LSB and
CF
 MOV CL, 04H Load number of bits to rotate in CL
ROL BL, CL Rotate BL 4 bit positions
 ROL FACTOR [BX], 1 Rotate the word or byte in DS at EA = FACTOR
[BX] by 1 bit position left into CF
ROR – ROR Destination, Count
This instruction rotates all the bits in a specified word or byte some number of
bit positions to right. The operation is desired as a rotate rather than shift, because
the bit moved out of the LSB is rotated around into the MSB. The data bit moved out
of the LSB is also copied into CF. In the case of multiple bit rotates, CF will contain a
copy of the bit most recently moved out of the LSB.
The destination can be a register or a memory location. If you want to rotate

the operand by one bit position, you can specify this by putting 1 in the count position
29
in the instruction. To rotate by more than one bit position, load the desired number
into the CL register and put “CL” in the count position of the instruction.
ROR affects only CF and OF. OF will be a 1 after a single bit ROR if the MSB
was changed by the rotate.
 ROR BL, 1 Rotate all bits in BL right 1 bit position LSB to

MSB and to CF
 MOV CL, 08H Load CL with number of bit positions to be
rotated
ROR WORD PTR [BX], CL Rotate word in DS at offset [BX] 8 bit
position right
SAL – SAL Destination, Count SHL – SHL Destination, Count
SAL and SHL are two mnemonics for the same instruction. This instruction
shifts each bit in the specified destination some number of bit positions to the left. As
a bit is shifted out of the LSB operation, a 0 is put in the LSB position. The MSB will
be shifted into CF. In the case of multi-bit shift, CF will contain the bit most recently
shifted out from the MSB. Bits shifted into CF previously will be lost.
The destination operand can be a byte or a word. It can be in a register or in a

memory location. If you want to shift the operand by one bit position, you can specify
this by putting a 1 in the count position of the instruction. For shifts of more than 1 bit
position, load the desired number of shifts into the CL register, and put “CL” in the
count position of the instruction.
The flags are affected as follow: CF contains the bit most recently shifted out from
MSB. For a count of one, OF will be 1 if CF and the current MSB are not the same.
For multiple-bit shifts, OF is undefined. SF and ZF will be updated to reflect the
condition of the destination. PF will have meaning only for an operand in AL. AF is
undefined.
 SAL BX, 1 Shift word in BX 1 bit position left, 0 in LSB

 MOV CL, 02h Load desired number of shifts in CL
SAL BP, CL Shift word in BP left CL bit positions, 0 in
LSBs
 SAL BYTE PTR [BX], 1 Shift byte in DX at offset [BX] 1 bit position
left, 0 in LSB
SAR – SAR Destination, Count
This instruction shifts each bit in the specified destination some number of bit
positions to the right. As a bit is shifted out of the MSB position, a copy of the old
30
MSB is put in the MSB position. In other words, the sign bit is copied into the MSB.
The LSB will be shifted into CF. In the case of multiple-bit shift, CF will contain the bit
most recently shifted out from the LSB. Bits shifted into CF previously will be lost.
The destination operand can be a byte or a word. It can be in a register or in a

memory location. If you want to shift the operand by one bit position, you can specify
this by putting a 1 in the count position of the instruction. For shifts of more than 1 bit
count position of the instruction.
The flags are affected as follow: CF contains the bit most recently shifted in from
LSB. For a count of one, OF will be 1 if the two MSBs are not the same. After a
multi-bit SAR, OF will be 0. SF and ZF will be updated to show the condition of the
destination. PF will have meaning only for an 8- bit destination. AF will be undefined
after SAR.
 SAR DX, 1 Shift word in DI one bit position right, new MSB =
old MSB
 MOV CL, 02H Load desired number of shifts in CL
SAR WORD PTR [BP], CL Shift word at offset [BP] in stack segment
right by two bit positions, the two MSBs are now
copies of original LSB
SHR – SHR Destination, Count
This instruction shifts each bit in the specified destination some number of bit
positions to the right. As a bit is shifted out of the MSB position, a 0 is put in its place.
The bit shifted out of the LSB position goes to CF. In the case of multi-bit shifts, CF
will contain the bit most recently shifted out from the LSB. Bits shifted into CF
previously will be lost.
The destination operand can be a byte or a word in a register or in a memory

location. If you want to shift the operand by one bit position, you can specify this by
putting a 1 in the count position of the instruction. For shifts of more than 1 bit
count position of the instruction. The flags are affected by SHR as follow: CF
contains the bit most recently shifted out from LSB. For a count of one, OF will be 1 if
the two MSBs are not both 0’s. For multiple-bit shifts, OF will be meaningless. SF
31
and ZF will be updated to show the condition of the destination. PF will have
meaning only for an 8-bit destination. AF is undefined.
 SHR BP, 1 Shift word in BP one bit position right, 0 in MSB

 MOV CL, 03H Load desired number of shifts into CL
SHR BYTE PTR [BX] Shift byte in DS at offset [BX] 3 bits right;
0’s in 3 MSBs
V. STRING MANIPULATION INSTRUCTIONS
MOVS – MOVS Destination String Name, Source String

Name
MOVSB – MOVSB Destination String Name, Source String
Name
MOVSW – MOVSW Destination String Name, Source String Name
This instruction copies a byte or a word from location in the data segment to a
location in the extra segment. The offset of the source in the data segment
must be in the SI register. The offset of the destination in the extra segment
must be in the DI register. For multiple-byte or multiple-word moves, the
number of elements to be moved is put in the CX register so that it can
function as a counter. After the byte or a word is moved, SI and DI are
automatically adjusted to point to the next source element and the next
destination element. If DF is 0, then SI and DI will incremented by 1 after a
byte move and by 2 after a word move. If DF is 1, then SI and DI will be
decremented by 1 after a byte move and by 2 after a word move. MOVS does
not affect any flag.
When using the MOVS instruction, you must in some way tell the assembler
whether you want to move a string as bytes or as word. There are two ways to
do this. The first way is to indicate the name of the source and destination
strings in the instruction, as, for example. MOVS DEST, SRC. The assembler
will code the instruction for a byte / word move if they were declared with a DB
/ DW. The second way is to add a “B” or a “W” to the MOVS mnemonic.
MOVSB says move a string as bytes; MOVSW says move a string as words.
 MOV SI, OFFSET SOURCE Load offset of start of source string in
DS into SI MOV DI, OFFSET DESTINATION Load offset of start of
destination string in ES into DI CLD Clear DF
to auto increment SI and DI after move MOV CX, 04H
Load length of string into CX as counter
REP MOVSB Move string byte until CX = 0
LODS / LODSB / LODSW (LOAD STRING BYTE INTO AL OR STRING WORD

INTO AX)
32
This instruction copies a byte from a string location pointed to by SI to AL, or a word
from a string location pointed to by SI to AX. If DF is 0, SI will be automatically
incremented (by 1 for a byte string, and 2 for a word string) to point to the next
element of the string. If DF is 1, SI will be automatically decremented (by 1 for a byte
string, and 2 for a word string) to point to the previous element of the string. LODS
does not affect any flag.
 CLD Clear direction flag so that SI is auto-

incremented
MOV SI, OFFSET SOURCE Point SI to start of string
LODS SOURCE Copy a byte or a word from string to AL or
AX
Note: The assembler uses the name of the string to determine whether the string is
of type bye or type word. Instead of using the string name to do this, you can use the
mnemonic LODSB to tell the assembler that the string is type byte or the mnemonic
LODSW to tell the assembler that the string is of type word.
STOS / STOSB / STOSW (STORE STRING BYTE OR STRING WORD)
This instruction copies a byte from AL or a word from AX to a memory location in the
extra segment pointed to by DI. In effect, it replaces a string element with a byte from
AL or a word from AX. After the copy, DI is automatically incremented or
decremented to point to next or previous element of the string. If DF is cleared, then
DI will automatically incremented by 1 for a byte string and by 2 for a word string. If
DI is set, DI will be automatically decremented by 1 for a byte string and by 2 for a
word string. STOS does not affect any flag.
 MOV DI, OFFSET TARGET

STOS TARGET
Note: The assembler uses the string name to determine whether the string is of type
byte or type word. If it is a byte string, then string byte is replaced with content of AL.
If it is a word string, then string word is replaced with content of AX.
 MOV DI, OFFSET TARGET

STOSB
“B” added to STOSB mnemonic tells assembler to replace byte in string with byte
from AL. STOSW would tell assembler directly to replace a word in the string with a
word from AX.
CMPS / CMPSB / CMPSW (COMPARE STRING BYTES OR STRING WORDS)
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This instruction can be used to compare a byte / word in one string with a byte / word
in another string. SI is used to hold the offset of the byte or word in the source string,
and DI is used to hold the offset of the byte or word in the destination string.
The AF, CF, OF, PF, SF, and ZF flags are affected by the comparison, but the two
operands are not affected. After the comparison, SI and DI will automatically be
incremented or decremented to point to the next or previous element in the two
strings. If DF is set, then SI and DI will automatically be decremented by 1 for a byte
string and by 2 for a word string. If DF is reset, then SI and DI will automatically be
incremented by 1 for byte strings and by 2 for word strings. The string pointed to by
SI must be in the data segment. The string pointed to by DI must be in the extra
segment.
The CMPS instruction can be used with a REPE or REPNE prefix to compare all the
elements of a string.
 MOV SI, OFFSET FIRST Point SI to source string

MOV DI, OFFSET SECOND Point DI to destination string
CLD DF cleared, SI and DI will auto-increment
after compare
MOV CX, 100 Put number of string elements in CX
REPE CMPSB Repeat the comparison of string bytes until
end of string or until compared bytes are not
equal
CX functions as a counter, which the REPE prefix will cause CX to be decremented

after each compare. The B attached to CMPS tells the assembler that the strings are
of type byte. If you want to tell the assembler that strings are of type word, write the
instruction as CMPSW. The REPE CMPSW instruction will cause the pointers in SI
and DI to be incremented by 2 after each compare, if the direction flag is set.
SCAS / SCASB / SCASW (SCAN A STRING BYTE OR A STRING WORD)
SCAS compares a byte in AL or a word in AX with a byte or a word in ES pointed to

by DI. Therefore, the string to be scanned must be in the extra segment, and DI must
contain the offset of the byte or the word to be compared. If DF is cleared, then DI
will be incremented by 1 for byte strings and by 2 for word strings. If DF is set, then
DI will be decremented by 1 for byte strings and by 2 for word strings. SCAS affects
AF, CF, OF, PF, SF, and ZF, but it does not change either the operand in AL (AX) or
the operand in the string.
The following program segment scans a text string of 80 characters for a carriage
return, 0DH, and puts the offset of string into DI:
 MOV DI, OFFSET STRING

MOV AL, 0DH Byte to be scanned for into AL
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MOV CX, 80 CX used as element counter
CLD Clear DF, so that DI auto increments
REPNE SCAS STRING Compare byte in string with byte in AL
REP / REPE / REPZ / REPNE / REPNZ (PREFIX) (REPEAT STRING

INSTRUCTION UNTIL SPECIFIED CONDITIONS EXIST)
REP is a prefix, which is written before one of the string instructions. It will cause the
CX register to be decremented and the string instruction to be repeated until CX = 0.
The instruction REP MOVSB, for example, will continue to copy string bytes until the
number of bytes loaded into CX has been copied.
REPE and REPZ are two mnemonics for the same prefix. They stand for repeat if
equal and repeat if zero, respectively. They are often used with the Compare String
instruction or with the Scan String instruction. They will cause the string instruction to
be repeated as long as the compared bytes or words are equal (ZF = 1) and CX is
not yet counted down to zero. In other words, there are two conditions that will stop
the repetition: CX = 0 or string bytes or words not equal.
REPE CMPSB Compare string bytes until end of string or until string
bytes not equal.
REPNE and REPNZ are also two mnemonics for the same prefix. They stand for
repeat if not equal and repeat if not zero, respectively. They are often used with the
Compare String instruction or with the Scan String instruction. They will cause the
string instruction to be repeated as long as the compared bytes or words are not
equal (ZF = 0) and CX is not yet counted down to zero.
REPNE SCASW Scan a string of word until a word in the string matches the word
in AX or until all of the string has been scanned.
The string instruction used with the prefix determines which flags are affected.
VI. CONTROL TRANSFER INSTRUCTIONS
JMP (UNCONDITIONAL JUMP TO SPECIFIED DESTINATION)
This instruction will fetch the next instruction from the location specified in the
instruction rather than from the next location after the JMP instruction. If the
destination is in the same code segment as the JMP instruction, then only the
instruction pointer will be changed to get the destination location. This is
referred to as a near jump. If the destination for the jump instruction is in a
segment with a name different from that of the segment containing the JMP
instruction, then both the instruction pointer and the code segment register
35
content will be changed to get the destination location. This referred to as a
far jump. The JMP instruction does not affect any flag.
JMP CONTINUE This instruction fetches the next instruction from

address at label CONTINUE. If the label is in the
same segment, an offset coded as part of the
instruction will be added to the instruction pointer
to produce the new fetch address. If the label is
another segment, then IP and CS will be replaced
with value coded in part of the instruction. This
type of jump is referred to as direct because the
displacement of the destination or the destination
itself is specified directly in the instruction.
JMP BX This instruction replaces the content of IP with the

content of BX. BX must first be loaded with the
offset of the destination instruction in CS. This is a
near jump. It is also referred to as an indirect jump
because the new value of IP comes from a register
rather than from the instruction itself, as in a direct
jump.
JMP WORD PTR [BX] This instruction replaces IP with word from a
memory location pointed to by BX in DX. This is an
indirect near jump.
JMP DWORD PTR [SI] This instruction replaces IP with word pointed to by
SI in DS. It replaces CS with a word pointed by SI
+ 2 in DS. This is an indirect far jump.
JAE / JNB / JNC (JUMP IF ABOVE OR EQUAL / JUMP IF NOT BELOW / JUMP
IF NO CARRY)
If, after a compare or some other instructions which affect flags, the carry flag
is 0, this instruction will cause execution to jump to a label given in the
instruction. If CF is 1, the instruction will have no effect on program execution.
 CMP AX, 4371H Compare (AX – 4371H)

JAE NEXT Jump to label NEXT if AX above 4371H
JNB NEXT Jump to label NEXT if AX not below 4371H
 ADD AL, BL Add two bytes
JNC NEXT If the result with in acceptable range, continue
36
JB / JC / JNAE (JUMP IF BELOW / JUMP IF CARRY / JUMP IF NOT ABOVE OR
EQUAL)
If, after a compare or some other instructions which affect flags, the carry flag
is a 1, this instruction will cause execution to jump to a label given in the
instruction. If CF is 0, the instruction will have no effect on program execution.

JB NEXT Jump to label NEXT if AX below 4371H
 ADD BX, CX Add two words
JC NEXT Jump to label NEXT if CF = 1
JNAE NEXT Jump to label NEXT if AX not above or
equal to 4371H
JBE / JNA (JUMP IF BELOW OR EQUAL / JUMP IF NOT ABOVE)
If, after a compare or some other instructions which affect flags, either the
zero flag or the carry flag is 1, this instruction will cause execution to jump to a
label given in the instruction. If CF and ZF are both 0, the instruction will have
no effect on program execution.

JBE NEXT Jump to label NEXT if AX is below or equal to
4371H
JNA NEXT Jump to label NEXT if AX not above 4371H
JG / JNLE (JUMP IF GREATER / JUMP IF NOT LESS THAN OR EQUAL)
This instruction is usually used after a Compare instruction. The instruction

will cause a jump to the label given in the instruction, if the zero flag is 0 and
the carry flag is the same as the overflow flag.
 CMP BL, 39H Compare by subtracting 39H from BL

JG NEXT Jump to label NEXT if BL more positive than 39H
JNLE NEXT Jump to label NEXT if BL is not less than or equal to 39H
JGE / JNL (JUMP IF GREATER THAN OR EQUAL / JUMP IF NOT LESS THAN)
37
This instruction is usually used after a Compare instruction. The instruction
will cause a jump to the label given in the instruction, if the sign flag is equal to
the overflow flag.

JGE NEXT Jump to label NEXT if BL more positive than or equal to
39H
JNL NEXT Jump to label NEXT if BL not less than 39H
JLE / JNG (JUMP IF LESS THAN OR EQUAL / JUMP IF NOT GREATER)
This instruction is usually used after a Compare instruction. The instruction will
cause a jump to the label given in the instruction if the zero flag is set, or if the sign
flag not equal to the overflow flag.

JLE NEXT Jump to label NEXT if BL more negative than or equal to
39H
JNG NEXT Jump to label NEXT if BL not more positive than
39H
JE / JZ (JUMP IF EQUAL / JUMP IF ZERO)
This instruction is usually used after a Compare instruction. If the zero flag is set,
then this instruction will cause a jump to the label given in the instruction.
 CMP BX, DX Compare (BX-DX)

JE DONE Jump to DONE if BX = DX
 IN AL, 30H Read data from port 8FH
SUB AL, 30H Subtract the minimum value.
JZ START Jump to label START if the result of subtraction is 0
JNE / JNZ (JUMP NOT EQUAL / JUMP IF NOT ZERO)
This instruction is usually used after a Compare instruction. If the zero flag is 0, then
this instruction will cause a jump to the label given in the instruction.
 IN AL, 0F8H Read data value from port

CMP AL, 72 Compare (AL –72)
JNE NEXT Jump to label NEXT if AL ≠ 72
 ADD AX, 0002H Add count factor 0002H to AX
DEC BX Decrement BX
JNZ NEXT Jump to label NEXT if BX ≠ 0
JS (JUMP IF SIGNED / JUMP IF NEGATIVE)
38
This instruction will cause a jump to the specified destination address if the sign flag
is set. Since a 1 in the sign flag indicates a negative signed number, you can think of
this instruction as saying “jump if negative”.
 ADD BL, DH Add signed byte in DH to signed byte in DL

JS NEXT Jump to label NEXT if result of addition is negative
number
JNS (JUMP IF NOT SIGNED / JUMP IF POSITIVE)
This instruction will cause a jump to the specified destination address if the sign flag
is 0. Since a 0 in the sign flag indicate a positive signed number, you can think to this
instruction as saying “jump if positive”.
 DEC AL Decrement AL
JNS NEXT Jump to label NEXT if AL has not decremented to FFH
JP / JPE (JUMP IF PARITY / JUMP IF PARITY EVEN)
If the number of 1’s left in the lower 8 bits of a data word after an instruction which
affects the parity flag is even, then the parity flag will be set. If the parity flag is set,
the JP / JPE instruction will cause a jump to the specified destination address.
 IN AL, 0F8H Read ASCII character from Port F8H

OR AL, AL Set flags
JPE ERROR Odd parity expected, send error message if parity
found even
JNP / JPO (JUMP IF NO PARITY / JUMP IF PARITY ODD)
If the number of 1’s left in the lower 8 bits of a data word after an instruction which
affects the parity flag is odd, then the parity flag is 0. The JNP / JPO instruction will
cause a jump to the specified destination address, if the parity flag is 0.
 IN AL, 0F8H Read ASCII character from Port F8H

OR AL, AL Set flags
JPO ERROR Even parity expected, send error message if parity
found odd
JO (JUMP IF OVERFLOW)
The overflow flag will be set if the magnitude of the result produced by some signed
arithmetic operation is too large to fit in the destination register or memory location.
39
The JO instruction will cause a jump to the destination given in the instruction, if the
overflow flag is set.
 ADD AL, BL Add signed bytes in AL and BL

 JO ERROR Jump to label ERROR if overflow from add
JNO (JUMP IF NO OVERFLOW)
The overflow flag will be set if some signed arithmetic operation is too large to fit in
the destination register or memory location. The JNO instruction will cause a jump to
the destination given in the instruction, if the overflow flag is not set.
 ADD AL, BL Add signed byte in AL and BL

JNO DONE Process DONE if no overflow
JCXZ (JUMP IF THE CX REGISTER IS ZERO)
This instruction will cause a jump to the label to a given in the instruction, if the CX
register contains all 0’s. The instruction does not look at the zero flag when it decides
whether to jump or not.
 JCXZ SKIP If CX = 0, skip the process

SUB [BX], 07H Subtract 7 from data value
SKIP: ADD C Next instruction
LOOP (JUMP TO SPECIFIED LABEL IF CX  0 AFTER AUTO DECREMENT)
This instruction is used to repeat a series of instructions some number of times. The
number of times the instruction sequence is to be repeated is loaded into CX. Each
time the LOOP instruction executes, CX is automatically decremented by 1. If CX is
not 0, execution will jump to a destination specified by a label in the instruction. If CX
= 0 after the auto decrement, execution will simply go on to the next instruction after
LOOP. The destination address for the jump must be in the range of –128 bytes to
+127 bytes from the address of the instruction after the LOOP instruction. This
instruction does not affect any flag.
 MOV BX, OFFSET PRICES Point BX at first element in array

MOV CX, 40 Load CX with number of elements in
array NEXT: MOV AL, [BX] Get element from array
INC AL Increment the content of AL
MOV [BX], AL Put result back in array
INC BX Increment BX to point to next location
LOOP NEXT Repeat until all elements adjusted
LOOPE / LOOPZ (LOOP WHILE CX  0 AND ZF = 1)
This instruction is used to repeat a group of instructions some number of times, or

until the zero flag becomes 0. The number of times the instruction sequence is to be
40
repeated is loaded into CX. Each time the LOOP instruction executes, CX is
automatically decremented by 1. If CX ≠0 and ZF = 1, execution will jump to a
destination specified by a label in the instruction. If CX = 0, execution simply go on
the next instruction after LOOPE / LOOPZ. In other words, the two ways to exit the
loop are CX = 0 or ZF = 0. The destination address for the jump must be in the
range of –128 bytes to +127 bytes from the address of the instruction after the
LOOPE / LOOPZ instruction. This instruction does not affect any flag.
 MOV BX, OFFSET ARRAY Point BX to address of ARRAY

before start of array DEC BX Decrement BX
MOV CX, 100 Put number of array elements in CX
NEXT: INC BX Point to next element in array
CMP [BX], OFFH Compare array element with FFH LOOPE
NEXT
LOOPNE / LOOPNZ (LOOP WHILE CX  0 AND ZF = 0)
This instruction is used to repeat a group of instructions some number of times, or

until the zero flag becomes a 1. The number of times the instruction sequence is to
be repeated is loaded into the count register CX. Each time the LOOPNE / LOOPNZ
instruction executes, CX is automatically decremented by 1. If CX  0 and ZF = 0,
execution will jump to a destination specified by a label in the instruction. If CX = 0,
after the auto decrement or if ZF = 1, execution simply go on the next instruction
after LOOPNE / LOOPNZ. In other words, the two ways to exit the loop are CX = 0
or ZF = 1. The destination address for the jump must be in the range of –128 bytes
to +127 bytes from the address of the instruction after the LOOPNE / LOOPZ
instruction. This instruction does not affect any flags.
 MOV BX, OFFSET ARRAY Point BX to adjust before start of

array
DEC BX Decrement BX
MOV CX, 100 Put number of array in CX
NEXT: INC BX Point to next element in array
CMP [BX], ODH Compare array element with 0DH
LOOPNZ NEXT
CALL (CALL A PROCEDURE)
The CALL instruction is used to transfer execution to a subprogram or a procedure.

There two basic type of calls near and far. 1. A near call is a call to a procedure,
which is in the same code segment as the CALL instruction. When the 8086
executes a near CALL instruction, it decrements the stack pointer by 2 and copies
the offset of the next instruction after the CALL into the stack. This offset saved in
the stack is referred to as the return address, because this is the address that
execution will return to after the procedure is executed. A near CALL instruction will
also load the instruction pointer with the offset of the first instruction in the procedure.
41
A RET instruction at the end of the procedure will return execution to the offset
saved on the stack which is copied back to IP. 2. A far call is a call to a procedure,
which is in a different segment from the one that contains the CALL instruction.
When the 8086 executes a far call, it decrements the stack pointer by 2 and copies
the content of the CS register to the stack. It then decrements the stack pointer by 2
again and copies the offset of the instruction after the CALL instruction to the stack.
Finally, it loads CS with the segment base of the segment that contains the
procedure, and loads IP with the offset of the first instruction of the procedure in that
segment. A RET instruction at the end of the procedure will return execution to the
next instruction after the CALL by restoring the saved values of CS and IP from the
stack.
 CALL MULT
This is a direct within segment (near or intra segment) call. MULT is the name
of the procedure. The assembler determines the displacement of MULT from
the instruction after the CALL and codes this displacement in as part of the
instruction.
 CALL BX
This is an indirect within-segment (near or intra-segment) call. BX contains
the offset of the first instruction of the procedure. It replaces content of IP with
content of register BX.
 CALL WORD PTR [BX]

This is an indirect within-segment (near or intra-segment) call. Offset of the
first instruction of the procedure is in two memory addresses in DS. Replaces
content of IP with content of word memory location in DS pointed to by BX.
 CALL DIVIDE
This is a direct call to another segment (far or inter-segment call). DIVIDE is
the name of the procedure. The procedure must be declared far with DIVIDE
PROC FAR at its start. The assembler will determine the code segment base
for the segment that contains the procedure and the offset of the start of the
procedure. It will put these values in as part of the instruction code.
 CALL DWORD PTR [BX]

This is an indirect call to another segment (far or inter-segment call). New
values for CS and IP are fetched from four-memory location in DS. The new
value for CS is fetched from [BX] and [BX + 1]; the new IP is fetched from [BX
+ 2] and [BX +3].
RET (RETURN EXECUTION FROM PROCEDURE TO CALLING PROGRAM)
42
The RET instruction will return execution from a procedure to the next instruction
after the CALL instruction which was used to call the procedure. If the procedure is
near procedure (in the same code segment as the CALL instruction), then the return
will be done by replacing the IP with a word from the top of the stack. The word from
the top of the stack is the offset of the next instruction after the CALL. This offset was
pushed into the stack as part of the operation of the CALL instruction. The stack
pointer will be incremented by 2 after the return address is popped off the stack.
If the procedure is a far procedure (in a code segment other than the one from which
it is called), then the instruction pointer will be replaced by the word at the top of the
stack. This word is the offset part of the return address put there by the CALL
instruction. The stack pointer will then be incremented by 2. The CS register is then
replaced with a word from the new top of the stack. This word is the segment base
part of the return address that was pushed onto the stack by a far call operation.
After this, the stack pointer is again incremented by 2.
A RET instruction can be followed by a number, for example, RET 6. In this case, the
stack pointer will be incremented by an additional six addresses after the IP when
the IP and CS are popped off the stack. This form is used to increment the stack
pointer over parameters passed to the procedure on the stack.
The RET instruction does not affect any flag.
VII. PROCESS CONTROL INSTRUCTIONS
 STC (SET CARRY FLAG)

This instruction sets the carry flag to 1. It does not affect any other flag.
 CLC (CLEAR CARRY FLAG)
This instruction resets the carry flag to 0. It does not affect any other flag.
 CMC (COMPLEMENT CARRY FLAG)
This instruction complements the carry flag. It does not affect any other flag.
 STD (SET DIRECTION FLAG)
This instruction sets the direction flag to 1. It does not affect any other flag.
 CLD (CLEAR DIRECTION FLAG)
This instruction resets the direction flag to 0. It does not affect any other flag.
 STI (SET INTERRUPT FLAG)
Setting the interrupt flag to a 1 enables the INTR interrupt input of the 8086.
The instruction will not take affect until the next instruction after STI. When the
INTR input is enabled, an interrupt signal on this input will then cause the
8086 to interrupt program execution, push the return address and flags on the
stack, and execute an interrupt service procedure. An IRET instruction at the
end of the interrupt service procedure will restore the return address and flags
that were pushed onto the stack and return execution to the interrupted
program. STI does not affect any other flag.
 CLI (CLEAR INTERRUPT FLAG)
43
This instruction resets the interrupt flag to 0. If the interrupt flag is reset, the
8086 will not respond to an interrupt signal on its INTR input. The CLI
instructions, however, has no effect on the non-maskable interrupt input, NMI.
It does not affect any other flag.
 HLT (HALT PROCESSING)
The HLT instruction causes the 8086 to stop fetching and executing
instructions. The 8086 will enter a halt state. The different ways to get the
processor out of the halt state are with an interrupt signal on the INTR pin, an
interrupt signal on the NMI pin, or a reset signal on the RESET input.
 NOP (PERFORM NO OPERATION)
This instruction simply uses up three clock cycles and increments the
instruction pointer to point to the next instruction. The NOP instruction can be
used to increase the delay of a delay loop. When hand coding, a NOP can
also be used to hold a place in a program for an instruction that will be added
later. NOP does not affect any flag.
 ESC (ESCAPE)
This instruction is used to pass instructions to a coprocessor, such as the
8087 Math coprocessor, which shares the address and data bus with 8086.
Instructions for the coprocessor are represented by a 6-bit code embedded in
the ESC instruction. As the 8086 fetches instruction bytes, the coprocessor
also fetches these bytes from the data bus and puts them in its queue.
However, the coprocessor treats all the normal 8086 instructions as NOPs.
When 8086 fetches an ESC instruction, the coprocessor decodes the
instruction and carries out the action specified by the 6-bit code specified in
the instruction. In most cases, the 8086 treats the ESC instruction as a NOP.
In some cases, the 8086 will access a data item in memory for the
coprocessor.
PROCEDURE
Procedure is a part of code that can be called from your program in order to make
some specific task. Procedures make program more structural and easier to
understand. Generally procedure returns to the same point from where it was called.
The syntax for procedure declaration:
 name PROC
; here goes the code
; of the procedure
.
.
RET
name ENDP
44
name - is the procedure name, the same name should be in the top and the bottom,
this is used to check correct closing of procedures.
ASSEMBLER DIRECTIVES
 PROC
 ENDP
PROC and ENDP are compiler directives, so they are not assembled into any real
machine code. Compiler just remembers the address of procedure. CALL instruction
is used to call a procedure.
 ORG
Eg: ORG 100h
ORG 100h is a compiler directive (it says to compiler how to handle the source
code). This directive is very important when you work with variables. It says to
compiler that the executable file will be loaded at the offset of 100h (256 bytes), so
compiler should calculate the correct address for all variables when it replaces the
variable names with their offsets. Directives are never converted to any real machine
code.
 ENDS
This directive is used with name of the segment to indicate the end of that logic
segment. For example
CODE SEGMENT ; this statement starts the segment

.
.
CODE ENDS ; this statement ends the segment
 ASSUME
This directive tells the assembler the name of the logical segment it should use for a
specified segment. For example ASSUME CS:CODE, tells the assembler that the
instructions for a program are in a logical segment named CODE. The 8086 works
directly with only 4 physical segments: a Code segment, a data segment, a stack
segment, and an extra segment.
8086 PROGRAMS
Program for find the ADDITION of two Program for find the SUBTRACTION
numbers: of two numbers:
MOV AX,05 MOV AX,05
MOV BX,03 MOV BX,03
45
ADD AX,BX SUB AX,BX
MOV SI,8000 MOV SI,8000
MOV [SI],AX MOV [SI],AX
INT 03 INT 03
Program for find the Program for find the DIVISION of two
MULTIPLICATION of two numbers: numbers:
MOV AX,05 MOV AX,05
MOV BX,03 MOV BX,03
MUL BX DIV BX
MOV [SI],AX MOV [SI],AX
INT 03 INT 03
Program for find the GREATEST OF 2- Program for find the AVERAGE OF N-
NUMBERS: NUMBERS:
MOV AX,04 MOV AX,0000
MOV BX,05 MOV SI,8000
CMP AX,BX MOV DI,8020
JNC LABEL1 MOV CX,5
MOV SI,8001 LABLE1: ADD AX,[SI]
MOV [SI],AX INC SI
LABEL1: MOV [SI],BX INC SI
INT 03 LOOP LABLE1
DIV CX
MOV [DI],AX
INT 03
Program for find the SUM OF N- Program for find the find the factorial
NUMBERS: of a number
46
MOV CX,[SI] MOV BX[SI]
MOV AX,0000 MOV AX,01
MOV BX,ax LABEL1: MUL BX
LABEL1: INC BX DEC BX
ADD AX,BX JNZ LABEL1
CMP BX,CX MOV DI,8050
JNZ LABEL1 MOV [DI],AX
MOV DI,8010 INT 03
MOV [DI],AX
INT 03
8284A Clock Generator
The 8284A is an ancillary component to the 8086/8088 microprocessor. Without the

clock generator, many additional circuits to generate the clock (CLK in an 8086/8088
based system. The clock Generator 8284A provides the following basic functions or
signals: clock generation, RESEST synchronization, READY synchronization, and a
TTL level peripheral clock signal.
47
Fig: Pin diagram of 8284
Pin Functions:
The 8284A is an 18-pin integrated circuit designed specifically for use with the
8086/8088 microprocessors as shown in fig1. The following is a list of each pin and
its function.
AEN1* and AEN2*:
The address enable pins are provided to qualify the ready signals. RDY1 and RDY2,
respectively. Which are used to cause wait states, along with the RDY1 and RDY2
inputs. Wait states are generated by the READY pin of the 8086/8088
microprocessor. This is controlled by these two inputs.
RDY1 and RDY2:
The bus ready inputs are provided in conjunction with the AEN1* and AEN2* pins to
cause wait states in an 8086/8088 microprocessor based system.
ASYNC*:
The ready synchronization selection input selects either one or two stages of
synchronization for the RDY1 and RDY2 inputs.
READY:
48
Ready is an output pin that connects to the 8086/8088 microprocessor READY input.
This signal is synchronized with the RDY1 and RDY2 inputs.
X1 and X2:
The Crystal Oscillator pins connect to an external crystal used as the timing source
for the clock generator and all its functions.
F/C*:
The Frequency/Crystal select input results the clocking source for the 8284A. If this
pin is held high, an external clock is provided to the EFI input pin, and if it is held low,
the internal crystal oscillator provides the timing signal.
EFI:
The External Frequency input is used when the F/C is pulled high. EFI supplies the
timing whenever the F/C* pin is high..
CLK:
The clock output pin provides CLK input signal to the 8086/8088 microprocessors
and other components in the system. The CLK pin has an output signal that is one-
third of the crystal or EFI input frequency and has a 33 percent duty cycle, which is
required by the 8086/8088 microprocessors.
PCLK:
The Peripheral Clock signal is one-sixth the crystal or EFI input frequency and has a
50 percent duty cycle. The PCLK output provides a clock signal to the peripheral
equipment in the system.
OSC:
The Oscillator output is a TTL level signal that is at the same frequency as the
crystal or EFI input. (The OSC output provides and EFI input to other 8284A clock
generators in some multiple processor systems).
RES*:
The reset input is an active-low input to the 8284A. The RES* pin is often connected
an RC network that provides power-on resetting.
RESET:
The Reset output is connected to the 8086/8088 microprocessors RESET input pin.
CSYNC:
49
The clock synchronization pin is used whenever the EFI input provides
synchronization in systems with multiple processors. When the internal crystal
oscillator is used, this pin must be grounded.
GND:
The ground pin is connects to ground.
Vcc:
This power supply pin connects to + 5.0V with a tolerance of ± 10 percent
Fig : Typical connection with 8086
That F/C and CSYNC are grounded to select the crystal oscillator and that a 15
MHz crystal provides the normal 5 MHz clock signal to the 8086/8088 as well as a
2.5 MH-z peripheral clock signal.
Operation of the Reset Section: The reset section of the 8284A is simple, and it
consists of a Schmitt trigger buffer and a single D-type flip-flop circuit. The D-type
flip-flop ensures that the timing requirement of the 8086 RESET input are fulfilled.
This circuit applies the RESET signal to the microprocessor on the negative edge
(1-to-0 transition) of each clock. The 8086/8088 microprocessors sample RESET at
the positive edge (0-to- 1 transition) of the clocks; therefore (this circuit meets the
timing requirements of the 8086). From Fig. it can be observed that an RC circuit
provides a logic 0 to the RES input pin when power is first applied to the system.
After a short time, the RES input becomes a logic 1 because the capacitor charges
toward +5.0 V through the resistor. A push button switch allows the microprocessor
to be reset by the operator. Exact rest timing requires the RESET input to become a
logic 1 no later than four clocks after system power is applied and to be held for at
least 50 µs. (The flip-flop makes certain that RESET goes high in four clocks, and
the RC time constant ensures that it stays high for at least 50 µs).
50
UNIT IV
PART A
Answer the following
1. What are the differences between 8085 and 8086?
2. How is physical address calculated in 8086 microprocessor?
3. How many address and data lines are there in 8086 microprocessor?
4. What is the need for segment registers in 8086 microprocessor?
5. What are the advantages and disadvantages of pipelined architectures?
6. Draw the flag register of 8086 microprocessor.
7. What is an overflow flag?
8. What is the need for direction flag in 8086?
9. What is the use for trap flag in 8086?
10. What do you mean by minimum and maximum mode operations of 8086
microprocessor?
11. What is the purpose of LOCK in 8086?
12. What is the need for Request and Grant signals in 8086 microprocessor?
13. What is the purpose of 8284 clock driver?
14. What are pseudocodes?
15. With is the need for index registers in 8086 microprocessor?
16. What is the use of AAA instruction?
PART B
Answer the following
1. With a neat diagram, explain the architecture of 8086 microprocessor.
2. With a neat signal diagram, explain the minimum mode operation of 8086
microprocessor.
3. With a diagram, explain the maximum mode operations of 8086
microprocessor.
4. With a neat diagram, explain the working of 8284 clock driver.
5. What is an addressing mode? Describe the different types of addressing
modes with suitable examples.
6. Explain any two types of instructions in 8086 microprocessor.
7. Write an assembly language program to perform block transfer of data.
51

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UNIT – II

SYLLABUS - 8086 PROCESSOR

8086 Architecture-Maximum and Minimum Mode-Memory Banks-Memory Segmentation-Programming Model -Instruction

Features of 8086 Microprocessor:

PIN DIAGRAM OF 8086

 A19/S6, A18/S5, A17/S4, A16/S3 [Pin 35-38 (Unidirectional)]

 BHE / S7 [Pin 34 (Output)]

 RD (Read) [Pin 32 (Output)]

 READY [ Pin 22 (Input)]

 INTR [Pin 18 (Input)]

 VCC and VSS[Pin 40 and Pin 20 (Input)]

PIN Description for Minimum Mode

 ALE [Pin 25 (Output)].

PIN Description for Maximum Mode

 QS1 and QS0 [Pin 24 and 25 (Output)]

QS1 QS0 STATUS

 S0, S1, S2 [Pin 26, 27, 28 (Output)]

 RQ/GT1 and RQ/GT0 [Pin 30 and 31 (Bi-directional)]

Bus Interface Unit (BIU)

The function of BIU is to:

 Fetch the instruction or data from memory.

 Write the data to memory.

 Write the data to the port.

 Read data from the port.

3. Then all bytes have to be given to EU one by one.

Execution Unit (EU)

The functions of execution unit are:

To tell BIU where to fetch the instructions or data from.

To decode the instructions.

To execute the instructions.

The EU contains the control circuitry to perform various internal operations. A

General Purpose Registers of 8086

1. AX Register: AX register is also known as accumulator register that stores

3. CX Register: It is defined as a counter. It is primarily used in loop instruction to

Additional registers called segment registers generate memory address when

Fig.: Memory Segments of 8086

1. Code Segment (CS): The CS register is used for addressing a

Flag register in EU is of 16-bit , is shown

Fig : Flag Register of 8086

Conditional flags represent result of last arithmetic or logical instruction executed.

 Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow

1. Trap Flag (TP):

a. It is used for single step control.

b. It allows user to execute one instruction of a program at a time for debugging.

2. Interrupt Flag (IF):

a. It is an interrupt enable/disable flag.

3. Direction Flag (DF):

a. It is used in string operation.

Addressing modes of 8086

I. Addressing modes for register and immediate data

1) Register Addressing mode

II. Addressing modes for memory data

3) Register Indirect Addressing mode

III. Addrressing modes for I/O port

IV. Relative Addressing mode

V. Implied Addressing Mode

Register Addressing Mode

Immediate Addressing mode

Direct Addressing mode

Register Indirect Addressing mode