HW3 Emi
HW3 Emi
HW3 Emi
Assignment 3
Due Date: October 23, 2024 (5pm)
Assignments should be returned in soft form only. Please try to be as professional as possible. Make
sure to provide references for all the information. The presentation of your assignment carries at least
10% of the total marks for the assignment.
Problem 1: Credits: 20
1. Do a survey or research on different impedance analyzers and vector network analyzers
(VNA) across the globe. Briefly make a list of them, their selling price, limitations in terms of
bandwidths, and benefits over the other vendors and any other useful information.
a. Each student should discuss ‘3’ impedance analyzers and ‘2’ VNAs.
b. Take the remainder of your roll number with ‘6’ and students with remainder:
i. ‘0’ find the products from companies in North America.
ii. ‘1’ find the products from companies in China.
iii. ‘2’ find the products from companies in Japan.
iv. ‘3’ find the products from companies in South Korea+UK.
v. ‘4’ find the products from companies in Europe.
vi. ‘5’ find the products from companies from the countries not listed above.
Problem 2: Credits: 20
a. Consider a common mode choke (CMC) placed/mounted on a real electronics board.
Impedances between different nodes and components have been labelled below. Please
device electrical measurement methods to characterize them all, i.e., find their values
and eventually make the equivalent circuit. You are allowed to do open circuits, short
circuits or any other possible (but valid) configuration to simplify the circuit. You can read
multiple papers for the best possible characterization of a real CMC, please do cite them
to get full credit. Fig1a and 1b should be referenced to this problem.
b. Consider the application Note by Würth Elektronik discussed in the class. The application
note can be found here. Simulate the circuit drawn in Fig. 15 and Fig. 16 for simulation of
CM and DM insertion losses. Please use the device models from manufacturer’s own
website and use LTspice for this simulation. You are supposed to reproduce the results
shown in Fig. 17 and Fig. 18. Attach your LTspice and other necessary files. Please make
effective plots to get full credit.
Fig. 1a: CMC mounted on real electronics Fig. 1b: Equivalent circuit of a CMC
board
Problem 3: Credits: 60
Simulate the problem3 provided in homework2 in your respective software using CISPR
standard LISN and determine the noise between 150 kHz and 30 MHz only.
a. Plot both the CM and DM noise when switching the converter at 70 kHz. Plot the standard
values on top of simulated value with different colors and reasonable linewidth. Make
sure X-axis is in log scale and Y-axis in dBuV. Also plot the required attenuation to pass
CISPR standards in conducted emissions provided below. Please make sure your
simulation closely resembles the original problem, otherwise onwards efforts will be a
mere waste of time. Once the simulation platform runs, make sure to collect EMI noise in
a steady state only. If the noise output does not makes sense, check with me at this point
before heading to ongoing parts of problem.
b. Repeat the above with a switching frequency of 100 kHz.
c. Based upon the attenuation required and above data, let’s design a single stage and two
stage filter which helps pass the CISPR standard. Please design filters for both the
switching frequencies, i.e. 70 khz and 100 kHz separately. For the simulations, find the
closest possible inductor/CMC/capacitor from any vendor in the world and use the actual
component model provided by the vendor. You are not allowed to use ideal and randomly
designed components in any case. Please consider if you will buy these filter
components from your vendor to be inserted in your electronics board design, so you
have no choice but to use standard components. Also consider your overall sum of Y-
caps in any of the designs should not go beyond 50 nF, or it will conflict with surge
protection devices. You need to fulfill the quasi-peak, class B limitations only.