LDO by NithinP

Low Drop-out Voltage
Regulators with SKY130PDK

- Nithin P
Gmail: [email protected]
Linkedin: https://www.linkedin.com/in/nithin-purushothama-70664727b/
Acknowledgement:
• I’m grateful to the constant mentoring and support of Manjunath
Kareppagoudar and Soumya Kanta Rana.
• I’m thankful to Ahmed Tawfiq for the help on Ngspice and Xschem
software, it simplified much of my work .
• This project wouldn’t have been possible without all the help I got.
Linear Regulators
• Regulations is achieved by dropping voltage

• Switches are in saturation region.
• Higher losses and low efficiency when dropout is high.
• We select linear regulators when there is a need of small voltage
drop.
• Efficiency is inversely proportional to Voltage drop.
• LDO have less noise , so they are preferred for RF sensors and others.
Important Concepts:
• Line transient and Load transient.
• Concept of negative feedback and why is it
necessary ???
• Second order system.
• Why pole splitting is required???
• Why do we need a phase margin of 60degree Line transient
or greater???
• How to stabilize a system ???
• How to analyze the stability ??
• How to get poles and decide which is
significant and which is not (dominant and
non dominant poles) ??? Load transient
• Types of Compensation employed.
Specifications:
Credits: Soumya Kanta rana, Analog Engineer (Texas Instruments)

Error Amplifier
• Here I’ve used a simple differential amplifier
because If we use a single stage Error
Amplifier, We will handle less poles as a
whole and the design will be easy for us.
• The design of the Error amplifier must be
robust and good so that the regulated output
voltage doesn’t deviate more than 5% of the
specified Vreg.
• Should provide a good gain and have a good
PSRR.
Design
• This is a linear regulator so all the Mosfets operate in saturation region.
Design of Error Amplifier:
• The Aspect ratio of Differential Pair:
• gm1 is the one that contributes to the gain and bandwidth of the error amplifier so
• gm1,2 = 2pi(GBW*CL)
• The Aspect ratio of the Current Mirror:

• Before finding the W/L3,4 we need to find the Vt max of current mirrors and Vtnmax , Vtnmin of Differential
pairs
• For Simplicity I’ve used the mosfet nfet_01v8_lvt and pfet_01v8_lvt whose Vt doesn’t change much unlike
nfet_01v8 and pfet_01v8.
• Vsg3=Vdd-Icmr(+)+Vtn1min
• The aspect ratio of the biasing mosfets:
• Aspect ratio of the Pass Transistor:

• Pass transistors are typically PowerFETs which are large in width.
• From the specifications we know that Vdrop=150mV, so Vsd of Mpass is 150mV, so I targeted an overdrive voltage of
100mV.
• (W/L)pass=2IL/upCoxVov^2
• From this for IL of 40mA I got a W/L ratio of 145454.5
• (W/L)pass = 145455
• Here I used pfet_01v8 because of all the parasitic capacitance the gate cap will be quite large and can have an effect
on the stability and add over miller cap, So I designed the error amp for a CL=50pF, the Mosfet pfet_01v8 offers the
least Cgg (approx 20pF).
Design Concessions I made
• I chose a bias current of 50uA because the specification needed a
settling time of 1us which will be very much affected if we decrease
Slew rate but the quiescent current (IQ) should be less than 50uA.
• Only way to not hamper the settling time was to choose a good Slew-
Rate, the only solution to do that was burn more current as I cannot
change the load cap.
• This has an affect of increasing the quiescent current (IQ) to more
than 50uA, the final result showed a IQ of around 100uA, this cannot
be avoided because of the PDK.
Intuitive Analysis of poles and Zeros
Error Amplifier Schematics
Spec Achieved:
(W/L)1,2 = 207
(W/L)3,4 = 7
(W/L)5,8 = 5
Gain : 37dB
GBW: 7MHz
Ibias: 50uA
Slew Rate: 1V/usec
VDD: 1.5V
ICMR+: 1.2V
ICMR-: 0.9V
CL: 50pF
Gain of the error amplifier
Gain and Phase margin of the error amplifier
LDO Schematics
Load Regulation of the LDO
Line Regulation of the LDO
Line + Load Regulation of the LDO
Temperature sweep of LD
Quiescent current of LDO
PSRR of LDO
Load transient of LDO
Line transient of LDO
Final Results
• Gain: 62dB (hand calculated)
• Pole1(dominant): 4kHz, Pole2(non dominant): 100MHz (hand
calculated)
• GBW: 4.8MHz(hand calculated)
• Phase margin: 82degree (hand calculated)
• |PSRR|: greater than 60dB
• Iq: 104uA
• Efficiency: 89.77%
Things I learnt from this Project
• This project helped me strengthen my concepts on Compensation,
Pole zero Analysis and Stability.
• I learnt how to approach the design for the topology with Mosfets in
saturation.
• Relearnt the concepts of small signal analysis and Transfer functions
• Improved my problem solving approach after many attempts.
• Learnt all the wrong approaches to do the design and learnt the
correct way.
• Improved my concepts of Analog and avoid silly mistakes.
References
[1]. A Low Drop Regulator (LDO) in UMC 180 nm Technology by Mohammed Rizwan
[2]. Low Drop-Out Voltage Regulators: Capacitor-less Architecture Comparison by Joselyn Torres, Mohamed El-
Nozahi, Ahmed Amer, Seenu Gopalraju, Reza Abdullah, Kamran Entesari, and Edgar Sánchez-Sinencio.
[3]. Full On-Chip CMOS Low-Dropout Voltage Regulator Robert J. Milliken, Jose Silva-Martínez
[4]. IC Design of Power Management Circuits (IV) Wing-Hung Ki Integrated Power Electronics Laboratory ECE
Dept., HKUST Clear Water Bay, Hong Kong.
[5]. Design of low-dropout voltage regulator Miroslav Čermák.
[6]. LDO Linear Regulator to Charge Battery by Ahmed tawfiq.
Thank you

LDO by NithinP

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LDO by NithinP

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Low Drop-out Voltage

Regulators with SKY130PDK

• Regulations is achieved by dropping voltage

Credits: Soumya Kanta rana, Analog Engineer (Texas Instruments)

• The Aspect ratio of the Current Mirror:

• Aspect ratio of the Pass Transistor:

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