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    1.7 Reduced Instruction Set Computer (RISC) : Characteristics of CISC Architecture

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    The document discusses RISC and CISC architectures. RISC uses fewer and simpler instructions that can be executed faster than the complex instructions of CISC architectures. While RISC chips are cheaper and faster, skeptics note that the simpler hardware puts more burden on software. Modern architectures incorporate features of both RISC and CISC designs. A key RISC technique is using overlapped register windows to speed up procedure calls by avoiding saving and restoring register values.

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    1.7 Reduced Instruction Set Computer (RISC) : Characteristics of CISC Architecture

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    omairali18
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    The document discusses RISC and CISC architectures. RISC uses fewer and simpler instructions that can be executed faster than the complex instructions of CISC architectures. While RISC chips are cheaper and faster, skeptics note that the simpler hardware puts more burden on software. Modern architectures incorporate features of both RISC and CISC designs. A key RISC technique is using overlapped register windows to speed up procedure calls by avoiding saving and restoring register values.

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    The document discusses RISC and CISC architectures. RISC uses fewer and simpler instructions that can be executed faster than the complex instructions of CISC architectures. While RISC chips are cheaper and faster, skeptics note that the simpler hardware puts more burden on software. Modern architectures incorporate features of both RISC and CISC designs. A key RISC technique is using overlapped register windows to speed up procedure calls by avoiding saving and restoring register values.

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    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    75 views6 pages

    1.7 Reduced Instruction Set Computer (RISC) : Characteristics of CISC Architecture

    Uploaded by

    omairali18
    The document discusses RISC and CISC architectures. RISC uses fewer and simpler instructions that can be executed faster than the complex instructions of CISC architectures. While RISC chips are cheaper and faster, skeptics note that the simpler hardware puts more burden on software. Modern architectures incorporate features of both RISC and CISC designs. A key RISC technique is using overlapped register windows to speed up procedure calls by avoiding saving and restoring register values.

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    1.

    7 Reduced Instruction Set Computer (RISC)


    Instruction set determines the way that machine language programs are constructed. Early computers had small and simple instruction sets in order to minimize the (expensive) hardware needed for their implementation. Today many computers have instructions that include 100 to 200 instructions variety of data types large number of addressing modes Complex instruction set computer (CISC) has complex hardware and large instruction set: functions from software to hardware. In contrast, reduced instruction set computer (RISC) uses fewer and simpler instructions which can be executed faster within the CPU. RISC chips require fewer transistors (than CISC), which makes them cheaper to design and produce. There is still considerable controversy among experts about the ultimate value of RISC architectures. Its proponents argue that RISC machines are both cheaper and faster, and are therefore the machines of the future. Skeptics note that by making the hardware simpler, RISC architectures put a greater burden on the software. They argue that this is not worth the trouble because conventional microprocessors are becoming increasingly fast and cheap anyway. However, CISC and RISC implementations are becoming more and more alike. Many of today's RISC chips support as many instructions as yesterday's CISC chips. Today's CISC chips use many techniques formerly associated with RISC chips. One reason for the trend to provide a complex instruction set is to simplify the translation from high-level to machine language programs.

    Characteristics of CISC architecture: 1. A large instruction set. 2. Instructions that perform special tasks and are used infrequently. 3. A large variety of addressing modes (5-20 different modes).

    4. Variable-length instruction formats. 5. Instructions that manipulate operands in memory.

    Characteristics of RISC architecture: 1. Relatively few instructions mostly register-to-register operations 2. Relatively few addressing modes (because of 1) 3. Memory access limited to load and store instructions. 4. All operations done within the register of the CPU. 5. Fixed-length, easily decoded instruction format aligned to word boundaries simplifies control logic 6. Single-cycle instruction execution fetch, decode, and execute phases for two to three instructions overlap: pipelining. Memory references may take more clock cycles. 7. Hardwired rather than microprogrammed control (faster).

    Other RISC characteristics


    1. A large number of register useful for storing intermediate results and for optimizing operand references: much faster than memory references. most frequent accessed operands are kept in registers. 2. Use of overlapped register windows to speed-up procedure call and return. 3. Efficient instruction pipeline 4. Compiler support for efficient translation of high-level language programs into machine language programs.

    1.7.1 Overlapped Register Windows


    A characteristic of some RISC processors is their use of overlapped register windows to provide the passing of parameters

    and avoid need for saving and restoring register values: speeds up procedure calls and returns. Each procedure call results in the allocation of a new window consisting of a set of registers current window pointer (CWP) is decremented: corresponds save in Figure 1.10. Each return statement increments the CWP: corresponds restore in Figure 1.10. Windows for adjacent procedures (nested calls) have overlapping registers that are shared to provide the passing of parameters and results. Local register can be used for local variables by using local registers there is no risk of corrupting data of another procedure (e.g. caller). Overlapped registers are used to pass parameters (in) and store results (out). Only one register windows is activated at any given time with a CWP. Each procedure call activates new register window by updating (decrementing) the CWP.

    CW

    CW

    CW

    CW CW

    rest ore
    CW

    sa

    Figure 1.10 Overlapped register windows To summarize: Register windows provide easy access to a large collection of registers and can reduce the need to save registers in memory. If you write a procedure with more parameters than common registers (reserved for input parameters), you will need to use the stack for any parameters beyond the amount of reserved number of registers. If your call sequence gets deeper than number of windows (as it probably will in most recursive procedures), you are again forced to use the stack. In general, the organization of register windows will have the following relationships: Number of global registers = G Number of local registers in each window = L Number of registers common to two windows = C Number of windows = W Number of registers available for each window is calculated as follows: window size = L + 2C + G The total number of registers needed in the processor is Register file = (L + C)W + G

    1.7.2 Berkeley RISC I


    One of the first projects for showing the advantages of RISC architecture (in University of California, Berkeley). 32-bit CPU 32-bit addresses 8-, 16-, or 32-bit data 32-bit instruction format 32 instructions three addressing modes: register, immediate operand, and relative to PC addressing for branch instructions. 138 registers

    10 global and 8 windows of 32 registers. Berkeley RISC I instruction formats are shown in Figure 1 11. And the instruction set are shown in Table 1.10.

    Figure 1.11 Berkeley RISC I instruction formats

    Where: Rd field: selects a destination register for result. Rs field: one of the source registers. S2 field: second source, can specify a register or an immediate operand. Y field: 19-bit relative address. COND field: specify one of the possible branch conditions.

    From Table 1.6, register R0 contains all 0's, so it can be used in any field to specify a zero quantity. Number sign # used in an immediate operands.

    Table 1.10 Instruction set of Berkeley RISC I

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