Full-Scan LBIST with Capture-per-Cycle Hybrid Test Points

Sylwester Milewski*, Nilanjan Mukherjee, Janusz Rajski

Jędrzej Solecki, Jerzy Tyszer*, Justyna Zawada*
*
Mentor Graphics Corporation Poznań University of Technology
Wilsonville, OR 97070, USA 60-965 Poznań, Poland

Abstract more advanced DFT technologies have been proposed.

Noticeably, many logic built-in self-test (LBIST) schemes
This paper presents a novel low-area scan-based logic employ scan as their operational baseline to achieve high
built-in self-test (LBIST) scheme that addresses stringent quality test while using a limited volume of test data. Usu-
test requirements of certain application domains such as ally, these solutions comprise a pseudorandom test pattern
the fast-growing automotive electronics market. These generator (PRPG) feeding scan chains and a multiple-input
requirements, largely driven by safety standards, are met signature register (MISR) compacting shifted-out respons-
by significantly reducing test application time while pre- es. The same rules apply to test data compression where
serving the high fault coverage of conventional BIST PRPG is typically replaced with an on-chip test data de-
schemes. Alternatively, one may consider applying a much compressor.
larger number of vectors within the same time interval.
Although the new scheme may resemble traditional BIST Drawbacks of scan-based testing are mainly related to the
logic, it is a combination of pseudorandom test patterns fact that all scan chains are filled with a test pattern before
delivered in a test-per-clock fashion through conventional it is applied. As a result, the vast majority of test time is
scan chains and per-cycle-driven hybrid test points that spent on just shifting test data. Consider a design with 100-
creates this new synergistic LBIST paradigm. The hybrid cell long scan chains. Applying 10,000 double-capture test
observation points, inserted at the most suitable locations, patterns will require 1,000,000 shift cycles and 20,000
capture faulty effects every shift cycle into dedicated flip- capture cycles. Thus, as low as 1.96% of cycles are actual-
flops that form separate scan chains. Their content is ly spent on testing. In terms of test time, this result would
gradually shifted into a compactor, which is shared with be visibly worse, as the scan shift frequency is usually
the remaining scan chains that still deliver test responses much lower than that of a capture (functional) mode. In
captured once the entire test pattern has been shifted-in. logic BIST, the test time efficiency could be even lower.
Experimental results obtained for industrial designs illus- With 100,000 single-capture test patterns, 10,000,000
trate feasibility of the proposed BIST scheme in terms of cycles are needed for scan shifting, while only 100,000
test time, test coverage, and area overhead, and they are cycles are deployed to capture test responses. Hence, 99%
reported herein. of test time is spent on scan shifting.
To overcome some of the issues recalled earlier, and, in
1. Introduction particular, to utilize the test application time in a more
efficient manner, a tri-modal scan (TMS) has been pro-
Since its advent nearly five decades ago, scan has become
posed recently in [16]. TMS differs from the conventional
one of the most influential and industry-proven structured
scan in having scan cells partitioned dynamically to work
design for test (DFT) technology. It allows a direct access
in three modes acting as either mission memory elements,
to memory elements of a circuit under test (CUT) by reus-
sources of test stimuli, or test response compactors. In the
ing them to form shift registers in a test mode. The opera-
last two cases, scan cells form the actual scan chains. As a
tive paradigm is then to employ ATE or another source of
result, TMS neither shifts all scan chains nor it captures
test patterns to feed serial inputs of the scan chains, with
test responses in all of them. Scan chains in the stimuli
the same ATE or a test response compactor capturing test
mode resemble the conventional scan chains in the shift
responses that leave the scan chains through their serial
mode. However, test data is applied to the CUT every
outputs. As all scan cells are typically controlled by a sin-
clock cycle. Moreover, scan chains in the stimuli mode do
gle scan enable signal, scan chains remain functionally
not capture test responses. These are scan chains in the
indistinguishable, i.e., they all either shift data in and out
compaction mode that accumulate test responses every
or capture test results. The resultant high controllability
clock cycle. At the same time, a single bit (per chain) of
and observability of internal nodes made it possible to
the resultant signature is always shifted-out. Scan chains in
automatically generate high quality tests and to debug the
the compaction mode can also drive the CUT. The remain-
first silicon. Moreover, simple architecture of scan chains
ing scan cells are kept in the mission mode. Test results
enables their automated stitching and insertion supported
propagating through the combinational part of the circuit
by electronic design automation tools.
can also reach the scan cells in the mission mode. These
With the scan-based test paradigm firmly in place, several responses further circulate within the circuit and eventually

Paper 10.3 INTERNATIONAL TEST CONFERENCE 1

978-1-5386-3413-4/17/$31.00 ©2017 IEEE
reach the observation scan chains during the subsequent As can be observed, LBIST keeps evolving to meet the
clock cycles. Since test patterns are applied every clock demands of new technologies and to become a valuable
cycle, the scheme is time-efficient and allows one – given test alternative, for example, in the fast-growing automo-
target defect coverage – to complete a test within much tive electronics market. ICs for this market must adhere to
shorter durations than done by conventional schemes. stringent requirements for quality and reliability, which are
Alternatively, it can reach higher defect coverage for oth- largely driven by safety standards such as ISO 26262 and
erwise similar test application conditions. TMS works with Automotive Safety Integrity Level (ASIL) targets. Clearly,
customized methods used to automate instantiation and ISO 26262 compliance requires the adoption of more ad-
application of its architecture, including scan stitching, vanced test solutions. In particular, for an IC to achieve
selection of scan configurations, test generation, and fault necessary levels of reliability, LBIST capabilities should
simulation. respond to challenges posed by automotive parts and to
support a number of in-field test requirements including an
Certain principles of TMS have been subsequently adapted
ability to run periodic tests during functional operations,
by the scheme of [25]. It employs an additional set of
very short test times due to strict limits on power-up or idle
shadow registers to capture test results during scan shift.
times, high test coverage, and others.
The shadow flip-flops are directly associated with scan
cells capable of observing the largest number of faults This paper proposes a new scan-based LBIST scheme that
during successive shift cycles. The same flip-flops form a aims at achieving high quality test offered by a conven-
compactor, e.g., a MISR that captures and accumulates tional LBIST in much shorter time. This is fulfilled by
results in a test-per-clock fashion. Although the scheme applying test patterns every clock cycle, thus increasing
can enhance fortuitous fault detection, it may also signifi- the percentage of test time used for actual testing as op-
cantly inflate the circuit sequential silicon real estate (even posed to the shift activity. Contrary, however, to TMS and
above 30% of the circuit’s original scan cell count). other schemes using similar principles, the new LBIST
works synergistically with hybrid test points [15]. In par-
Introduction of TMS has been preceded by many test-per-
ticular, observation hybrid test points, inserted at the most
clock schemes. One of the first BIST schemes of this kind
suitable locations, capture faulty effects every shift cycle
was designed for circuits with independent combinational
into dedicated flip-flops that form a separate scan chain (or
blocks whose input and output registers are converted into
scan chains). The content of these scan chains is gradually
built-in logic block observers (BILBO) [12] working either
shifted into a compactor, which is shared with the remain-
as test generators or compactors. Another scheme – a cir-
ing scan chains that still deliver test responses captured
cular self-test path (CSTP) [13] – forms a feedback shift
once the entire test pattern has been shifted-in. As properly
register by connecting selected circuit state elements. Con-
selected observation points allow one to keep the number
trary to the scan chain, the circular register produces test
of associated flip-flops as a small fraction of the number of
stimuli and compacts test responses every clock cycle.
scan cells (typically below 2%), the proposed scheme has a
Unfortunately, CSTP requires a time-consuming fault
low area overhead, is routing friendly, and allows flexible
grading. Moreover, the fault coverage tends to level off in
trade-offs between test time, test coverage, and area over-
a manner similar to other BIST schemes. Some works
head.
address this issue by applying state skipping logic, using
an appropriate selection of the CSTP initial state [7], or
choosing suitable PRPG seeds [11]. A technique similar to 2. Test points
CSTP was also proposed in [23], with additional features A successful application of the approach proposed in this
to handle deterministic test patterns. Furthermore, the E- paper depends on the ability to find complementary control
BIST architecture [22], by building on the scheme of [4], and observation points maximizing test coverage by re-
converts scan chains into MISRs using additional gates cording test results every scan shift clock cycle. In its early
associated with all scan cells. Every clock cycle, these days, LBIST used test points to improve the probability of
modified scan chains provide test stimuli and compact test detecting random-resistant faults. Test point insertion (TPI)
responses. algorithms were selecting hard-to-control and hard-to-
observe sites to subsequently insert control and observation
Unlike logic BIST, an approach of [10] applies determinis-
points. When active, a control point forced a circuit’s node
tic test-per-scan and weighted random test-per-clock pat-
to a specific logic value, whereas an observation point acted
terns. However, scan chains have to be modified to enable
as a pseudo-primary output. Identification of the most ef-
their parallel load and PRPG capabilities. Deterministic
fective test points while minimizing their total number and
data are applied in a test-per-clock manner in [18] while
a possible impact on a design performance was by no
primary outputs and scan cell outputs are directly observa-
means a complex process. Thus, numerous approximate
ble. The technique of [19] can be placed somewhere be-
techniques have been proposed to find the most suitable
tween the test-per-clock and the test-per-scan schemes. It
locations for control and observation points. These TPI
uses a part of the former test response to form a subsequent
algorithms are guided by exact fault simulation [9], approx-
test pattern. A test-per-clock access to a scan chain can
imate testability measures [17], [24], cost functions [8],
also be accomplished by making scan cells randomly ad-
gradient-based metrics [21], or signal correlation [6].
dressable [2], [3].
Paper 10.3 INTERNATIONAL TEST CONFERENCE 2
Although testability-driven TPI techniques may occasional-
ly decrease deterministic pattern counts [14], their overall
performance remains here unpredictable. Consequently, a
different TPI paradigm was introduced in [1] to reduce the
number of deterministic scan test patterns in a much more
consistent manner. Contrary to LBIST test points, the new
approach aims at identifying and resolving conflicts be-
tween ATPG-assigned internal signals through insertion of
conflict-aware test points. This ability allows one to in-
crease the number of faults detected by a single pattern, and
thus to reduce both the number of deterministic tests and
test data volume in a test compression environment.
Another class of test points [15] has been proposed recently
to enhance performance of a hybrid EDT/LBIST technolo- Figure 1 Test architecture
gy. This novel TPI technique simultaneously reduces de-
terministic test pattern counts and increases detectability of ed with data provided by another scan cell, thus incorpo-
random-resistant faults by means of the same minimal set rating shift and capture functionality within a single clock
of test points. A key feature of the hybrid test points is the cycle. Optionally, a clock gating (CG) circuitry may be
ability to resolve cases where demands of internal nets for a used to control whether scan chains operating in the com-
given logic value come up against very low likelihood of paction mode are actually active after asserting the corre-
getting this value with pseudorandom tests. sponding enable (CGEN) signal.

The method presented in this work deploys hybrid control Initially, the first pseudorandom test pattern is shifted-in,
points of [15] to facilitate propagation of faults towards and all scan chains (both the regular ones and those work-
test-per-clock-driven observation points inserted at loca- ing with observation points) capture a test response. Next,
tions where they can cast significant groups of faults whose when the response is shifted-out with the subsequent test
effects propagate along these nodes. The next section de- pattern filling gradually both the regular scan chains and
scribes the overall test architecture with the new observa- the control point drivers, the content of these scan cells
tion test points. In the subsequent parts of the paper, we becomes stimuli feeding the circuit every clock cycle. It
will demonstrate that this scheme allows one to achieve a allows the observation-point-scan-chains to capture and to
high quality test, at least matching that of conventional accumulate test responses every clock cycle, as well. Fur-
LBIST schemes, but in a visibly shorter test application thermore, a single bit of the resultant response enters a
time. MISR in a per-cycle regime. It is worth noting that the
scan chains operating in the compaction mode do not drive
3. Test architecture any CUT logic, i.e., the test responses captured in these
scan chains are not fed back to the design, thus greatly
Fig. 1 illustrates a basic architecture of the proposed BIST simplifying fault simulation. Clearly, when the regular
scheme. The vast majority of scan cells form conventional scan chains are fully loaded with a new test pattern, the
scan chains (gray blocks in Fig. 1), i.e., they operate either regular scan chains as well as the compaction chains cap-
in the shift mode (with the asserted scan enable signal) or ture a test response in a conventional manner. As a result,
in the capture mode. Since control test points are used to the circuit is tested in accordance with the test-per-clock
set internal lines to specific logic values, all flip-flops (red paradigm, while preserving all benefits of the test-per-shift
parts in Fig. 1) associated with these points work only in approach intact.
the shift mode and are arranged in two different ways:
either dedicated scan chains host exclusively drivers of
control points (such as the top chain in Fig. 1) or scan cells
driving control points are interspersed among other (regu-
lar) scan cells (the second chain in the figure).
Scan cells serving the observation points (the green part in
Fig. 1) are arranged into separate (independent) scan
chains that operate in a compaction mode, i.e., they accu-
mulate test responses using XOR gates placed in the front
of their successive cells. A scan cell working for the ob-
servation point is shown in Fig. 2. The global test point
enable (TPE) signal is employed to activate observation
points in the test mode, and to disable them in the mission
mode. Test results received from CUT (input D) are XOR- Figure 2 New scan cell for observation point

Paper 10.3 INTERNATIONAL TEST CONFERENCE 3

Although compaction of test responses is the primary op-
eration mode of the observation-point-scan-chains, their
cells can be modified in order to run scan chain integrity
test and to help in silicon debug and diagnosis by follow-
ing the rules presented in [16].

4. Test point sites

In order to identify the most suitable test point locations,
we look for internal lines with low observability, which are
nevertheless the most preferable propagation paths for a
significant number of faults. Moreover, we deploy control
points to improve fault propagation towards test-per-clock-
driven observation points, and thus increase their detection
probability. For the sake of simplicity, we assume that the
term “faults” refers both to stuck-at-0 and stuck-at-1 faults. Figure 3 Fault propagation

The number of faults propagating through a net is a key

factor necessary to introduce the new observation points,
4.1 Observation points
and to demonstrate how they work synergistically with the In many circuits, there are faults, which are difficult to
corresponding hybrid control points. To model how many detect by means of pseudorandom patterns due to severe
faults can potentially reach every single line in a circuit, propagation conditions. In those cases, observation points
we use weighted testability measures introduced in [15]. In can be added to shorten propagation paths. In our scheme,
particular, they quantify a given stem’s impact on lines it however, the observation points’ functionality is enriched
drives and lines it is driven by in terms of controllability by the ability to capture as many faults as possible every
and observability. As several stems may affect a single line shift clock cycle.
x, the testability responsiveness to changes occurring at
those stems must be also computed [15]. The resultant Note that the conventional testability measures grant all
controllability and observability of line x are eventually outputs (and pseudo-outputs, e.g., regular scan cells) full
chosen as maxima over metrics obtained for all stems af- observability all the time. However, in our test point analy-
fecting x. It is worth noting that the weighted metrics are sis, the observability measures must be appropriately ad-
more accurate than conventional COP-based [5] analysis in justed to represent the fact that observation points capture
handling reconvergent fan-outs and in estimating fault faulty effects into dedicated flip-flops every shift cycle,
detection likelihood. whereas regular scan cells collect test responses only during
a single (or double) capture cycles that occur at the end of
Having determined testability measures, a circuit is pro- the entire scan shift-in phase. Hence, we modify observabil-
cessed in a gate-level order. Starting from the first level, ity metrics so that every single observation point x gets Ox
the number of faults occurring at the output of each gate is = 1.0 during all shift and capture cycles, while observabili-
computed as a sum of faults reaching its inputs. If a stem ties for the remaining scan cells are set to 1/n, where n is
with fan-out branches is encountered, faults are distributed the size of the longest scan chain.
to its branches proportionally to their observabilities. For
instance, consider a circuit of Fig. 3. Let Pa and Pd be 1- To identify low observability internal lines propagating, at
controllabilites that reflect difficulty of setting lines a and the same time, prominent number of faults, we propose to
d to 1, respectively. Let Pa = Pd = 0.1. Lines e and f, as compute observation performance Wx for line x as follows:
primary outputs, are fully observable, i.e., Oe = Of = 1.0. Wx = – Dx × log10 Ox (2)
The observabilities of branches b and c are Ob = Oe × (1 –
Pa) = 0.9 and Oc = Of × Pd = 0.1. Note that the line observ- where Dx is the number of faults propagating through net x,
ability is the probability of sensitizing a fault propagation and Ox represents line x observability. Since Ox ≤ 1, the
path from that particular line to any output. The size of larger the value of Dx, the more attractive observation
arrow Ds represents faults propagating through stem s. point line x can make. For example, if Dx = 1000 and Ox =
Clearly, line b has much better observability than line c, 10-4, then Wx = 4000. However, if the number of faults is
thus the number of faults propagating through branch b is relatively small, say Dx = 10, the observation performance
greater than faults reaching input c of gate G2, accordingly. drops to Wx = 40. The former case clearly indicates that an
In general, the number of faults propagating from stem s observation point at x is highly desired and is expected to
through branch x is determined as follows: facilitate detection of a significant number of faults. It is
also worth noting that observabilities of regular scan cells
Dx = a × Ds (1) (recall that all of them are set to 1/n) discourage the TPI
where a is a distribution factor computed as a ratio of line procedure from assuming that conventional scan chains
x observability and the sum of all branches observabilities. may suffice as effective observation points. Instead, TPI
tries to identify bottlenecks in a design, where fault propa-

Paper 10.3 INTERNATIONAL TEST CONFERENCE 4

gation is systematically hampered and can be cured by propagate faults D1 and D3, x must be set to 1 at least D1 +
adding observation points of the new class. D3 times. Furthermore, to enable propagation of faults D2
through gate G3, one needs to set y to 1 for each fault of D2.
Since a new observation point may affect observabilities of
As a result, in order to propagate faults D1, D2, and D3,
other nets, and thus it may change fault propagation paths,
stem s must be set to 1 at least D1 + D2 + D3 times. Note that
the remaining testability metrics need to be updated. Hence,
the same analysis may be done in a contrapositive fashion.
once an observation point is inserted, we update the observ-
Indeed, if one applies 0 at the output of gate G1, then prop-
abilities of other nets as well as quantities of faults propa-
agation of faults D1 and D3 is blocked (they cannot be ob-
gating through lines within a circuit area affected by the
served at the output of gates G2 and G4, respectively).
observation point as follows:
Moreover, faults D2 are also blocked since 0 is a controlling
1) Starting from the location of the newly inserted obser- value for gate G3.
vation point, move backward towards inputs and up-
As can be seen in Fig. 4, stem s must be set to 1 in a rela-
date observability of each traversed line marking all
tively large number of cases. However, getting 1 at the
visited stems, until no changes can be made.
output of G1 is very unlikely (1 out of 232) random event.
2) Given all visited stems, pick the lowest-level stem s. Fortunately, an OR-type control point can be placed on the
output of G1 to resolve this conflict. As a result, chances of
3) Beginning with stem s and by using formula (1), move
propagating faults D1, D2, and D3 forward are significantly
forward towards outputs in a gate-level order updating
increased. A comprehensive analysis of such hybrid con-
fault propagation data until no further changes can be
flicts and methods to resolve them through insertion of
made.
hybrid control points can be found in [15].
4.2 Control points
5. Test point insertion
In our method, control points are primarily used to facilitate
Inserting successive test points requires a circuit to be
fault propagation towards scan chains operating in the
processed in a gate-level order in two major steps. First,
compaction mode. Consider the circuit of Fig. 4. Let the
we compute testability measures for each net and prepare
black arrows denote faults propagating through the lines the
two lists of the most suitable locations for control and
arrows are placed next to, and let D1, D2, and D3 represent
observation points, respectively. To begin with, controlla-
bilites and observabilities for each line are determined, as
shown in [15]. Next, starting from the primary inputs,
faults are propagated forward, and subsequently perfor-
mance of a candidate observation point is determined for
each net in accordance with formula (2). The last iteration
of the first step computes requirements for 0s and 1s for
each internal line (see Section 4.2) by traversing the entire
circuit in a reversed gate-level order. At the same time, the
hybrid conflicts for control points are computed. As a
result, the first part of this procedure yields two sorted lists
(in a descending order) representing the best locations for
control and observation points.
Typically, the number of test points and its breakdown into
control and observation points is a design-dependent fac-
tor. Thus, to guide test point insertion, we propose to
monitor the resultant test coverage, as we keep adding new
control and observation points into a design. Let Tx be fault
x detection probability defined as follows:
Tx/0 = Px · Ox (3)
Tx/1 = (1 – Px) · Ox (4)
Figure 4 Hybrid control points
where x/0 and x/1 are line x stuck-at-0 and stuck-at-1 faults.
their quantities – further referred to as faults Di. To propa- The values of Px and (1 – Px) represent a degree of difficul-
gate faults D3 through OR gate G4, input z must be set to 0 ty in setting line x to 1 and 0, respectively. Consequently,
at least D3 times. The logic value of 0 at the output of gate test coverage for T test patterns can be estimated as the
G2 implies, inter alia, x = 1, and since it is a non-controlling average over the entire list of testable faults by using the
value for the NAND gate, faults D1 reaching gate G2 can probabilities of detecting successive faults by at least one
propagate towards scan cells or primary outputs. Clearly, to out of T test patterns.

Paper 10.3 INTERNATIONAL TEST CONFERENCE 5

In the second phase of this TPI process, we repeatedly TABLE I
DESIGN CHARACTERISTICS
remove the top of the control point list, insert the corre-
sponding CP into a design, and determine its impact on test Scan Scan Longest
Gates TC [%] Faults
coverage. Next, we withdraw the newly inserted control cells chains chain
point, restore previous state of a circuit and perform exact- D1 453K 45K 226 200 81.07 1.6M
ly the same actions as before, but now we consider inser-
D2 1.21M 72K 382 190 78.53 4.5M
tion of an observation point from the current top of obser-
vation point list. The decision which test point should be D3 1.19M 85K 427 200 86.54 4.1M
actually added into a design is made based on the resultant D4 2.62M 160K 1,015 158 90.34 9.2M
test coverage improvements achieved in each case. The D5 1.62M 144K 700 207 88.83 4.3M
rejected test point returns to its list. Note that after insert- D6 372K 31K 54 647 73.33 1.1M
ing every control point, all testability measures and other
metrics must be updated, accordingly [15]. In the case of
ble detection of faults during scan-shift cycles. As a result,
observation points, this process is executed as described in
observation points allow one to capture faulty effects every
Section 4.1. The TPI procedure iterates until the number of
shift cycle, while control points facilitate fault propagation
inserted test points matches the desired and user-defined
towards additional scan chains operating in the compaction
number of test points that can be added into the design.
mode (observation point cells). This is accomplished by
assigning all regular scan cells the observability value of
6. Experimental results 1/n (where n is the size of the longest scan chain), whereas
Experiments were performed on six industrial designs that the remaining observation sites have the observability set to
are currently in a high-volume production. Relevant infor- 1.0. As in the previous case, the target pattern count com-
mation about the designs, including the number of gates, prises 10K base pseudorandom patterns. However, addi-
the number of scan cells, the number of scan chains, the tional (intermediate) test patterns are also taken into ac-
size of the longest scan chain, a baseline (no test points) count. Let Ti and Ti+1 be two subsequent base test patterns.
test coverage after applying 10K pseudorandom test pat- Their intermediate patterns consist of capture values corre-
terns, and the number of testable faults is reported in Table sponding to Ti and PRPG-produced values that correspond
I. To evaluate the performance of the proposed fast LBIST to Ti+1. Clearly, the first intermediate vector of a given
scheme, we compare its test coverage with test coverage bundle is always equal to a test response obtained for Ti,
provided by a conventional LBIST. while the remaining ones are gradually generated on the
In preparations for the experiments, we had generated two fly as a result of scanning-out a test response of Ti and
groups of hybrid test points for each design. These test scanning-in a new pattern Ti+1 at the same time. This pro-
points were inserted by employing the algorithm of Sec- cess repeats until a predetermined number of R pseudoran-
tion 5. The first group is designated for designs imple- dom base test patterns are generated. As can be easily
menting the conventional BIST environment, further re- verified, the total number P of patterns applied to the CUT
ferred to as a reference case, where all regular scan cells by the new LBIST scheme is given by
and additional observation points are fully observable once P = R + (R – 1) × n (5)
a test pattern is entirely shifted into internal scan chains, where (R – 1) × n is the number of intermediate test patterns
and a circuit becomes ready to capture a test response. We applied when the regular scan chains are shifting, and n, as
apply 10K pseudorandom test patterns in this case. earlier, is the size of the longest scan chain.
The second group of test points is used, for each design, in Table II lists the experimental results obtained for stuck-at
conjunction with the new BIST framework. Recall that faults. The first two columns report the breakdown of test
these test points not only increase the detection probability points (control points – CPs and observation points – OPs)
of random-resistant faults but also, more importantly, ena- obtained by deploying the algorithm of Section 5. Recall

TABLE II
EXPERIMENTAL RESULTS FOR STUCK- AT FAULTS

1,000 patterns 2,000 patterns 4,000 patterns 10,000 patterns

CPs OPs
TC [%] DTC [%] TC [%] DTC [%] TC [%] DTC [%] TC [%] DTC [%]
D1 320 580 91.22 2.15 92.48 1.4 93.29 0.9 93.99 0.52
D2 700 800 85.14 2.98 87.74 2.25 89.44 1.89 90.88 1.5
D3 720 980 89.34 1.69 90.65 1.8 91.39 0.89 92.05 0.55
D4 1,000 2,000 93.06 1.29 95.12 0.73 96.34 0.36 97.21 0.09
D5 1,225 1,275 93.41 1.48 94.62 0.89 95.35 0.56 95.93 0.35
D6 1,019 780 81.13 10.08 85.09 8.26 88.24 6.99 91.54 5.26

Paper 10.3 INTERNATIONAL TEST CONFERENCE 6

 number of test points is 2% of the entire scan cell popula-
tion except design D6 where this fraction is equal to 5.7%.
The next columns of Table II give test coverage TC ob-
tained in the reference case, and then test coverage in-
crease DTC is reported for the new LBIST scheme after
applying 1K, 2K, 4K, and 10K base pseudorandom pat-
terns. It is worth observing that given, for example, 2K
base pseudorandom patterns, the new method is using
2000 + 1999 n test vectors (see formula 5). For scan of a
moderate size, say n = 100, the total number of actually
applied patterns amounts then to almost 202K.
Fig. 5 demonstrates how many test patterns it takes for
both the conventional LBIST and the proposed scheme to
reach target 90% test coverage – an industry-wide accept-
Figure 5 Patterns needed to reach 90% test coverage
ed automotive electronics in-field-test-quality standard. As
can be seen, superiority of the new solution is clearly pro-
that the very same number of control and observation nounced. The new LBIST outperforms the traditional ap-
points is used for every reference test case. The actual proach, on the average, by a factor of 3.6. In other words,

Figure 6 Test coverage as a function of test pattern count

Paper 10.3 INTERNATIONAL TEST CONFERENCE 7

the new LBIST is capable of providing 90% test coverage tomotive electronics and other safety critical systems.
more than 3.5 times faster than its state-of-the-art conven-
The presented BIST scheme may help in improving quality
tional counterpart. With the transition to fully computer-
of fault diagnosis, as the compaction scan chains are not
ized vehicles speeding-up and breaking into the main-
allowed to propagate the erroneous responses back to the
stream automobile market, the above result is definitely
circuit. Thus, the existing partial-scan-based diagnostic
worth noting.
techniques turn out to be applicable. Moreover, an obser-
The charts of Fig. 6 provide a much more comprehensive vation scan cell puts an XOR gate on the scan path only in
illustration of test coverage as a function of test application the dedicated chains. Hence, patterns can be shifted intact
time. As can be seen, in all examined test cases, the pro- allowing one to run chain diagnostic tests in a conventional
posed method (the red curve) reaches a given test coverage manner.
level in much shorter test time than the conventional
LBIST (the blue curve) does. Furthermore, in the case of
8. Acknowledgement
designs D1, D2, D3, and D6 test coverage provided by the
new scheme remains noticeably higher (after 10K base The work of S. Milewski, J. Tyszer, and J. Zawada was
pseudorandom patterns) than that of the reference case. supported in part by the Polish Ministry of Science and
Higher Education under Grant DS-811/17.
One final note regarding the above experiments is needed
here. Whenever a fault propagates to scan chains operating
in the compaction mode, it is temporarily marked as de- 9. References
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Paper 10.3 INTERNATIONAL TEST CONFERENCE 9