CH 4 Lecture 3f

Chapter 4 01 Introduction
Sequential Circuit
02
Design Multivibrators
“Tell me and I forget, teach me and I may

remember, involve me and I understand” 03 Latch, Flip-Flop,
(Benjamin Franklin) 04 and Timers
Register and
Counters
View slide
Register and Counters Counters
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▪ Moreover, flip-flops can be linked to one another to carry out counting tasks.
• The number of flip-flops used and The way in flip-flops connected
✓ determine the number of states (called the modulus) and also
✓ the specific sequence of states that the counter goes through during each complete cycle.
▪ A counter is an example of a state machine;
• Where a state machine is a sequential circuit with a finite number of states that happen in a
predetermined order. Two basic types of state machines are the
1. Moore (is one where the outputs depend only on the internal present state. )
2. Mealy (is one where the outputs depend on both the internal present state and on the inputs.)
By Abdulaziz J. Sequential Circuit Design 6/1/2024

3
FIGURE 4.3.1 Two types of sequential logic.

▪ In the Moore machine, the combinational logic is a gate array with outputs that
▪ For the Mealy machine, the present state affects
determine the next state of the flip-flops in the memory.
the outputs, just as in the Moore machine; but in
▪ There may or may not be inputs to the combinational logic.
addition, the inputs also affect the outputs.
▪ There may also be output combinational logic, such as a decoder.
▪ The outputs come directly from the
▪ If there is an input(s), it does not affect the outputs because they always
combinational logic and not the memory.
correspond to and are dependent only on the present state of the memory.
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Counters are classified into two broad categories according to the way they are clocked:
▪ Each flip-flop is triggered by the output of the previous flip- ▪ All flip-flops are triggered by the same clock signal,
flop, allowing for sequential operation without the need for ensuring that the outputs change simultaneously.
a common clock signal. ▪ Typically require more complex circuitry due to the
▪ Asynchronous counters are simpler in design as they rely need for a synchronized clock signal and additional
on the propagation of signals through individual flip-flops control logic to coordinate the flip-flop outputs.
without the need for synchronization, resulting in
potentially lower complexity and faster propagation times.
▪ It is also called Ripple counters

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▪ The term asynchronous refers to events that do not have a fixed time relationship with
each other and, generally, do not occur at the same time.
▪ An asynchronous counter is one in which the flip-flops (FF) within the counter do not change states at
exactly the same time because they do not have a common clock pulse.
▪ For illustration we will examine
1. 2-bit asynchronous binary counter

4. Asynchronous decade counter

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Example-1 Create a 2-bit asynchronous counter, then use a truth table and a time
diagram to display the sequence. • Notice that the clock (CLK) is applied to the
clock input (C) of only the first flip-flop, FF0,
Solution
which is always the least significant bit (LSB).
Figure 4.3.2 shows a 2-bit counter connected for asynchronous operation.
• The second flip-flop, FF1, is triggered by the
Q0’ output of FF0.
• FF0 changes state at the positive-going edge of
each clock pulse, but FF1 changes only when
triggered by a positive-going transition of the
a) Using D flip flop b) Using J-K Flip-flop Q0’ output of FF0. Therefore, the two flip-flops
are never simultaneously triggered, so the
FIGURE 4.3.2 A 2-bit asynchronous binary counter.
counter operation is asynchronous.
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1. 2-bit asynchronous binary counter Solution

a) Let’s examine the basic operation of the asynchronous counter of Figure 4.3.2a
• By applying four clock pulses to FF0 and observing the Q output of each flip-flop. Figure 4.3.3
illustrates the changes in the state of the flip-flop outputs in response to the clock pulses.
• Both flip-flops are connected for toggle operation (D = Q’) and are assumed to be initially
RESET (Q LOW). The positive-going edge of CLK1 (clock pulse 1) causes the Q0 output of FF0
to go HIGH, as shown in Figure 4.3.3. At the same time the Q0’ output goes LOW, but it has
no effect on FF1 because a positive-going transition must occur to trigger the flip-flop. After
Figure 4.3.3Timing diagram for the counter of Figure 3.3.2. the leading edge of CLK1, Q0 = 1 and Q1 = 0.
• For simplicity, the transitions of Q0 , Q1 , and the clock pulses are shown as simultaneous even though this is an asynchronous counter. There is, of
course, some small delay between the CLK and the Q0 transition and between the Q0 transition and the Q1 transition.
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Note in Figure 4.3.3 that the 2-bit counter exhibits four different states, as you would
expect with two flip-flops (2^2 = 4). Also, notice that
• if Q0 represents the least significant bit (LSB)
• Q1 represents the most significant bit (MSB), the sequence of counter states represents a sequence
of binary numbers as listed in Table 4.3.1.
TABLE 4.3.1 Binary state sequence for the counter in Figure 4.3.2. • Since it goes through a binary sequence, the counter in Figure 4.3.2 is a binary
counter. It actually counts the number of clock pulses up to three, and on the
fourth pulse it recycles to its original state (Q0 = 0, Q1 = 0).
• The term recycle is commonly applied to counter operation; it refers to the
transition of the counter from its final state back to its original state.
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Example-1 Create a 3-bit asynchronous counter, then use a truth table and a time
diagram to display the sequence.
Solution
Figure 4.3.4 shows a 3-bit counter connected for asynchronous operation.
• The basic operation is the same as that of the 2-bitcounter except that the 3-bit
counter has eight states, due to its three flip-flops. A timing diagram is shown in
Figure 4.3.5(b) for eight clock pulses.
• Notice that the counter progresses through a binary count of zero through seven
and then recycles to the zero state. This counter can be easily expanded for
FIGURE 4.3.4 A 2-bit asynchronous binary counter. higher count, by connecting additional toggle flip-flops.

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Figure 4.3.5 shows a 3-bit counter timing diagram for one cycle.

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Propagation Delay Asynchronous counters are commonly referred to as ripple counters

for the following reason:
▪ The effect of the input clock pulse is first “felt” by FF0. This effect cannot get to FF1 immediately because of the propagation
delay through FF0. Then there is the propagation delay through FF1 before FF2 can be triggered. Thus, the effect of an input
clock pulse “ripples” through the counter, taking some time, due to propagation delays, to reach the last flip-flop.
▪ To illustrate, notice that all three flip-flops in the
counter of Figure 4.3.4 change state on the leading
edge of CLK4. This ripple clocking effect is shown in
Figure 4.3.6 for the first four clock pulses, with the
propagation delays indicated. Figure 4.3.6Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.
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Thus, it takes three propagation delay times for the effect of the clock pulse, CLK4,
Propagation Delay
to ripple through the counter and change Q2 from LOW to HIGH.
The maximum cumulative delay in a counter must be less than the period of the clock waveform.
▪ This cumulative delay of an asynchronous counter is a major disadvantage in many applications

because it limits the rate at which the counter can be clocked and creates decoding problems.
EXAMPLE 1 A 4-bit asynchronous binary counter is shown in Figure 4.3.7(a). Each D flip-flop is negative edge-triggered
and has a propagation delay for 10 nanoseconds (ns). Develop a timing diagram showing the Q output of each flip-flop, and
determine the total propagation delay time from the triggering edge of a clock pulse until a corresponding change can occur in
the state of Q3 . Also determine the maximum clock frequency at which the counter can be operated.

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Propagation Delay Solution
Figure 4.3.7(a). Four-bit asynchronous binary counter and its timing diagram.
▪ The timing diagram with delays omitted is as shown in Figure 4.3.7(b). For the total delay time, the
effect of CLK8 or CLK16 must propagate through four flip-flops before Q3 changes, so
𝒕𝒑(𝒕𝒐𝒕) =
𝟒 ∗ 𝟏𝟎 𝒏𝒔 = 𝟒𝟎 𝒏𝒔
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Propagation Delay Solution
1 1
▪ The maximum clock frequency is 𝑓𝑚𝑎𝑥 = = 𝑛𝑠 = 25 𝑀𝐻𝑧
𝑡𝑝 40
𝑡𝑜𝑡
▪ The counter should be operated below this frequency to avoid problems due to the propagation delay.
Related Problem Show the timing diagram if all of the flip-flops in Figure 4.3.7(a) are positive edg
etriggered.

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3. Decade asynchronous binary counter

▪ A counter's modulus is the total number of distinct states it can go through in order to sequence.
• Given n, the number of flip-flops in the counter, the maximum number of states (maximum modulus) that a counter
can have is 𝟐𝒏 .
▪ Counters can be made to have fewer states in their sequence than the maximum of 2𝑛 . A truncated
sequence is the name given to this kind of sequence. Ten, sometimes known as MOD10, is a typical
modulus for counters with shortened sequences. The term "decade counter" refers to counters that have
ten states in their sequence.

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▪ Because the BCD code is produced by the ten-state sequence of a decade counter, a decade counter
having a count sequence of zero (0000) through nine (1001) is a BCD decade counter.
▪ When converting BCD data to a decimal readout for display purposes, this kind of counter can be
helpful. The counter must be forced to recycle before it can reach all of its possible states in order to
produce a shortened sequence. The BCD decade counter, for instance, needs to recycle from the 1001
state back to the 0000 state.
Example: Design decade counter
Solution
▪ A decade counter requires four flip-flops (three flip-flops are insufficient because 23 = 8).

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Solution 3. Decade asynchronous binary counter

▪ Let’s use a 4-bit asynchronous counter One way to make the counter recycle after the count of nine
(1001) is to decode count ten (1010) with a NAND gate and connect the output of the NAND gate to
the clear (CLR)’ inputs of the flip-flops, as shown in Figure 4.3.8(a).
FIGURE 4.3.8 An asynchronously clocked decade counter with asynchronous recycling.

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▪ Notice in Figure 4.3.8(a) that only Q1 and Q3 are connected to the NAND gate inputs. This
arrangement is an example of partial decoding, in which the two unique states (Q1 = 1 and Q3 = 1)
are sufficient to decode the count of ten because none of the other states (zero through nine) have
both Q1 and Q3 HIGH at the same time.
▪ When the counter goes into count ten (1010), the decoding gate output goes LOW and
asynchronously resets all the flip-flops. The resulting timing diagram is shown in Figure 4.3.8(b).

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▪ Notice that there is a glitch on the Q1 waveform. The reason for this glitch is that Q1 must first go
HIGH before the count of ten can be decoded. Not until several nanoseconds after the counter goes to
the count of ten does the output of the decoding gate go LOW (both inputs are HIGH).
▪ Thus, the counter is in the 1010 state for a short time before it is reset to 0000, thus producing the glitch
on Q1 and the resulting glitch on the CLR line that resets the counter. We will see about glitch in
chapter five
▪ Other truncated sequences can be implemented in a similar way, as Example 2 shows.

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EXAMPLE 2 Show how an asynchronous counter with J-K flip-flops can be implemented having a
modulus of twelve with a straight binary sequence from 0000 through 1011.
Solution
▪ Since three flip-flops can produce a maximum of eight states, four flip-flops are required to produce
any modulus greater than eight but less than or equal to sixteen.
▪ When the counter gets to its last state, 1011, it must recycle
back to 0000 rather than going to its normal next state of
1100, as illustrated in the following sequence chart:

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▪ Observe that Q0 and Q1 both go to 0 anyway, but Q2 and Q3 must be forced to 0 on the twelfth clock
pulse. Figure 4.3.9(a) shows the modulus-12 counter.
FIGURE 4.3.9 Asynchronously clocked modulus-12 counter with asynchronous recycling.

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▪ The NAND gate partially decodes count twelve (1100) and resets flip-flop 2 and flip-flop 3.
Related Problem
1. How can the counter in Figure 4.3.9(a) be modified to make it a modulus-13 counter?
2. What does the term asynchronous mean in relation to counters?
3. How many states does a modulus-14 counter have? What is the minimum number of flip-flops
required

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IMPLEMENTATION: 4-BIT ASYNCHRONOUS BINARY COUNTER Fixed-Function Device The 74HC93
▪ It is an example of a specific integrated circuit asynchronous counter. This device actually consists of a
single flip-flop (CLK A) and a 3-bit asynchronous counter (CLK B). This arrangement is for flexibility.
▪ It can be used as a divide-by-2 device if only the single flip-flop is used, or it can be used as a modulus-
8 counter if only the 3-bit counter portion is used.
▪ This device also provides gated reset inputs, RO(1) and RO(2). When both of these inputs are HIGH, the
counter is reset to the 0000 state CLR.
▪ Additionally, the 74HC93 can be used as a 4-bit modulus-16 counter (counts 0 through 15) by
connecting the Q0 output to the CLK B input as shown by the logic symbol in Figure 4.3.10(a).

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IMPLEMENTATION: 4-BIT ASYNCHRONOUS BINARY COUNTER Fixed-Function Device The 74HC93
▪ It can also be configured as a decade counter (counts 0 through 9) with asynchronous

▪ recycling by using the gated reset inputs for partial decoding of count ten, as shown by the logic
symbol in Figure 4.3.10(b).
FIGURE 4.3.10 Two configurations of the 74HC93 asynchronous counter. (The qualifying label, CTR DIV n,
indicates a counter with n states.)
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▪ The term synchronous refers to events that have a fixed time relationship with
each other. A synchronous counter is one in which all the flip-flops in the counter
are clocked at the same time by a common clock pulse.
▪ J-K flip-flops are used to illustrate most synchronous counters.
▪ D flip-flops can also be used but generally require more logic because of having no direct toggle or no-
change states. For illustration we will examine
1. 2-bit synchronous binary counter
4. Synchronous decade counter
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▪ Figure 4.3.11 shows a 2-bit synchronous binary counter.
FIGURE 4.3.11 2-bit synchronous binary counters.

▪ Notice that an arrangement different from that for the asynchronous counter must be used for the J1 and
K1 inputs of FF1 in order to achieve a binary sequence.
▪ A D flip-flop implementation is shown in part (b).
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The operation of a J-K flip-flop synchronous counter is as follows:
✓ First, assume that the counter is initially in the binary 0 state; that is, both flip-flops are RESET.
✓ When the positive edge of the first clock pulse is applied, FF0 will toggle and Q0 will therefore go
HIGH because the inputs are 1 and 0 respectively. What happens to FF1 at the positive-going edge of CLK1? To
find out, let’s look at the input conditions of FF1.
• Inputs J1 and K1 are both LOW because Q0 , to which they are connected, has not yet gone HIGH. Remember, there is a
propagation delay from the triggering edge of the clock pulse until the Q output actually makes a transition.
• So, J1 = 0 and K1 = 0 when the leading edge of the first clock pulse is applied.
• This is a no-change condition, and therefore FF1 does not change state.
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The operation of a J-K flip-flop synchronous counter is as follows:
✓ A timing detail of this portion of the counter operation is shown in Figure 4.3.12(a).
FIGURE 4.3.12Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal).
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✓ The complete timing diagram for the counters in Figure 4. 3.11is shown in Figure 4.3.13.
✓ Notice that all the waveform transitions appear
coincident; that is, the propagation delays are not
indicated.
FIGURE 4.3.13 Timing diagram for the counters of Figure 4.3.11.
✓ Although the delays are an important factor in the synchronous counter operation, in an overall timing diagram they are
normally omitted for simplicity. Major waveform relationships resulting from the normal operation of a circuit can be conveyed
completely without showing small delay and timing differences. However, in high-speed digital circuits, these small delays are
an important consideration in design and troubleshooting.
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2. A 3-Bit Synchronous Binary Counter

✓ A 3-bit synchronous binary counter is shown in Figure 4.3.14a, and its timing diagram is shown in
Figure 4.3.14b.
b) Timing diagram
a) A 3-bit synchronous binary counter.
FIGURE 4.3.14
✓ You can understand this counter operation by examining its sequence of states as shown in Table 4.3.2.

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TABLE 4.3.2 State sequence for a 3-bit binary counter.
✓ First, let’s look at Q0 . Notice that Q0 changes on each clock pulse as the counter
progresses from its original state to its final state and then back to its original state.
✓ To produce this operation, FF0 must be held in the toggle mode by constant HIGHs
on its J0 and K0 inputs. Notice that Q1 goes to the opposite state following each time
Q0 is a 1. This change occurs at CLK2, CLK4, CLK6, and CLK8. The CLK8 pulse
✓ causes the counter to recycle. To produce this operation, Q0 is connected to the J1 and K1 inputs of FF1. When Q0 is a 1 and a
clock pulse occurs, FF1 is in the toggle mode and therefore changes state.
✓ The other times, when Q0 is a 0, FF1 is in the no-change mode and remains in its present state.
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✓ Next, let’s see how FF2 is made to change at the proper times according to the binary sequence.
• Notice that both times Q2 changes state, it is preceded by the unique condition in which both Q0 and Q1 are HIGH.
• This condition is detected by the AND gate and applied to the J2 and K2 inputs of FF2.
• Whenever both Q0 and Q1 are HIGH, the output of the AND gate makes the J2 and K2 inputs of FF2 HIGH, and FF2
toggles on the following clock pulse.
• At all other times, the J2 and K2 inputs of FF2 are held LOW by the AND gate output, and FF2 does not change state.
• The analysis of the counter in Figure 4.3.14 is summarized in Table 4.3.3

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TABLE 4.3.2 Summary of the analysis of the counter in Figure 4.3.14.

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▪ Figure 4.3.15(a) shows a 4-bit synchronous binary counter, and Figure 4.3.15(b) shows its timing
diagram. This particular counter is implemented with negative edge-triggered flipflops.
FIGURE 4.3.15 A 4-bit synchronous binary counter and timing diagram. Times
where the AND gate outputs are HIGH are indicated by the shaded areas.
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▪ The reasoning behind the J and K input control for the first three flip-flops is the same as previously
discussed for the 3-bit counter. The fourth stage, FF3, changes only twice in the sequence.
▪ Notice that both of these transitions occur following the times that Q0 , Q1 , and Q2 are all HIGH.
▪ This condition is decoded by AND gate G2 so that when a clock pulse occurs, FF3 will change state.
▪ For all other times the J3 and K3 inputs of FF3 are LOW, and it is in a no-change condition.

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4. Synchronous Decade Counter

▪ A synchronous BCD decade counter is shown in Figure 4.3.16a. The timing diagram for the decade
counter is shown in Figure 4.3.16b.
a) b)
Figure 4.3.16 A synchronous BCD decade counter. Timing diagram for the BCD decade counter (Q0 is the LSB).

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▪ The counter operation is shown by the sequence of states in Table 4.3.4.
TABLE 4.3.4 States of a BCD decade counter.
▪ First, notice that FF0 (Q0 ) toggles on each clock pulse, so
the logic equation for its J0 and K0 inputs is J0 = K0 = 1
▪ This equation is implemented by connecting J0 and K0 to
a constant HIGH level.
▪ Next, notice in Table 4.3.4 that FF1 (Q1 ) changes on the
next clock pulse each time Q0 = 1 and Q3 = 0, so the logic
equation for the J1 and K1 inputs is J1 = K1 = Q0Q3’
▪ This equation is implemented by ANDing Q0 and Q3 and connecting the gate output to the J1 and K1 inputs of FF1.
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▪ Flip-flop 2 (Q2 ) changes on the next clock pulse each time both Q0 = 1 and Q1 = 1.
▪ This requires an input logic equation as follows: J2 = K2 = Q0Q1
• This equation is implemented by ANDing Q0 and Q1 and connecting the gate output to the
J2 and K2 inputs of FF2.
▪ Finally, FF3 (Q3 ) changes to the opposite state on the next clock pulse each time Q0 = 1, Q1 = 1, and
Q2 = 1 (state 7), or when Q0 = 1 and Q3 = 1 (state 9).
▪ The equation for this is as follows: J3 = K3 = Q0Q1Q2 + Q0Q3
▪ This function is implemented with the AND/OR logic connected to the J3 and K3 inputs of FF3 as
shown in the logic diagram in Figure 4.3.16.
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IMPLEMENTATION: 4-BIT SYNCHRONOUS BINARY COUNTER Fixed-Function Device 74HC163
▪ It is an example of an integrated circuit 4-bit synchronous binary counter. A logic

symbol is shown in Figure 4.3.17 with pin numbers in parentheses.
▪ This counter has several features in addition to the basic functions

previously discussed for the general synchronous binary counter.
▪ First, the counter can be synchronously preset to any 4-bit binary
number by applying the proper levels to the parallel data inputs.
FIGURE 4.3.17 The 74HC163 4-bit synchronous binary counter. (The

qualifying label CTR DIV 16 indicates a counter with sixteen states.)
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▪ When a LOW is applied to the LOAD’ input, the counter will assume the state of the data inputs on
the next clock pulse. Thus, the counter sequence can be started with any 4-bit binary number.
▪ Also, there is an active-LOW clear input (CLR)’, which synchronously resets all four flip-flops in the
counter. There are two enable inputs, ENP and ENT. These inputs must both be HIGH for the counter to
sequence through its binary states. When at least one input is LOW, the counter is disabled.
▪ The ripple clock output (RCO) goes HIGH when the counter reaches the last state in its sequence of
fifteen, called the terminal count (TC = 15).
▪ This output, in conjunction with the enable inputs, allows these counters to be cascaded for higher
count sequences.
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▪ Figure 4.3.18 shows a timing diagram of this counter being preset to twelve (1100) and then counting up
to its terminal count, fifteen (1111). Input D0 is the
least significant input bit, and Q0 is the leas
significant output bit.
▪ Let’s examine this timing diagram in detail. This will

aid you in interpreting timing diagrams in this chapter
or on manufacturers’ data sheets
FIGURE 4.3.18Timing example for a 74HC163.

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1. To begin, the LOW level pulse on the CLR’ input causes all the outputs (Q0 , Q1 , Q2 , and Q3 ) to go LOW.
2. Next, the LOW level pulse on the LOAD’ input synchronously enters the data on the data inputs (D0 , D1 , D2 , and D3 ) into
the counter. These data appear on the Q outputs at the time of the first positive-going clock edge after LOAD’ goes LOW.
• This is the preset operation. In this particular example, Q0 is LOW, Q1 is LOW, Q2 is HIGH, and Q3 is HIGH.
• This, of course, is a binary 12 (Q0 is the LSB). The counter now advances through states 13, 14, and 15 on the next three
positive going clock edges. It then recycles to 0, 1, 2 on the following clock pulses.
• Notice that both ENP and ENT inputs are HIGH during the state sequence. When ENP goes LOW, the counter is
inhibited and remains in the binary 2 state.

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Problems
1. How does a synchronous counter differ from an asynchronous counter?

2. Explain the function of the preset feature of counters such as the 74HC163.
3. Describe the purpose of the ENP and ENT inputs and the RCO output for the 74HC163 counter.

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4. Up/Down Synchronous Counters

▪ An up/down counter is one that is capable of progressing in either direction
through a certain sequence. An up/down counter, sometimes called a bidirectional counter, can have any
specified sequence of states.
▪ A 3-bit binary counter that advances upward through its sequence (0, 1, 2, 3, 4, 5, 6, 7) and then can be
reversed so that it goes through the sequence in the opposite direction (7, 6, 5, 4, 3, 2, 1, 0) is an
illustration of up/down sequential operation.
▪ In general, most up/down counters can be reversed at any point in their sequence.
▪ For instance, the 3-bit binary counter can be made to go through the following sequence:

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Table 4.3.5 shows the complete up/down sequence for a 3-bit binary counter.
▪ The arrows indicate the state-to-state movement of the
counter for both its UP and its DOWN modes of
operation. An examination of Q0 for both the up and
down sequences shows that FF0 toggles on each clock
pulse. Thus, the J0 and K0 inputs of FF0 are J0 = K0 = 1
▪ For the up sequence, Q1 changes state on the next clock pulse when Q0 = 1. For the down sequence, Q1
changes on the next clock pulse when Q0 = 0. Thus, the J1 and K1 inputs of FF1 must equal 1 under the
conditions expressed by the following equation: J1 = K1 = (Q0 UP) + (Q0 DOWN’)
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▪ For the up sequence, Q2 changes state on the next clock pulse when Q0 = Q1 = 1.
▪ For the down sequence, Q2 changes on the next clock pulse when Q0 = Q1 = 0. Thus, the J2 and K2
inputs of FF2 must equal 1 under the conditions expressed by the following equation:
J2 = K2 = (Q0 Q1 UP) + (Q0 ‘Q1 ‘DOWN)
▪ Each of the conditions for the J and K inputs of each flip-flop produces a toggle at the appropriate point
in the counter sequence.
▪ Figure 4.3.19 shows a basic implementation of a 3-bit up/down binary counter using the logic
equations just developed for the J and K inputs of each flip-flop. Notice that the UP/DOWN’ control
input is HIGH for UP and LOW for DOWN.
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FIGURE 4.3.19 A basic 3-bit up/down synchronous counter.

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EXAMPLE Show the timing diagram and determine the sequence of a 4-bit synchronous binary
up/down counter if the clock and UP/DOWN’ control inputs have waveforms as shown in Figure below
The counter starts in the all-0s state and is positive edge-triggered.
Related Problem Show the

timing diagram if the
UP/DOWN’ control waveform
is inverted.

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IMPLEMENTATION: UP/DOWN DECADE COUNTER Fixed-Function Device 74HC190,
▪ Figure4.3.20 shows a logic diagram for the 74HC190, an example of an integrated circuit up/down
synchronous decade counter. ▪ The direction of the count is determined by the level of the
up/down input (D/U’).
• When this input is HIGH, the counter counts down; when it is
LOW, the counter counts up.
▪ Also, this device can be preset to any desired BCD digit as
determined by the states of the data inputs when the LOAD’
FIGURE 4.3.20 The 74HC190 up/down
input is LOW.
synchronous decade counter.
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IMPLEMENTATION: UP/DOWN DECADE COUNTER Fixed-Function Device 74HC190,
▪ The MAX/MIN output produces a HIGH pulse when the terminal count nine (1001) is reached in the
UP mode or when the terminal count zero (0000) is reached in the DOWN mode.
▪ The MAX/MIN output, the ripple clock output (RCO)’, and the count enable input (CTEN)’ are used
when cascading counters.
▪ Figure 4.3.21 is a timing diagram that shows the 74HC190 counter preset to seven (0111) and then
going through a count-up sequence followed by a count-down sequence.
▪ The MAX/MIN output is HIGH when the counter is in either the all-0s state (MIN) or the 1001 state
(MAX).

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FIGURE 4.3.21 Timing

example for a 74HC190.

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1. A 4-bit up/down binary counter is in the DOWN mode and in the 1010 state. On the next clock
pulse, to what state does the counter go?
2. What is the terminal count of a 4-bit binary counter in the UP mode? In the DOWN mode? What is
the next state after the terminal count in the DOWN mode?

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Design of Synchronous Counters

▪ Let us see the six steps to design a counter (state machine), which also used to state machine design in
general. As an example, let us see a 3-bit Gray code counter.
Example 1 Design a 3-bit Gray code counter

Solution Steps
1. Specify the counter sequence and draw a state diagram.
✓ The first step in the design of a state machine (counter) is to create a state diagram.
✓ A state diagram shows the progression of states through which the counter advances when it is clocked.
✓ Figure 4.3.22 is a state diagram for a basic 3-bit Gray code counter.

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Solution Design of Synchronous Counters Steps
✓ This particular circuit has no inputs other than the clock and no outputs other
than the outputs taken off each flip-flop in the counter.
✓ You may wish to review the coverage of the Gray code in Chapter 1 at this
time.
FIGURE 4.3.22 State diagram
for a 3-bit Gray code counter.
2. Derive a next-state table from the state diagram.
✓ Once the sequential circuit is defined by a state diagram, the second step is to derive a next-state
table, which lists each state of the counter (present state) along with the corresponding next state.
55

2. Derive a next-state table from the state diagram.
✓ The next state is the state that the counter goes to from its present state upon application of a clock
pulse. The next-state table is derived from the state diagram and is shown in Table 4.3.6 for the 3-bit
Gray code counter. Q0 is the least significant bit. TABLE 4.3.6

56

3. Develop a transition table showing the flip-flop inputs required for each transition. The transition table
is always the same for a given type of flip-flop. Table 4.3.7 is a transition table for the J-K flip-flop.
TABLE 4.3.7 ✓ For each output transition, the J and K inputs that will cause the
transition to occur are listed. An X indicates a “don’t care” (the
input can be either a 1 or a 0).
✓ To design the counter, the transition table is applied to each of
the flip-flops in the counter, based on the next-state table (Table
4.3.6). For example, for the present state 000, Q0 goes from a
present state of 0 to a next state of 1.
57

3. Develop a transition table showing the flip-flop inputs required for each transition. The transition table
is always the same for a given type of flip-flop. Table 4.3.7 is a transition table for the J-K flip-flop.
✓ To make this happen, J0 must be a 1 and you don’t care what K0 is (J0 = 1, K0 = X), as you can see in the
transition table.
✓ Next, Q1 is 0 in the present state and remains a 0 in the next state. For this transition, J1 = 0 and K1 = X.
Finally, Q2 is 0 in the present state and remains a 0 in the next state.
✓ Therefore, J2 = 0 and K2 = X. This analysis is repeated for each present state in Table 4.3.6.

58

4. Transfer the J and K states from the transition table to Karnaugh maps. There is a Karnaugh map for
each input of each flip-flop.
✓ Karnaugh maps can be used to determine the logic required for the J and K inputs of each flip-flop in the
counter. There is a Karnaugh map for the J input and a Karnaugh map for the K input of each flip-flop.
✓ In this design procedure, each cell in a Karnaugh map represents one of the present states in the counter
sequence listed in Table 4.3.6.
✓ From the J and K states in the transition table (Table 4.3.7) a 1, 0, or X is entered into each present-state
cell on the maps depending on the transition of the Q output for a particular flip-flop.
To illustrate this procedure, two sample entries are shown for the J0 and the K0 inputs to the least significant flip-flop (Q0 ) in Figure 4.3.23.
59
FIGURE 4.3.23 Examples of the mapping

procedure for the counter sequence
represented in Table 4.3.6 and Table 4.3.7.
✓ The completed Karnaugh maps for all

three flip-flops in the counter are shown
in Figure 4.3.24.
✓ The cells are grouped as indicated and
the corresponding Boolean expressions
for each group are derived.

60

4. Transfer the J and K states from the transition table to Karnaugh maps. There is a Karnaugh map for
each input of each flip-flop.
FIGURE 4.3.24 Karnaugh maps for present-state J and K inputs

61

4. Group the Karnaugh map cells to generate and derive the logic expression for each flip-flop input.
▪ Logic Expressions for Flip-Flop Inputs From the Karnaugh maps of Figure 4.3.24 you obtain the
following expressions for the J and K inputs of each flip-flop:

62

6. Implement the expressions with combinational logic, and combine with the flip-flops to create the
counter.
So, implement the combinational logic from the expressions for the J and K inputs and connect the flip-
flops to form the complete 3-bit Gray code counter as shown in Figure 4.3.25.
FIGURE 4.3.25 Three-bit Gray code counter. Open file F09-29 to verify operation.
63

EXAMPLE 2 Design a counter with the irregular binary count sequence shown in the state diagram of
Figure 4.3.26. Use D flip-flops and J-K flip flop. Solution
Step 1: The state diagram is as shown. Although there are only four states, a 3-
bit counter is required to implement this sequence because the maximum
binary count is seven. Since the required sequence does not include all the
possible binary states, the invalid states (0, 3, 4, and 6) can be treated as “don’t
FIGURE 4.3.26 cares” in the design. However, if the counter should erroneously get into an
invalid state, you must make sure that it goes back to a valid state.

64
Solution Design of Synchronous Counters
Step 2: The next-state table is developed from the state diagram and is given in Table 4.3.8.
Table 4.3.8.
Step 3: The transition table for the D flip-flop is
shown in Table 4.3.9.
Table 4.3.9.

65
Step 4: The D inputs are plotted on the present-state Karnaugh maps in Figure 4.3.27. Also “don’t cares”
can be placed in the cells corresponding to the invalid states of 000, 011, 100, and 110, as indicated by the
red Xs.
Figure 4.3.27

66

Step 5: Group the 1s, taking advantage of as many of the “don’t care” states as possible for maximum
simplification, as shown in Figure 4.3.27. The expression for each D input taken from the maps is as follows:
D0 = Q0’ + Q2 D1 = Q1’ D2 = Q0’ + Q2Q1’
Step 6: The implementation of the counter is shown in Figure 4.3.28.
Figure 4.3.27
67

Example 3 Develop a synchronous 3-bit up/down counter with a Gray code sequence using J-K flip-flops.
The counter should count up when an UP/DOWN’ control input is 1 and count down when the control
input is 0. Solution
Step 1: The state diagram is shown in Figure 4.3.28. The 1 or 0 beside each arrow indicates the state of the
UP/DOWN’ control input, Y.
Step 2: The next-state table is derived from the state diagram and
is shown in Table 4.3.10. Notice that for each present state there
are two possible next states, depending on the UP/DOWN’
control variable, Y
Figure 4.3.28

68

TABLE 4.3.10
Step 3: The transition table for the J-K flip-flops is
repeated in Table 4.3.11.
Table 4.3.11.

69

Step 4: The Karnaugh maps for the J and K inputs of the flip-flops are shown in Figure 4.3.30.
FIGURE 4.3.30
70
Step 4: The UP/DOWN’ control input, Y, is considered one of the state variables along with Q0 , Q1 , and
Q2 . Using the next-state table, the information in the “Flip-Flop Inputs” column of Table 4.3.11 is
transferred onto the maps as indicated for each present state of the counter.
Step 5: The 1s are combined in the largest possible groupings, with “don’t cares” (Xs) used where possible.
The groups are factored, and the expressions for the J and K inputs are as follows:
Step 6: The J and K equations are implemented with combinational logic. Specify the number of flip-
flops, gates, and inverters that are required to implement the logic described in Step 5.

71
Design of Synchronous Counters Solution

Problems
1. A flip-flop is presently in the RESET state and must go to the
SET state on the next clock pulse. What must J and K be?
2. A flip-flop is presently in the SET state and must remain SET
on the next clock pulse. What must J and K be?
3. A binary counter is in the Q3Q2Q1Q0 = 1010 state.
(a) What is its next state?
(b) What condition must exist on each flip-flop input to ensure
that it goes to the proper next state on the clock pulse?

72
▪ Counters can be connected in cascade to achieve higher-modulus operation. In essence, cascading

means that the last-stage output of one counter drives the input of the next counter.
Asynchronous Cascading
▪ An example of two asynchronous counters connected in cascade is shown in Figure 4.3.31 for a 2-
bit and a 3-bit ripple counter. The timing diagram is shown in Figure 4.3.32. Notice
FIGURE 4.3.31 Two cascaded asynchronous

counters (all J and K inputs are HIGH).

73
Asynchronous Cascading
FIGURE 4.3.32 Timing diagram for the

cascaded counter configuration of Figure 4.3.31.
▪ Notice that the final output of the modulus-8 counter, Q4 , occurs once for every 32 input clock
pulses. The overall modulus of the two cascaded counters is 4 * 8 = 32; that is, they act as a divide-
by-32 counter.

74
Synchronous Cascading
▪ When operating synchronous counters in a cascaded configuration, it is necessary to use the count
enable and the terminal count functions to achieve higher-modulus operation.
▪ On some devices the count enable is labeled simply CTEN (or some other designation such as G),
and terminal count (TC) is analogous to ripple clock output (RCO) on some IC counters.
▪ Figure 4.3.33 shows two decade counters connected in cascade.
FIGURE 4.3.33 A modulus-100 counter

using two cascaded decade counters.

75
▪ The terminal count (TC) output of counter 1 is connected to the count enable (CTEN) input of counter 2.
▪ Counter 2 is inhibited by the LOW on its CTEN input until counter 1 reaches its last, or terminal, state
and its terminal count output goes HIGH.
▪ This HIGH now enables counter 2, so that when the first clock pulse after counter 1 reaches its terminal
count (CLK10), counter 2 goes from its initial state to its second state.
▪ Upon completion of the entire second cycle of counter 1 (when counter 1 reaches terminal count the
second time), counter 2 is again enabled and advances to its next state. This sequence continues.
▪ Since these are decade counters, counter 1 must go through ten complete cycles before counter 2
completes its first cycle.
76
▪ In other words, for every ten cycles of counter 1, counter 2 goes through one cycle. Thus, counter 2 wil
complete one cycle after one hundred clock pulses. The overall modulus of these two cascaded counter
is 10 * 10 = 100. When viewed as a frequency divider, the circuit of Figure 4.3.33 divides the input clock
frequency by 100.
▪ Cascaded counters are often used to divide a high-frequency clock signal to obtain highly accurate
pulse frequencies. Cascaded counter configurations used for such purposes are sometimes called
countdown chains.

77
▪ For example, suppose that you have a basic clock frequency of 1 MHz and you wish to obtain 100 kHz,
10 kHz, and 1 kHz; a series of cascaded decade counters can be used.
▪ If the 1 MHz signal is divided by 10, the output is 100 kHz. Then if the 100 kHz signal is divided by 10, the
output is 10 kHz. Another division by 10 produces the 1 kHz frequency. The general implementation of
this countdown chain is shown in Figure 4.3.34.
FIGURE 4.3.34 Three cascaded decade counters

forming a divide-by-1000 frequency divider with
intermediate divide-by-10 and divide-by-100 outputs.
78
EXAMPLE Determine the overall modulus of the two cascaded counter configurations in Figure below.
Solution
a) The overall modulus for the 3-counter configuration is 8 * 12 * 16 = 1536
b) The overall modulus for the 4-counter configuration is 10 * 4 * 7 * 5 = 1400
Related Problem How many cascaded decade counters are required to divide a clock frequency by
100,000?
79
EXAMPLE 1 Use 74HC190 up/down decade counters connected in the UP mode to obtain a 10 kHz
waveform from a 1 MHz clock. Show the logic diagram.
Solution
▪ To obtain 10 kHz from a 1 MHz clock requires a division factor of 100. Two 74HC190 counters must be
cascaded as shown in Figure 4.3.46. The left counter produces a terminal count (MAX/MIN) pulse for
every 10 clock pulses.
▪ The right counter produces a terminal count (MAX/MIN) pulse for every 100 clock pulses.

80
Solution
Related Problem Determine the frequency of the waveform at the Q0 output of the second counter (the
one on the right) in Figure above.

81
Cascaded Counters with Truncated Sequences

▪ The preceding discussion has shown how to achieve an overall modulus (divide-by-factor) that is the
product of the individual moduli of all the cascaded counters. This can be considered full-modulus
cascading. Often an application requires an overall modulus that is less than that achieved by full
modulus cascading. That is, a truncated sequence must be implemented with cascaded counters.
▪ To illustrate this method, we will use the cascaded counter configuration in Figure 4.3.37.
FIGURE 4.3.37 A divide-by-40,000 counter using

74HC161 4-bit binary counters. Note that each of
the parallel data inputs is shown in binary order
(the right-most bit D0 is the LSB in each
counter).
82

▪ This particular circuit uses four 74HC161 4-bit synchronous binary counters. If these four counters
(sixteen bits total) were cascaded in a full-modulus arrangement, the modulus would be
216 = 65,536
▪ Let’s assume that a certain application requires a divide-by-40,000 counter (modulus 40,000).
▪ The difference between 65,536 and 40,000 is 25,536, which is the number of states that must be
deleted from the full-modulus sequence. The technique used in the circuit of Figure 4.3.37 is to preset
the cascaded counter to 25,536 (63C0 in hexadecimal) each time it recycles, so that it will count
from 25,536 up to 65,535 on each full cycle.
▪ Therefore, each full cycle of the counter consists of 40,000 states.

83
▪ Notice in Figure 4.3.47 that the RCO output of the right-most counter is inverted and applied to the
LOAD input of each 4-bit counter. Each time the count reaches its terminal value of 65,535, which is
(1111111111111111)2 , RCO goes HIGH and causes the number on the parallel data inputs (63C016) to be
synchronously loaded into the counter with the clock pulse.
▪ Thus, there is one RCO pulse from the right-most 4-bit counter for every 40,000 clock pulses.
▪ With this technique any modulus can be achieved by synchronous loading of the counter to the
appropriate initial state on each cycle.

84
1. How many decade counters are necessary to implement a divide-by-1000 (modulus1000) counter?
A divide-by-10,000?
2. Show with general block diagrams how to achieve each of the following, using a flipflop, a decade
counter, and a 4-bit binary counter, or any combination of these:
(a) Divide-by-20 counter
(b) Divide-by-32 counter
(c) Divide-by-160 counter
(d) Divide-by-320 counter

85
▪ In many applications, it is necessary that some or all of the counter states be decoded.
▪ The decoding of a counter involves using decoders or logic gates to determine when the counter is in
a certain binary state in its sequence. For instance, the terminal count function previously discussed is
a single decoded state (the last state) in the counter sequence.
▪ Suppose that you wish to decode binary state 6 (110) of a 3-bit binary counter. When Q2 = 1, Q1 = 1,
and Q0 = 0, a HIGH appears on the output of the decoding gate, indicating that the counter is at
state 6. This can be done as shown in Figure 4.3.38.
▪ This is called active-HIGH decoding. Replacing the AND gate with a NAND gate provides active-
LOW decoding

86
FIGURE 4.3.38 Decoding of state 6 (110).
Decoding Glitches
87
1. A Digital Clock
FIGURE 4.3.39 Simplified logic diagram

for a 12-hour digital clock.

88
2. Automobile Parking Control
FIGURE 4.3.40 Functional block diagram for parking garage control.

89
3. Parallel-to-Serial Data Conversion (Multiplexing)
FIGURE 4.3.41 Parallel-to-serial data conversion logic.

THANK YOU!
Abdulaziz J.
Email:-
[email protected]

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Chapter 4 01 Introduction

“Tell me and I forget, teach me and I may

By Abdulaziz J. Sequential Circuit Design 6/1/2024

FIGURE 4.3.1 Two types of sequential logic.

▪ It is also called Ripple counters

1. 2-bit asynchronous binary counter

By Abdulaziz J. Sequential Circuit Design 6/1/2024

1. 2-bit asynchronous binary counter

1. 2-bit asynchronous binary counter Solution

1. 2-bit asynchronous binary counter Solution

2. 3-bit asynchronous binary counter

By Abdulaziz J. Sequential Circuit Design 6/1/2024

2. 3-bit asynchronous binary counter Solution

By Abdulaziz J. Sequential Circuit Design 6/1/2024

Propagation Delay Asynchronous counters are commonly referred to as ripple counters

▪ This cumulative delay of an asynchronous counter is a major disadvantage in many applications

By Abdulaziz J. Sequential Circuit Design 6/1/2024

Propagation Delay Solution

Propagation Delay Solution

By Abdulaziz J. Sequential Circuit Design 6/1/2024

3. Decade asynchronous binary counter

By Abdulaziz J. Sequential Circuit Design 6/1/2024

3. Decade asynchronous binary counter

By Abdulaziz J. Sequential Circuit Design 6/1/2024

Solution 3. Decade asynchronous binary counter

FIGURE 4.3.8 An asynchronously clocked decade counter with asynchronous recycling.

Solution 3. Decade asynchronous binary counter

By Abdulaziz J. Sequential Circuit Design 6/1/2024

Solution 3. Decade asynchronous binary counter

By Abdulaziz J. Sequential Circuit Design 6/1/2024

3. Decade asynchronous binary counter

By Abdulaziz J. Sequential Circuit Design 6/1/2024

Solution 3. Decade asynchronous binary counter

FIGURE 4.3.9 Asynchronously clocked modulus-12 counter with asynchronous recycling.

Solution 3. Decade asynchronous binary counter

By Abdulaziz J. Sequential Circuit Design 6/1/2024

IMPLEMENTATION: 4-BIT ASYNCHRONOUS BINARY COUNTER Fixed-Function Device The 74HC93

By Abdulaziz J. Sequential Circuit Design 6/1/2024

IMPLEMENTATION: 4-BIT ASYNCHRONOUS BINARY COUNTER Fixed-Function Device The 74HC93

▪ It can also be configured as a decade counter (counts 0 through 9) with asynchronous

1. 2-bit synchronous binary counter

FIGURE 4.3.11 2-bit synchronous binary counters.

1. 2-bit synchronous binary counter

1. 2-bit synchronous binary counter

1. 2-bit synchronous binary counter

2. A 3-Bit Synchronous Binary Counter

By Abdulaziz J. Sequential Circuit Design 6/1/2024

2. A 3-Bit Synchronous Binary Counter

2. A 3-Bit Synchronous Binary Counter

By Abdulaziz J. Sequential Circuit Design 6/1/2024

2. A 3-Bit Synchronous Binary Counter

By Abdulaziz J. Sequential Circuit Design 6/1/2024

3. A 4-Bit Synchronous Binary Counter

3. A 4-Bit Synchronous Binary Counter

By Abdulaziz J. Sequential Circuit Design 6/1/2024

4. Synchronous Decade Counter

By Abdulaziz J. Sequential Circuit Design 6/1/2024

4. Synchronous Decade Counter

4. Synchronous Decade Counter