ADE Lab Manual CSE Sep 2024

Analog and Digital Electronics Lab REVA University
BENGALURU, INDIA
School of Computer Science and Engineering
Analog and Digital Electronics Lab Manual

B22EF0307
Third Semester CSE
2023-2027(Odd Semester)
Name
SRN
Branch CSE
Semester 3rd
Section
Academic Year 2024 - 25
Department of Computer Science and Engineering Page 1

Vision of the Department
Department of Computer Science and Engineering aspires to create a pool of high-caliber technologists and
researchers in the field of computer science and engineering who have potential to contribute for development
of the nation and society with their expertise, skills, innovative problem-solving abilities and strong ethical
values.
Mission of the Department
MD1: To create center of excellence where new ideas flourish and from which emerge
tomorrow’s researchers, scholars, leaders, and innovators.
MD2: Provide quality education in both theoretical and applied foundations of
computer science and engineering, related inter-disciplinary areas and train
students to effectively apply the knowledge to solve real-world problems.
MD3: Amplify student’s potential for life-long high-quality careers and make
them competitive in ever-changing and challenging global work
environment.
MD4: Forge research and academic collaboration with industries and top global
universities in order to provide students with greater opportunities.
MD5: Support the society by encouraging and participating in technology transfer.

COURSE OVERVIEW:
This course covers basic concepts of Electrical Engineering. The course introduces the working of analog
components and helps in understanding basics in digital electronics by applying the knowledge of logic gates
and learning the applications of diodes and opamps. The course provides foundation on designing and
implementation of logic circuits. Analog circuits are simulated using ORCAD tool and digital circuits using
XILINX tool which helps in gaining experience in creating and testing of circuits.
COURSE OBJECTIVE (S):

The objectives of this course are to:
1. Discuss the applications of diode in rectifiers, filter circuits and wave shaping.
2. Describe the foundation on designing, building and testing of common
combinational and sequential Digital logic circuits.
3. Explain the procedure required for simulation of digital logic circuits.
4. Demonstrate the use of general electronic instruments in design and testing of digital logic
circuits.
COURSE OUTCOMES (COs)

After the completion of the course, the student will be able to:
CO# Course Outcomes POs PSOs
Analyze the use of diodes in rectifiers, filter circuits and wave shaping 1 to
CO1 1
4,7,8,9,10,12
Apply the basic knowledge used in solid state electronics including diodes, and
1 to 3, 5,
CO2 1
operational amplifiers for specific engineering applications. 7,8,9,10,12
Identify the different families of digital integrated circuits build, and

1 to 5,
CO3 2
troubleshoot combinatorial circuits using digital integrated circuits 7,8,9,10,12
Develop the ability to analyze and design analog electronic circuits using
CO4 1,4,5,
3
discrete components
7,8,9,10,12
Model the schematics of some electronic circuits to interpret its working.
CO5 1,3,5,
3
7,8,9,10,12
Solve the implementation of logic circuit using programming.
CO6 1,2,4,
3
7,8,9,10,12

BLOOM’S LEVEL OF THE COURSE OUTCOMES
Bloom’s Level
Remember Understand Apply Analyze Evaluate Create
CO#
(L1) (L2) (L3) (L4) (L5) (L6)
CO1 √
CO2 √
CO3 √
CO4 √
CO5 √
CO6 √
COURSE ARTICULATION MATRIX
PO10
PO11
PO12
PSO1
PSO2
PSO3
PO1
PO2
PO3
PO4
PO5
PO6
PO7
PO8
PO9
CO#/
POs
3 3
CO1 3 1 1 2 2 2 2 3
3 3
CO2 3 2 3 2 2 2 3
2
3 3
CO3 3 1 2 1 1 2 2 3
2
3 3 3
CO4 3 2 2 1 2 1
3 3 3
CO5 3 2 2 1 2 1
3 3 3
CO6 3 3 2 1 2 1
Note: 1-Low, 2-Medium, 3-High

CONTENTS
SL.NO LAB EXPERIMENTS PAGE NO

To simulate a positive clipper, double ended clipper & positive clamper
1 circuits using diodes. 6
To simulate a rectangular wave form generator (Op-amp relaxation

oscillator) and compare the frequency and duty cycle with the design 10
2 specifications.
To simulate a Schmitt trigger using Op-amp and compare the UTP and
3 LTP values with the given specification. 10
4 To simulate a Wien bridge Oscillator. 13
5 To determine the working of a power supply and observe the waveforms. 16
6. To build and simulate CE amplifier (RC coupled amplifier) for its 20

frequency response and measure the bandwidth.
22
7. Realization of Half/Full adder and Half/Full Subtractors using logic
gates.
8. Design and develop VHDL code to realize Full adder and Full 24
Subtractors.
9. Given a 4-variable logic expression, simplify it using Entered Variable 27
Map and realize the simplified logic expression using 8:1 multiplexer IC.
10. Design and develop the VHDL code for an 8:1 multiplexer. Simulate 29
and verify it’s working.
11. Design and implement a ring counter using 4-bit shift register and 31
demonstrate its working.
12. Design and develop the VHDL code for switched tail counter. 32
IC Pin Configuration Sheet. 34

Experiment No. 1
CLIPPING & CLAMPING CIRCUITS
Aim: To simulate a positive clipper, double ended clipper & positive clamper circuits using diodes.
Theory: An electronic device that is used to evade the output of a circuit to go beyond the preset
value (voltage level) without varying the remaining part of the input waveform is called as Clipper
circuit. An electronic circuit that is used to alter the positive peak or negative peak of the input signal
to a definite value by shifting the entire signal up or down to obtain the output signal peaks at desired
level is called as Clamper circuit.
Components Required:
1) Diodes - D1N4007 - 2 Nos.

2) Resistor – 10K
3) Power supply VDC - 2 Nos.
4) Sinusoidal signal generator(VAC) 12V(PP), 1 KHz
A) Positive clipping
CIRCUIT DIAGRAM:
Vsin
WAVEFORMS:

Vin
+6v
Vout
TRANSFER CHARACTERISTICS: +Vout

X
-Vin +Vin
-Vout
B) DOUBLE ENDED CLIPPER
CIRCUIT DIAGRAM:
R=10KΩ
D1
D2
VAC= Vi CRO Vo
12V(pp) VR1=2V
1KHz VR2=2V
WAVEFORMS:

Vin
+6v
Vout
-6v
X
Y
TRANSFER CHARACTERISTICS:
+Vout
x
-Vin +Vin
y
-Vout
1. POSITIVE CLAMPING CIRCUIT
Components/Apparatus required:
1) Diodes - D1N4007
2) Resistor – 1MΩ
3) Capacitor – 10uf
4) Power supply VDC
5) Sinusoidal signal generator(VAC) 12V(PP), 1 KHz
C) Positive clamping

CIRCUIT DIAGRAM:
R=1MΩ
C =10uf
D
CRO
VAC= Vi Vo
12V(pp) VR=2V
1kHz
WAVEFORMS:
Vin
+6v
0 t
-6v
Procedure:
1. Follow the simulation steps given in Expt No 6
2. Use the available cursor on the simulated window to note down the clipped voltage level.
3. Repeat the above steps for the clamping circuits.
Results:
Quantity/Circuit Positive cilpper Double-ended clipper Clamper
Y --- ---------

Experiment No. 2
RELAXATION OSCILLATOR USING OP - AMP
Aim: To simulate a rectangular wave form generator (Opamp relaxation oscillator) and compare
the frequency and duty cycle with the design specifications
Theory:
The circuits generate rectangular waveform of specified frequency. Op-Amp is used as comparator
which compares the voltage at non inverting terminal with capacitor voltage. When the voltage at the
output is +βVsat, the capacitor charges to this voltage through R1 during which output remains at
+βVsat. When the capacitor voltage exceeds +βVsat output switches to –βVsat and the capacitor
starts discharging through R2 to –βVsat. When the capacitor voltage goes below –βVsat, the output
again switches back to +βVsat. Thus oscillations are generated, and the time period of oscillation
depends on R1, R2, R3, Rf and C.
Components and Equipments required:

1) Op-Amp – μA741
2) Resistors - 1K, 2K, 10K, 20K.
3) Capacitor – 0.1uf
5) Power supply (±15V) DC voltage
6) Diodes – D1N4007 – 2Nos.
CIRCUIT DIAGRAM:
D2 R2=2kΩ
D2 R1= 1kΩ
R4= 10kΩ
R3= 10kΩ
CALCULATION:
R3 10k
β= = = 0.5
R3 + R4 10k + 10k
For the above circuit

1 +  
TON = R1 C ln  
1 −  
= 1k * 0.1uf * 1.1
TON = 0.11mSec
1 +  
TOFF = R2 C ln  
1 −  
= 2k * 0.1uf * 1.1
TOFF = 0.22mSec
Total time period T = TON + TOFF = 0.11mSec + 0.22mSec

T = 0.33mSec
TON 0.11m sec

Duty cycle (D) = = = 0.33 *100 = 33%
T 0.33m sec
1 1
F= = = 3kHz
T 0.33m sec
WAVEFORMS:
V
+Vsat Vo
+βVsat Vc
-βVsat
-Vsat
TON TOFF
Procedure:
1. Follow the simulation steps given in Expt No 6.
2. Use the available cursor on the simulated window to measure the frequency and duty cycle
and compare with the theoretical value.

Results:
The practical time periods are measured and compared with theoretical values and tabulated as
shown below:
TON TOFF VoMAx Vo MIN Vc MAX Vc MIN Duty

Cycle
Theoretical 0.11m 0.22m +Vsat = –Vsat = - +βVsat = –βVsat

33%
value Sec Sec 12v 12v 6v =-6v
Practical
Value

Experiment No. 3
SCHMITT TRIGGER
Aim: To simulate a Schmitt trigger using Op-amp and compare the UTP andLTP values with the
given specification.
Theory:
A Schmitt trigger is a circuit which converts any slow varying waveform into a waveform having
abrupt transitions. In the Schmitt trigger circuit op-amp is used as a comparator. A Schmitt trigger
is characterized by two voltage levels :
1. UTP – Upper Trigger Point
2. LTP - Lower Trigger Point
The circuits can be realized to have equal UTP and LTP values or with unequal values using a
reference voltage.
Components/ Apparatus Required:

1) OP-AMP - μA74l
2) Resistors l0KΩ, 3.3KΩ
3) Power supply l2V DC voltage – 2 no.
4) Sinusoidal signal generator(VAC) 12V, 1kHz.
CIRCUIT DIAGRAM:
+12v
2 7
6
µA 741
3
4 R1=10kΩ
-12v
VAC=
12Vpeak Vi CRO Vo
1kHz
R2=3.3kΩ
VR=1.5V

WAVEFOREMS:
Vin
+6v
UTP
t
LTP
-6v
+Vsat
Vout
-Vsat
t
CALCULATIONS:
For the above circuit:
+ Vsat R2 VR R1
UTP = +
R1 + R2 R1 + R2
12V * 3.3K 1.5V * 10 K

= +
10 K + 3.3K 10 K + 3.3K
UTP = 4.32v
− Vsat R2 VR R1
LTP = +
R1 + R2 R1 + R2
− 12V * 3.3K 1.5V * 10 K

= +
10 K + 3.3K 10 K + 3.3K
LTP = -1.62v

Procedure:
2. Use the available cursor on the simulated window to measure the UTP and LTP values and
compare with the theoretical values.
Result:
Theoretical UTP : ___________ Theoretical LTP : ___________
Practical UTP : _____________ Practical LTP : ____________

Experiment No. 4
WEIN BRIDGE OSCILLATOR
Aim: To simulate Wein Bridge Ocsillator circuit and verify the frequency generated.
Theory:
The Wien bridge oscillator is developed by Maxwien in the year 1981. The Wien bridge oscillator is
based on the bridge circuit it consists of four resistors and two capacitors and it is used for the
measurement of impedance.The feedback circuit is used by the Wien bridge oscillator and the circuit
consists of a series RC circuit which is connected to the parallel RC circuit. The Wien bridge
oscillator is also called as a Wheatstone bridge circuit.
Components and Equipments required:

1) Op-Amp – μA741
2) Resistors - 1k,1k,10k,20k
3) Capacitor – 0.1uf(2 no.)
5) Power supply (±12V) DC voltage
CIRCUIT DIAGRAM:
V2
R1 12V C2
1k 0.1uf
7
U1
3 5
V+
+ OS2
6
OUT
R2 C1 2 1
V-
1k - OS1
0.1uf uA741 R3
4
20k
V1
0 R4
12V 10k
CALCULATION:
1
Frequency of Oscillation fo = = 1.59 K Hz
2* * R *C
Where R=1K, C=0.1uf

WAVEFORM:
Procedure:
2. Use the available cursor on the simulated window to note down the frequency of oscillation.
Results:
Observations/ Quantity Time Period(T) Voltage(V)

Theoretical:
Practical:

Experiment No. 5
POWER SUPPLY
Aim: To determine the working of a power supply and observe the waveforms.
Theory:
Regulated power supply is necessary in some electronic circuits especially in Amplifier circuits.
Poorly regulated power may cause buzzing and unwanted noise in RF and amplifier circuits.Rectifier
is an electronic circuit consisting of diodes which carries out the rectification process. Rectification
is the process of converting an alternating voltage or current into corresponding direct (DC) quantity.
The input to a rectifier is AC whereas its output is unidirectional pulsating DC.Although a half wave
rectifier could technically be used, its power losses are significant compared to a full wave rectifier.
As such, a full wave rectifier or a bridge rectifier is used to rectify both the half cycles of the ac
supply (full wave rectification). The rectified voltage from the rectifier is a pulsating DC voltage
having very high ripple content. But this is not we want, we want a pure ripple free DC waveform.
Hence a filter is used. Different types of filters are used such as capacitor filter, LC filter, Choke
input filter, π type filter. The figure shows a capacitor filter connected along the output of the rectifier
and the resultant output waveform.The output voltage or current will change or fluctuate when there
is a change in the input from ac mains or due to change in load current at the output of the regulated
power supply or due to other factors like temperature changes. This problem can be eliminated by
using a regulator. A regulator will maintain the output constant even when changes at the input or
any other changes occur. Transistor series regulator, Fixed and variable IC regulators or a zener
diode operated in the zener region can be used depending on their applications. IC’s like 78XX and
79XX (such as the IC 7805) are used to obtained fixed values of voltages at the output.
Components and Equipment’s required:

1) Diodes-DIN4007( 1 Nos)
2) Resistor 0.5K,10k
3) Capacitor 470uf
4) Sinusoidal signal generator(Vsin) 12V(PP), 1 kHz
5) LM 7805 IC
Circuit diagram:
U1
D1 LM7805C
1 2
GND
IN OUT
D1N4007
AC = 12 V1 R2
3
FREQ = 1k R1 C1
VAMPL = 12 10k
VOFF = 0 0.5k 470uf
DC = 0

Waveform:
Procedure:
1. Use the available cursor on the simulated window to observe different waveform at various
output points.
Results:

Experiment No. 6
RC COUPLED AMPLIFIER
Aim: To build and simulate CE amplifier (RC coupled amplifier) for its frequency response and
measure the bandwidth.
Theory:
RC Coupled Amplifier is an audio frequency amplifier. It is an amplifier that couples input signal to
the output by coupling capacitors and collector resistance. The amplifier is biased using voltage
divider bias which provides highest stability. The 3db point helps on determining the Bandwidth of
the amplifier. The Amplifier has a bypass capacitor which avoids negative feedback and thus
increases the amplifier gain.
Components and Equipment’s required:

1) Transistor (BJT) – Q2N2222
2) Resistors – 82K, 18K, 4.7K, 1K and 1000K
3) Capacitors – 0.1uf (2 each), 10uf(2 each), 47uf
4) Sinusoidal signal generator(VAC) 20mV(PP), 1 kHz
5) Power supply 10V (VDC)
CIRCUIT DIAGRAM:
82K 4.7K
10uf
10uf
Q2N2222
CRO 10V
Vsin= 1000K
20mv(pp) 18K 1K 47uf
, 1KHz

FREQUENCY RESPONSE:
Vo
In max Vo
volts
max Vo/ √2
0
fL fH Freq
BW = fH - fL
Procedure:
1. Create the schematic shown above using the following steps.
• Double click on “capture CIS” icon on the desktop
• Click on file – New – Project to create a new project
• Name the project (Preferably same name as of the circuit)
• Create the schematic on the schematic window by selecting the parts from the library
and inter connecting them using wires.
• The parts will have default values and are to be changed to the required design values
• Place voltage markers on the input and output ends of the circuit
2. Apply parameters for simulation in the new simulation profile window and click on Run
3. Use the available cursor on the simulated window to note down the bandwidth
Results:
The response of the RC coupled amplifier is simulated and the Bandwidth is _________ Hz

Experiment No 7.
HALF/FULL ADDER AND HALF/FULL SUBTRACTORS
Aim: Realization of Half/Full adder and Half/Full Subtractors using logic gates.
1) AND, OR, NOT, EX-OR gates -02 Nos. each

2) Digital trainer kit.
3) Patch chords.
1) Half adder
Circuit diagram: Truth Table
INPUT INPUT OUTPUT OUTPUT
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
2) Full adder
Circuitdiagram:
Truth Table
INPUT INPUT INPUT OUTPUT OUTPUT

A B CIN S COUT
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0

1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
3) Half Subtractor
Circuit diagram: Truth Table

INPUT INPUT OUTPUT OUTPUT
X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
4)Full Subtractor
Circuit diagram:
Truth Table
INPUT INPUT INPUT OUTPUT OUTPUT

X Y Z D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1

1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Procedure:
1) Make connections as shown in the circuit diagram.
2) Connect input to +5v for logic 1 and to ground for logic 0
3) Verify the truth table.
Experiment No. 8
VHDL CODE TO REALIZE FULL ADDER AND FULL SUBTRACTORS
Aim: Design and develop VHDL code to realize Full adder and Full Subtractors.
Steps in Using the Xilinx software for writing VHDL Code:
1. Double click on “Xilinx ISE 9.1i” icon on the desktop.

2. Click on File- New project.
3. Give a name (preferably same name as the experiment name) and click on next.
4. In the new project wizard select Family as “Automotive Spartan3” and simulator “ISE
simulator (VHDL/Verilog)” and prefer language“VHDL”. Click on next.
5. Click on “New source” and next.
6. Enter the same file name as given in step 3 and select “VHDL module” click on next.
7. Enter the port name, direction and bus information given in the VHDLprogram under Entity.
Click on next.
8. After ensuring the port definition clicks on finish if not go back to re-enter the values for step
7 and then click on next.
9. Click on finish to enter the editor window and enter the VHDL code.
10. Save the file and check for syntax (by expanding codes “synthesize-XST”)
11. Double click on “Create new source” and enter the file name. Select“Test Bench
Waveform” and click on next - next – finish.
12. Select single clock/ combinational under “clock information” and clickon finish.
13. Select the inputs as high and low by clicking the mouse on the required inputs and save.
14. Select “Behavioral simulation” under sources and select “.tbw file”
15. Click on process and expand “Xlinx ISE simulator” and double click on simulate
behavioral module to observe the output waveforms.
16. Use cursor to verify truth table / result
Note: The above steps have to be used for all VHDL simulations.

1) VHDL code for Full adder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entityfull_adder is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end full_adder;
architecture behavioural of full_adder is
begin
sum<= a xor b xor c;
carry<=((a xor b )and c) or (a and b) ;
end behavioural;
Output waveform:
2)VHDL code for Full Subtractor:
library IEEE;
entity full_subtractor is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
difference : out STD_LOGIC;
borrow : out STD_LOGIC);
end full_subtractor;

architecture behavioural of full_subtractor is
begin
difference <= a xor b xor c;

borrow <= ((not a) and b) or ((not(a xor b)) and c);
end behavioural;
Output Waveform:
OBSERVATIONS
1.) What are the errors encountered in conducting the experiment/compilation?
2.) Measures taken to fix the problem (circuit debug/logical errors)?
3.) Results
ASSIGNMENT
1.) Realize the full adder using 3:8 decoder and verify the behavior.
VIVA QUESTIONS
1.) The full adder realized in this experiment is
a.) 4-bit adder b) 2-bit adder c) 3-bit adder d) 1-bit adder
2.) Draw the block diagram for 3-bit parallel adder.
3.) Write the 2’s compliment of the following numbers
a.) 00001111
b.) 01011010
c.) 10111110
4.) Subtract 64 from 89 using 2’s compliment addition.

Experiment No. 9
8:1 MULTIPLEXER
Aim: Given a 4-variable logic expression, simplify it using Entered Variable Map and realize the
simplified logic expression using 8:1 multiplexer IC
1) Multiplexer IC74151.
2) Digital IC Trainer Kit.
3) Patch Chords.
TRUTH TABLE:

A B C D Y
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
IMPLEMENTATION TABLE:
ABC 000 001 010 011 100 101 110 111
D=0 Y=0 Y=1 Y=0 Y=1 Y=1 Y=1 Y=1 Y=1
D =1 Y=1 Y=1 Y=0 Y=0 Y=1 Y=0 Y=1 Y=0
Mux I/P I0 = D I1 = 1 I2 = 0 I3 = D I4 = 1 I5 = D I6 = 1 I7 = D
CIRCUIT DIAGRAM:

D
1
74LS04
2 4 5 Y
3 I0 Z 6
2 I1 Z
I2
1
I3 I
15
14 I4 C
13 I5 7
I6
12
I7 4
1
C 11
B 10 S0 5
S1
A
9
S2
1
7
E
8
16 GND
VCC
74HC151
+5V
0
PROCEDURE:
1. Convert any given Boolean Expression into Σm( ) notation.

2. Write the Implementation table for the given expression.
3. Find the inputs to be applied to the inputs of the Multiplexer.
4. Make connections as per the implementation table.
5. Apply the inputs using Switches on the Trainer kit and verify the output LEDs on the Trainer kit.
6. Verify the truth table
Experiment No. 10

VHDL CODE FOR AN 8:1 MULTIPLEXER
Aim: Design and develop the VHDL code for an 8:1 multiplexer. Simulate and verify it’s working.
VHDL code for 8:1 MUX
library IEEE;
entity mux8to1 is
Port ( sel : in STD_LOGIC_vector(2 downto 0);
din : in STD_LOGIC_vector(7 downto 0);
dout : out STD_LOGIC);
end mux8to1;
architecture Behavioral of mux8to1 is

begin
process(sel,din(7), din(6), din(5), din(4), din(3), din(2), din(1), din(0))
begin
case sel is
when "000"=>dout<=din(7);
when "001"=>dout<= din(6);
when others=>null;
end case;
end process;
end Behavioral;
Output waveform:

OBSERVATIONS

2.) Measures taken to fix the problem(circuit debug/logical errors)
3.) Results
ASSIGNMENT
1.) Realize the Boolean Expression Y= πM(1,2,3,6,8,9,10,12,13,14) using 8:1 Multiplexer IC
VIVA QUESTIONS
1.) Draw the block diagram of a 4:1 multiplexer and a 2:1 multiplexer.
2.) Realize a 8:1 multiplexer using two 4:1 multiplexer and a 2:1 multiplexer.
3.) A circuit with many inputs and only one output is called a ___________________
4.) Write a VHDL code for 4:1 multiplexer.
Experiment No. 11

RING COUNTER
Aim: Design and implement a ring counter using 4-bit shift register and demonstrate its working.
1) Shift Register IC 7495

2) Digital IC Trainer Kit
3) Patch Chords
CIRCUIT DIAGRAM:
Q0
Vcc
Q3 Q2 Q1 Clk1 Clk2
14 13 12 11 10 9 8
IC7495
1 2 3 4 5 6 7
Ds D3 D2 D1 D0 M
Gnd
Procedure:
Experiment No. 12

VHDL code for switched tail counter
Aim: Design and develop the Verilog / VHDL code for switched tail counter.
VHDL code
library IEEE;
entity johnson is
Port ( clk : in STD_LOGIC;
q :inout STD_LOGIC_VECTOR (3 to 0) :="0000");
end johnson;
architecture Behavioral of johnson is
begin
process(clk)
begin
if(clk'event and clk='0') then
q(3)<= not(q(0));
for i in 3 downto 1 loop
q(i-1)<= q(i);
end loop;
end if;
end process;
end Behavioral;
WAVEFORM:
Clk
q3
q2
q1
q0
Procedure: Follow the steps given for simulation of experiment 1b.

OBSERVATIONS
2.) Measures taken to fix the problem (circuit debug/logical errors)
3.) Results
ASSIGNMENTS
1.) Modify the above ring counter circuit to Johnson counter.
2.) Modify the above VHDL code for a ring counter.
VIVA QUESTIONS
1.) List the difference between ring counter and Johnson counter.
2.) List the different type of shift register.
3.) Draw the circuit of a 3-bit ring counter using JK-flip flop.
IC Pin Configuration Sheet:

IC 7400 2 I/P NAND GATE IC 7402 2 I/P NOR GATE
IC 7404 NOT GATE IC 7408 2 I/P AND GATE
IC 7410 3 I/P NAND GATE IC 7432 2 I/P OR GATE
IC 7420 4 I/P NAND GATE IC 7427 3 I/P NOR GATE

IC 7476 JK FLIP FLOP

IC 7411 3 I/P AND GATE
IC 7486 2 I/P EXOR GATE IC 74138 Decoder
IC 74151 8:1 Mux IC uA741 OPAMP

IC 555 Timer
Components names of Analog Circuits
Sl.No Component Name Library Part Code

1 Resistor Analog R
2 Capacitor Analog C
3 Sine wave Source Vsin
4 DC supply Source Vdc
5 Opamp Opamp uA741
6 Diode Diode D1N4007
7 Transistor Bipolar Q2N2222
8 Voltage Regulator Opamp LM7805C
9 Ground GND(0/Source)

List of ADE Lab Experiments
SL.NO LAB EXPERIMENTS PAGE NO

To simulate a positive clipper, double ended clipper & positive clamper
1 circuits using diodes. 6
To simulate a rectangular wave form generator (Op-amp relaxation

oscillator) and compare the frequency and duty cycle with the design 10
2 specifications.
To simulate a Schmitt trigger using Op-amp and compare the UTP and
3 LTP values with the given specification. 10
4 To simulate a Wien bridge Oscillator. 13
5 To determine the working of a power supply and observe the waveforms. 16
6. To build and simulate CE amplifier (RC coupled amplifier) for its 20

frequency response and measure the bandwidth.
22
7. Realization of Half/Full adder and Half/Full Subtractors using logic
gates.
8. Design and develop VHDL code to realize Full adder and Full 24
Subtractors.
9. Given a 4-variable logic expression, simplify it using Entered Variable 27
Map and realize the simplified logic expression using 8:1 multiplexer IC.
10. Design and develop the VHDL code for an 8:1 multiplexer. Simulate 29
and verify it’s working.
11. Design and implement a ring counter using 4-bit shift register and 31
demonstrate its working.
12. Design and develop the VHDL code for switched tail counter. 32
IC Pin Configuration Sheet. 34

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Analog and Digital Electronics Lab REVA University

School of Computer Science and Engineering

Analog and Digital Electronics Lab Manual

Department of Computer Science and Engineering Page 1

Vision of the Department

Mission of the Department

Department of Computer Science and Engineering Page 2

COURSE OBJECTIVE (S):

COURSE OUTCOMES (COs)

CO# Course Outcomes POs PSOs

Identify the different families of digital integrated circuits build, and

Department of Computer Science and Engineering Page 3

BLOOM’S LEVEL OF THE COURSE OUTCOMES

COURSE ARTICULATION MATRIX

Note: 1-Low, 2-Medium, 3-High

Department of Computer Science and Engineering Page 4

SL.NO LAB EXPERIMENTS PAGE NO

To simulate a rectangular wave form generator (Op-amp relaxation

4 To simulate a Wien bridge Oscillator. 13

5 To determine the working of a power supply and observe the waveforms. 16

6. To build and simulate CE amplifier (RC coupled amplifier) for its 20

IC Pin Configuration Sheet. 34

Department of Computer Science and Engineering Page 5

CLIPPING & CLAMPING CIRCUITS

1) Diodes - D1N4007 - 2 Nos.

Department of Computer Science and Engineering Page 6

TRANSFER CHARACTERISTICS: +Vout

B) DOUBLE ENDED CLIPPER

Department of Computer Science and Engineering Page 7

1. POSITIVE CLAMPING CIRCUIT

Department of Computer Science and Engineering Page 8

Department of Computer Science and Engineering Page 9

RELAXATION OSCILLATOR USING OP - AMP

Components and Equipments required:

For the above circuit

Department of Computer Science and Engineering Page 10

Total time period T = TON + TOFF = 0.11mSec + 0.22mSec

TON 0.11m sec

Department of Computer Science and Engineering Page 11

TON TOFF VoMAx Vo MIN Vc MAX Vc MIN Duty

Theoretical 0.11m 0.22m +Vsat = –Vsat = - +βVsat = –βVsat

Department of Computer Science and Engineering Page 12

Components/ Apparatus Required:

Department of Computer Science and Engineering Page 13

For the above circuit:

12V * 3.3K 1.5V * 10 K

− 12V * 3.3K 1.5V * 10 K

Department of Computer Science and Engineering Page 14

Department of Computer Science and Engineering Page 15

WEIN BRIDGE OSCILLATOR

Components and Equipments required:

Department of Computer Science and Engineering Page 16

Observations/ Quantity Time Period(T) Voltage(V)

Department of Computer Science and Engineering Page 17

Components and Equipment’s required:

Department of Computer Science and Engineering Page 18

Department of Computer Science and Engineering Page 19

Components and Equipment’s required:

Department of Computer Science and Engineering Page 20

Department of Computer Science and Engineering Page 21