Examination Paper Analysis

To Winter-23 Summer 23
pic Name of Topic
No. Question Marks Question Marks
Topic 1: Number System 1.(a) 2 1.(a) 2
and Digital Logic Gates 1.(d) 2 1.(d) 2
2.(a) 4 2.(a) 4
2.(d) 4 2.(d) 4
1
3.(a) 4 3.(a) 4
5.(b) 6 5.(c) 6
6.(b) 6
Total 22 Total 28
Topic 2: Combinational 1.(b) 2 1.(b) 2
and sequential Logic 1.(c) 2 1.(c) 2
circuits 2.(a) 4 2.(b) 4
2.(d) 4 2.(c) 4
3.(c) 4 3.(c) 4
2
3.(d) 4 4.(b) 4
4.(b) 4 4.(c) 4
4.(c) 4 4.(e) 4
6.(b) 6
Total 34 Total 28
Topic 3: 16 bit 1.(e) 2 1.(f) 2
Microprocessor 8086 1.(f) 2 3.(d) 4
4.(d) 4 4.(a) 4
3 5.(c) 6 4.(d) 4
6.(a) 6 5.(b) 6
6.(a) 6
Total 20 Total 26
Topic 4: Basic assembly 1.(g) 2 1.(e) 2
language programming 3.(b) 4 1.(g) 2
4 using 8086
5.(a) 6 3.(b) 4
6.(c) 6
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Total 18 Total 8
Topic 5: Assembly 4.(a) 4 5.(a) 6
Language Programming 5.(c) 6
5 using Loops and Total 4 Total 12
Branching instructions

Exam Unit No and Question no as per MSBTE paper Marks

Year Name

Winter - Unit 1 2
2023 Q1 (a) _ Define following terms: (1) Fan in (2) Power dissipation

Ans: - 1. Fan in: Fan-In is defined as the number of inputs the gate has. For e.g. a two-input gate will have
fan- in equal to two.

2. Power dissipation: Power dissipation is the process by which electrical energy is converted into
heat energy. It is measured in Watts. (W)

Q1. (d) _ Draw symbol and truth table of (1) AND gate (2) NOR gate 2
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Winter Unit 1
2023
Q.2 (a) _ Convert the following: (i) (105)10 = (?)2 (ii) (126)8 = (?)16

4
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Q.2(d) _ Implement basic gates using NAND gate only.

Q.3 (a) _ Interpret De Morgan's theorem with its statement &proof.

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Q.5 (b) _ Refer given figure and write the o/p for each of the following input
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----------------------------------------------------------------------------------------------------------------------------- -------------------

Q.1 (b) _ Define the following: (1) Minterm (2) Maxterm

Unit 2
Minterm: A minterm is a product of all variables in a Boolean expression, either in their original form or
complemented in which each variable occurs exactly once. The output result of the minterm
functions is 1.
Example: For a function with three variables (A, B, C), a minterm could be ABC, A'BC, AB'C, A'B'C,
AB'C', A'BC', AB'C', or A'B'C'.

Maxterm: A maxterm is a sum of all variables in a Boolean expression, either in their original form or
complemented in which each variable occurs exactly once. The output result of the maxterm
functions is 0
Example: For the same three variables (A, B, C), a maxterm could be A+B+C, A'+B+C, A+B'+C,
A'+B'+C, A+B+C', A'+B+C', A+B'+C', or A'+B'+C'.

Q.1(c) _ List the difference between level triggering and edge triggering
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1. Level Triggering: Responds to the signal when it is at a specific logic level (e.g., high or low).
2. Edge Triggering: Responds to a specific transition of the signal, rising either edge (transition from low to
high) or falling edge (transition from high to low).

Q. 2(b) _ Explain rules to simplify Boolean expression using K-map

1. Enter 1 / 0 for the cell numbers specified in the expression for SOP / POS from.
2. Identify 1 / 0 that cannot be grouped with adjacent 1 / 0 i.e. identify a single isolated 1 / 0. This is known as
PRIME IMPLICANT & it is represented by all the variables.
3. Identify a group of two adjacent 1 /0 (duplet) either in horizontal or vertical span or in rolling and represent it
with one variable less than total number of variables.
4. Identify a group of four adjacent 1 /0 (quad) either in horizontal or vertical span or in rolling and represent it
with two variables less than total numbers of variables.
5. Identify a group of eight adjacent 1 /0 (octet) either in horizontal or vertical span or in rolling and represent
it with three variables less than total numbers of variables.

Q. 2 (c)_ Draw and explain the working of D flip flop with truth table
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Q.3 (c) Describe JK flip flop with its truth table and logic diagram.
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Q.3 (d) Design half adder using K-map and basic gates

Half Adder: Half Adder is a combinational circuit that performs simple addition of two binary digits.

Half Adder Truth Table: If we assume A and B as the two bits whose addition is to be performed, a truth table
for half adder with A, B as inputs and Sum, carry as outputs can be tabulated as follow
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Q.4 (b) _ Simplify following equation using K-map and realize expression using basic gates
f(A, B, C, D) : €m (1,3,4,5,7,9,11,13,15).

Q.4 (C) _ Differentiate between sequential and combinational circuits (4 points).

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Q.6(b) _ Design 32:1 mux using 8:1 mux.

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Q.1 (e)_ Identify the use of Index Register, Base Pointer and Instruction Pointer
Unit 3

1. Index Register: An index register in a computer's CPU is a processor register (or an assigned
memory location) used for pointing to operand addresses during the run of a program.
2. Base Pointer: Base pointers are used to point the offset address either for the given segment register
or used in accessing parameters passed by stack.
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3. Instruction Pointer: Instruction pointer is used to point to the location from where the instruction is
to be fetched. The content of the instruction pointer is always incremented by one after the instruction
is fetched. It is responsible for sequential execution of instructions.

Q.1 (f)_ List features of 8086

1. It operates on a single +5v power supply.

2. 8086 has 20-bit address lines; hence, it can address 1M byte memory locations.
3. It operates with 5 MHz clock frequency.
4. The 6-byte queue is used in 8086 to speed up instructions’ execution.
5. It has 16-bit multiplexed address/data bus, which reduces the number of pins.
6. The 8086 performs arithmetic and logical operations on bit, byte, and words including multiply
and divide operations.
7. The 8086 operates in minimum and maximum mode. When one microprocessor is used in the
system, the 8086 operates in minimum mode. When two or more processors are used, it operates in
maximum mode.
8. The 8086 supports multiprogramming.
9. It provides 16-bit registers like AX, BX, CX, DX, index register SI and DI, base pointers BP and
stack pointer SP.
10. It consists of four segments CS (code segment), DS (data segment), ES (extra segment), and SS
(stack segment).

Q.4 (d) _Describe pipelined architecture concept of CISC, which helps in improving system throughput.

Pipelining in CISC Processors.

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RISC style instructions provide ease to implement pipelining as they all are of one word. The operands
of all the instructions are present in the same position within the word. Excluding Load and Store
instructions, all other instructions operate on the register operands.
So, it becomes easy to implement pipelining for RISC style instructions. But the same is not the case
of CISC style instructions. CISC instructions are of “variable length”, they have “multiple operands”,
“complex addressing modes” & “complex instructions”.

Now, CISC instruction occupies more than a memory word. So, it will take several cycles for operand
fetch. Further, we know instructions are of variable sizes and format, this complicates the decoding
of instruction and operand fetch. That’s why implementing pipelining to CISC style instructions is a
complicated task. Let us understand this with the help of an example:
Move (R2), (R3)
Move (R4), R5

In the first Move instruction, the effective address of both the operands is a memory location. So, it
will require two memory accesses.

In the second Move instruction, the effective address of the „first operand‟ is a memory location and
effective address of the „second operand‟ is a register. The second instruction needs only one memory
access.

Here, the second Move instruction needs to be stalled so sthat the first Move instruction can complete
accessing of both the operands from the memory. Hence, implementing pipelining to CISC style
instructions is quite complicated
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Q.5(C) _ Draw maximum mode configuration of 8086 and explain any four-control signal generated by
bus controller.

• When MN/ MX‟ = 0, 8086 works in max mode.

• Clock is provided by 8284 clock generators.
• Control signals for all operations are generated by decoding S‟2, S‟1 and S‟0 using 8288
bus controller.
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Q.6(a) _ Calculate the physical address of the following. (1) 4370 H : 561E H (2) 7A32 H : 6028H. Also
explain the process of calculating the physical address.\
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The content of a segment registers also called as segment address, and content of an offset register
also called as offset address. To get total physical address, put the lower nibble 0H to segment address
and add offset address. The figure shows the formation of 20-bit physical address.
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Unit 4
Q.1(g) _ List any four addressing modes of 8086 and give one example of each.

1. Immediate addressing mode: MOV Al, 23H

2. Register addressing mode: MOV AX, BX
3. Memory direct addressing mode: MOV AL, [2000H] Memory Indirect addressing mode: ADD Dl,
[BX + 1234H]
4. Implied Addressing mode: STC

Q.4(b) _ Describe any four logical instructions with example

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Q.5(a)_ Interpret the given program and specify the o/p for the following situations:

MOV AX, 3459 H,

MOV BX, 3A69H

(i) Masking of lower nibble of AX

(ii) Rotate Right through carry contents of BX by 4 positions
(iii) Shift left content of BX by 6 positions
(iv) XOR AX, BX
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Q.6 (c) _ Identify the addressing mode of the following instruction

(1) MOV AL, [3000H]

(2) MOV AX, [BX+SI]
(3) ADD AL, [BX+04]
(4) MOV BX,0354H
(5) MOV AL, BL
(6) MOV AX, [BX+SI+04]

(1) MOV AL, [3000 H]: Direct addressing mode

(2) MOV AX, [BX+SI]: Based Indexed addressing mode
(3) ADD AL, [BX+04]: Based Addressed with displacement addressing mode
(4) MOV BX, 0354 H: Immediate addressing mode
(5) MOV AL, BL: Register addressing mode
(6) MOV AX, [BX+SI+04]: Base Indexed Addressing with displacement addressing mode
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Unit 5 Q.4(a)_ Write 8086 assembly language program with algorithm to add two 16 bit numbers.
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Summer 2023
Chapter 1
1. (a)_Define - Word & Nibble

1. Word: - A group of 16 binary bits is called as a Word. Ex. 1011 0010 1100 0101
2. Nibble: - A group of 4 binary bits is called as a Nibble. Ex. 1011

1. (b)_State any one application of 1. OR gate 2. AND gate

Ans
1. OR Gate
• Simple Alarm System: An OR gate can be used to trigger an alarm if either of two conditions are met. For example, if a door sensor or a motion sensor
detects activity, an OR gate can be used to activate the alarm.

2. AND Gate
• Security System: An AND gate can be used to ensure that multiple conditions must be met for a security system to be activated. For instance, a security
system might require both a valid password and a fingerprint scan to grant access. An AND gate would ensure that both conditions are necessary for
the system to allow entry.

2. (a)_Convert decimal numbers 129 and 181 into Binary.

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Q.2 (d) _ Simplify the following expression and draw logic diagram: Y = (A B’ + A + B’) A · B
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Q.3(a) _ Design the following gates using universal logic gate and write their truth table : (i) OR (ii) NOT

Or gate using Nand Gate;

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Q.5(c) _ Explain binary to Gray code conversion with suitable example.

1. The MSB (Most Significant Bit) of the gray code will be exactly equal to the first bit of the given binary number.
2. The second bit of the code will be exclusive-or (XOR) of the first and second bit of the given binary number, i.e if both the bits are same
the result will be 0 and if they are different the result will be 1.
3. The third bit of gray code will be equal to the exclusive-or (XOR) of the second and third bit of the given binary number. Thus the binary
to gray code conversion goes on. An example is given below to illustrate these steps.
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Q.6(b) _Given the following logic diagram in Fig. (1), write its truth table. Identify equivalent gate for the obtained truth table.

A B Y
0 0 0
0 1 1
1 0 1
1 1 0
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Chapter 2

Q.1 _ (b) State the number of select lines for (i) 8 : 1 Mux (ii) 4 : 1 Mux

No of selected lines can be given by N=2n

Where N= No of Inputs to the mux
n = No of select lines

therefore,
1) Mux having 8 inputs will have
N=2n
8=23

3 select lines

2) Mux having 4 inputs will have

N=2n
4=22

2 select lines.

Q.1 _ (c) State any four applications of flip-flops.

Application -
1) Memory Devices – SRAM, DRAM
2) Digital Logic Circuits – Latches, Clock Generation
3) Microprocessor
4) Microcontrollers
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5) Sequential circuits – Registers, Counter

Q.2 _ (b) Simplify the given minterm into standard SOP form Y{A, B, C, D} = {A + C’ + D) + ( B’ + C + D’)

Y{A,B,C,D} = {A+C’+D+B’+C+D’}…………..(Open the brackets)

= {A+1+1+B’}…………………….(C+C’ = 1 and D+D’ =1)

= 1…………………………………(1+A =1)

Q.2 _ (c) Draw symbol and truth table for SR and T-Flip-flop.

1. S-R Flip Flop

Symbol Truth Tab

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2. T Flip Flop

Symbol Truth Table

Q.2 _ (d) Simplify the following expression and draw logic diagram : Y = (A B’ + A + B’) A · B
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Q.3 _ (c) Represent following expression using MUX : Y = m (0, 3, 5, 9, 10, 12, 14)
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Q.4 _ (b) Draw and explain Half Adder and specify its truth table.

A half-adder is a digital circuit that performs the addition of two single bits. It produces a sum bit and a carry bit as its output.
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Logical Expression for Sum

Y=A’B + AB’ = A XOR B

Logical Expression for Carry

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Y = A and B

Implementation

Q.4 _ (c) Draw symbols and write truth table for : (i) JK-Flip-flop (ii) D-Flip-flop
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D flip Flop

Symbol
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Q.4 (e) _ With suitable example, explain types of triggering the flip-flop.

There are four types of triggering in Flip flop

Flip flop Triggering ----- 1) Level Triggering ------- A) Positive Level Triggering
B) Negative Level Triggering

------2) Edge Triggering-------- A) Positive Edge Triggering

B) Negative Edge Triggering
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Chapter 3
Q.1 (d) _ State applications of segment and pointer registers.

Applications of segment register

1) Memory Management: Segment registers like CS (Code Segment), DS (Data Segment), SS (Stack Segment), and ES (Extra
Segment) help manage different segments of memory. This segmentation allows for more efficient memory use and protection.
2) Address Calculation: They are used to calculate the physical address by combining the segment address with an offset. This is
essential for accessing memory locations.
3) Code Execution: The CS register points to the segment containing the current program code, ensuring the CPU executes the correct
instructions

Applications of pointer registers

1) Instruction Pointer (IP): This register holds the address of the next instruction to be executed. It ensures the CPU fetches instructions
in the correct sequence.
2) Stack Pointer (SP): Used to manage the stack, which is crucial for function calls, local variable storage, and handling interrupts.
3) Base Pointer (BP): Often used in stack frame management, helping to access function parameters and local variables.

Q.3 (d) _ Compare Min. and Max. mode of operation of 8086.

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Q.4 (a) _ Explain the process of physical address calculation with suitable example.

Physical Address Generation :

• 8086 contain memory of 1MB which is divide into 4 segments. Each segment has it
own base / segment register to return the base address and a offset / special
register to return the offset address of the data in the segment.
• Thus there are 4 type of segment register and 5 type of offset registers namely –
CS , SS , DS , ES and IP , SP , BP , SI , DI.
• This segment address and the offset address are required to calculate the physical
address of the data in the segment. There is a formula use to calculate the physical
address as –
• Physical address = segment address * 10H + offset address.
• Example: we have 3000H as segment address and 0123H as offset address then
• Physical Address = 3000H * 10H + 0123H
• = 30123H

Q.4 (d) _ Compare CISC with RISC processor (at least four points).
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Q.5 (b) _ State and explain concept of memory segmentation and pipelining

• Segmentation means dividing the memory into logically different

parts called segments.
• Here the memory is divided into 4 segments: Code, Stack, Data
and Extra.
• The max size of a segment is 64KB and the minimum size is 16
bytes.
• Moreover, dividing Code, stack and Data into different segments,
makes the memory more organized and prevents accidental
overwrites between them.
• The Maximum Size of a segment is 64KB because offset
addresses are of 16 bits. 216 = 64KB.

As max size of a segment is 64KB, programmer can create multiple

Code/Stack/Data segments till the entire 1 MB is utilized, but only one
of each type will be currently active
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Concept of Pipelining
▪ 8086 Microprocessor uses Pipelined structure for executing the instructions.
▪ On a pipelined processor, fetch, decode and execute are performed in parallel
and only 5 clock cycles are required to execute three instructions
▪ Fetching the next instruction while executing the current instruction is called
pipelining.
▪ BIU Fetches the next six byte instruction from the code segment and stores it
into the queue.
▪ Execution Unit (EU) removes instruction from the queue and executes them.
▪ Queue is refilled when at least two bytes are empty as 8086 has a 16 bit data
bus.
▪ Pipelining increases the efficiency of the microprocessor.
▪ Pipelining fails when a branch occurs, as the pre-fetched instruction are no
longer useful.
▪ Hence as soon as 8086 detects a branch operation, it clears/discards the entire
queue.
▪ Now the next six bytes from the new location (branch address) are fetched
and stored in the queue and pipelining continues

Q.6 (a) _ Describe pipeline architecture concept of CISC which help in improving system throughput.
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Chapter 4
Q.1 (e) _ List different addressing modes of 8086

ANS : The addressing mode of the 8086 are: ( write any two )
(1) Intermediate addressing mode : In this mode the operand is itself specified in the instruction.
MOV CL , 04H
(2) Direct addressing mode : In this mode the address of the operand is used in the instruction
MOV CL , [0123H]
(3) Register addressing mode : In this mode the operand is specified using the register in the instruction.
MOV CL , BL
(4) Register indirect addressing mode : In this the address of the operand is specified in the register in the instruction.
MOV CL , [BL]
(5) Register relative addressing mode : In this addressing mode the address of the operand is calculated using base register and the 8 to 16 bit
displacement.
MOV CL , [ BX + 05H ]
(6) Base index addressing mode : In this addressing mode the address of the operand is calculated using base register and the index register.
MOV CL , [ BX + IP ]
(7) Base index relative addressing mode : In this mode the address of the operand ois calculated using the base register , index register and the 8 to
16 bit displacement.
MOV CL , [ BX + IP + 0123H ]
(8) Implied addressing mode : In this mode the operand is implied i.e. the operand is not specified in the instruction.
STC

Q.1 (g) _ State any two shift instructions of 8086 with format
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Q.3 (b) _ Interpret the following program and specify the output of the following situation:
MOV BX, 55F9 H
MOV AX, 3A69 H
(i) Masking of higher nibble of AX (ii) Rotate left through carry contents of BX by four positions. (iii) Shift left contents of AX
by 6 position (iv) ADD AX, BX

1) Masking of higher nibble of AX ----------------------------------------------------------------------------In this case Ax = 3000 H

AND content of AX by masking word F000H

Ax 0 0 1 1 1 0 1 0 0 1 1 0 1 0 0 1
Mask 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Word
Ans 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
(AX) 3 0 0 0
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2) Rotate left through carry contents of BX by four positions ------------------------------------------ Considering CF =1 _____ in
this case After execution, Content of BX = 5F9A with CF = 1

3) Shift left contents of AX by 6 positions------------------In this case After execution, Content of AX = 9A40 H with CF = 1

Ax 0 0 1 1 1 0 1 0 0 1 1 0 1 0 0 1
Ax_1 0 1 1 1 0 1 0 0 1 1 0 1 0 0 1 0
Ax_2 1 1 1 0 1 0 0 1 1 0 1 0 0 1 0 0
Ax_3 1 1 0 1 0 0 1 1 0 1 0 0 1 0 0 0
Ax_4 1 0 1 0 0 1 1 0 1 0 0 1 0 0 0 0
Ax_5 0 1 0 0 1 1 0 1 0 0 1 0 0 0 0 0
Ax_6 1 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0
ANS 9 A 4 0

4) ADD AX, BX-----------------------------------After execution of this instruction content of Ax register will be Ax = 9062 H

Ax 0 0 1 1 1 0 1 0 0 1 1 0 1 0 0 1
Bx 0 1 0 1 0 1 0 1 1 1 1 1 1 0 0 1
Carry 1 1 1 1 1 1 1 1 1 1 1 1 1
Ans 1 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0
(AX) 9 0 6 2
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Chapter 5
Q.5 (a) _ Write ALP to multiply 8-bit number and 16 bit number.
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Q.6 (c) _ Write ALP for finding smallest number from Array of ‘n’ numbers
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