Evt de U3 01

UV Patel College of Engineering
Bachelor of Technology - Electrical Engg. (EVT) Topics Covered:

IV Sem
DIGITAL ELECTRONICS Adders &
Unit-III Subtractors
Combinational Digital Circuits
Q.1 What is a Combinational Circuit and its features?

A combinational circuit is the digital logic circuit in which the output depends on the
combination of inputs at that point of time with total disregard to the past state of the inputs.
The digital logic gate is the building block of combinational circuits. The function
implemented by combinational circuit is depend upon the Boolean expressions.
Features of Combinational Circuit:
 In this output depends only upon present input.
 Its Speed is fast.
 Easy designed.
 There is no feedback between input and output.
 It is time independent.
 Elementary building blocks are Logic gates.
 Used for both arithmetic and Boolean operations.
 Combinational circuits don’t have the capability to store any state.
Q.2 Give the Classification of Combinational Logic Circuits,

1. Arithmetic:
Adders
Subtractors
Multipliers
Comparators
2. Data Handling:
Multiplexers
De-Multiplexers
Encoders and Decoders
3. Code Converters:
BCD to Excess-3 code and vice versa
BCD to Gray code and vice versa
IV Sem B.Tech. (EVT) 1

Q.3 What is Half Adder?

A combinational logic circuit that performs the addition of two single bits is called Half
Adder. It is a arithmetic combinational logic circuit designed to perform addition of two
single bits. It contains two inputs and produces two outputs.
Q.4 Explain and design a Half Adder circuit using logic gates.
Half-adder is used to add two bits. Therefore, half-adder has two inputs and two outputs, with
SUM and CARRY. Figure shows the truth table of a half adder.
Let us observe the addition of single bits,
0+0=0
0+1=1
1+0=1
1+1=10
Since 1+1=10, the result must be two-bit output. So, Above can be rewritten as,
0+0=00
0+1=01
1+0=01
1+1=10
The result of 1+1 is 10, where ‘1’ is carry-output (Cout) and ‘0’ is Sum-output (Normal
Output).
K-map for output variable Sum ‘S’ K-map for output variable Carry ‘C’

K-map is of Sum of products form. The equation obtained is

S = AB' + A'B
which can be logically written in XOR operation form as,
S=A⊕B
The equation obtained from K-map is,
C = AB
Using the Boolean Expression, we can draw logic diagram of Half Adder as follows
Q.4 Explain and design a Full Adder Circuit.

Full Adder is the adder that adds three inputs and produces two outputs. The first two inputs
are A and B and the third input is an input carry as C-IN. The output carry is designated as C-
OUT and the normal output is designated as S which is SUM.
 To overcome the limitation faced with Half adders, Full Adders are implemented.
 It is a arithmetic combinational logic circuit that performs addition of three single bits.
 It contains three inputs (A, B, Cin) and produces two outputs (Sum and Cout).
 Where, Cin = Carry In and Cout = Carry Out

K-map for SUM: K-map for Cout:
The equation obtained is,

S = A'B'Cin + AB'Cin' + ABC + A'BCin'
The equation can be simplified as,

S = B'(A'Cin+ACin') + B(AC + A'Cin')
S = B'(A xor Cin) + B (A xor Cin)'
S = A xor B xor Cin
Cout = B Cin + A B + A Cin
Q.5 Explain & design Half Subtractor circuit.

• The half subtractor is also a building block for subtracting two binary numbers. It has
two inputs and two outputs.
• This circuit is used to subtract two single bit binary numbers A and B. The 'diff' and
'borrow' are two output states of the half subtractor.

The Boolean expression of the Half Adder circuit is given below:

Diff = A'B+AB' = A XOR B = (A⊕B)
Borrow = A'B
In the block diagram, we have seen that it contains two inputs and two outputs. The carry and
sum are the output states of the half subtractor.
The half subtractor is designed with the help of the following logic gates:
• 2-input AND gate.
• 2-input Exclusive-OR Gate or Ex-OR Gate
• NOT or inverter Gate

Q.6 Explain & design Full Subtractor circuit.


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UV Patel College of Engineering

Bachelor of Technology - Electrical Engg. (EVT) Topics Covered:

Q.1 What is a Combinational Circuit and its features?

Q.2 Give the Classification of Combinational Logic Circuits,

IV Sem B.Tech. (EVT) 1

Q.3 What is Half Adder?

IV Sem B.Tech. (EVT) 2

K-map is of Sum of products form. The equation obtained is

Q.4 Explain and design a Full Adder Circuit.

IV Sem B.Tech. (EVT) 3

K-map for SUM: K-map for Cout:

The equation obtained is,

The equation can be simplified as,

Cout = B Cin + A B + A Cin

Q.5 Explain & design Half Subtractor circuit.

IV Sem B.Tech. (EVT) 4

The Boolean expression of the Half Adder circuit is given below:

IV Sem B.Tech. (EVT) 5

Q.6 Explain & design Full Subtractor circuit.

IV Sem B.Tech. (EVT) 6

IV Sem B.Tech. (EVT) 7

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