EEE 3103 Spring 2020 Final Question
EEE 3103 Spring 2020 Final Question
EEE 3103 Spring 2020 Final Question
Examination: 27/05/2021
:
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PART A
The answer script (one single pdf file) of this part (Part A) must be uploaded at designated location in
the provided google form link(https://forms.gle/nYEkruYbg43f6vWd7)available in the google classroom.
a) Describe a logic circuit with input signal A, control input B, and outputs X and Y to [3]
operate as follows:
i. When B=1, output X will follow input A, and output Y will be 0.
ii. When B=0, output X will be 0, and output Y will follow input A.
b) If the last digit of your student ID>5, describe a logic circuit to produce a HIGH output [5]
only if the input, represented by a 4-bit binary number ,is greater than twelve or less than
three,
Else define a logic circuit with four input variables that will only produce a 1 output when
exactly three input variables are 1s.
F(x,y,z)=Σ(0,6)
[5]
b)
Figure 2(b)
Figure 2(b) shows four switches that are part of the control circuitry in a copy machine.
The switches are at various points along the path of the copy paper as the paper passes
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through the machine. Each switch is normally open, and as the paper passes over a switch,
the switch closes. It is impossible for switches SW1 and SW4 to be closed at the same time.
Describe the logic circuit to produce a HIGH output whenever two or more switches are
closed at the same time. Use K mapping and take advantage of the don’t-care conditions.
c) [2]
Figure 2(c)
Figure 3(a)
Interpret the expression for the output of Figure 3(a), and use it to compute the complete
truth table.
c) If the last digit of your student ID is an even number, demonstrate the parity generator’s [2]
output for each of the following sets of input data, D3D2D1D0: (a) 0111; (b) 1001; (c) 0000;
(d) 0100 for an even parity system ,
else assess the parity generator’s output for an odd parity system.
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Question 4. [Marks: 10]
a) Using four MSI circuits (IC 74283), build a binary parallel adder to add two 14-bit binary [3]
numbers. Label all carries between the MSI circuits.
b) A 4 to 1 multiplexer has inputs B,C connected to the selection inputs S1 and S0 respectively. [5]
The data inputs I0 through I3 are as follows:
I0 =0, I1 =1, I2 =A and I3=A’
Construct the Boolean function that the multiplexer implements.
c) Construct a full –subtractor circuit with three inputs, x, y, Bin, and two outputs Diff and Bout. [2]
The circuit subtracts x-y-Bin, where Bin is the input borrow, Bout is the output borrow, and
Diff is the difference.
PART B
The answer script (one single pdf file) of this part (Part B) must be uploaded at designated location in
the provided google form link (https://forms.gle/2t1iGQDG36NLZFL68) available in the google classroom.
a) Analyze an active low JK flipflop with preset and clear option. Show the timing diagram [3]
also.
b) If there is any Sensor circuit A as Figure 5(b), which will detect any object and whenever [7]
there is any object in front of the sensor it will give output 0 otherwise 1. There is another
system, C consisting Seven segment display which will show output between 0-9
corresponding to the BCD input of the system.
i. Determine a digital circuit for system B which will take the output of A system and
provide input to the C system and it’ll count how many object is coming in front
of the sensor, highest value will be 9 then system C output will be 0 again.
ii. To show two digits in the output identify necessary modifications in the circuit.
Figure 5(b)
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Question 6. [Marks:10]
a) Designate a 4 bit synchronous counter where after each clock pulse output will be each [5]
unique digit of your student ID.( for example if student ID is 180105027 then counter
sequence will be like 1->8->0->5->2->7->1)
b) Evaluate a universal shift register that can perform both serial input shifting and parallel [5]
input loading. Your design should follow the following conditions (Sum last 6 digits of
your ID. If it's an odd no then X=0, Y=1; if it's even no than X=1, Y=0).
S1 S0 Operation
X X Parallel input
Y X Left shift
Y Y Right shift
X Y No change
Question 7. [Marks:10]
a) Determine a 3 bit up/down synchronous counter with a gray code sequence. The counter [5]
should count up when control bit is 1 and count down when the control bit is 0.
i. Evaluate the state diagram for the condition stated in the above question.
ii. Recommend the logic circuit using D flip flop.
b) With necessary circuit and timing diagrams assess the operation of a positive edge [5]
triggered asynchronous decade counter (MOD-X).
If sum of last three digit of your ID is greater than or equal to 7 then X= 19
If sum of last three digit of your ID is less than 7 then X= 18
Question 8. [Marks:10]
a) A digital system is illustrated using following State Diagram as Figure 8(a) [5]
Figure 8(a)
[ if sum of last 2 digits of your ID is even then M= 10, N=01, P=11, X=10, Y=00 , Z=01
If sum of last 2 digits of your ID is odd then M= 11, N=10, P= 00, X=01, Y=11, Z=11]
i. Revise the State Table of the above system. Also recommend the excitation table for
D, T and J-K flip-flop.
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ii. Recommend the system using D flip-flops.
b) If There is a system with three push buttons Red, Green and Black. Whichever button will [5]
be pressed (value 1) corresponding color LED will be on. For example if red push button
is pressed then Red Led will be on same for others. If more than one button is pressed
simultaneously then Green button will have highest priority then Black then Red. If no
button is pressed then Yellow led will be on.
Recommend an encoder circuit which will check push button state and provide required
output to turn on respective light.
[In the system to turn ON Red Led encoder output should be 101, to turn ON Green Led
encoder output should be 110, to turn ON Red Led encoder output should be 011, to turn
ON yellow Led encoder output should be 111, no need to design the part of the circuit
which will take these encoder binary output values and turn on respective Leds]
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