Semiconductor

Manufacturing Technology
Michael Quirk & Julian Serda
© October 2001 by Prentice Hall

Chapter 3

Device Technologies

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 Objectives
After studying the material in this chapter, you will be able to:

1. Identify differences between analog and digital devices and passive and
active components. Explain the effects of parasitic structures in passive
components.
2. Describe the PN junction, why it is important, and explain reverse and
forward biasing.
3. State the characteristics of bipolar technology and the bipolar junction
transistor in terms of function, biasing, structure and applications.
4. Explain the basic characteristics of CMOS technology, including the field
effect transistor, biasing and the CMOS inverter.
5. Explain the difference between enhancement and depletion mode
MOSFETs.
6. Explain the effects of parasitic transistors and the implications for CMOS
latchup.
7. Give examples of IC products and state some applications of each.
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 Circuit Types

• Analog Circuits
– Radio transceivers, audio, automotive ignition
• Digital Circuits
– Computer, calculator, “high” or “low”

3/38
Components on Printed Circuit Board

Photo 3.1 4/38

 Passive Component Structures
An active element is capable of generating energy while a passive element is not.

• IC Resistor Structures (R)

– Parasitic Resistor Structures
• IC Capacitor Structures (C)
– Parasitic Capacitance Structures
• IC Inductor Structures (L)

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Examples of Resistor Structures in ICs

Metal contact
Metal contact
Film type resistor

SiO2, dielectric
material
SiO2, dielectric
material

Metal film type Diffusion dopant

Figure 3.1 6/38

 Cross Section of Parasitic Resistances
in a Transistor

Base Emitter Collector Metal contact resistance

RBC REC RCC

RBB REB RCB

n+
p-
n+
Bulk resistance
p- Substrate

• It reduces the operational performance of IC devices.

• Higher density comes higher resistance .

Figure 3.2 7/38

 Examples of Capacitors Structures in ICs
Metal contact
to 1st poly
Metal contacts
2nd doped
poly layer

1st doped
poly layer
Substrate Substrate
Dielectric material
(oxide)

2nd, n+ poly
Doped poly layer plate
Metal contact
to diffused region 1st, n+ poly
plate

Substrate Substrate
Dielectric material
(oxide)

Figure 3.3 8/38

 Parasitic Capacitance in Transistors

G
E B C S D doped poly

n
n n n
p
n oxide

p- Substrate p- Substrate

Bipolar junction transistor Field effect transistor

• Parasitic capacitance may create instability in

circuits, even short-circuit paths for AC signals
where they are not need.

Figure 3.4 9/38

Integrated-Circuit Inductor

L ~ n2

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 Active Component Structures

• Used to control current direction and

amplify small signal
• The pn Junction Diode
• The Bipolar Junction Transistor
• Schottky Diode
• Bipolar IC Technology
• CMOS IC Technology
• Enhancement and Depletion-Mode
MOSFETs
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 Basic Symbol and Structure
of the pn Junction Diode

pn junction diode
Heavily doped p region
Cathode Anode Heavily doped n region

Metal contact

p- Substrate

Figure 3.5 12/38

Open-Circuit Condition of a pn Junction Diode
Depletion
region

}
p-type Si n-type Si Metal contact

Anode Cathode

Potential
hill

Charge distribution
of barrier voltage Barrier
0
voltage
across a pn Junction.

Figure 3.6 13/38

Reverse-Biased PN Junction Diode
Open-circuit condition
(high resistance)
p n

3V Lamp

Figure 3.7 14/38

Forward-Biased PN Junction Diode

p n

Hole flow Electron flow

3V
Lamp

Figure 3.8 15/38

 Forward and Reverse Electrical
Characteristics of a Silicon Diode
+I

Forward bias
curve

Junction voltage
120 100 80 60 40 20
-V +V
Leakage .4 .8 1.2 1.6
current
Breakdown
voltage

Reverse bias
curve

-I

Figure 3.9 16/38

 Two Types of Bipolar Transistors
npn transistor Collector pnp transistor Collector

Physical structure n Physical structure p

Base p Base n

n p

Emitter Emitter
Schematic symbol C Schematic symbol C

B B

E E

• The emitter arrows indicate the direction of hole or current. 17/38

 NPN Transistor Biasing Circuit
h+
C C

n n
Lamp Lamp

Electron
S1 S1
B B
p p

flow
n 3V n 3V
1.5 V 1.5 V

E E
e- e-

Nonconduction mode Conduction mode

Figure 3.11 18/38

 PNP transistor biasing circuit
e-

C C

p p
Lamp Lamp
S1

Hole flow
S1
B B
n n

p 3V p 3V
1.5 V 1.5 V

E E
h+ h+

Nonconduction mode Conduction mode

Figure 3.12 19/38

 Cross Section of an NPN BJT

C E B
Metal contact

n+
p
n+
p- substrate

Figure 3.13 20/38

 Schematic Symbol and Structural Cross
Section of the Schottky Diode

Anode Cathode
Schottky contact Normal ohmic contact

n-
n+

• The forward junction voltage drop 0.3~0.5 V is nearly half that of pn-junction 0.6~ 0.8V.
• It formed when metal is brought in contact with lightly doped n-type semiconductor materials.
• Faster switching than pn diode, no minority.
Figure 3.14 21/38
 Bipolar Logic Families
• It has fast speeds, durability, and power-controlling ability
• The biggest drawback is high power consumption
Table 3.1
Bipolar Logic Families
Bipolar Logic Family Abbreviation
Direct-Coupled Transistor Logic DCTL1
Resistor-Transistor Logic RTL2
Resistor-Capacitor-Transistor Logic RCTL3
Diode-Transistor Logic DTL4
Transistor-Transistor Logic* TTL5
Schottky TTL Logic* STTL6
Emitter-Coupled Logic* ECL7

1
G. Deboo and C. Burrous, Integrated Circuits and Semiconductor Devices: Theory and Application, 2nd
edition, McGraw-Hill, New York, NY, 1977, p. 192.
2
G. Deboo and C. Burrous, ibid.
3
G. Deboo and C. Burrous, ibid.
4
G. Deboo and C. Burrous, ibid.
5
G. Deboo and C. Burrous, ibid.
6
A. Sedra, K. Smith, Microelectronic Circuits, Oxford University Press, 1998, p. 1187.
7
A. Sedra, K. Smith, Microelectronic Circuits,Table 3.1University Press, 1998, p. 1196.
Oxford 22/38
 BJT vs. MOSFET

• FET is a voltage-amplifying device, BJT is a

current-amplifying device
• Greatest advantage: low voltage and low power
operation
• BJT requires input current to turn on, FET as a
result of electric field created by gate voltage- thus
the name field-effect transistor
• It has infinite Rin and moderate gain make it an
excellent device for use in instrumentation and
communications.
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 CMOS IC Technology
• The Field Effect Transistor (less power)
– MOSFETs
• nMOSFET
• pMOSFET
– Biasing the nMOSFET
– Biasing the pMOSFET
• CMOS Technology
• BiCMOS Technology
• Enhancement and Depletion-Mode

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 Two Types of MOSFETs
pMOSFET nMOSFET
(p-channel) (n-channel)
Gate Gate
Source Drain Source Drain
p+ p+ n+ n+
n-type silicon substrate p-type silicon substrate

Drain Drain

Gate Gate Substrate

Substrate

Source Source
Figure 3.15 25/38
Biasing Circuit for an NMOS Transistor
S1

Open gate (no charge)

VGG = + 0.7 V

Gate
Source Drain
n+ n+

p-type silicon substrate

Lamp
(no conduction)

VDD = + 3.0 V

Figure 3.16 26/38

NMOS Transistor in Conduction Mode
S1

VGG = + 0.7 V Positive charge

Gate
e- ++++++
++++++
Source ++++++ Drain IDS
n+ n+
Holes Lamp
p-type silicon substrate

e- e-

VDD = + 3.0 V

Figure 3.17 27/38

Example of Characteristics Curves
of an N-channel MOSFET
600 Linear Region Saturation Region
VGS = +5V
500

VGS = +4V
Drain Current, IDS (ma)

400

300 VGS = +3V

200
VGS = +2V

100 VGS = +1V

0
0 1 2 3 4 5 6
Drain-Source Voltage, VDS (volts)

Figure 3.18 28/38

Biasing Circuit for a P-Channel MOSFET
S1
Open gate (no charge)
VGG = - 0.7 V
Gate
Source Drain
p+ p+

n-type silicon substrate

Lamp
(no conduction)

VDD = -3.0 V

Figure 3.19 29/38

PMOS Transistor in Conduction Mode
S1

VGG = - 0.7 V Negative charge

Gate
--------
e- Source
--------
-------- Drain IDS
p+ p+
Electrons
n-type silicon substrate Lamp

e- e-
VDD = - 3.0 V

Figure 3.20 30/38

Schematic of a CMOS Inverter
+ VDD

S
G
pMOSFET

Input Output

nMOSFET
G
S

- VSS

Figure 3.21 31/38

 Top View of CMOS Inverter
n-type silicon substrate

Polysilicon

n-well p-well

+VDD G G -VSS
S D D S
Metal
p+ p+ n+ n+

pMOSFET nMOSFET

Figure 3.22 32/38

 Cross-section of CMOS Inverter

Interlayer Metal
Oxide
pMOSFET nMOSFET
G G -VSS
+VDD S D D S

n+ p+ p+ n+ n+ p+
p-well

n-type silicon substrate

Field oxide

Figure 3.23 33/38

 BiCMOS Chips used in the Control of a
Simple Heating System
• BiCMOS technology makes use of the best feature of both CMOS and bipolar technology.
• BiCMOS incorporates the low-power, high-density CMOS with high current drive capability of BJT.

+ 48 VDC Process
chamber
Setpoint
Drive signal
BiCMOS 0-5 V
Output AMP
DAC
Heating
CPU Digital Analog element
Temperature
side side sensor

BiCMOS 0-5 V
Input AMP
ADC
Feedback
mV Measured signal

Figure 3.24 34/38

 Simple BiCMOS Inverter

CMOS Bipolar
section section

Q1
Q3

INPUT

OUTPUT
Q2

Q4

Redrawn from H. Lin, J. Ho, R. Iyer, and K. Kwong, “Complementary MOS-Bipolar Transistor
Structure,” IEEE Transactions Electron Devices, ED-16, 11 Nov. 1969, p. 945 - 951.

Figure 3.25 35/38

Comparison of Enhancement and
Depletion Mode MOSFETs
MOSFET Mode Standby VGG Switching Physical Structure
Type Condition Requirements
nMOS Enhancement Off + Gate
Source Drain
n+ n+
p-type silicon substrate

nMOS Depletion On - Gate

Source Drain
n+ n+
p-type silicon substrate
p-type silicon substrate

pMOS Enhancement Off - Gate

Source Drain
p+ p+
n-type silicon substrate

pMOS Depletion On + Gate

Source Drain
p+ p+
n-type silicon substrate

Figure 3.26 36/38

 Latchup in CMOS Devices

pMOSFET nMOSFET

VDD G G
S D D S VSS

n+ p+ p+ n+ n+ p+
RW

T1
T2
p-well
RS

n-type substrate

Parasitic Junction Transistors within a CMOS Structure

Figure 3.27 37/38

 Integrated Circuit Products

• Linear IC Products • Digital IC Products

– Operational Amplifier (continued)
– Voltage Regulator – Nonvolatile Memory
• ROM
– Stepper Motor Driver
• PROM
• EPROM
• Digital IC Products • EEPROM
– Volatile Memory • ASIC
• RAM • PLD
• DRAM • PAL
• SRAM • PLA
• MPU or CPU • MPGA
• FPGA
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