How Paging Works

How Paging Works?
Paging is a method used by operating systems to manage memory

efficiently. It breaks physical memory into fixed-size blocks called “frames”
and logical memory into blocks of the same size called “pages.” When a
program runs, its pages are loaded into any available frames in the physical
memory.
This approach prevents fragmentation issues by keeping memory allocation
uniform. Each program has a page table, which the operating system uses to
keep track of where each page is stored in physical memory. When a
program accesses data, the system uses this table to convert the program’s
address into a physical memory address.
Paging allows for better memory use and makes it easier to manage. It also
supports virtual memory, letting parts of programs be stored on disk and
loaded into memory only when needed. This way, even large programs can
run without fitting entirely into main memory.
 If Logical Address = 31 bit, then Logical Address Space = 2 31 words = 2 G
words (1 G = 230)
 If Logical Address Space = 128 M words = 2 7 * 220 words, then Logical
Address = log2 227 = 27 bits
 If Physical Address = 22 bit, then Physical Address Space = 2 22 words =
4 M words (1 M = 220)
 If Physical Address Space = 16 M words = 2 4 * 220 words, then Physical
Address = log2 224 = 24 bits
The mapping from virtual to physical address is done by the Memory
Management Unit (MMU) which is a hardware device and this mapping is
known as the paging technique.
 The Physical Address Space is conceptually divided into a number of
fixed-size blocks, called frames.
 The Logical Address Space is also split into fixed-size blocks,
called pages.
 Page Size = Frame Size
Example
 Physical Address = 12 bits, then Physical Address Space = 4 K words
 Logical Address = 13 bits, then Logical Address Space = 8 K words
 Page size = frame size = 1 K words (assumption)
Paging
The address generated by the CPU is divided into

 Page number(p): Number of bits required to represent the pages
in Logical Address Space or Page number
 Page offset(d): Number of bits required to represent a particular word in
a page or page size of Logical Address Space or word number of a page
or page offset.
In a paging scheme, the physical cope with the area is divided into fixed-
length frames, each of which contains some bytes or words. When a manner
is running, its logical address space is split into constant-size pages, which
might be mapped to corresponding frames within the physical address
space.
Physical Address is divided into:
To represent a physical address in this scheme, parts are commonly used:
Frame Range: This is the variety of the frame within the physical cope with
the area that consists of the byte or phrase being addressed. The wide
variety of bits required to represent the body range relies upon the scale of
the physical cope with the area and the size of each frame. For instance, if
the physical cope with area carries 2^20 frames and each frame is 4KB
(2^12 bytes) in size, then the frame range could require 20-12 = 8 bits.
Frame Offset: This is the wide variety of the byte or word within the body
this is being addressed. The number of bits required to represent the frame
offset relies upon the size of every frame. For instance, if everybody is 4KB
in size, then the frame offset could require 12 bits. So, a physical address in
this scheme may be represented as follows:
Physical Address = (Frame Number << Number of Bits in Frame Offset)
+ Frame Offset, where “<<” represents a bitwise left shift operation.
 The TLB is associative, high-speed memory.
 Each entry in TLB consists of two parts: a tag and a value.
 When this memory is used, then an item is compared with all tags
simultaneously. If the item is found, then the corresponding value is
returned.
Paging is a memory management technique used in operating systems to
manage memory and allocate memory to processes. In paging, memory is
divided into fixed-size blocks called pages, and processes are allocated
memory in terms of these pages. Each page is of the same size, and the
size is typically a power of 2, such as 4KB or 8 KB.
Dedicated registers can be used to implement the page table in hardware. However,
using a register for the page table is only useful if the page table is tiny. We can
employ TLB (translation look-aside buffer), a particular, tiny, fast look-up
hardware cache if the page table has a significant number of entries.
 The TLB is a high-speed, associative memory.

 LB entries are made up of two parts: a value and a tag.
 When this memory is accessed, an item is compared to all tags at the same time.
 If the object is located, the value associated with it is returned.
m = main memory access time
In case the page table is kept in the main memory,
then the effective access time would be = m(page table) + m(page in page table)
m = main memory access time
In case the page table is kept in the main memory,
then the effective access time would be = m(page table) + m(page in page table)

How Paging Works

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How Paging Works

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How Paging Works?

Paging is a method used by operating systems to manage memory

The address generated by the CPU is divided into

 The TLB is a high-speed, associative memory.

m = main memory access time

In case the page table is kept in the main memory,

In case the page table is kept in the main memory,

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