Scribd Logo
Upload

Welcome to Scribd!

  • 51 views

    Bcs302 Computer Organization and Architecture

    Uploaded by

    Amit Yadav

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Bcs302 Computer Organization and Architecture

    Uploaded by

    Amit Yadav
    51 views2 pages

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    51 views2 pages

    Bcs302 Computer Organization and Architecture

    Uploaded by

    Amit Yadav

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    You are on page 1of 2

    Printed Page: 1 of 2

    Subject Code: BCS302


    0Roll No: 0 0 0 0 0 0 0 0 0 0 0 0 0

    BTECH
    (SEM III) THEORY EXAMINATION 2023-24
    COMPUTER ORGANIZATION AND ARCHITECTURE
    TIME: 3HRS M.MARKS: 70

    Note: 1. Attempt all sections. If require any missing data; then choose suitably.
    SECTION A

    1. Attempt all questions in brief.


    Q no. Question Marks
    a. What are the different types of Buses used in computer architecture? 2
    b. Name the different types of multipliers. 2
    c. What are the different phases of an instruction cycle? 2
    d. How does control unit of a computer works? 2
    e. Write a short not on locality of reference. 2
    f. Define 2 ½ D memory organization. 2
    g. In what way synchronous and asynchronous serial modes of data transfer differ? 2
    SECTION B

    2. Attempt any three of the following:


    a. What is meant by the term BUS arbitration? Why is it needed? How can bus 7
    90

    2
    arbitration be implemented in Daisy changing scheme?

    13
    _2

    b. Show the multiplication process using Booth’s algorithm when the following 7

    2.
    numbers are multiplied: -
    P2

    24
    (-12) *(-18).
    4D

    c. What is pipelining? What are the different stages of pipelining? Explain in detail. 7

    5.
    d. Give classification of memory based on the method of access. Also discuss 7
    .5
    P2

    construction and working of magnetic disk and various components of disk access
    17
    Q

    time.
    |1

    e. What are the basic differences between interrupt initiated I/O and programmed 7
    I/O? Explain in detail.
    5 6

    SECTION C
    2:

    3. Attempt any one part of the following:


    :2
    13

    a. What do you mean by processor organization? Explain various types of processor 7


    organization with suitable example.
    4

    b. Differentiate between Memory stack and register stack. 7


    02

    4. Attempt any one part of the following:


    -2

    a. Explain in detail the principle of carry looks ahead adder and design 4-bit CLA 7
    03

    adder.
    1-

    b. Represent the following decimal number in IEEE standard floating-point format in 7


    |2

    a single precision method (32 bit) representation method.


    (i) (85.125)10
    (ii) (-307.1875)10
    5. Attempt any one part of the following:
    a. Explain the different cycles of an instruction execution. 7
    b. Differentiate between hardwired and micro programmed control unit. Explain each 7
    component of hardwired control unit organization.

    1|Page
    QP24DP2_290 | 21-03-2024 13:22:56 | 117.55.242.132
    Printed Page: 2 of 2
    Subject Code: BCS302
    0Roll No: 0 0 0 0 0 0 0 0 0 0 0 0 0

    BTECH
    (SEM III) THEORY EXAMINATION 2023-24
    COMPUTER ORGANIZATION AND ARCHITECTURE
    TIME: 3HRS M.MARKS: 70

    6. Attempt any one part of the following:


    a. Consider a cache (M1) and memory (M2) hierarchy with following characteristics: 7
    -
    M1 : 16K word, 50 ns Access time
    M2 : 1M word, 400 ns Access time
    Assume 8-word cache blocks and set size 256 words with set associative mapping.
    (i) Show and explain the mapping between M2 and M1.
    (ii) Calculate the effective memory access time with cache hit ratio=0.95.
    b. Explain the direct mapping technique. Consider a digital computer has a memory 7
    unit of 64k*16 and cache memory of 1k words. The cache uses direct mapping with
    4 block size of four words.
    (i) How many bits are there in the tag, block and word fields of the address
    format?
    (ii) How many blocks can the cache accommodate?
    7. Attempt any one part of the following: 7x1=7
    a. What do you mean by asynchronous data transfer? Explain strobe control and 7
    90

    2
    handshaking mechanism.

    13
    _2

    b. Explain the various modes of data transfer and discuss direct memory access mode 7

    2.
    in detail. Also explain how DMA is superior to other modes.
    P2

    24
    4D

    5.
    .5
    P2

    17
    Q

    |1
    56
    2:
    :2
    13
    4
    02
    -2
    03
    1-
    |2

    2|Page
    QP24DP2_290 | 21-03-2024 13:22:56 | 117.55.242.132

    You might also like