MCXC44XP64M48SF6 3476088

NXP Semiconductors MCXC44XP64M48SF6
Data Sheet: Technical Data Rev. 2, 07/2024
MCX C44X Microcontroller MCXC4x4(R)

ARM® Cortex®-M0+ 48MHz 32-bit MCU, 128/256KB Flash, MCXC4x3(R)
16/32KB SRAM, USB, LCD
MCXC2x4(R)
MCXC2x3(R)
Features MCXC1x4(R)
• ARM® Cortex®-M0+ 48MHz with low power MCXC1x3(R)
• Up to 256KB Flash, up to 32KB SRAM, 16KB Boot ROM
• USB FS 2.0 device without requiring an external crystal
• Segment LCD supporting up to 24x8 or 28x4 segments
• Embedded ROM with boot loader for flexible program
upgrade
• FlexIO to support any standard and customized serial 32 QFN 48 QFN
5x5 mm P 0.5 mm 7x7 mm P 0.5 mm
peripheral emulation
• Down to 54uA/MHz in very low power run mode and
1.96uA in deep sleep mode (RAM + RTC retained)
• - 40 °C to + 125 °C (Tj) temperature range
64 LQFP 64 BGA
10x10 mm P 0.5 mm 5x5 mm P 0.5 mm
Core Processor
• ARM® 32-bit Cortex®-M0+ core up to 48 MHz
Memories
• 128/256 KB program flash memory
• 16/32 KB SRAM
• 16 KB ROM with build-in bootloader
• 32-byte backup register
Security
• 80-bit unique identification number per chip
• Advanced flash security
System and clocks

• 4-channel asynchronous DMA controller
• COP Software watchdog
• SWD debug interface and Micro Trace Buffer
• Bit manipulation engine
• Interrupt controller
• 48 MHz high accuracy internal reference clock
• 8/2 MHz low-power internal reference clock
• 32–40 kHz and 3–32 MHz crystal oscillator
• 1 KHz reference clock active under all low-power modes (except VLLS0)
Communication interfaces for connectivity

• Segment LCD supporting up to 24x8 or 28x4 segments
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• USB full-speed 2.0 device controller supporting crystal-less operation
• One UART module supporting ISO7816, operating up to 1.5 Mbit/s
• Two low-power UART modules supporting asynchronous operation in low-power modes
• Two I2C modules and I2C0 supporting up to 1 Mbit/s
• Two 16-bit SPI modules supporting up to 24 Mbit/s
• One FlexIO module supporting emulation of additional UART, SPI, I2C, I2S, PWM and other serial modules, and
so on
• One serial audio interface I2S
Analog
• One 16-bit 818 ksps ADC module with high accuracy internal voltage reference (Vref) and up to 18 channels
• High-speed analog comparator containing a 6-bit DAC for programmable reference input
• One 12-bit DAC
• 1.2 V internal voltage reference
Timers
• One 6-channel Timer/PWM module
• Two 2-channel Timer/PWM modules
• One low-power timer
• Periodic interrupt timer
• Real time clock
General-purpose input/outputs
• Up to 50 general-purpose input/output
Power management
• Down to 54 uA/MHz in very low power run mode
• Down to 1.96 uA in VLLS3 mode (RAM + RTC retained)
• Six flexible static modes
• Low-leakage wakeup unit
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range : -40 to 125°C(Tj)
Target applications
• Small to medium appliances
• Home security and surveillance
• Smart lighting
• Smart power socket
• DC fan
Ordering information
Part number Marking (Line1/ Core Flash SRAM GPIOs USB/LCD Package Packing
Line2) Speed (KB) (KB)
(MHz)
(P)MCXC143VFM(R) (P)MC143M 48 128 16 28 -/- 32QFN Tray and
Reel
(P)MCXC143VFT (P)MC143T 48 128 16 40 -/- 48QFN Tray
(P)MCXC243VFT (P)MC243T 48 128 16 36 USB/- 48QFN Tray
Table continues on the next page...
2 MCX C44X Microcontroller, Rev. 2, 07/2024

NXP Semiconductors
Ordering information (continued)
Part number Marking (Line1/ Core Flash SRAM GPIOs USB/LCD Package Packing
Line2) Speed (KB) (KB)
(MHz)
(P)MCXC443VMP (P)MC443P 48 128 16 50 USB/LCD 64BGA Tray
(P)MCXC443VLH (P)MCXC443/VLH 48 128 16 50 USB/LCD 64LQFP Tray
(P)MCXC144VFM(R) (P)MC144M 48 256 32 28 -/- 32QFN Tray and
Reel
(P)MCXC244VFM(R) (P)MC244M 48 256 32 23 USB/- 32QFN Tray and
Reel
(P)MCXC144VFT (P)MC144T 48 256 32 40 -/- 48QFN Tray
(P)MCXC244VFT (P)MC244T 48 256 32 36 USB/- 48QFN Tray
(P)MCXC444VMP (P)MC444P 48 256 32 50 USB/LCD 64BGA Tray
(P)MCXC444VLH (P)MCXC444/VLH 48 256 32 50 USB/LCD 64LQFP Tray
The following figure shows the block diagram of this device:
Figure 1. Block diagram
MCX C44X Microcontroller, Rev. 2, 07/2024 3

NXP Semiconductors
The following figure shows the architecture diagram of this device:
Figure 2. Architecture diagram

NXP Semiconductors
Table of Contents
1 Ratings....................................................................................... 6 3.7 Timers............................................................................... 43
1.1 Thermal handling ratings.................................................... 6 3.8 Communication interfaces................................................ 43
1.2 Moisture handling ratings....................................................6 3.8.1 USB electrical specifications.................................43
1.3 ESD handling ratings.......................................................... 6 3.8.2 USB VREG electrical specifications......................44
1.4 Voltage and current operating ratings.................................6 3.8.3 SPI switching specifications..................................44
2 General...................................................................................... 7 3.8.4 I2C........................................................................ 49
2.1 AC electrical characteristics................................................7 3.8.5 UART.................................................................... 51
2.2 Nonswitching electrical specifications.................................8 3.8.6 I2S/SAI switching specifications........................... 51
2.2.1 Voltage and current operating requirements...........8 3.9 Human-machine interfaces (HMI)..................................... 55
2.2.2 LVD and POR operating requirements................... 8 3.9.1 LCD electrical characteristics................................55
2.2.3 Voltage and current operating behaviors................ 9 4 Dimensions.............................................................................. 56
2.2.4 Power mode transition operating behaviors..........10 4.1 Obtaining package dimensions.........................................57
2.2.5 Power consumption operating behaviors..............11 5 Pinouts and Packaging............................................................ 57
2.2.6 EMC radiated emissions operating behaviors...... 21 5.1 Signal Multiplexing and Pin Assignments......................... 57
2.2.7 Designing with radiated emissions in mind........... 22 5.1.1 MCX C44x Pin Assignments.................................57
2.2.8 Capacitance attributes.......................................... 22 5.1.2 MCX C24x Pin Assignments.................................60
2.3 Switching specifications.................................................... 22 5.1.3 MCX C14x Pin Assignments.................................62
2.3.1 Device clock specifications................................... 22 5.2 MCX C44X Family Pinouts............................................... 64
2.3.2 General switching specifications...........................23 5.2.1 MCX C44x Pinouts................................................64
2.4 Thermal specifications...................................................... 23 5.2.2 MCX C24x Pinouts................................................66
2.4.1 Thermal operating requirements...........................23 5.2.3 MCX C14x Pinouts................................................68
2.4.2 Thermal attributes................................................. 24 6 Ordering parts.......................................................................... 70
3 Peripheral operating requirements and behaviors................... 25 6.1 Determining valid orderable parts..................................... 70
3.1 Core modules................................................................... 25 7 Part identification......................................................................70
3.1.1 SWD electricals ....................................................25 7.1 Description........................................................................ 70
3.2 System modules............................................................... 26 7.2 Format.............................................................................. 71
3.3 Clock modules.................................................................. 26 7.3 Fields................................................................................ 71
3.3.1 MCG-Lite specifications........................................ 26 7.4 Example............................................................................ 72
3.3.2 Oscillator electrical specifications......................... 28 8 Terminology and guidelines..................................................... 72
3.4 Memories and memory interfaces.................................... 30 8.1 Definitions......................................................................... 72
3.4.1 Flash electrical specifications............................... 30 8.2 Examples.......................................................................... 72
3.5 Security and integrity modules..........................................32 8.3 Typical-value conditions................................................... 73
3.6 Analog...............................................................................32 8.4 Relationship between ratings and operating
3.6.1 ADC electrical specifications.................................32 requirements..................................................................... 73
3.6.2 Voltage reference electrical specifications............37 8.5 Guidelines for ratings and operating requirements........... 74
3.6.3 CMP and 6-bit DAC electrical specifications.........38 9 Revision History....................................................................... 74
3.6.4 12-bit DAC electrical characteristics..................... 40

NXP Semiconductors
Ratings
1 Ratings
1.1 Thermal handling ratings

Table 1. Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings

Table 2. Moisture handling ratings
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings

Table 3. ESD handling ratings
VHBM Electrostatic discharge voltage, human body model –2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device –500 +500 V 2
model
ILAT Latch-up current at ambient temperature of 105 °C –100 +100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

NXP Semiconductors
General
1.4 Voltage and current operating ratings

Table 4. Voltage and current operating ratings
Symbol Description Min. Max. Unit
VDD Digital supply voltage –0.3 3.8 V
IDD Digital supply current — 120 mA
VIO IO pin input voltage –0.3 VDD + 0.3 V
ID Instantaneous maximum current single pin limit (applies to –25 25 mA
all port pins)
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
VUSB_DP USB_DP input voltage –0.3 3.63 V
VUSB_DM USB_DM input voltage –0.3 3.63 V
VREGIN USB regulator input –0.3 6.0 V
2 General
2.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Low High
VIH
80%
Input Signal Midpoint1 50%
20%
VIL
Fall Time Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 3. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength

NXP Semiconductors
General
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements

Table 5. Voltage and current operating requirements
VDD Supply voltage 1.71 3.6 V
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
VIH Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V
• 1.7 V ≤ VDD ≤ 2.7 V 0.75 × VDD — V
VIL Input low voltage

• 2.7 V ≤ VDD ≤ 3.6 V — 0.35 × VDD V
• 1.7 V ≤ VDD ≤ 2.7 V — 0.3 × VDD V
VHYS Input hysteresis 0.06 × VDD — V

IICIO IO pin negative DC injection current — single pin 1
-3 — mA
• VIN < VSS-0.3V
IICcont Contiguous pin DC injection current —regional limit,

includes sum of negative injection currents of 16
contiguous pins
-25 — mA
• Negative current injection
VODPU Open drain pullup voltage level VDD VDD V 2

VRAM VDD voltage required to retain RAM 1.2 — V
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements

Table 6. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V —

NXP Semiconductors
General
Table 6. VDD supply LVD and POR operating requirements (continued)

VLVDH Falling low-voltage detect threshold — high 2.48 2.56 2.64 V —
range (LVDV = 01)
Low-voltage warning thresholds — high range 1
VLVW1H • Level 1 falling (LVWV = 00)
2.62 2.70 2.78 V
2.72 2.80 2.88 V
2.82 2.90 2.98 V
2.92 3.00 3.08 V
VHYSH Low-voltage inhibit reset/recover hysteresis — — ±60 — mV —
high range
VLVDL Falling low-voltage detect threshold — low 1.54 1.60 1.66 V —
range (LVDV=00)
Low-voltage warning thresholds — low range 1
VLVW1L • Level 1 falling (LVWV = 00)
1.74 1.80 1.86 V
1.84 1.90 1.96 V
1.94 2.00 2.06 V
2.04 2.10 2.16 V
VHYSL Low-voltage inhibit reset/recover hysteresis — — ±40 — mV —
low range
VBG Bandgap voltage reference 0.97 1.00 1.03 V —
tLPO Internal low power oscillator period — factory 900 1000 1100 μs —
trimmed
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors

Table 7. Voltage and current operating behaviors
VOH Output high voltage — normal drive pad 1
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA VDD – 0.5 — V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA VDD – 0.5 — V
VOH Output high voltage — high drive pad 1

• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –18 mA VDD – 0.5 — V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA VDD – 0.5 — V
IOHT Output high current total for all ports — 100 mA

VOL Output low voltage — normal drive pad 1
— 0.5 V

NXP Semiconductors
General
Table 7. Voltage and current operating behaviors (continued)

• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA — 0.5 V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
VOL Output low voltage — high drive pad 1
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA — 0.5 V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA — 0.5 V
IOLT Output low current total for all ports — 100 mA

IIN Input leakage current (per pin) for full temperature — 1 μA 2
range
IIN Input leakage current (per pin) at 25 °C — 0.025 μA 2
IIN Input leakage current (total all pins) for full — 64 μA 2
temperature range
IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA
RPU Internal pullup resistors 20 50 kΩ 3
1. PTB0, PTB1, PTC3, PTC4, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the
associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD = 3.6 V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
2.2.4 Power mode transition operating behaviors

All specifications except tPOR and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• HIRC clock mode
Table 8. Power mode transition operating behaviors
tPOR After a POR event, amount of time from the — — 300 μs 1
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
• VLLS0 → RUN
— 152 166 μs
• VLLS1 → RUN
— 152 166 μs
• VLLS3 → RUN
— 93 104 μs

NXP Semiconductors
General
Table 8. Power mode transition operating behaviors (continued)

• LLS → RUN
— 7.5 8 μs
• VLPS → RUN
— 7.5 8 μs
• STOP → RUN
— 7.5 8 μs
1. Normal boot (FTFA_FOPT[LPBOOT]=11)
2.2.5 Power consumption operating behaviors

The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
NOTE
The while (1) test is executed with flash cache enabled.
Table 9. Power consumption operating behaviors
IDDA Analog supply current — — See note mA 1
IDD_RUNCO Running CoreMark in flash in compute operation 2
mode—48M HIRC mode, 48 MHz core / 24 MHz
flash, VDD = 3.0 V
• at 25 °C — 5.76 6.40 mA
• at 105 °C 6.04 6.68
IDD_RUNCO Running While(1) loop in flash in compute

operation mode—48M HIRC mode, 48 MHz
core / 24 MHz flash, VDD = 3.0 V
• at 25 °C — 3.21 3.85 mA
• at 105 °C 3.49 4.13
IDD_RUN Run mode current—48M HIRC mode, running 2

CoreMark in Flash all peripheral clock disable 48
MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C — 6.45 7.09 mA
• at 105 °C — 6.75 7.39

CoreMark in flash all peripheral clock disable, 24

NXP Semiconductors
General
Table 9. Power consumption operating behaviors (continued)

• at 25 °C — 3.95 4.59 mA
• at 105 °C — 4.23 4.87

CoreMark in Flash all peripheral clock disable 12
• at 25 °C — 2.68 3.32 mA
• at 105 °C 2.96 3.60

CoreMark in Flash all peripheral clock enable 48
• at 25 °C — 8.08 8.72 mA
• at 105 °C 8.39 9.03
IDD_RUN Run mode current—48M HIRC mode, running

While(1) loop in flash all peripheral clock disable,
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C — 3.90 4.54 mA
• at 105 °C 4.21 4.85

While(1) loop in Flash all peripheral clock
disable, 24 MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C — 2.66 3.30 mA
• at 105 °C 2.94 3.58
IDD_RUN Run mode current—48M HIRC mode, Running

• at 25 °C — 2.03 2.67 mA
• at 105 °C 2.31 2.95
IDD_RUN Run mode current—48M HIRC mode, Running

enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C — 5.52 6.16 mA
• at 105 °C 5.83 6.47

While(1) loop in SRAM all peripheral clock
• at 25 °C — 5.29 5.93 mA
• at 105 °C 5.56 6.20

While(1) loop in SRAM all peripheral clock
enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
mA

NXP Semiconductors
General

• at 25 °C — 6.91 7.55
• at 105 °C 7.19 7.91
IDD_VLPRC Very Low Power Run Core Mark in Flash in

O Compute Operation mode: Core@4MHz, Flash
@1MHz, VDD = 3.0 V
• at 25 °C — 826 907 μA
IDD_VLPRC Very-low-power-run While(1) loop in SRAM in
O compute operation mode— 8 MHz LIRC mode, 4
MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C — 405 486 μA
IDD_VLPRC Very-low-power run While(1) loop in SRAM in
O compute operation mode:—2 MHz LIRC mode, 2
MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C — 154 235 μA
IDD_VLPR Very-low-power run mode current— 2 MHz LIRC
mode, While(1) loop in flash all peripheral clock
disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C — 108 189 μA
disable, 125 kHz core / 31.25 kHz flash, VDD =
3.0 V — 39 120 μA
• at 25 °C
disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C — 249 330 μA
enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C — 337 418 μA
mode, While(1) loop in SRAM in all peripheral
clock disable, 4 MHz core / 1 MHz flash, VDD =
3.0 V — 416 497 μA
• at 25 °C
mode, While(1) loop in SRAM all peripheral clock
enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C — 494 575 μA
IDD_VLPR Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM in all peripheral
clock disable, 2 MHz core / 0.5 MHz flash, VDD =
3.0 V — 166 247 μA
• at 25 °C

NXP Semiconductors
General

disable, 125 kHz core / 31.25 kHz flash, VDD = — 50 131 μA
3.0 V
• at 25 °C
enable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C — 208 289 μA
IDD_WAIT Wait mode current—core disabled, 48 MHz
system/24 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V — 1.81 1.89 mA
IDD_WAIT Wait mode current—core disabled, 24 MHz
system/12 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V — 1.22 1.39 mA
IDD_VLPW Very-low-power wait mode current, core — 172 182 μA
disabled, 4 MHz system/ 1 MHz bus and flash,
all peripheral clocks disabled, VDD = 3.0 V
disabled, 2 MHz system/ 0.5 MHz bus and flash,
all peripheral clocks disabled, VDD = 3.0 V
disabled, 125 kHz system/ 31.25 kHz bus and
flash, all peripheral clocks disabled, VDD = 3.0 V
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
12 MHz bus and flash, VDD = 3.0 V
— 1.81 2.06 mA
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
flash doze enabled, 12 MHz bus, VDD = 3.0 V
— 1.00 1.25 mA
IDD_STOP Stop mode current at 3.0 V
• at 25 °C and below
— 161.93 171.82
• at 50 °C
— 181.45 191.96
• at 85 °C
— 236.29 271.17 μA
• at 105 °C
— 390.33 465.58
IDD_VLPS Very-low-power stop mode current at 3.0 V
— 3.31 5.14
• at 50 °C
— 10.43 17.68
• at 85 °C
— 34.14 61.06 μA
• at 105 °C
— 104.38 164.44
IDD_VLPS Very-low-power stop mode current at 1.8 V
— 3.21 5.22

NXP Semiconductors
General

• at 50 °C — 10.26 17.62
• at 85 °C — 33.49 60.19 μA
• at 105 °C — 102.92 162.20
IDD_LLS Low-leakage stop mode current, all peripheral

disable, at 3.0 V μA
— 2.06 3.33
— 4.72 6.85
• at 50 °C
— 8.13 13.30
• at 70 °C
— 13.34 24.70
• at 85 °C
— 41.08 52.43
• at 105 °C
IDD_LLS Low-leakage stop mode current with RTC

current, at 3.0 V μA
— 2.46 3.73
— 5.12 7.25
• at 50 °C
— 8.53 11.78
• at 70 °C
— 13.74 18.91
• at 85 °C
— 41.48 52.83
• at 105 °C
IDD_LLS Low-leakage stop mode current with RTC 3

— 2.35 2.70
— 4.91 6.75
• at 50 °C
— 8.32 11.78
• at 70 °C
— 13.44 18.21
• at 85 °C
— 40.47 51.85
• at 105 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current, all

peripheral disable, at 3.0 V μA
— 1.45 1.85
— 3.37 4.39
• at 50 °C
— 5.76 8.48
• at 70 °C
— 9.72 14.30
• at 85 °C
— 30.41 37.50
• at 105 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC 3

— 2.05 2.45
— 3.97 4.99
• at 50 °C
— 6.36 9.08
• at 70 °C
— 10.32 14.73
• at 85 °C
— 31.01 38.10
• at 105 °C

NXP Semiconductors
General

IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC 3
— 1.96 2.36
— 3.86 5.67
• at 50 °C
— 6.23 8.53
• at 70 °C
— 10.21 13.37
• at 85 °C
— 30.25 37.02
• at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current all

peripheral disabled at 3.0 V
— 0.66 0.80
— 1.78 3.87
• at 50°C
— 2.55 4.26 μA
• at 70°C
— 4.83 6.64
• at 85°C
— 16.42 20.49
• at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC 3

enabled at 3.0 V
— 1.26 1.40
— 2.38 4.47
• at 50°C
— 3.15 4.86 μA
• at 70°C
— 5.43 7.24
• at 85°C
— 17.02 21.09
• at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC 3

enabled at 1.8 V
— 1.16 1.30
— 1.96 2.28
• at 50°C
— 2.78 3.37 μA
• at 70°C
— 4.85 6.88
• at 85°C
— 15.78 18.81
• at 105 °C

peripheral disabled (SMC_STOPCTRL[PORPO]
= 0) at 3.0 V
• at 25 °C and below — 0.35 0.47 μA
• at 50 °C — 1.25 1.44
• at 70 °C — 2.53 3.24
• at 85 °C — 4.40 5.24
• at 105 °C — 16.09 19.29

peripheral disabled (SMC_STOPCTRL[PORPO]
= 1) at 3 V

NXP Semiconductors
General
Table 9. Power consumption operating behaviors

• at 25 °C and below — 0.18 0.28
• at 50 °C — 1.09 1.31 μA
• at 70 °C — 2.25 2.94
• at 85 °C — 4.25 5.10
• at 105 °C — 15.95 19.10
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR with optimization level high,
optimized for balanced.
3. RTC uses external 32 kHz crystal as clock source, and the current includes ERCLK32K power consumption.
Table 10. Low power mode peripheral adders — typical value

Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IIRC8MHz 8 MHz internal reference clock (IRC) 93 93 93 93 93 93 µA
adder. Measured by entering STOP or
VLPS mode with 8 MHz IRC enabled,
MCG_SC[FCRDIV]=000b,
MCG_MC[LIRC_DIV2]=000b.
IIRC2MHz 2 MHz internal reference clock (IRC) 29 29 29 29 29 29 µA
adder. Measured by entering STOP mode
with the 2 MHz IRC enabled,
MCG_SC[FCRDIV]=000b,
MCG_MC[LIRC_DIV2]=000b.
IEREFSTEN4MHz External 4 MHz crystal clock adder. 206 224 230 238 245 253 µA
Measured by entering STOP or VLPS
mode with the crystal enabled.
IEREFSTEN32KHz External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN and
EREFSTEN] bits. Measured by entering
all modes with the crystal enabled.
• VLLS1
440 490 540 560 570 580
• VLLS3
440 490 540 560 570 580
• LLS
490 490 540 560 570 680
• VLPS
510 560 560 560 610 680 nA
• STOP
510 560 560 560 610 680
ILPTMR LPTMR peripheral adder measured by
placing the device in VLLS1 mode with
LPTMR enabled using LPO.
30 30 30 85 100 200

NXP Semiconductors
General
Table 10. Low power mode peripheral adders — typical value (continued)
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
nA
ICMP CMP peripheral adder measured by 22 22 22 22 22 22 µA
CMP enabled using the 6-bit DAC and a
single external input for compare.
Includes 6-bit DAC power consumption.
IUART UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate. Includes
selected clock source power
consumption.
• IRC8M (8 MHz internal reference 114 114 114 114 114 114 µA
clock)
34 34 34 34 34 34
• IRC2M (2 MHz internal reference
clock)
ITPM TPM peripheral adder measured by
mode with selected clock source
configured for output compare generating
100 Hz clock signal. No load is placed on
the I/O generating the clock signal.
Includes selected clock source and I/O
switching currents.
147 147 147 147 147 147 µA
clock) 42 42 42 42 42 42
clock)
IBG Bandgap adder when BGEN bit is set and 45 45 45 45 45 45 µA
device is placed in VLPx or VLLSx mode.
IADC ADC peripheral adder combining the 330 330 330 330 330 330 µA
measured values at VDD and VDDA by
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
ILCD LCD peripheral adder measured by 4.5 4.5 4.5 4.5 4.5 4.5 µA
external 32 kHz crystal enabled by means
of the OSC0_CR[EREFSTEN,
EREFSTEN] bits. VIREG disabled,
resistor bias network enabled, 1/8 duty
cycle, 8 x 36 configuration for driving 288
Segments, 32 Hz frame rate, no LCD
glass connected. Includes ERCLK32K (32
kHz external crystal) power consumption.

NXP Semiconductors
General
2.2.5.1 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:
• MCG-Lite in HIRC for run mode, and LIRC for VLPR mode
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Figure 4. Run mode supply current vs. core frequency

NXP Semiconductors
General

NXP Semiconductors
General
Consumpt
CurrentC
Current ionon
onsumption VDD
onVDD (A)
(A)
Figure 5. VLPR mode current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors

Table 11. EMC radiated emissions operating behaviors for 64-pin LQFP package
Symbol Description Frequency Typ. Unit Notes
band
(MHz)
VRE1 Radiated emissions voltage, band 1 0.15–50 11 dBμV 1, 2
VRE2 Radiated emissions voltage, band 2 50–150 12 dBμV
VRE_IEC IEC level 0.15–1000 N — 2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions,
150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits -
Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM
Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic

NXP Semiconductors
General
application code. The reported emission level is the value of the maximum measured emission, rounded up to the next
whole number, from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = IRC48M, fSYS = 48 MHz, fBUS = 24 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes

Table 12. Capacitance attributes
CIN Input capacitance — 7 pF
2.3 Switching specifications
2.3.1 Device clock specifications

Table 13. Device clock specifications
Normal run mode
fSYS System and core clock1 — 48 MHz
fBUS Bus clock1 — 24 MHz
fFLASH Flash clock1 — 24 MHz
fSYS_USB System and core clock when Full Speed USB in operation 20 — MHz
fLPTMR LPTMR clock — 24 MHz
VLPR and VLPS modes2
fSYS System and core clock — 4 MHz
fBUS Bus clock — 1 MHz
fFLASH Flash clock — 1 MHz
fLPTMR LPTMR clock3 — 24 MHz

NXP Semiconductors
General
Table 13. Device clock specifications (continued)

fLPTMR_ERCLK LPTMR external reference clock — 16 MHz
fosc_hi_2 Oscillator crystal or resonator frequency — high frequency — 16 MHz
mode (high range) (MCG_C2[RANGE]=1x)
fTPM TPM asynchronous clock — 8 MHz
fLPUART0/1 LPUART0/1 asynchronous clock — 8 MHz
1. The maximum value of system clock, core clock, bus clock, and flash clock under normal run mode can be 3% higher
than the specified maximum frequency when IRC 48MHz is used as the clock source.
2. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
3. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
2.3.2 General switching specifications

These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 14. General switching specifications
Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) 1.5 — Bus clock 1
— Synchronous path cycles
External RESET and NMI pin interrupt pulse width — 100 — ns 2
Asynchronous path
GPIO pin interrupt pulse width — Asynchronous path 16 — ns 2
Port rise and fall time — 36 ns 3
1. The synchronous and asynchronous timing must be met.

2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements

Table 15. Thermal operating requirements
TJ Die junction temperature –40 125 °C
TA Ambient temperature 125 °C 1, 2

NXP Semiconductors
General
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
2. The device operating specification is not guaranteed beyond 125 °C TJ.
2.4.2 Thermal attributes

Table 16. Thermal attributes
Board type Symbol Description 48 QFN 32 QFN 64 64 Unit Notes
LQFP MAPBG
A
Single-layer (1S) RθJA Thermal resistance, junction 86 101 70 50.3 °C/W 1
to ambient (natural
convection)
Four-layer (2s2p) RθJA Thermal resistance, junction 29 33 51 42.9 °C/W
to ambient (natural
convection)
Single-layer (1S) RθJMA Thermal resistance, junction 71 84 58 41.4 °C/W
to ambient (200 ft./min. air
speed)
Four-layer (2s2p) RθJMA Thermal resistance, junction 24 28 45 38.0 °C/W
to ambient (200 ft./min. air
speed)
— RθJB Thermal resistance, junction 12 13 33 39.6 °C/W 2
to board
— RθJC Thermal resistance, junction 1.7 1.7 20 27.3 °C/W 3
to case
— ΨJT Thermal characterization 2 3 4 0.4 °C/W 4
parameter, junction to
package top outside center
(natural convection)
— ΨJB Thermal characterization - - - 12.6 °C/W 5
parameter, junction to
package bottom (natural
convection)
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
5. Thermal characterization parameter indicating the temperature difference between package bottom center and the
junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JB.

NXP Semiconductors
Peripheral operating requirements and behaviors
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals

Table 17. SWD full voltage range electricals
Operating voltage 1.71 3.6 V
J1 SWD_CLK frequency of operation
• Serial wire debug 0 25 MHz
J2 SWD_CLK cycle period 1/J1 — ns

J3 SWD_CLK clock pulse width
• Serial wire debug 20 — ns
J4 SWD_CLK rise and fall times — 3 ns

J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns
J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns
J11 SWD_CLK high to SWD_DIO data valid — 32 ns
J12 SWD_CLK high to SWD_DIO high-Z 5 — ns
J2
J3 J3
SWD_CLK (input)
J4 J4
Figure 6. Serial wire clock input timing

NXP Semiconductors
SWD_CLK
J9 J10
SWD_DIO Input data valid
J11
SWD_DIO Output data valid
J12
SWD_DIO
J11
SWD_DIO Output data valid
Figure 7. Serial wire data timing
3.2 System modules

There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG-Lite specifications

Table 18. IRC48M specification
IDD Supply current — 400 500 µA —
fIRC Output frequency — 48 — MHz —
Δfirc48m_ol_lv Open loop total deviation of IRC48M 1
— ± 0.5 ± 1.5 %firc48m
frequency at low voltage
(VDD=1.71V-1.89V) over temperature
Δfirc48m_ol_hv Open loop total deviation of IRC48M 1
— ± 0.5 ± 1.0 %firc48m
frequency at high voltage
(VDD=1.89V-3.6V) over temperature

NXP Semiconductors
Table 18. IRC48M specification (continued)

Tj Period jitter (RMS) — 35 150 ps —
Tsu Startup time — 2 3 µs —
1. The maximum value represents characterized results equivalent to mean plus or minus three times the standard
deviation (mean +/-3sigma).
Table 19. IRC8M/2M specification

IDD_2M Supply current in 2 MHz mode — 14 17 µA —
IDD_8M Supply current in 8 MHz mode — 30 35 µA —
fIRC_2M Output frequency — 2 — MHz —
fIRC_8M Output frequency — 8 — MHz —
fIRC_T_2M Output frequency range (trimmed) — — ±3 %fIRC —
fIRC_T_8M Output frequency range (trimmed) — — ±3 %fIRC —
Tsu_2M Startup time — — 12.5 µs —
Tsu_8M Startup time — — 12.5 µs —

NXP Semiconductors
Figure 8. IRC8M Frequency Drift vs Temperature curve
3.3.2 Oscillator electrical specifications
3.3.2.1 Oscillator DC electrical specifications

Table 20. Oscillator DC electrical specifications
VDD Supply voltage 1.71 — 3.6 V
IDDOSC Supply current — low-power mode (HGO=0) 1
• 32 kHz — 500 — nA
• 4 MHz — 200 — μA
• 8 MHz (RANGE=01) — 300 — μA
• 16 MHz — 950 — μA
— 1.2 — mA

NXP Semiconductors
Table 20. Oscillator DC electrical specifications (continued)

• 24 MHz — 1.5 — mA
• 32 MHz
IDDOSC Supply current — high gain mode (HGO=1) 1

• 32 kHz — 25 — μA
• 4 MHz — 400 — μA
• 8 MHz (RANGE=01) — 500 — μA
• 16 MHz — 2.5 — mA
• 24 MHz — 3 — mA
• 32 MHz — 4 — mA
Cx EXTAL load capacitance — — — 2, 3

Cy XTAL load capacitance — — — 2, 3
RF Feedback resistor — low-frequency, low-power — — — MΩ 2, 4
mode (HGO=0)
Feedback resistor — low-frequency, high-gain — 10 — MΩ
mode (HGO=1)
Feedback resistor — high-frequency, low-power — — — MΩ
mode (HGO=0)
Feedback resistor — high-frequency, high-gain — 1 — MΩ
mode (HGO=1)
RS Series resistor — low-frequency, low-power — — — kΩ
mode (HGO=0)
Series resistor — low-frequency, high-gain — 200 — kΩ
mode (HGO=1)
Series resistor — high-frequency, low-power — — — kΩ
mode (HGO=0)
Series resistor — high-frequency, high-gain
mode (HGO=1)
— 0 — kΩ
Vpp5 Peak-to-peak amplitude of oscillation (oscillator — 0.6 — V
mode) — low-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator — VDD — V
mode) — low-frequency, high-gain mode
(HGO=1)
Peak-to-peak amplitude of oscillation (oscillator — 0.6 — V
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator — VDD — V
mode) — high-frequency, high-gain mode
(HGO=1)
1. VDD=3.3 V, Temperature =25 °C

2. See crystal or resonator manufacturer's recommendation

NXP Semiconductors
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2 Oscillator frequency specifications

Table 21. Oscillator frequency specifications
fosc_lo Oscillator crystal or resonator frequency — low- 32 — 40 kHz
frequency mode (MCG_C2[RANGE]=00)
fosc_hi_1 Oscillator crystal or resonator frequency — high- 3 — 8 MHz
frequency mode (low range)
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency — high 8 — 32 MHz
frequency mode (high range)
(MCG_C2[RANGE]=1x)
fec_extal Input clock frequency (external clock mode) — — 48 MHz 1, 2
tdc_extal Input clock duty cycle (external clock mode) 40 50 60 %
tcst Crystal startup time — 32 kHz low-frequency, — 750 — ms 3, 4
low-power mode (HGO=0)
Crystal startup time — 32 kHz low-frequency, — 250 — ms
high-gain mode (HGO=1)
Crystal startup time — 8 MHz high-frequency — 0.6 — ms
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency — 1 — ms
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
1. Other frequency limits may apply when external clock is being used as a reference for the FLL
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

NXP Semiconductors
3.4.1.1 Flash timing specifications — program and erase

The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 22. NVM program/erase timing specifications
thvpgm4 Longword Program high-voltage time — 7.5 18 μs —
thversscr Sector Erase high-voltage time — 13 113 ms 1
thversblk128k Erase Block high-voltage time for 128 KB — 52 452 ms 1
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands

Table 23. Flash command timing specifications
Read 1s Block execution time 1
trd1blk128k • 128 KB program flash — — 1.7 ms
trd1sec1k Read 1s Section execution time (flash sector) — — 60 μs 1

tpgmchk Program Check execution time — — 45 μs 1
trdrsrc Read Resource execution time — — 30 μs 1
tpgm4 Program Longword execution time — 65 145 μs —
Erase Flash Block execution time 2
tersblk128k • 128 KB program flash — 88 600 ms
tersscr Erase Flash Sector execution time — 14 114 ms 2

trd1all Read 1s All Blocks execution time — — 1.8 ms 1
trdonce Read Once execution time — — 25 μs 1
tpgmonce Program Once execution time — 65 — μs —
tersall Erase All Blocks execution time — 175 1300 ms 2
tvfykey Verify Backdoor Access Key execution time — — 30 μs 1
tersallu Erase All Blocks Unsecure execution time — 175 1300 ms 2
1. Assumes 25 MHz flash clock frequency.

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

NXP Semiconductors
3.4.1.3 Flash high voltage current behaviors

Table 24. Flash high voltage current behaviors
Symbol Description Min. Typ. Max. Unit
IDD_PGM Average current adder during high voltage — 2.5 6.0 mA
flash programming operation
IDD_ERS Average current adder during high voltage — 1.5 4.0 mA
flash erase operation
3.4.1.4 Reliability specifications

Table 25. NVM reliability specifications
Symbol Description Min. Typ.1 Max. Unit Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles 5 50 — years —
tnvmretp1k Data retention after up to 1 K cycles 20 100 — years —
nnvmcycp Cycling endurance 10 K 50 K — cycles 2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
3.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications

Using differential inputs can achieve better system accuracy than using single-end
inputs.

NXP Semiconductors
3.6.1.1 16-bit ADC operating conditions

Table 26. 16-bit ADC operating conditions
Symbol Description Conditions Min. Typ.1 Max. Unit Notes
VDDA Supply voltage Absolute 1.71 — 3.6 V —
ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2
ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2
VREFH ADC reference 1.13 VDDA VDDA V 3
voltage high
VREFL ADC reference VSSA VSSA VSSA V 3
voltage low
VADIN Input voltage • 16-bit differential mode VREFL — 31/32 × V —
VREFH
• All other modes VREFL —
VREFH
CADIN Input • 16-bit mode — 8 10 pF —
capacitance
• 8-bit / 10-bit / 12-bit — 4 5
modes
RADIN Input series — 2 5 kΩ —

resistance
RAS Analog source 13-bit / 12-bit modes 4
resistance
fADCK < 4 MHz — — 5 kΩ
(external)
fADCK ADC conversion ≤ 13-bit mode 1.0 — 24 MHz 5

clock frequency
fADCK ADC conversion 16-bit mode 2.0 — 12.0 MHz 5
clock frequency
Crate ADC conversion ≤ 13-bit modes 6
rate
No ADC hardware averaging 20.000 — 1200 ksps
Continuous conversions
enabled, subsequent
conversion time
Crate ADC conversion 16-bit mode 6
rate
No ADC hardware averaging 37.037 — 461.467 ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. VREFH can act as VREF_OUT when VREFV1 module is enabled.
4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

NXP Semiconductors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT ZADIN
Pad
SIMPLIFIED
ZAS leakage CHANNEL SELECT
due to CIRCUIT
ADC SAR
input ENGINE
RAS protection
RADIN
VADIN
VAS CAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN CADIN
Figure 9. ADC input impedance equivalency diagram
3.6.1.2 16-bit ADC electrical characteristics
Table 27. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)

Symbol Description Conditions1 Min. Typ.2 Max. Unit Notes
IDDA_ADC Supply current 0.215 — 1.7 mA 3
ADC • ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz tADACK =
asynchronous 1/fADACK
• ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz
clock source
fADACK
• ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz
• ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz
Sample Time See Reference Manual chapter for sample times

TUE Total • 12-bit modes — ±4 ±6.8 LSB4 5
unadjusted error
• <12-bit modes — ±1.4 ±2.1
DNL Differential non- • 12-bit modes — ±0.7 –1.1 to LSB4 5

linearity +1.9
• <12-bit modes — ±0.2
–0.3 to 0.5
INL Integral non- • 12-bit modes — ±1.0 –2.7 to LSB4 5
linearity +1.9
• <12-bit modes — ±0.5

NXP Semiconductors
Table 27. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description Conditions1 Min. Typ.2 Max. Unit Notes
–0.7 to
+0.5
EFS Full-scale error • 12-bit modes — –4 –5.4 LSB4 VADIN =
VDDA5
• <12-bit modes — –1.4 –1.8
EQ Quantization • 16-bit modes — –1 to 0 — LSB4
error
• ≤13-bit modes — — ±0.5
ENOB Effective 16-bit differential mode 6

bits
number of bits
• Avg = 32 12.8 14.5 —
bits
• Avg = 4 11.9 13.8
—
bits
16-bit single-ended mode
bits
12.2
• Avg = 32
13.9
11.4 —
• Avg = 4
13.1
—
Signal-to-noise See ENOB
SINAD 6.02 × ENOB + 1.76 dB
plus distortion
THD Total harmonic 16-bit differential mode 7
dB
distortion
• Avg = 32 — -94 —
dB
16-bit single-ended mode
— -85 —
• Avg = 32
SFDR Spurious free 16-bit differential mode 7

— dB
dynamic range 82 95
• Avg = 32
— dB
16-bit single-ended mode 78 90
• Avg = 32
EIL Input leakage IIn × RAS mV IIn =

error leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor Across the full temperature range 1.55 1.62 1.69 mV/°C 8
slope of the device
VTEMP25 Temp sensor 25 °C 706 716 726 mV 8
voltage
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA

NXP Semiconductors
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock

100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
13.80
ENOB
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
12.30 Averaging of 4 samples
Averaging of 8 samples
12.00
1 2 3 4 5 6 7 8 9 10 11 12
ADC Clock Frequency (MHz)
Figure 10. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock

100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
12.75
ENOB
12.50
12.25
12.00
11.75
11.50
11.25 Averaging of 4 samples

11.00
1 2 3 4 5 6 7 8 9 10 11 12
ADC Clock Frequency (MHz)
Figure 11. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

NXP Semiconductors
3.6.2 Voltage reference electrical specifications
Table 28. VREF full-range operating requirements

VDDA Supply voltage 3.6 V —
TA Temperature Operating temperature °C —
range of the device
CL Output load capacitance 100 nF 1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
range of the device.
Table 29 is tested under the condition of setting VREF_TRM[CHOPEN],

VREF_SC[REGEN] and VREF_SC[ICOMPEN] bits to 1.
Table 29. VREF full-range operating behaviors
Vout Voltage reference output with factory trim at 1.1915 1.195 1.1977 V 1
nominal VDDA and temperature=25C
Vout Voltage reference output — factory trim 1.1584 — 1.2376 V 1
Vout Voltage reference output — user trim 1.193 — 1.197 V 1
Vstep Voltage reference trim step — 0.5 — mV 1
Vtdrift Temperature drift (Vmax -Vmin across the full — — 50 mV 1
temperature range: 0 to 70°C)
Ibg Bandgap only current — — 80 µA 1
Ilp Low-power buffer current — — 360 uA 1
Ihp High-power buffer current — — 1 mA 1
ΔVLOAD Load regulation µV 1, 2
• current = ± 1.0 mA — 200 —
Tstup Buffer startup time — — 100 µs —

Tchop_osc_st Internal bandgap start-up delay with chop — — 35 ms —
up oscillator enabled
Vvdrift Voltage drift (Vmax -Vmin across the full — 2 — mV 1
voltage range)
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

NXP Semiconductors
Table 30. VREF limited-range operating requirements

TA Temperature 0 50 °C —
Table 31. VREF limited-range operating behaviors

Vout Voltage reference output with factory trim 1.173 1.225 V —
3.6.3 CMP and 6-bit DAC electrical specifications

Table 32. Comparator and 6-bit DAC electrical specifications
Symbol Description Min. Typ. Max. Unit
VDD Supply voltage 1.71 — 3.6 V
IDDHS Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA
IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA
VAIN Analog input voltage VSS – 0.3 — VDD V
VAIO Analog input offset voltage — — 20 mV
VH Analog comparator hysteresis1
• CR0[HYSTCTR] = 00 — 5 — mV
• CR0[HYSTCTR] = 01 — 10 — mV
• CR0[HYSTCTR] = 10 — 20 — mV
• CR0[HYSTCTR] = 11 — 30 — mV
VCMPOh Output high VDD – 0.5 — — V

VCMPOl Output low — — 0.5 V
tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns
tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns
Analog comparator initialization delay2 — — 40 μs
IDAC6b 6-bit DAC current adder (enabled) — 7 — μA
INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3
DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64

NXP Semiconductors
0.08
0.07
0.06
HYSTCTR
0.05
CMP Hystereris (V)
Setting
00
0.04 01
10
11
0.03
0.02
0.01
0
0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1
Vin level (V)
Figure 12. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

NXP Semiconductors
0.18
0.16
0.14
0.12
HYSTCTR
CMP Hysteresis (V)
Setting
0.1 00
01
0.08 10
11
0.06
0.04
0.02
0
0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1
Vin level (V)
Figure 13. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.4 12-bit DAC electrical characteristics
3.6.4.1 12-bit DAC operating requirements

Table 33. 12-bit DAC operating requirements
Symbol Desciption Min. Max. Unit Notes
VDDA Supply voltage 3.6 V
VDACR Reference voltage 1.13 3.6 V 1
CL Output load capacitance — 100 pF 2
IL Output load current — 1 mA
1. The DAC reference can be selected to be VDDA or VREFH.

2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

NXP Semiconductors
3.6.4.2 12-bit DAC operating behaviors

Table 34. 12-bit DAC operating behaviors
IDDA_DACL Supply current — low-power mode — — 250 μA
P
IDDA_DACH Supply current — high-speed mode — — 900 μA

P
tDACLP Full-scale settling time (0x080 to 0xF7F) — — 100 200 μs 1

low-power mode
tDACHP Full-scale settling time (0x080 to 0xF7F) — — 15 30 μs 1
high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to — 0.7 1 μs 1
0xC08) — low-power mode and high-
speed mode
Vdacoutl DAC output voltage range low — high- — — 100 mV
speed mode, no load, DAC set to 0x000
Vdacouth DAC output voltage range high — high- VDACR — VDACR mV
speed mode, no load, DAC set to 0xFFF −100
INL Integral non-linearity error — high speed — — ±8 LSB 2
mode
DNL Differential non-linearity error — VDACR > 2 — — ±1 LSB 3
V
DNL Differential non-linearity error — VDACR = — — ±1 LSB 4
VREF_OUT
VOFFSET Offset error — ±0.4 ±0.8 %FSR 5
EG Gain error — ±0.1 ±0.6 %FSR 5
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V 60 — 90 dB
TCO Temperature coefficient offset voltage — 3.7 — μV/C 6
TGE Temperature coefficient gain error — 0.000421 — %FSR/C
Rop Output resistance (load = 3 kΩ) — — 250 Ω
SR Slew rate -80h→ F7Fh→ 80h V/μs
• High power (SPHP) 1.2 1.7 —
• Low power (SPLP) 0.05 0.12 —
BW 3dB bandwidth kHz

• High power (SPHP) 550 — —
• Low power (SPLP) 40 — —
1. Settling within ±1 LSB

2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC
set to 0x800, temperature range is across the full range of the device

NXP Semiconductors
2
DAC12 INL (LSB)
-2
-4
-6
-8
0 500 1000 1500 2000 2500 3000 3500 4000
Digital Code
Figure 14. Typical INL error vs. digital code

NXP Semiconductors
1.499
1.4985
1.498
DAC12 Mid Level Code Voltage
1.4975
1.497
1.4965
1.496
-40 25 55 85 105 125
Temperature °C
Figure 15. Offset at half scale vs. temperature
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
3.8.1 USB electrical specifications

The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-
date standards, visit usb.org .

NXP Semiconductors
NOTE
The IRC48M do not meet the USB jitter specifications for
certification for Host mode operation.
This device cannot support Host mode operation.
3.8.2 USB VREG electrical specifications

Table 35. USB VREG electrical specifications
Symbol Description Min. Typ.1 Max. Unit Notes
VREGIN Input supply voltage 2.7 — 5.5 V
IDDon Quiescent current — Run mode, load current — 125 186 μA
equal zero, input supply (VREGIN) > 3.6 V
IDDstby Quiescent current — Standby mode, load — 1.1 10 μA
current equal zero
IDDoff Quiescent current — Shutdown mode
— 650 — nA
• VREGIN = 5.0 V and temperature=25 °C
— — 4 μA
• Across operating voltage and temperature
ILOADrun Maximum load current — Run mode — — 120 mA

ILOADstby Maximum load current — Standby mode — — 1 mA
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
3 3.3 3.6 V
• Standby mode
2.1 2.8 3.6 V
VReg33out Regulator output voltage — Input supply 2.1 — 3.6 V 2
(VREGIN) < 3.6 V, pass-through mode
COUT External output capacitor 1.76 2.2 8.16 μF
ESR External output capacitor equivalent series 1 — 100 mΩ
resistance
ILIM Short circuit current — 290 — mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.

2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.

NXP Semiconductors
3.8.3 SPI switching specifications

The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master
and slave operations. Many of the transfer attributes are programmable. The following
tables provide timing characteristics for classic SPI timing modes. See the SPI chapter
of the chip's Reference Manual for information about the modified transfer formats
used for communicating with slower peripheral devices.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted,
as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 36. SPI master mode timing on slew rate disabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation fperiph/2048 fperiph/2 Hz 1
2 tSPSCK SPSCK period 2 x tperiph 2048 x ns 2
tperiph
3 tLead Enable lead time 1/2 — tSPSCK —
4 tLag Enable lag time 1/2 — tSPSCK —
5 tWSPSCK Clock (SPSCK) high or low time tperiph - 30 1024 x ns —
tperiph
6 tSU Data setup time (inputs) 18 — ns —
7 tHI Data hold time (inputs) 0 — ns —
8 tv Data valid (after SPSCK edge) — 15 ns —
9 tHO Data hold time (outputs) 0 — ns —
10 tRI Rise time input — tperiph - 25 ns —
tFI Fall time input
11 tRO Rise time output — 25 ns —
tFO Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
Table 37. SPI master mode timing on slew rate enabled pads
1 fop Frequency of operation fperiph/2048 fperiph/2 Hz 1
2 tSPSCK SPSCK period 2 x tperiph 2048 x ns 2
tperiph
3 tLead Enable lead time 1/2 — tSPSCK —
4 tLag Enable lag time 1/2 — tSPSCK —
5 tWSPSCK Clock (SPSCK) high or low time tperiph - 30 1024 x ns —
tperiph

NXP Semiconductors
Table 37. SPI master mode timing on slew rate enabled pads (continued)
tFI Fall time input
SS1
(OUTPUT)
3 2 10 11 4
SPSCK 5
(CPOL=0)
(OUTPUT) 5
10 11
SPSCK
(CPOL=1)
(OUTPUT)
6 7
MISO
MSB IN2 BIT 6 . . . 1 LSB IN
(INPUT)
8 9
MOSI
(OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 16. SPI master mode timing (CPHA = 0)

NXP Semiconductors
SS1
(OUTPUT)
2
3 10 11 4
SPSCK
(CPOL=0)
(OUTPUT)
5 5 10 11
SPSCK
(CPOL=1)
(OUTPUT)
6 7
MISO
(INPUT) MSB IN2 BIT 6 . . . 1 LSB IN
8 9
MOSI
(OUTPUT) PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA
1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 17. SPI master mode timing (CPHA = 1)
Table 38. SPI slave mode timing on slew rate disabled pads
1 fop Frequency of operation 0 fperiph/4 Hz 1
2 tSPSCK SPSCK period 4 x tperiph — ns 2
3 tLead Enable lead time 1 — tperiph —
4 tLag Enable lag time 1 — tperiph —
5 tWSPSCK Clock (SPSCK) high or low time tperiph - 30 — ns —
6 tSU Data setup time (inputs) 2.5 — ns —
7 tHI Data hold time (inputs) 3.5 — ns —
8 ta Slave access time — tperiph ns 3
9 tdis Slave MISO disable time — tperiph ns 4
tFI Fall time input
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
38 <<CLASSIFICATION>>
<<NDA MESSAGE>>
NXP Semiconductors
Table 39. SPI slave mode timing on slew rate enabled pads
1 fop Frequency of operation 0 fperiph/4 Hz 1
2 tSPSCK SPSCK period 4 x tperiph — ns 2
3 tLead Enable lead time 1 — tperiph —
4 tLag Enable lag time 1 — tperiph —
5 tWSPSCK Clock (SPSCK) high or low time tperiph - 30 — ns —
8 ta Slave access time — tperiph ns 3
9 tdis Slave MISO disable time — tperiph ns 4
tFI Fall time input
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
SS
(INPUT)
2 12 13 4
SPSCK
(CPOL=0)
(INPUT)
3 5 5
SPSCK 12 13
(CPOL=1)
(INPUT)
9
8 10 11 11
MISO see SEE

note SLAVE MSB BIT 6 . . . 1 SLAVE LSB OUT
(OUTPUT) NOTE
6 7
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN
NOTE: Not defined
Figure 18. SPI slave mode timing (CPHA = 0)

NXP Semiconductors
SS
(INPUT)
2 4
3 12 13
SPSCK
(CPOL=0)
(INPUT)
5 5 12 13
SPSCK
(CPOL=1)
(INPUT)
10 11 9
MISO see
SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT
(OUTPUT) note
8 6 7
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN
NOTE: Not defined
Figure 19. SPI slave mode timing (CPHA = 1)
3.8.4 I2C
3.8.4.1 Inter-Integrated Circuit Interface (I2C) timing

Table 40. I2C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency fSCL 0 100 0 4001 kHz
Hold time (repeated) START condition. tHD; STA 4 — 0.6 — µs
After this period, the first clock pulse is
generated.
LOW period of the SCL clock tLOW 4.7 — 1.25 — µs
HIGH period of the SCL clock tHIGH 4 — 0.6 — µs
Set-up time for a repeated START tSU; STA 4.7 — 0.6 — µs
condition
Data hold time for I2C bus devices tHD; DAT 02 3.453 04 0.92 µs
Data set-up time tSU; DAT 2505 — 1003, 6 — ns
Rise time of SDA and SCL signals tr — 1000 20 +0.1Cb 7 300 ns
Fall time of SDA and SCL signals tf — 300 20 +0.1Cb 6 300 ns
Set-up time for STOP condition tSU; STO 4 — 0.6 — µs
Bus free time between STOP and tBUF 4.7 — 1.3 — µs
START condition
Pulse width of spikes that must be tSP N/A N/A 0 50 ns
suppressed by the input filter

NXP Semiconductors
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the high
drive pins across the full voltage range and when using the normal drive pins and VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU;
2
DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification) before the SCL line is released.
7. Cb = total capacitance of the one bus line in pF.
To achieve 1MHz I2C clock rates, consider the following recommendations:

• To counter the effects of clock stretching, the I2C baud Rate select bits can be
configured for faster than desired baud rate.
• Use high drive pad and DSE bit should be set in PORTx_PCRn register.
• Minimize loading on the I2C SDA and SCL pins to ensure fastest rise times for the
SCL line to avoid clock stretching.
• Use smaller pull up resistors on SDA and SCL to reduce the RC time constant.
Table 41. I 2C 1Mbit/s timing
Characteristic Symbol Minimum Maximum Unit
SCL Clock Frequency fSCL 0 11 MHz
Hold time (repeated) START condition. After this tHD; STA 0.26 — µs
period, the first clock pulse is generated.
LOW period of the SCL clock tLOW 0.5 — µs
HIGH period of the SCL clock tHIGH 0.26 — µs
Set-up time for a repeated START condition tSU; STA 0.26 — µs
Data hold time for I2C bus devices tHD; DAT 0 — µs
Data set-up time tSU; DAT 50 — ns
Rise time of SDA and SCL signals tr 20 +0.1Cb 120 ns
Fall time of SDA and SCL signals tf 20 +0.1Cb 2 120 ns
Set-up time for STOP condition tSU; STO 0.26 — µs
Bus free time between STOP and START condition tBUF 0.5 — µs
Pulse width of spikes that must be suppressed by tSP 0 50 ns
the input filter
1. The maximum SCL clock frequency of 1 Mbit/s can support maximum bus loading when using the high drive pins across
the full voltage range.
2. Cb = total capacitance of the one bus line in pF.

NXP Semiconductors
SDA
tSU; DAT tf
tf tLOW tr tHD; STA tSP tr tBUF
SCL
HD; STA tSU; STA tSU; STO

S tHD; DAT tHIGH SR P S
Figure 20. Timing definition for devices on the I2C bus
3.8.5 UART
See General switching specifications.
3.8.6 I2S/SAI switching specifications

This section provides the AC timing for the I2S/SAI module in master mode (clocks
are driven) and slave mode (clocks are input). All timing is given for noninverted
serial clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame
sync (TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame
sync have been inverted, all the timing remains valid by inverting the bit clock signal
(BCLK) and/or the frame sync (FS) signal shown in the following figures.
3.8.6.1 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 42. I2S/SAI master mode timing
Num. Characteristic Min. Max. Unit
S1 I2S_MCLK cycle time 40 — ns
S2 I2S_MCLK (as an input) pulse width high/low 45% 55% MCLK period
S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 — ns
S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ — 15.5 ns
I2S_RX_FS output valid

NXP Semiconductors
Table 42. I2S/SAI master mode timing (continued)

S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ 0 — ns
I2S_RX_FS output invalid
S7 I2S_TX_BCLK to I2S_TXD valid — 19 ns
S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns
S9 I2S_RXD/I2S_RX_FS input setup before 26 — ns
I2S_RX_BCLK
S10 I2S_RXD/I2S_RX_FS input hold after 0 — ns
I2S_RX_BCLK
S1 S2 S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/ S4
I2S_RX_BCLK (output) S4
S5 S6
I2S_TX_FS/
I2S_RX_FS (output)
S9 S10
I2S_TX_FS/
S7
I2S_RX_FS (input)
S7 S8
S8
I2S_TXD
S9 S10
I2S_RXD
Figure 21. I2S/SAI timing — master modes
Table 43. I2S/SAI slave mode timing

S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 — ns
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% MCLK period
(input)
S13 I2S_TX_FS/I2S_RX_FS input setup before 10 — ns
I2S_TX_BCLK/I2S_RX_BCLK
S14 I2S_TX_FS/I2S_RX_FS input hold after 2 — ns
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 33 ns
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns
S17 I2S_RXD setup before I2S_RX_BCLK 10 — ns

NXP Semiconductors
Table 43. I2S/SAI slave mode timing (continued)

S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid1 — 28 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/ S12
I2S_RX_BCLK (input)
S15 S16
I2S_TX_FS/
I2S_RX_FS (output) S13 S14
I2S_TX_FS/
I2S_RX_FS (input) S15
S19
S15 S16 S16
I2S_TXD
S17 S18
I2S_RXD
Figure 22. I2S/SAI timing — slave modes
3.8.6.2 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 44. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
S1 I2S_MCLK cycle time 62.5 — ns
S2 I2S_MCLK pulse width high/low 45% 55% MCLK period
S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 — ns
S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ — 45 ns
I2S_RX_FS output valid
S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ 0 — ns
I2S_RX_FS output invalid
S7 I2S_TX_BCLK to I2S_TXD valid — 45 ns
S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns

NXP Semiconductors
Table 44. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
S9 I2S_RXD/I2S_RX_FS input setup before — ns
I2S_RX_BCLK
S10 I2S_RXD/I2S_RX_FS input hold after 0 — ns
I2S_RX_BCLK
S1 S2 S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/ S4
I2S_RX_BCLK (output) S4
S5 S6
I2S_TX_FS/
I2S_RX_FS (output)
S9 S10
I2S_TX_FS/
S7
I2S_RX_FS (input)
S7 S8
S8
I2S_TXD
S9 S10
I2S_RXD
Figure 23. I2S/SAI timing — master modes
Table 45. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 — ns
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% MCLK period
(input)
S13 I2S_TX_FS/I2S_RX_FS input setup before 30 — ns
S14 I2S_TX_FS/I2S_RX_FS input hold after 2 — ns
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 87 ns
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns
S17 I2S_RXD setup before I2S_RX_BCLK 30 — ns
S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid1 — 72 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

NXP Semiconductors
S11
S12
I2S_TX_BCLK/ S12
I2S_RX_BCLK (input)
S15 S16
I2S_TX_FS/
I2S_RX_FS (output) S13 S14
I2S_TX_FS/
I2S_RX_FS (input) S15
S19
S15 S16 S16
I2S_TXD
S17 S18
I2S_RXD
Figure 24. I2S/SAI timing — slave modes
3.9 Human-machine interfaces (HMI)
3.9.1 LCD electrical characteristics

Table 46. LCD electricals
fFrame LCD frame frequency
• GCR[FFR]=0 23.3 — 73.1 Hz
• GCR[FFR]=1 46.6 — 146.2 Hz
CLCD LCD charge pump capacitance — nominal — 100 — nF

value
CBYLCD LCD bypass capacitance — nominal value — 100 — nF 1
CGlass LCD glass capacitance — 2000 8000 pF 2
VIREG VIREG V 3
• RVTRIM=0000 — 0.91 —
• RVTRIM=1000 — 0.92 —
• RVTRIM=0100 — 0.93 —
• RVTRIM=1100 — 0.94 —
• RVTRIM=0010 — 0.96 —
• RVTRIM=1010 — 0.97 —
• RVTRIM=0110 — 0.98 —
• RVTRIM=1110 — 0.99 —
• RVTRIM=0001 — 1.01 —

NXP Semiconductors
Dimensions
Table 46. LCD electricals (continued)

• RVTRIM=1001 — 1.02 —
• RVTRIM=0101 — 1.03 —
• RVTRIM=1101 — 1.05 —
• RVTRIM=0011 — 1.06 —
• RVTRIM=1011 — 1.07 —
• RVTRIM=0111 — 1.08 —
• RVTRIM=1111 — 1.09 —
ΔRTRIM VIREG TRIM resolution — — 3.0 % VIREG

IVIREG VIREG current adder — RVEN = 1 — 1 — µA
IRBIAS RBIAS current adder
• LADJ = 10 or 11 — High load (LCD glass — 10 — µA
capacitance ≤ 8000 pF)
• LADJ = 00 or 01 — Low load (LCD glass
— 1 — µA
RRBIAS RBIAS resistor values

• LADJ = 10 or 11 — High load (LCD glass — 0.28 — MΩ
• LADJ = 00 or 01 — Low load (LCD glass
— 2.98 — MΩ
VLL1 VLL1 voltage — — VIREG V 4

VLL2 VLL2 voltage — — 2 x VIREG V 4
VLL3 VLL3 voltage — — 3 x VIREG V 4
VLL1 VLL1 voltage — — VDDA / 3 V 5
VLL2 VLL2 voltage — — VDDA / 1.5 V 5
VLL3 VLL3 voltage — — VDDA V 5
1. The actual value used could vary with tolerance.

2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller chapter
within the device's reference manual.
3. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V
4. VLL1, VLL2 and VLL3 are a function of VIREG only when the regulator is enabled (GCR[RVEN]=1) and the charge pump
is enabled (GCR[CPSEL]=1).
5. VLL1, VLL2 and VLL3 are a function of VDDA only under either of the following conditions:
• The charge pump is enabled (GCR[CPSEL]=1), the regulator is disabled (GCR[RVEN]=0), and VLL3 = VDDA
through the internal power switch (GCR[VSUPPLY]=0).
• The resistor bias string is enabled (GCR[CPSEL]=0), the regulator is disabled (GCR[RVEN]=0), and VLL3 is
connected to VDDA externally (GCR[VSUPPLY]=1).
4 Dimensions
NXP Semiconductors
Pinouts and Packaging
4.1 Obtaining package dimensions

Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package Then use this document number
32-pin QFN 98ASA00615D
48-pin QFN 98ASA00616D
64-pin LQFP 98ASS23234W
64-pin MAPBGA 98ASA00420D
5 Pinouts and Packaging
5.1 Signal Multiplexing and Pin Assignments
5.1.1 MCX C44x Pin Assignments

The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
VREFH can act as VREF_OUT when VREFV1 module is
enabled.
64 64 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
MAP LQFP
BGA
A1 1 PTE0 DISABLED LCD_P48 PTE0/ SPI1_MISO LPUART1_TX RTC_CLKOUT CMP0_OUT I2C1_SDA LCD_P48
CLKOUT32K
B1 2 PTE1 DISABLED LCD_P49 PTE1 SPI1_MOSI LPUART1_RX SPI1_MISO I2C1_SCL LCD_P49
— 3 VDD VDD VDD
C4 4 VSS VSS VSS

NXP Semiconductors
MAP LQFP
BGA
E1 5 USB0_DP USB0_DP USB0_DP
D1 6 USB0_DM USB0_DM USB0_DM
E2 7 VOUT33 VOUT33 VOUT33
D2 8 VREGIN VREGIN VREGIN
G1 9 PTE20 ADC0_DP0/ LCD_P59/ PTE20 TPM1_CH0 LPUART0_TX FXI00_D4 LCD_P59
ADC0_SE0 ADC0_DP0/
ADC0_SE0
F1 10 PTE21 ADC0_DM0/ LCD_P60/ PTE21 TPM1_CH1 LPUART0_RX FXIO0_D5 LCD_P60
ADC0_SE4a ADC0_DM0/
ADC0_SE4a
G2 11 PTE22 ADC0_DP3/ ADC0_DP3/ PTE22 TPM2_CH0 UART2_TX FXIO0_D6
ADC0_SE3 ADC0_SE3
F2 12 PTE23 ADC0_DM3/ ADC0_DM3/ PTE23 TPM2_CH1 UART2_RX FXIO0_D7
ADC0_SE7a ADC0_SE7a
F4 13 VDDA VDDA VDDA
G4 14 VREFH VREFH VREFH
G3 15 VREFL VREFL VREFL
F3 16 VSSA VSSA VSSA
H1 17 PTE29 CMP0_IN5/ CMP0_IN5/ PTE29 TPM0_CH2 TPM_CLKIN0
ADC0_SE4b ADC0_SE4b
H2 18 PTE30 DAC0_OUT/ DAC0_OUT/ PTE30 TPM0_CH3 TPM_CLKIN1 LPUART1_TX LPTMR0_
ADC0_SE23/ ADC0_SE23/ ALT1
CMP0_IN4 CMP0_IN4
H3 19 PTE31 DISABLED PTE31 TPM0_CH4
H4 20 PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL
H5 21 PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA
D3 22 PTA0 SWD_CLK PTA0 TPM0_CH5 SWD_CLK
D4 23 PTA1 DISABLED PTA1 LPUART0_RX TPM2_CH0
E5 24 PTA2 DISABLED PTA2 LPUART0_TX TPM2_CH1
D5 25 PTA3 SWD_DIO PTA3 I2C1_SCL TPM0_CH0 SWD_DIO
G5 26 PTA4 NMI_b PTA4 I2C1_SDA TPM0_CH1 NMI_b
F5 27 PTA5 DISABLED PTA5 USB_CLKIN TPM0_CH2 I2S0_TX_
BCLK
H6 28 PTA12 DISABLED PTA12 TPM1_CH0 I2S0_TXD0
G6 29 PTA13 DISABLED PTA13 TPM1_CH1 I2S0_TX_FS
G7 30 VDD VDD VDD
H7 31 VSS VSS VSS
H8 32 PTA18 EXTAL0 EXTAL0 PTA18 LPUART1_RX TPM_CLKIN0
G8 33 PTA19 XTAL0 XTAL0 PTA19 LPUART1_TX TPM_CLKIN1 LPTMR0_
ALT1
F8 34 PTA20 RESET_b PTA20 RESET_b

NXP Semiconductors
MAP LQFP
BGA
F7 35 PTB0/ LCD_P0/ LCD_P0/ PTB0/ I2C0_SCL TPM1_CH0 LCD_P0
LLWU_P5 ADC0_SE8 ADC0_SE8 LLWU_P5
F6 36 PTB1 LCD_P1/ LCD_P1/ PTB1 I2C0_SDA TPM1_CH1 LCD_P1
ADC0_SE9 ADC0_SE9
E7 37 PTB2 LCD_P2/ LCD_P2/ PTB2 I2C0_SCL TPM2_CH0 LCD_P2
ADC0_SE12 ADC0_SE12
E8 38 PTB3 LCD_P3/ LCD_P3/ PTB3 I2C0_SDA TPM2_CH1 LCD_P3
ADC0_SE13 ADC0_SE13
E6 39 PTB16 LCD_P12 LCD_P12 PTB16 SPI1_MOSI LPUART0_RX TPM_CLKIN0 SPI1_MISO LCD_P12
D7 40 PTB17 LCD_P13 LCD_P13 PTB17 SPI1_MISO LPUART0_TX TPM_CLKIN1 SPI1_MOSI LCD_P13
D6 41 PTB18 LCD_P14 LCD_P14 PTB18 TPM2_CH0 I2S0_TX_ LCD_P14
BCLK
C7 42 PTB19 LCD_P15 LCD_P15 PTB19 TPM2_CH1 I2S0_TX_FS LCD_P15
D8 43 PTC0 LCD_P20/ LCD_P20/ PTC0 EXTRG_IN audioUSB_ CMP0_OUT I2S0_TXD0 LCD_P20
ADC0_SE14 ADC0_SE14 SOF_OUT
C6 44 PTC1/ LCD_P21/ LCD_P21/ PTC1/ I2C1_SCL TPM0_CH0 I2S0_TXD0 LCD_P21
LLWU_P6/ ADC0_SE15 ADC0_SE15 LLWU_P6/
RTC_CLKIN RTC_CLKIN
B7 45 PTC2 LCD_P22/ LCD_P22/ PTC2 I2C1_SDA TPM0_CH1 I2S0_TX_FS LCD_P22
ADC0_SE11 ADC0_SE11
C8 46 PTC3/ LCD_P23 LCD_P23 PTC3/ SPI1_SCK LPUART1_RX TPM0_CH2 CLKOUT I2S0_TX_ LCD_P23
LLWU_P7 LLWU_P7 BCLK
E3 47 VSS VSS VSS
E4 — VDD VDD VDD
C5 48 VLL3 VLL3 VLL3
A6 49 VLL2 VLL2 VLL2/ PTC20 LCD_P4
LCD_P4
B5 50 VLL1 VLL1 VLL1/ PTC21 LCD_P5
LCD_P5
B4 51 VCAP2 VCAP2 VCAP2/ PTC22 LCD_P6
LCD_P6
A5 52 VCAP1 VCAP1 VCAP1/ PTC23 LCD_P39
LCD_P39
B8 53 PTC4/ LCD_P24 LCD_P24 PTC4/ SPI0_SS LPUART1_TX TPM0_CH3 I2S0_MCLK LCD_P24
LLWU_P8 LLWU_P8
A8 54 PTC5/ LCD_P25 LCD_P25 PTC5/ SPI0_SCK LPTMR0_ I2S0_RXD0 CMP0_OUT LCD_P25
LLWU_P9 LLWU_P9 ALT2
A7 55 PTC6/ LCD_P26/ LCD_P26/ PTC6/ SPI0_MOSI EXTRG_IN I2S0_RX_ SPI0_MISO I2S0_MCLK LCD_P26
LLWU_P10 CMP0_IN0 CMP0_IN0 LLWU_P10 BCLK
B6 56 PTC7 LCD_P27/ LCD_P27/ PTC7 SPI0_MISO audioUSB_ I2S0_RX_FS SPI0_MOSI LCD_P27
CMP0_IN1 CMP0_IN1 SOF_OUT
C3 57 PTD0 LCD_P40 LCD_P40 PTD0 SPI0_SS TPM0_CH0 FXI00_D0 LCD_P40
A4 58 PTD1 LCD_P41/ LCD_P41/ PTD1 SPI0_SCK TPM0_CH1 FXIO0_D1 LCD_P41
ADC0_SE5b ADC0_SE5b

NXP Semiconductors
MAP LQFP
BGA
C2 59 PTD2 LCD_P42 LCD_P42 PTD2 SPI0_MOSI UART2_RX TPM0_CH2 SPI0_MISO FXIO0_D2 LCD_P42
B3 60 PTD3 LCD_P43 LCD_P43 PTD3 SPI0_MISO UART2_TX TPM0_CH3 SPI0_MOSI FXIO0_D3 LCD_P43
A3 61 PTD4/ LCD_P44 LCD_P44 PTD4/ SPI1_SS UART2_RX TPM0_CH4 FXI00_D4 LCD_P44
LLWU_P14 LLWU_P14
C1 62 PTD5 LCD_P45/ LCD_P45/ PTD5 SPI1_SCK UART2_TX TPM0_CH5 FXIO0_D5 LCD_P45
ADC0_SE6b ADC0_SE6b
B2 63 PTD6/ LCD_P46/ LCD_P46/ PTD6/ SPI1_MOSI LPUART0_RX SPI1_MISO FXIO0_D6 LCD_P46
LLWU_P15 ADC0_SE7b ADC0_SE7b LLWU_P15
A2 64 PTD7 LCD_P47 LCD_P47 PTD7 SPI1_MISO LPUART0_TX SPI1_MOSI FXIO0_D7 LCD_P47

pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
enabled.
NOTE
It is prohibited to set VREFEN in 32 QFN pin package as 1.2
V on-chip voltage is not available in this package.
QFN QFN
— 1 VDD VDD VDD
— 7 PTE20 ADC0_DP0/ ADC0_DP0/ PTE20 TPM1_CH0 LPUART0_TX FXI00_D4
ADC0_SE0 ADC0_SE0
— 8 PTE21 ADC0_DM0/ ADC0_DM0/ PTE21 TPM1_CH1 LPUART0_RX FXIO0_D5
ADC0_SE4a ADC0_SE4a
— 10 VREFH VREFH VREFH
— 11 VREFL VREFL VREFL
— 13 PTE29 CMP0_IN5/ CMP0_IN5/ PTE29 TPM0_CH2 TPM_CLKIN0
ADC0_SE4b ADC0_SE4b
— 15 PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL
— 16 PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA
— 29 PTB2 ADC0_SE12 ADC0_SE12 PTB2 I2C0_SCL TPM2_CH0
— 30 PTB3 ADC0_SE13 ADC0_SE13 PTB3 I2C0_SDA TPM2_CH1
— 31 PTB16 Disabled PTB16 SPI1_MOSI LPUART0_RX TPM_CLKIN0 SPI1_MISO
— 32 PTB17 Disabled PTB17 SPI1_MISO LPUART0_TX TPM_CLKIN1 SPI1_MOSI

NXP Semiconductors
QFN QFN
— 33 PTC0 ADC0_SE14 ADC0_SE14 PTC0 EXTRG_IN audioUSB_ CMP0_OUT I2S0_TXD0
SOF_OUT
— 41 PTD0 DISABLED PTD0 SPI0_SS TPM0_CH0 FXI00_D0
— 42 PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK TPM0_CH1 FXIO0_D1
— 43 PTD2 DISABLED PTD2 SPI0_MOSI UART2_RX TPM0_CH2 SPI0_MISO FXIO0_D2
— 44 PTD3 DISABLED PTD3 SPI0_MISO UART2_TX TPM0_CH3 SPI0_MOSI FXIO0_D3
1 — PTE0 DISABLED PTE0/ SPI1_MISO LPUART1_TX RTC_CLKOUT CMP0_OUT I2C1_SDA
CLKOUT32K
2 2 VSS VSS VSS
3 3 USB0_DP USB0_DP USB0_DP
4 4 USB0_DM USB0_DM USB0_DM
5 5 VOUT33 VOUT33 VOUT33
6 6 VREGIN VREGIN VREGIN
7 9 VDDA VDDA VDDA
8 12 VSSA VSSA VSSA
9 14 PTE30 DAC0_OUT/ DAC0_OUT/ PTE30 TPM0_CH3 TPM_CLKIN1 LPUART1_TX LPTMR0_
CMP0_IN4 CMP0_IN4
10 17 PTA0 SWD_CLK PTA0 TPM0_CH5 SWD_CLK
11 18 PTA1 DISABLED PTA1 LPUART0_RX TPM2_CH0
12 19 PTA2 DISABLED PTA2 LPUART0_TX TPM2_CH1
13 20 PTA3 SWD_DIO PTA3 I2C1_SCL TPM0_CH0 SWD_DIO
14 21 PTA4 NMI_b PTA4 I2C1_SDA TPM0_CH1 NMI_b
15 22 VDD VDD VDD
16 23 VSS VSS VSS
17 24 PTA18 EXTAL0 EXTAL0 PTA18 LPUART1_RX TPM_CLKIN0
18 25 PTA19 XTAL0 XTAL0 PTA19 LPUART1_TX TPM_CLKIN1 LPTMR0_
ALT1
19 26 PTA20 RESET_b PTA20 RESET_b
20 27 PTB0/ ADC0_SE8 ADC0_SE8 PTB0/ I2C0_SCL TPM1_CH0
LLWU_P5 LLWU_P5
21 28 PTB1 ADC0_SE9 ADC0_SE9 PTB1 I2C0_SDA TPM1_CH1
22 34 PTC1/ ADC0_SE15 ADC0_SE15 PTC1/ I2C1_SCL TPM0_CH0 I2S0_TXD0
LLWU_P6/ LLWU_P6/
RTC_CLKIN RTC_CLKIN
23 35 PTC2 ADC0_SE11 ADC0_SE11 PTC2 I2C1_SDA TPM0_CH1 I2S0_TX_FS
24 36 PTC3/ DISABLED PTC3/ SPI1_SCK LPUART1_RX TPM0_CH2 CLKOUT I2S0_TX_
25 37 PTC4/ DISABLED PTC4/ SPI0_SS LPUART1_TX TPM0_CH3 I2S0_MCLK
LLWU_P8 LLWU_P8
26 38 PTC5/ DISABLED PTC5/ SPI0_SCK LPTMR0_ I2S0_RXD0 CMP0_OUT

NXP Semiconductors
QFN QFN
27 39 PTC6/ CMP0_IN0 CMP0_IN0 PTC6/ SPI0_MOSI EXTRG_IN I2S0_RX_ SPI0_MISO I2S0_MCLK
28 40 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_MISO audioUSB_ I2S0_RX_FS SPI0_MOSI
SOF_OUT
29 45 PTD4/ DISABLED PTD4/ SPI1_SS UART2_RX TPM0_CH4 FXI00_D4
LLWU_P14 LLWU_P14
30 46 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI1_SCK UART2_TX TPM0_CH5 FXIO0_D5
31 47 PTD6/ ADC0_SE7b ADC0_SE7b PTD6/ SPI1_MOSI LPUART0_RX SPI1_MISO FXIO0_D6
LLWU_P15 LLWU_P15
32 48 PTD7 DISABLED PTD7 SPI1_MISO LPUART0_TX SPI1_MOSI FXIO0_D7

pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
enabled.
QFN QFN
— 1 VDD VDD VDD
— 2 VSS VSS VSS
— 7 PTE20 ADC0_DP0/ ADC0_DP0/ PTE20 TPM1_CH0 LPUART0_TX FXI00_D4
ADC0_SE0 ADC0_SE0
— 8 PTE21 ADC0_DM0/ ADC0_DM0/ PTE21 TPM1_CH1 LPUART0_RX FXIO0_D5
ADC0_SE4a ADC0_SE4a
— 10 VREFH VREFH VREFH
— 11 VREFL VREFL VREFL
— 13 PTE29 CMP0_IN5/ CMP0_IN5/ PTE29 TPM0_CH2 TPM_CLKIN0
ADC0_SE4b ADC0_SE4b
— 15 PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL
— 16 PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA
— 29 PTB2 ADC0_SE12 ADC0_SE12 PTB2 I2C0_SCL TPM2_CH0
— 30 PTB3 ADC0_SE13 ADC0_SE13 PTB3 I2C0_SDA TPM2_CH1
— 31 PTB16 DISABLED PTB16 SPI1_MOSI LPUART0_RX TPM_CLKIN0 SPI1_MISO
— 32 PTB17 DISABLED PTB17 SPI1_MISO LPUART0_TX TPM_CLKIN1 SPI1_MOSI
— 33 PTC0 ADC0_SE14 ADC0_SE14 PTC0 EXTRG_IN audioUSB_ CMP0_OUT I2S0_TXD0
SOF_OUT
— 41 PTD0 DISABLED PTD0 SPI0_PCS0 TPM0_CH0 FXI00_D0
— 42 PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK TPM0_CH1 FXIO0_D1

NXP Semiconductors
QFN QFN
— 43 PTD2 DISABLED PTD2 SPI0_MOSI UART2_RX TPM0_CH2 SPI0_MISO FXIO0_D2
— 44 PTD3 DISABLED PTD3 SPI0_MISO UART2_TX TPM0_CH3 SPI0_MOSI FXIO0_D3
— — Reserved Reserved Reserved
1 — PTE0 DISABLED PTE0/ SPI1_MISO LPUART1_TX RTC_CLKOUT CMP0_OUT I2C1_SDA
CLKOUT32K
2 — PTE1 DISABLED PTE1 SPI1_MOSI LPUART1_RX SPI1_MISO I2C1_SCL
3 3 PTE16 ADC0_DP1/ ADC0_DP1/ PTE16 SPI0_PCS0 UART2_TX TPM_CLKIN0 FXI00_D0
ADC0_SE1 ADC0_SE1
4 4 PTE17 ADC0_DM1/ ADC0_DM1/ PTE17 SPI0_SCK UART2_RX TPM_CLKIN1 LPTMR0_ FXI00_D1
ADC0_SE5a ADC0_SE5a ALT3
5 5 PTE18 ADC0_DP2/ ADC0_DP2/ PTE18 SPI0_MOSI I2C0_SDA SPI0_MISO FXI00_D2
ADC0_SE2 ADC0_SE2
6 6 PTE19 ADC0_DM2/ ADC0_DM2/ PTE19 SPI0_MISO I2C0_SCL SPI0_MOSI FXI00_D3
ADC0_SE6a ADC0_SE6a
7 9 VDDA VDDA VDDA
8 12 VSSA VSSA VSSA
9 14 PTE30 DAC0_OUT/ DAC0_OUT/ PTE30 TPM0_CH3 TPM_CLKIN1 LPUART1_TX LPTMR0_
CMP0_IN4 CMP0_IN4
10 17 PTA0 SWD_CLK PTA0 TPM0_CH5 SWD_CLK
11 18 PTA1 DISABLED PTA1 LPUART0_RX TPM2_CH0
12 19 PTA2 DISABLED PTA2 LPUART0_TX TPM2_CH1
13 20 PTA3 SWD_DIO PTA3 I2C1_SCL TPM0_CH0 SWD_DIO
14 21 PTA4 NMI_b PTA4 I2C1_SDA TPM0_CH1 NMI_b
15 22 VDD VDD VDD
16 23 VSS VSS VSS
17 24 PTA18 EXTAL0 EXTAL0 PTA18 LPUART1_RX TPM_CLKIN0
18 25 PTA19 XTAL0 XTAL0 PTA19 LPUART1_TX TPM_CLKIN1 LPTMR0_
ALT1
19 26 PTA20 RESET_b PTA20 RESET_b
20 27 PTB0/ ADC0_SE8 ADC0_SE8 PTB0/ I2C0_SCL TPM1_CH0
LLWU_P5 LLWU_P5
21 28 PTB1 ADC0_SE9 ADC0_SE9 PTB1 I2C0_SDA TPM1_CH1
22 34 PTC1/ ADC0_SE15 ADC0_SE15 PTC1/ I2C1_SCL TPM0_CH0 I2S0_TXD0
LLWU_P6/ LLWU_P6/
RTC_CLKIN RTC_CLKIN
23 35 PTC2 ADC0_SE11 ADC0_SE11 PTC2 I2C1_SDA TPM0_CH1 I2S0_TX_FS
24 36 PTC3/ DISABLED PTC3/ SPI1_SCK LPUART1_RX TPM0_CH2 CLKOUT I2S0_TX_

NXP Semiconductors
QFN QFN
25 37 PTC4/ DISABLED PTC4/ SPI0_PCS0 LPUART1_TX TPM0_CH3 I2S0_MCLK
LLWU_P8 LLWU_P8
26 38 PTC5/ DISABLED PTC5/ SPI0_SCK LPTMR0_ I2S0_RXD0 CMP0_OUT
27 39 PTC6/ CMP0_IN0 CMP0_IN0 PTC6/ SPI0_MOSI EXTRG_IN I2S0_RX_ SPI0_MISO I2S0_MCLK
28 40 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_MISO audioUSB_ I2S0_RX_FS SPI0_MOSI
SOF_OUT
29 45 PTD4/ DISABLED PTD4/ SPI1_PCS0 UART2_RX TPM0_CH4 FXI00_D4
LLWU_P14 LLWU_P14
30 46 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI1_SCK UART2_TX TPM0_CH5 FXIO0_D5
31 47 PTD6/ ADC0_SE7b ADC0_SE7b PTD6/ SPI1_MOSI LPUART0_RX SPI1_MISO FXIO0_D6
LLWU_P15 LLWU_P15
32 48 PTD7 DISABLED PTD7 SPI1_MISO LPUART0_TX SPI1_MOSI FXIO0_D7
5.2 MCX C44X Family Pinouts
5.2.1 MCX C44x Pinouts

Figure below shows the 64 LQFP pinouts

NXP Semiconductors
PTD4/LLWU_P14
PTD6/LLWU_P15
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
VCAP2
VCAP1
PTD5
PTD2
PTD3
PTD1
PTC7
PTD0
PTD7
VLL2
VLL1
61
51
62
52
59
55
49
58
56
60
50
64
63
57
54
53
PTE0 1 48 VLL3
PTE1 2 47 VSS
VDD 3 46 PTC3/LLWU_P7
VSS 4 45 PTC2
USB0_DP 5 44 PTC1/LLWU_P6/RTC_CLKIN
USB0_DM 6 43 PTC0
VOUT33 7 42 PTB19
VREGIN 8 41 PTB18
PTE20 9 40 PTB17
PTE21 10 39 PTB16
PTE22 11 38 PTB3
PTE23 12 37 PTB2
VDDA 13 36 PTB1
VREFH 14 35 PTB0/LLWU_P5
VREFL 15 34 PTA20
VSSA 16 33 PTA19
21
31
22
25
26
28
29
23
24
27
32
30
20
19
18
17
PTE31
PTE30
PTE24
PTE29
PTE25
VSS
PTA0
PTA3
PTA4
PTA13
PTA12
PTA1
PTA2
PTA5
PTA18
VDD
Figure 25. 64 LQFP Pinout diagram
Figure below shows the 64 MAPBGA pinouts

NXP Semiconductors
1 2 3 4 5 6 7 8
PTD4/ PTC6/
A PTE0 PTD7 PTD1 VCAP1 VLL2 PTC5/ A
LLWU_P14 LLWU_P10 LLWU_P9
PTD6/ PTC4/
B PTE1 PTD3 VCAP2 VLL1 PTC7 PTC2 B
LLWU_P15 LLWU_P8
PTC1/
PTC3/
C PTD5 PTD2 PTD0 VSS VLL3 LLWU_P6/ PTB19 C
LLWU_P7
RTC_CLKIN
D USB0_DM VREGIN PTA0 PTA1 PTA3 PTB18 PTB17 PTC0 D
E USB0_DP VOUT33 VSS VDD PTA2 PTB16 PTB2 PTB3 E
PTB0/
F PTE21 PTE23 VSSA VDDA PTA5 PTB1 PTA20 F
LLWU_P5
G PTE20 PTE22 VREFL VREFH PTA4 PTA13 VDD PTA19 G
H PTE29 PTE30 PTE31 PTE24 PTE25 PTA12 VSS PTA18 H
1 2 3 4 5 6 7 8
Figure 26. 64 MAPBGA Pinout diagram

Figure below shows the 32 QFN pinouts:

NXP Semiconductors
PTD6/LLWU_P15
PTD4/LLWU_P14
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
PTD7
PTD5
PTC7
31
32
29
25
30
28
26
27
PTE0 1 24 PTC3/LLWU_P7
VSS 2 23 PTC2
USB0_DM 4 21 PTB1
VOUT33 5 20 PTB0/LLWU_P5
VREGIN 6 19 PTA20
VDDA 7 18 PTA19
VSSA 8 17 PTA18
12
13
14
15
16
10
11
9
PTA1
PTA2
PTE30
VDD
PTA0
VSS
PTA3
PTA4
Figure 27. 32 QFN Pinout diagram
Figure below shows the 48 QFN pinouts:

NXP Semiconductors
PTD6/LLWU_P15
PTD4/LLWU_P14
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
PTD7
PTD5
PTD3
PTD2
PTD1
PTD0
PTC7
41
42
45
48
46
47
44
43
39
40
38
37
VSS 2 35 PTC2
USB0_DM 4 33 PTC0
VOUT33 5 32 PTB17
VREGIN 6 31 PTB16
PTE20 7 30 PTB3
PTE21 8 29 PTB2
VDDA 9 28 PTB1
VREFH 10 27 PTB0/LLWU_P5
VREFL 11 26 PTA20
VSSA 12 25 PTA19
21
22
23
24
20
13
14
15
16
18
19
17
PTE24
PTA2
PTE25
PTA1
PTA3
PTE29
PTE30
PTA0
PTA4
VDD
VSS
PTA18

Figure below shows the 32 QFN pinouts

NXP Semiconductors
PTD6/LLWU_P15
PTD4/LLWU_P14
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
PTD7
PTD5
PTC7
31
32
29
25
30
28
26
27
PTE0 1 24 PTC3/LLWU_P7
PTE1 2 23 PTC2
PTE16 3 22 PTC1/LLWU_P6/RTC_CLKIN
PTE17 4 21 PTB1
PTE18 5 20 PTB0/LLWU_P5
PTE19 6 19 PTA20
VDDA 7 18 PTA19
VSSA 8 17 PTA18
12
13
14
15
16
10
11
9
PTA1
PTE30
PTA2
VDD
VSS
PTA0
PTA3
PTA4
Figure below shows the 48 QFN pinouts

NXP Semiconductors
Ordering parts
PTD6/LLWU_P15
PTD4/LLWU_P14
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
PTD7
PTD5
PTD3
PTD2
PTD1
PTD0
PTC7
41
42
48
46
45
47
44
43
39
38
40
37
VSS 2 35 PTC2
PTE16 3 34 PTC1/LLWU_P6/RTC_CLKIN
PTE17 4 33 PTC0
PTE18 5 32 PTB17
PTE19 6 31 PTB16
PTE20 7 30 PTB3
PTE21 8 29 PTB2
VDDA 9 28 PTB1
VREFH VREFO 10 27 PTB0/LLWU_P5
VREFL 11 26 PTA20
VSSA 12 25 PTA19
21
22
23
24
20
19
13
14
15
16
18
17
PTE24
PTA2
PTE25
PTA1
PTA3
PTE29
PTE30
PTA0
PTA4
VDD
VSS
PTA18
6 Ordering parts
6.1 Determining valid orderable parts

Valid orderable part numbers are provided on the Web. To determine the orderable part
numbers for this device, go to nxp.com and perform a part number search for the
following device numbers:
7 Part identification

NXP Semiconductors
Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
B PS F C FS T PG SR PT
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 47. Part number fields descriptions
Field Description Values
B Brand • MCX
PS Product series name • C
F Family • 0 = Entry
• 1 = Baseline
• 2 = Baseline Enhance
• 3 = Reserved
• 4 = HMI
C Core feature • 4 = 48MHz
FS Flash size • 1 = 32 KB
• 2 = 64 KB
• 3 = 128 KB
• 4 = 256 KB
T Temperature range (°C) • V = –40 to 125
PG Package • FG = 16QFN: 3x3x0.65 mm
• FK = 24QFN: 4x4x0.65 mm
• FM = 32QFN: 5x5x0.9 mm
• FT = 48QFN: 7x7x0.9 mm
• LH = 64LQFP: 10x10x1.6mm
• MP = 64MAPBGA: 5x5x1.23mm
SR Silicon revision • A = Initial Mask set
• B = 1st Major spin
PT Packaging type • R = Tape and reel
• T = Tray

NXP Semiconductors
Terminology and guidelines
7.4 Example
This is an example part number:
MCXC444VLH
8 Terminology and guidelines
8.1 Definitions
Key terms are defined in the following table:
Term Definition
Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.

NXP Semiconductors
Terminology and guidelines
8.2 Examples
Operating rating:
E
PL
AM
EX
Operating requirement:
E
PL
AM
EX
Operating behavior that includes a typical value:
E
PL
AM
EX
8.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol Description Value Unit
TA Ambient temperature 25 °C
VDD 3.3 V supply voltage 3.3 V

NXP Semiconductors
Revision History
8.4 Relationship between ratings and operating requirements

) .)
in. ax
(m (m .)
n.) nt en
t
ax
( mi eme em (m
tin
g uir uir tin
g
gr
a req r eq ra
tin t ing tin
g ing
ra era era rat
O pe Op Op Ope
Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range
Expected permanent failure - No permanent failure - No permanent failure - No permanent failure Expected permanent failure
- Possible decreased life - Correct operation - Possible decreased life
- Possible incorrect operation - Possible incorrect operation
–∞ ∞
Operating (power on)
in.
)
ax.)
(m (m
i ng i ng
rat rat
ng ng
n dli nd
li
Ha Ha
Fatal range Handling range Fatal range
Expected permanent failure No permanent failure Expected permanent failure
–∞ ∞
Handling (power off)
8.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
9 Revision History
The following table provides a revision history for this document.
Table 48. Revision History
Rev. No. Date Substantial Changes
2 07/2024 Initial release

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Date of release: 07/2024

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Data Sheet: Technical Data Rev. 2, 07/2024

MCX C44X Microcontroller MCXC4x4(R)

System and clocks

Communication interfaces for connectivity

Table continues on the next page...

2 MCX C44X Microcontroller, Rev. 2, 07/2024

The following figure shows the block diagram of this device:

Figure 1. Block diagram

MCX C44X Microcontroller, Rev. 2, 07/2024 3

Figure 2. Architecture diagram

4 MCX C44X Microcontroller, Rev. 2, 07/2024

MCX C44X Microcontroller, Rev. 2, 07/2024 5

1.1 Thermal handling ratings

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

1.2 Moisture handling ratings

1.3 ESD handling ratings

6 MCX C44X Microcontroller, Rev. 2, 07/2024

1.4 Voltage and current operating ratings

2.1 AC electrical characteristics

The midpoint is VIL + (VIH - VIL) / 2

Figure 3. Input signal measurement reference

MCX C44X Microcontroller, Rev. 2, 07/2024 7

2.2 Nonswitching electrical specifications

2.2.1 Voltage and current operating requirements

VIL Input low voltage

VHYS Input hysteresis 0.06 × VDD — V

IICcont Contiguous pin DC injection current —regional limit,

VODPU Open drain pullup voltage level VDD VDD V 2

2.2.2 LVD and POR operating requirements

Table continues on the next page...

8 MCX C44X Microcontroller, Rev. 2, 07/2024

Table 6. VDD supply LVD and POR operating requirements (continued)

1. Rising thresholds are falling threshold + hysteresis voltage

2.2.3 Voltage and current operating behaviors

VOH Output high voltage — high drive pad 1

IOHT Output high current total for all ports — 100 mA

MCX C44X Microcontroller, Rev. 2, 07/2024 9

Table 7. Voltage and current operating behaviors (continued)

IOLT Output low current total for all ports — 100 mA

2.2.4 Power mode transition operating behaviors

Table continues on the next page...

10 MCX C44X Microcontroller, Rev. 2, 07/2024

Table 8. Power mode transition operating behaviors (continued)

1. Normal boot (FTFA_FOPT[LPBOOT]=11)

2.2.5 Power consumption operating behaviors

IDD_RUNCO Running While(1) loop in flash in compute

IDD_RUN Run mode current—48M HIRC mode, running 2

IDD_RUN Run mode current—48M HIRC mode, running 2

Table continues on the next page...

MCX C44X Microcontroller, Rev. 2, 07/2024 11

Table 9. Power consumption operating behaviors (continued)

IDD_RUN Run mode current—48M HIRC mode, running 2

IDD_RUN Run mode current—48M HIRC mode, running 2

IDD_RUN Run mode current—48M HIRC mode, running

IDD_RUN Run mode current—48M HIRC mode, running

IDD_RUN Run mode current—48M HIRC mode, Running

IDD_RUN Run mode current—48M HIRC mode, Running

IDD_RUN Run mode current—48M HIRC mode, running