Computer Architecture-UNIT II

Register Transfer and Micro-operations

In symbolic notation, it is used to describe the micro-operations transfer among registers. It is a kind of
intermediate representation (IR) that is very close to assembly language, such as that which is used in a
compiler.The term “Register Transfer” can perform micro-operations and transfer the result of operation to
the same or other register.
Micro-operations :
The operation executed on the data store in registers are called micro-operations. They are detailed low-
level instructions used in some designs to implement complex machine instructions.
Register Transfer :
The information transformed from one register to another register is represented in symbolic form by
replacement operator is called Register Transfer.
Replacement Operator :
In the statement, R2 <- R1, <- acts as a replacement operator. This statement defines the transfer of content
of register R1 into register R2.

Basic symbols of RTL :

Symbol Description Example

Letters and Numbers Denotes a Register MAR, R1, R2

R1(8-bit)

() Denotes a part of register R1(0-7)

<- Denotes a transfer of information R2 <- R1

R1 <- R2

, Specify two micro-operations of Register Transfer R2 <- R

P : R2 <- R1

: Denotes conditional operations if P=1

Naming Operator (:=) Denotes another name for an already existing register/alias Ra := R1

Bus and Memory Transfers:

 A more efficient scheme for transferring information between registers in a multiple-register

configuration is a Common Bus System.
 A common bus consists of a set of common lines, one for each bit of a register.
 Control signals determine which register is selected by the bus during each particular register
transfer.
 Different ways of constructing a Common Bus System
 Using Multiplexers
 Using Tri-state Buffers
Memory Transfer:

 The transfer of information from a memory word to the outside environment is called a read
operation.
 The transfer of new information to be stored into the memory is called a write operation.
 A memory word will be symbolized by the letter M.
 The particular memory word among the many available is selected by the memory address during
the transfer.
 It is necessary to specify the address of M when writing memory transfer operations.
 This will be done by enclosing the address in square brackets following the letter M.
 Consider a memory unit that receives the address from a register, called the address register,
symbolized by AR.
 The data are transferred to another register, called the data register, symbolized by DR.
 The read operation can be stated as follows:

Read:DR<-M[AR]

 This causes a transfer of information into DR from the memory word M selected by the address in
AR.
 The write operation transfers the content of a data register to a memory word M selected by the
address. Assume that the input data are in register R1 and the address is in AR.
 The write operation can be stated as follows:
Write:M[AR]<- R1

Types of Micro-operations:

 Arithmetic Micro-operations: Perform arithmetic operation on numeric data stored in registers.

 Logical Micro-operations: Perform bit manipulation operations on data stored in registers.
 Shift Micro-operations: Perform shift operations on data stored in registers.

ArithmeticMicro-operations:

 The basic arithmetic micro-operations are

o Addition
o Subtraction
o Increment
o Decrement
o Shift
 The arithmetic Micro-operation defined by the statement below specifies the add micro-
operation.
R3 ←R1+R2
 It states that the contents of R1 are added to contents of R2 and sum is transferred to R3.
 To implement this statement hardware requires 3 registers and digital component that performs
addition
 Subtraction is most often implemented through complementation and addition.
 The subtract operation is specified by the following statement
 R3←R1+R2+1
 in stead of minus operator,we can write as

 R2 is the symbol for the1’s complement ofR2

 Adding 1to1’ s complement produces 2’scomplement
 Adding the contents of R1 to the2's complement of R2 is equivalent to R1-R2.

BinaryAdder:

 Digital circuit that forms the arithmetic sum of 2bits and the previous carry is called FULLADDER.
 Digital circuit that generates the arithmetic sum of 2binary umbers of any lengths is called
BINARYADDER.
 Figure4-6 shows the inter connections of four full-adders (FA)to provide a 4-bit binary adder.

 The augends bits of A and the addend bits of B are designated by subscript numbers from
right to left, with subscript 0 denoting the low-order bit.
 The carries are connected in a chain through the full-adders. The input carry to the
binary adder is Co and the out put carry is C4.The S outputs of the full-adders
generate the required sum bits.
 An n-bit binary adder requires n full-adders.

BinaryAdder–Subtractor:

 The addition and subtraction operations can be combined into one common circuit by including an
exclusive-OR gate with each full-adder.
 A 4-bitadder-subtractor circuit is showninFig.4-7.

 The mode input M controls the operation. When M = 0 the circuit is an adder and when M = 1 the
circuit be comesa subtractor.
 Each exclusive-OR gate receives input M and one of the inputs o fB
 When M = 0, we have B xor 0 = B. The full-adders receive the value of B, the input carry is 0,
and the circuit performs A plus B.
 When M=1,wehaveBxor 1 =B' and Co= 1.
  The B inputs are all complemented and a 1 is added through the input carry.
 The circuit performs the operation A plus the 2'scomplement of B.

BinaryIncrementer:

 The increment microoperation adds one to a number in a register.

 Forexample,ifa4-bit registerhasabinaryvalue0110,itwillgoto0111 after it is incremented.
 This can be accomplished by means of half-adders connected in cascade.
 Thediagramofa4-bit 'combinational circuit incrementerisshowninFig.4-8.

 One of the inputs to the least significant half-adder (HA) is connected to logic-1 and the other
input is connected to the least significant bit of the number to be incremented.
 The output carry from one half-adder is connected to one of the inputs of the next-higher-order
half-adder.
 The circuit receives the four bits from A0 through A3, adds one to it, and generates
theincrementedoutputinS0throughS3.
 The output carry C4will be 1 only after incrementing binary 1111. This also causes outputs
S0throughS3togoto0.

 The circuit of Fig. 4-8 can be extended to an n -bit binary incrementer by extending the diagram to
include n half-adders.
 The least significant bit must have one input connected to logic-1. The other inputs receive the
number to be incremented or the carry from the previous stage.
Logic Micro-operations:

 Logic micro operations specify binary operations for strings of bits stored in registers.
 These operations consider each bit of the register separately and treat them as binary variables.
 For example, the exclusive-OR micro operation with the contents of two registers RI and R2
is symbolized by the statement

 It specifies a logic micro operation to be executed on the individual bits of the registers provided
that the control variable P=1.

List of Logic Micro operations:

 Thereare16differentlogicoperationsthatcanbeperformedwithtwobinaryvariables.

 The 16 Boolean functions of two variables x and y are expressed in algebraic form in the
firstcolumnofTable4-6.
 The16 logic micro operations are derived from these functions by replacing variable x by the
binary content of register A and variable y by the binary content of register B.
 The logic micro-operations listed in the second column represent a relationship between the
binary content of two registers A and B.

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Shift Micro operations:

 Shift micro operations are used for serial transfer of data.

 The contents of a register can be shifted to the left or the right.
 During a shift-left operation the serial in put transfers a bit into the right most position.
 During a shift-right operation the serial in put transfers a bit into the left most position.
 There are three types of shifts: logical, circular, and arithmetic.
 The symbolic notation for the shift micro operations is shown inTable4-7.

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  Logical Shift:
o A logical shift is one that transfers 0 through the serial input.
o The symbols shl and shr for logical shift-left and shift-right micro operations.

o The micro operations that specify a 1-bit shift to the left of the content of register R and
a1-bit shift to the right of the content of register R shown intable4.7.
o The bit transferred to the end position through the serial input is assumed to be 0 during a
logical shift.

 Circular Shift:
o The Circular shift (also known as a rotate operation) circulates the bits of the register
a round the two ends without loss of information.
o This is accomplished by connecting the serial output of the shift register to its serial input.
o We will use the symbols cil and cir for the circular shift left and right, respectively.
 Arithmetic Shift:
o An arithmetic shift is a micro operation that shifts a signed binary number to the left or
right.
o An arithmetic shift-left multiplies a signed binary number by 2.
o An arithmetic shift-right divides the numberby2.
o Arithmetic shifts must leave the sign bit unchanged because the sign of the number
remains the same when it is multiplied or divided by 2.

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Arithmetic Logic Shift Unit:

 Instead of having individual registers performing the micro operations directly, computer systems
employ a number of storage registers connected to a common operational unit called an arithmetic
logic unit, abbreviated ALU.
 The ALU is a combinational circuits that the entire register transfer operation from the
source registers through the ALU and into the destination register can be performed during one
clock pulse period.
 The shift micro operations are often performed in a separate unit, but sometimes the shift unit is
made part of the over all ALU.
 The arithmetic, logic, and shift circuits introduced in previous sections can be combined into one
ALU with common selection variables. One stage of an arithmetic logic shift unit is shown in Fig.
4-13.
 Particular micro operation is selected with inputs S1 and S0.A 4 x 1 multiplexer at the output
chooses between an arithmetic output in Di and a logic output in Ei.
 The data in the multiplexer are selected with inputs S3 and S2.The other two data inputs to
themultiplexerreceiveinputsAi-1forthe shift-right operation and Ai+1fortheshift-leftoperation.
 The circuit whose one stage is specified in Fig. 4-13 provides eight arithmetic operation, four logic
operations, and two shift operations.
 Each operation is selected withthefivevariablesS3,S2,S1,S0and Cin.
 The input carry Cin is used for selecting n arithmetic operation only.

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  Table 4-8 lists the 14 operations of the ALU. The first eight are arithmetic operations and are
selected with S3S2=00.
 The next four are logic and are selected withS3S2= 01.
 The input carry has no effect during the logic operations and is marked with don't-care x’ s.
 The last two operations are shift operations and are selected withS3S2=10 and11.
 The other three selection inputs have no effect on the shift.

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 MICROPROGRAMMEDCONTROL

Introduction:
 The function of the control unit in a digital computer is to initiate sequence of micro operations.
 Control unit can be implemented in two ways
o Hardwired control
o Microprogrammed

control

Hardwired Control:

 When the control signals are generated by hardware using conventional logic design techniques, the
control unit is said to be hardwired.
 The key characteristics are
O High speed of operation
O Expensive
O Relatively complex
O No flexibility of adding new instructions
 Examples of CPU with hardwired control unit are Intel 8085, Motorola 6802, Zilog 80, and any

RISC CPUs.

Microprogrammed Control:

 Control information is stored in control memory.

 Control memory is programmed to initiate the required sequence of micro-operations.
 The key characteristics are
 Speed of operation is low when compared with hardwired
 Less complex
 Less expensive
 Flexibility to add new instructions
 Examples of CPU with microprogrammed control unit are Intel8080,Motorola68000andanyCISCCPUs.

1. Control Memory:

 The control function that specifies a microoperation is called as control variable.

 When control variable is in one binary state, the corresponding micro peration is executed. For
the other binary state the state of registers does not change.
 The active state of a control variable may be either 1 state or the 0 state, depending on the application.
 For bus-organized systems the control signals that specify micro operations are groups of bits
that select the paths in multiplexers, decoders, and arithmetic logic units.
 Control Word: The control variables at any given time can be represented by a string of 1’s and
0's called a control word.
 All control words can be programmed to perform various operations on the components of the system.
 Microprogram control unit: A control unit whose binary control variables are stored in memory
is called a micro program control unit.
 The control word in control memory contains with in it a microinstruction.
 The micro instruction specifies one or more micro-operations for the system.
 A sequence of microinstructions constitutes a micro program.

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 The control unit consists of control memory used to store the micro program.

 Control memory is a permanent i.e., read only memory(ROM).

 The general configuration of a micro-programmed control unit organization is shown as block diagram
below.

 The control memory is ROM so all control information is permanently stored.

 The control memory address register (CAR) specifies the address of the microinstruction and the
control data register(CDR) holds the micro instruction read from memory.
 The next address generator is sometimes called a microprogram sequencer. It is used to generate
the next micro instruction address.
 The location of the next microinstruction may be the one next in sequence or it may be located
some where else in the control memory.
 So it is necessary to use some bits of the present microinstruction to control the generation of the
address of the microinstruction.
 Some times the next address may also be a function of external input conditions.
 The control data register holds the present micro instruction while next address is computed and
read from memory. The data register is called a pipeline register.

 A computer with a microprogrammed control unit will have two separate memories: a main
memory and a control memory
 The microprogram consists of microinstructions that specify various internal control signals for
execution of register micro operations
 These micro instructions generate the micro operations to:
 Fetch the instruction from main memory
 Evaluate the effective address
 execute the operation
 return control to the fetch phase for the next instruction

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2. AddressSequencing:

 Micro instructions are stored in control memory in groups, with each group specifying a routine.
 Each computer instruction has its own micro program routine to generate the micro operations.
 The hardware that controls the address sequencing of the control memory must be capable of
sequencing the microinstructions within a routine and be able to branch from one routine to another
 Steps the control must undergo during the execution of a single computer instruction:
o Load an initial address into the CAR when power is turned on in the computer. This address
is usually the address of the first microinstruction that activates the instruction fetch routine –
IR holds instruction
o The control memory then goes through the routine to determine the effective address of the
operand
– AR holds operand address
o The next step is to generate the micro operations that execute the instruction by
considering the opcode and applying a mapping process.
 The transformation of the instruction code bits to an address in control memory
where the routine of instruction located is referred to as mapping process.

o After execution, control must return to the fetch routine by executing an unconditional branch
 In brief the address sequencing capabilities required in a control memory are:
o Incrementing of the control address register.
o Unconditional branch or conditional branch ,depending on status bit conditions.
o A mapping process from the bits of the instruction to an address o control memory. A facility
for subroutine call and return.
 The below figure shows a block diagram of a control memory and the associated hardware
needed for selecting the next microinstruction address.

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 The microinstruction in control memory contains a set of bits to initiate micro operations in computer
registers and other bits to specify the method by which the next address is obtained.
 In the figure four different paths form which the control address register(CAR) receives the address.
o The increment increments the content of the control register address register by one, to select
the next micro instruction in sequence.
o Branching is achieved by specifying the branch address in one of the fields of the
microinstruction.
o Conditional branching is obtained by using part of the microinstruction to select a specific
status bit in order to determine its condition.
o An external address is transferred in to control memory via a mapping logic circuit.
o The return address for a subroutine is stored in a special register, that value is used
when the micro program wishes to return from the subroutine.

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3.MicroprogramExample:
 The process of code generation for the control memory is called microprogramming.
 The block diagram of the computer configuration is shown in below figure.
 Two memory units:
 Main memory – stores instructions and data
 Control memory– stores microprogram
 Four processor registers
 Program counter–PC
 Address register –AR
 Data register–DR
 Accumulator register-AC
 Two control unit registers
 Control address register–CAR
 Subroutine register– SBR

 Transfer of information among registers in the processor is through MUXs rather than a bus.

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 4. Design of control Unit:

 The control memory out of each sub field must be decoded to provide the distinct micro operations.
 The outputs of the decoders are connected to the appropriate inputs in the process or unit.
 The below figure shows the three decoders and some of the connections that must be made
from theiroutputs.

 The three fields of the microinstruction in the output of control memory are decoded with a 3x8
decoder to provide eight outputs.
 Each of the output must be connected to proper circuit to initiate the corresponding
microoperation as specified in previous topic.

 WhenF1=101(binary5),the next pulse transition transfers the content of DR(0-10) to AR.

 Similarly, when F1= 110 (binary 6) there is a transfer from PC to AR (symbolized by
PCTAR). As shown inFig,outputs 5 and6 of decoder F1 a reconnected to the load input
of AR
so that when either one of these outputs is active, information from the multiplexers is
transferred to AR.
 The multiplexers select the information from DR when output5 is active and from
PC when output 5 is inactive.
 The transfer into AR occurs with a clock transition only when output 5 or output 6 of the
decode r is active.
 For the arithmetic logic shift unit the controls signals are instead of coming from the
logical gates, now these inputs will now come from the outputs of AND, ADD and
DRTAC respectively.

Input/Output Subsystem

The I/O subsystem of a computer provides an efficient mode of communication between the central system
and the outside environment. It handles all the input-output operations of the computer system.

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Peripheral Devices

Input or output devices that are connected to computer are called peripheral devices. These devices are
designed to read information into or out of the memory unit upon command from the CPU and are considered
to be the part of computer system. These devices are also called peripherals.

For example: Keyboards, display units and printers are common peripheral devices.

There are three types of peripherals:

1. Input peripherals : Allows user input, from the outside world to the computer. Example: Keyboard,
Mouse etc.

2. Output peripherals: Allows information output, from the computer to the outside world. Example:
Printer, Monitor etc

3. Input-Output peripherals: Allows both input(from outised world to computer) as well as,
output(from computer to the outside world). Example: Touch screen etc.

Interfaces

Interface is a shared boundary between two separate components of the computer system which can be used to
attach two or more components to the system for communication purposes.

There are two types of interface:

1. CPU Inteface

2. I/O Interface

Let's understand the I/O Interface in details,

Input-Output Interface

Peripherals connected to a computer need special communication links for interfacing with CPU. In computer
system, there are special hardware components between the CPU and peripherals to control or manage the
input-output transfers. These components are called input-output interface units because they provide
communication links between processor bus and peripherals. They provide a method for transferring
information between internal system and input-output devices.

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Modes of I/O Data Transfer

Data transfer between the central unit and I/O devices can be handled in generally three types of modes which
are given below:

1. Programmed I/O

2. Interrupt Initiated I/O

3. Direct Memory Access

Programmed I/O

Programmed I/O uses the I/O instructions written in the computer program. The instructions in the program
initiate every data item transfer. Usually, the data transfer is from a memory and CPU register. This case
requires constant monitoring by the peripheral device's CPU.

Interrupt Initiated I/O

In the programmed I/O method the CPU stays in the program loop until the I/O unit indicates that it is ready
for data transfer. This is time consuming process because it keeps the processor busy needlessly.

This problem can be overcome by using interrupt initiated I/O. In this when the interface determines that the
peripheral is ready for data transfer, it generates an interrupt. After receiving the interrupt signal, the CPU
stops the task which it is processing and service the I/O transfer and then returns back to its previous
processing task.
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Example

Below step by step execution will happen when we pressed a key on the keyboard:-

1) The keyboard sends a scan code of the key to the keyboard controller (Scan code for key pressed and key
released is different)

2) The keyboard controller interprets the scan code and stores it in a buffer

3) The keyboard controller sends a hardware interrupt to the processor.This is done by putting signal on
“interrupt request line”: IRQ 1

4) The interrupt controller maps IRQ 1 into INT 9

5) An interrupt is a signal which tells the processor to stop what it was doing currently and do some special
task

6) The processor invokes the “Interrupt handler” CPU fetches the address of “Interrupt Service Routine”
(ISR) from “Interrupt Vector Table” maintained by the OS (Processor use the IRQ number for this)

7) The ISR reads the scan code from port 60h and decides whether to process it or pass the control to
program for taking action.

Direct Memory Access

Direct memory access (DMA) is a method that allows an input/output (I/O) device to send or receive data
directly to or from the main memory, bypassing the CPU to speed up memory operations.

The process is managed by a device known as a DMA controller (DMAC).

DMA controller provides an interface between the bus and the input-output devices. Although it transfers data
without intervention of processor, it is controlled by the processor. The processor initiates the DMA controller
by sending the starting address, Number of words in the data block and direction of transfer of data .i.e. from
I/O devices to the memory or from main memory to I/O devices. More than one external device can be
connected to the DMA controller.

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DMA controller contains an address unit, for generating addresses and selecting I/O device for transfer. It also
contains the control unit and data count for keeping counts of the number of blocks transferred and indicating
the direction of transfer of data. When the transfer is completed, DMA informs the processor by raising an
interrupt.

Instruction-level parallelism

Instruction-level parallelism (ILP) is a measure of how many operations in a computer program can be
performed "in-parallel" at the same time

1. e = a + b
2. f = c + d
3. g = e * f

Operation 3 depends on the results of "e" and "f" which are calculated from operations 1 and 2, so "g" cannot
be calculated until both of "e" and "f" are computed. However, operations 1 and 2 do not depend on any other
operation, so they can be computed simultaneously. If we assume that each operation can be completed in one
unit of time then these three instructions can be completed in a total of two units of time, giving an ILP factor
of 3/2; which means 3/2 = 1.5 greater than without ILP.

Data Hazards
Data Hazards occur when an instruction depends on the result of previous instruction and that result of
instruction has not yet been computed. whenever two different instructions use the same storage. the
location must appear as if it is executed in sequential order.
There are four types of data dependencies: Read after Write (RAW), Write after Read (WAR), Write after

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Write (WAW), and Read after Read (RAR). These are explained as follows below.
 Read after Write (RAW) :
It is also known as True dependency or Flow dependency. It occurs when the value produced by an
instruction is required by a subsequent instruction. For example,
ADD R1, --, --;
SUB --, R1, --;
Stalls are required to handle these hazards.
 Write after Read (WAR) :
It is also known as anti dependency. These hazards occur when the output register of an instruction is
used right after read by a previous instruction. For example,
ADD --, R1, --;
SUB R1, --, --;

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