Cpe117 E01 Cordova, Vincent

CPE117 Activity 1
Student Name: Vincent M. Cordova
Title: A Power-Aware Heterogeneous Architecture Scaling

Model for Energy-Harvesting Computers
Author/s: Harsh Desai, Brandon Lucia
I. Describing the Tools of Research

Using your one of your chosen IEEE research article, describe
how the author/s was able to utilize/apply the following research
tools.
a. The Library and its Resources

In the references, the list of the references was browsed by the authors in
books and journals both online and libraries.
b. The Computer and its Software

As shown in the references, the authors took most of it in the internet
through journals and databases in some websites.
c. Techniques of Measurement
Energy-harvesting equipment is essential for enabling future widespread
applications that involve sensing because they last a long time and need
little upkeep. The energy cost of sending data to the edge or cloud is
avoided when felt data, like photos, are processed locally on the device.
Implementing a PHASE architecture reduces end-to-end latency, including
recharging time, by combining heterogeneous components. The standard
energy-harvesting device's architecture is displayed. An integrated low-
power microcontroller (MCU) is linked to auxiliary devices and a power
supply. Energy-capturing elements energy from sources, such as radio
waves (RF), and storing it.
d. Statistics
The authors used three different input traces Indoors+Outdoors, Road
trip and NYC night-time in this iterator. They have common tests include t-
tests, ANOVA, or non-parametric equivalents.
e. The Human Mind

The authors provides a methodology or framework for creating and
improving computer systems that can run on gathered energy, with an
emphasis on reducing power usage and maximizing energy efficiency.
f. Language
The language used by the authors was English, so every reader can
understand what they were trying to say by they creating.
II. The Problem and its Setting

1. Write the statement of the problem
To ensure they are durable and require minimal upkeep. The significant
energy cost of processing sensed data on-device, such as pictures, is
avoided by sending data to the cloud or the edge.
2. Identify the research objective/s.

To ensure that the PHASE model helps us to understand end-to-end
latency in an energy harvesting device.
3. What are the delimitations?

The researchers has given the single-workload heterogeneity, utilizing a
variety of architectural elements that can carry out the same calculation with
varying levels of performance and efficiency. The second form, known as
PHASE-parallel, divides a workload. On a variety of components
simultaneously. The key is workload and how to transfer it to parallel
members.
4. Enumerate the importance of the study

In constructing PHASE structures that can do up to 9 times as much work
on a fixed energy budget as conventional energy-harvesting architectures,
our results demonstrate that the PHASE model contributes to
understanding end-to-end latency in an energy harvesting device.
Compared to fixed, naïve partitionings, the best division of labor in PHASE-
parallel systems speeds things up by up to 10. In our opinion, the PHASE
model will serve as a roadmap for scientists as they develop future, high-
performance energy harvesting devices.
III. Methodology
Enumerate the author’s step by step research methodologies in
terms of
1. Data Gathering
The authors did not put any method of data gathering.
2. Experimentation
The authors did not put any method of experimentation.
3. Evaluation/Testing
The authors used simulation to demonstrate that PHASE is power-
dependent. In PHASE-serial, core switching reduces latency while
increasing throughout. Total work done in a specific length of time. It also
demonstrate that Parallel work is dynamically partitioned based on input
power. A PHASE-parallel architecture results in a speedup over a power-
oblivious, fixed partitioning.
4. Processes to arrive at a conclusion

In order to meet the objectives and eventually solve the problem.
It indicates that a PHASE-serial multi-accelerator architecture may perform
up to 9 times the work of a single-accelerator system. Furthermore, efficient
work partitioning in PHASE-parallel systems yields up to 10 times the
performance. Over naïve, fixed partitionings. The PHASE model will aid
researchers in developing future high-performance energy-harvesting devices.
The statistics provide an upper bound on performance while neglecting work
migration overheads and granularity, but they demonstrate the promise of
PHASE-serial heterogeneity.
Title: CashHMC: A Cycle-Accurate Simulator for Hybrid
Memory Cube
Author/s: Dong-Ik Jeon, Ki-Seok Chung
I. Describing the Tools of Research

Using your one of your chosen IEEE research article, describe
how the author/s was able to utilize/apply the following research
tools.
a. The Library and its Resources

In the references, the list of the references was browsed by the authors in
books and journals both online and libraries.
b. The Computer and its Software

As shown in the references, the authors took most of it in the internet
through journals and databases in some websites.
c. Techniques of Measurement
Dynamic random access memory, commonly used as the primary
memory, has been constantly developed for several decades. As far as
semiconductor manufacturing technology is concerned, DRAM capacity,
bandwidth, and power consumption have all advanced. have all been
enhanced.
d. Statistics
The authors used many methods of statistics during HMC bandwidth and
It’s table.
e. The Human Mind

The authors provides a great attention because of its usability for server
systems and processing-in-memory architecture.
f. Language
The language used by the authors was English, so every reader can
understand what they were trying to say by they creating.
II. The Problem and its Setting

1. Write the statement of the problem
To ensure that the limits of the conventional DRAM has been actively
studied.
2. Identify the research objective/s.

To be linked to the other processor components through high speed serial
links.
3. What are the delimitations?
The researchers has given the power is used extensively by high-speed
serial communications. As a result, HMC power modeling will be valuable
for power-aware HMC memory scheduling. Simultaneous simulation in
parallel with other simulators that create memory access patterns, such as
a CPU simulator or a memory trace generator, is made possible by
instantiating this single-wrapped object.
4. Enumerate the importance of the study

High-speed serial connections need a lot of power. As a result, power
modeling for HMCs will be helpful for power-aware HMC memory
scheduling. This single-wrapped object allows for concurrent simulation with
other simulators that generate memory access patterns, such as a CPU
simulator or a memory trace generator. The development is frequently said
to have hit a stalemate as a result of the technological limit of
semiconductor manufacturing and circuit design. 3D-stacked DRAM has
been developed to address this limitation much attention.
III. Methodology
Enumerate the author’s step by step research methodologies in
terms of
1. Data Gathering
The authors did not put any method of data gathering.
2. Experimentation
The authors did not put any method of experimentation.
3. Evaluation/Testing
The authors used the CasHMC simulation run is completed with four log
files. The debugging and log files listed above are the state files. The
configuration file contains the simulation run's parameter information. The
end outcome the file contains the simulation results, including the number of
requests, reads, writes, packet flow, bandwidth, and average
latency. These outcomes are also presented per link.
4. Processes to arrive at a conclusion

In order to meet the objectives and eventually solve the problem.
HMC must be connected to other CPU components through
Serial connections with high throughput. As a result, communication capacity and
delay should be considered.HMC's performance should be carefully estimated.
However, the majority of current
HMC simulators only use basic HMC modeling. In this study, we offer CasHMC, a
cycle accurate simulator for hybrid memory cubes. It offers a
cycle-by-cycle simulation of each module in an HMC, producing an analysis. A
bandwidth graph and statistical data are included in the results.

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CPE117 Activity 1

Student Name: Vincent M. Cordova

Title: A Power-Aware Heterogeneous Architecture Scaling

I. Describing the Tools of Research

a. The Library and its Resources

b. The Computer and its Software

e. The Human Mind

II. The Problem and its Setting

2. Identify the research objective/s.

3. What are the delimitations?

4. Enumerate the importance of the study

4. Processes to arrive at a conclusion

I. Describing the Tools of Research

a. The Library and its Resources

b. The Computer and its Software

e. The Human Mind

II. The Problem and its Setting

2. Identify the research objective/s.

4. Enumerate the importance of the study

4. Processes to arrive at a conclusion

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