STV 2310

® STV2310
Multistandard TV digital video decoder

with adaptive comb filter and RGB/YCrCb input
Features
■ Worldwide TV Standards Compatible
■ Automatic NTSC/PAL/SECAM Digital Chroma
Decoder
■ NTSC/PAL Adaptive 4H/2D Comb Filter
■ VBI Data Slicer for Teletext, Closed Caption,
WSS and other systems TQFP64 14x14x1.4 mm
(Thin Quad Flat Package)
■ Analog RGB/Fast Blanking Capture and
Insertion in YCrCb Output Flow (SCART
s)
t(
ORDER CODE: STV2310D/DT
legacy)
■ Analog YCrCb inputs with Tint Control
u c
■ 10-bit, 30-MSPS A/D Converter for Y/CVBS
o d
input
■ 8-bit, 30-MSPS A/D Converter for C and RGB/ P r
CrCb inputs
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■ Hue control and automatic flesh control for le
so
TQFP64 10x10x1.4 mm
NTSC CVBS/YC signals (Thin Quad Flat Package)
■ Programmable Horizontal Scaling (x0.25 to
x4 Scaling Factor) and Panorama Vision Ob ORDER CODE: STV2310SD/SDT
■ Copy-Protection System compatible

) -
( s The STV2310 is a high-quality front-end video
ct
■ H and V Synchronisation Processing that is
circuit for processing all analog NTSC/PAL/SECAM
robust to non-standard sources such as
d u
VCR, and to weak and noisy signals
standards into a 4:2:2 YCrCb digital video format
,as well as conventional analog RGB or YCrCb
r o
■ 8-bit Pixel Output Interface Line-Locked ITU- signals. The STV2310 is programmable through an
e P
R BT_656/601 or square pixel YCrCb outputs
■ Single System Clock for all Video Input
I²C interface.
Formats
l et The STV2310 provides a cost-effective solution for
digitized TV, LCD TV/monitors, digital TV, STB,
s o
■ Two-wire I²C Bus Interface up to 400 kHz video surveillance/security, video conferencing,
O b
■ Typical Power Consumption: 550 mW
■ Power Supply: 1.8 V and 3.3 V
video capturing devices and PC video card.
It can be used as a stand-alone chip working with
third-party products, as a companion chip to the TV
processor STV3500, STV3600 for digitized 100-Hz/
ProScan CRT TVs, or as a companion chip to the
TV processor STV3550 for LCD-TVs.
November 2008 Rev 4 1/113

2/113
O b s
o l ete
Fully Automatic Line
P
Luma PAL/NTSC/
r
C Chro Form
SECAM at
o
Analog ma
Conve
d
to Sepa
CVBS1/Y rter
u
Digital rator Adaptive
CVBS2/Y Luminance
and
Conver
ct
Outpu
(
sion 4H/
s
VBI
)
Data
-
R/Cr Analog Cr
to Cb
O
G Tint
Data Selection YCrCb[7:0]
Digital
b
B/Cb and Output
s
Clock
o
I2C
le
Figure 1: STV2310 Block Diagram
Clock Synchronizatio HSYNC
t
Bus Gener n VSYNC
STV2310 e P Field
r o d u ct( s)
STV2310
STV2310
Table of Contents
Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Chapter 2 Pin Allocation and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

2.1 Pinout Diagram ................................................................................................................... 9
2.2 Pin Descriptions ................................................................................................................. 9
Chapter 3 Default Setup At Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.1 System Clock Generation .................................................................................................. 13
Chapter 4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4.1 Analog Input Stage ............................................................................................................. 14
s)
4.1.1
t(
General Description ..............................................................................................................................14
c
4.2
4.1.2
d
Synchronization and Monitoring Unit ................................................................................. 16 u
Programming ........................................................................................................................................16
4.2.1
r o
4.2.2
P
Programming ........................................................................................................................................17
e
4.3 t
Input Sample Rate Conversion .......................................................................................... 18
le
4.3.1
o
s
4.4
4.4.1
Ob
Luminance and Chrominance Separation .......................................................................... 19
4.4.2
-
Programming ........................................................................................................................................19
)
4.5
s
Standard Research Sequence Programming .................................................................... 21
(
4.6
ct
Standard Identification ....................................................................................................... 23
u
4.7
d
Chroma Demodulation ....................................................................................................... 23
o
4.7.1
4.7.2
Pr General Description ..............................................................................................................................23
Programming ........................................................................................................................................23
4.8
t e
Soft Mixer ........................................................................................................................... 24
e
o l4.8.1 General Description ..............................................................................................................................24
bs
4.8.2 Programming ........................................................................................................................................24
4.9 Output Scaler and Format Converter ................................................................................. 25

O 4.9.1
4.9.2
Programming ........................................................................................................................................27
4.10 RGB Insertion ..................................................................................................................... 28

4.10.1 General Description ..............................................................................................................................28
4.10.2 Programming ........................................................................................................................................29
4.11 Analog YCrCb Mode .......................................................................................................... 29
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STV2310
4.11.1 General Description ............................................................................................................................. 29

4.11.2 Programming ....................................................................................................................................... 29
4.12 Output FIFO and Line-locked Ouput Pixel Clock Generator ..............................................29
4.12.1 General Description ............................................................................................................................. 29
4.12.2 Output Data ......................................................................................................................................... 30
4.12.3 Insertion of Ancillary Data .................................................................................................................... 40
4.12.4 Line-Locked Output Pixel Clock Generation ........................................................................................ 41
4.12.5 Alternate Functions: Bus Extensions ................................................................................................... 41
4.12.6 Output Code Clipping ........................................................................................................................... 41
4.12.7 Programming ....................................................................................................................................... 41
4.13 VBI Data Slicing and Insertion ............................................................................................42

4.13.1 VBI Formatting Features ...................................................................................................................... 43
4.13.2 Data Output Format (DOF) .................................................................................................................. 44
4.14 I²C Bus Specifications ........................................................................................................53
Chapter 5 Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

s)
5.1 Register Map .....................................................................................................................55
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5.2 Non-VBI Control Register Descriptions ..............................................................................59
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5.3
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VBI Control Register Descriptions ......................................................................................87
5.4 P
Acknowledge Registers ......................................................................................................96
e
5.5
le t
Status Registers .................................................................................................................97
s o
Chapter 6
b
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
O
6.1
-
Absolute Maximum Ratings .............................................................................................101
)
6.2
s
Thermal Data ...................................................................................................................101
(
6.3
ct
Operating Conditions .......................................................................................................101
u
6.4
d
CVBS/Y/C Analog Inputs ..................................................................................................101
o
6.5
r
R/G/B and Cr/Cb Inputs ....................................................................................................102
P
6.6
e
FB Input ...........................................................................................................................103
et
6.7
o lAnalog-to-Digital Converter (ADC) ..................................................................................103
bs
6.8 Analog Reference Levels .................................................................................................103
O 6.9
6.10
YCrCb, Hsync, Vsync, Field and PLL Lock Outputs .........................................................103
Clock Data Output ...........................................................................................................104
6.11 CLKSEL, TST_MODE, NRESET and I2CADD Inputs .....................................................104
6.12 Main Clock Characteristics ..............................................................................................104
6.13 Horizontal/Vertical Synchronization Block .......................................................................106
6.14 Chroma Block ..................................................................................................................106
6.15 I²C Bus Characteristics ...................................................................................................106
4/113
STV2310
Chapter 7 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

7.1 TQFP64 14x14 Package ................................................................................................. 108
7.2 TQFP64 10x10 Package ................................................................................................. 109
7.3 Lead-free Packaging ........................................................................................................ 109
Chapter 8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
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General Description STV2310
1 General Description
The STV2310 is a high-quality video front-end circuit for processing all analog standards into a
digitalized 4:2:2 YCrCb video format. It processes NTSC/PAL/SECAM CVBS signals, as well as
conventional analog RGB or YCrCb signals.
This circuit outputs demodulated chrominance, in-phased luminance and sliced Vertical Blanking
Interval (VBI) data for the most common services such as Teletext, Closed Caption, WSS, VPS,
Gemstar.
The STV2310 does not need an external synchronization system. It extracts all necessary
synchronization signals from CVBS or Y signals, and delivers the horizontal, vertical and frame
signals either on dedicated pins or embedded into the digital bit stream.
It features automatic standard recognition and automatic selection of the optimal Y/C separation
algorithm according to the standard and has extensive output scaling capabilities. The STV2310
chip includes an analog RGB capture feature and programmable automatic mixing with the main
picture digital output.
8-bit ITU-R BT.601/656 and Square Pixel output standards are supported.
s)
c t(
The STV2310 provides a cost-effective solution for digitized TV, LCD TV/monitors, digital TV, STB,
u
video surveillance/security, video conferencing, video capturing devices and PC video card.
d
r o
It can be used as a stand-alone chip working with third-party products, as a companion chip to the
to the TV processor STV3550 for LCD-TVs.

e P
TV processor STV3500, STV3600 for digitized 100-Hz/ProScan CRT TVs, or as a companion chip
le t
All sub-level blocks operate at the frequency used as a sampling frequency (fS) for the five
o
embedded A/D converters. This free-running clock is called the system clock (fS) and is provided
s
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STV2310 General Description
either by an embedded crystal oscillator or an external clock generator (27 MHz).The only
exception is the output stage which operates at the line-locked output pixel clock frequency.
Figure 2: Architectural Block Diagram
CVBS1/Y
Luma Standard Identifier
CVBS2/Y
Chroma & Chroma Demodulator
C Input Separator PAL/NTSC/SECAM
Adaptive Luminance Delay
SRC 4H/2D
Analog
Input Comb
Stage Filter
Soft Mixer
R/Cr
G RGB/CrCb
B/Cb Processing
CrCb Tint
FB Format Converter
RGB Gain & Output Scaler
FB Delay
s)
t(
Video Correction
SDA
SCL
I²C
Interface VBI Slicer
u c
o d YCrCb[7:0]
HSYNC
CLKSEL
CLKXTH
System
Clock
Synchronization
and Monitoring Unit
Output FIFO
P r
Line-locked Output Pixel Clock
VSYNC
Field
Generation
e
Line-locked
le t Ouput Pixel
Clock
27 MHz
PLLLOCK/IRQ
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General Description STV2310
Figure 3: Application Block Diagram
1.8 VANA 1.8 VANA

150 Ω
470 Ω
1 64 60 59 58 62 61 11 12
4
CVBS1/Y 63 1.8 VANA
5
VREF ADC
CVBS2/Y 2
7
57 10 1.8 VANA
3.3 VANA
8
56
C 3 ADC 14
3.3 VANA
45 SHIELD 15
47 8
s)
t(
R_CR 17
8 Chroma/Luma VBI 1.8 VANA
c
51
Processing Data Slicer 18
G 52 ADC
8
d u
B_CB
53
8
r o 24
3.3 VOUT
48
e P 23
Optional
FB 46
le t Digital Core
28
so
27
Data Formatting
49
1.8 VANA
50
Ob 26
25
-
Y Cr Cb Output
54 22
(t s)
1.8 VANA
55 21
c
3.3 V 20
d u 19
SCL 10
r o Synchronization and Monitoring 33 HSYNC
P
SDA 9
34 VSYNC
3.3 VANA
et e 35 FIELD
o l 13 NRESET Digital Core 32 PLLLOCK
bs
31 CLK_DATA
16 I2CADD*
O 40
Time
Base 29
1.8 VOUT
30
36 38 37 39 44 42 41 43 6
NC
1.8 VANA
27 MHz CLKXTM TST_MODE
CLKSEL
1.8 VANA
* Possible alternate I²C address. See Section 5.1: Register Map on page 55.
8/113
STV2310 Pin Allocation and Description
2 Pin Allocation and Description
2.1 Pinout Diagram

Figure 4: 64-Pin 14 x 14 TQFP Package Pinout
VIDEOCOMM
REFM_CVBS
REFP_CVBS
VCC18_RGB
VIDEO_OUT
VCC18_DIG
GND_CVBS
GND_RGB
VCC33_IO
GND_DIG
CVBS1_Y
GND_IO
ADCIN
R_CR
B_CB
G
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
CC18_CVBS 1 48 REFM_RGB
VBS2_Y 2 47 REFP_RGB
3 46 FB
DD18_CORE
S
4
5
45
44
SHIELD
CLKSEL
s)
T_MODE 6 43 CLKXTM
c t(
XTALIN_CLKXTP
u
DD18_CORE 7 42
S 8 41
40
o d
XTALOUT
GND_CLK
r
DA 9
39
P
CL 10 VCC18_CLK
DD18_CORE 11 38 VCC18_SUB
S 12
te 37 GND_SUB
RESET
DD33_IO
13
14
o le 36
35
NC
FIELD
S_IO 15
b s 34
33
VSYNC
HSYNC
O
CADD 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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Pin Descriptions
b s Table 1: Power Supply Pins (page 1 of 2)
O Pin Pin Name Pin Description
Analog
1 VCC18_CVBS 1.8 V Analog Voltage Supply for Analog Input Stage
36 NC Not connected
37 GND_SUB Analog Ground Supply (Substrate Polarization)
38 VCC18_SUB 1.8 V Analog Voltage Supply (Output and Pin Isolation layer)
39 VCC18_CLK 1.8 V Analog Voltage Supply for Clock Generator
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Pin Allocation and Description STV2310
Table 1: Power Supply Pins (page 2 of 2)
Pin Pin Name Pin Description
40 GND_CLK Analog Ground Supply for Clock Generator
45 SHIELD Guard Ring (Analog Input Stage) To be connected to Analog Ground Supply
49 VCC18_RGB 1.8 V Analog Voltage Supply (RGB)
50 GND_RGB Analog Ground Supply (RGB)
54 VCC18_DIG 1.8 V Analog Voltage Supply (Analog Input Stage)
55 GND_DIG Analog Ground Supply (Analog Input Stage)
56 GND_IO Analog Ground Supply (Analog Input Stage)
57 VCC33_IO 3.3 V Analog Voltage Supply (Analog Input Stage)
64 GND_CVBS Analog Ground Supply (Analog Input Stage)
Digital
4 VDD18_CORE 1.8 V Digital Voltage Supply (Digital Core)
s)
5 VSS Digital Ground Supply (Digital Core)
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8 VSS Digital Ground Supply (Digital Core)
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12
14
VSS
VDD33_IO
Digital Ground Supply (Digital Core)
3.3 V I/O Voltage Supply (Digital Core)

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15 VSS_IO I/O Ground Supply
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17 VDD18_CORE
Ob
1.8 V Digital Voltage Supply (Digital Core)
18 VSS
-
Digital Ground Supply (Digital Core)
)
23 VSS_IOOUT
( s
Output Ground Supply (Output Stage)
24 VDD33_OUT
ct
3.3 V Output Voltage Supply (Output Stage)
u
29 VDD18_OUT
o d
1.8 V Digital Voltage Supply (Output Stage)
30 VSS_OUT
Pr Digital Ground Supply (Output Stage)
et e Table 2: Analog Pins (page 1 of 2)
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bs
O
2
3
CVBS2_Y
C
CVBS or Y Input 2 (Selected by programming)
Chroma Input (Y/C inputs used for S-Video) (Selected by programming)
46 FB Fast Blanking Input (To be used only when R_CR, G, and B_CB inputs are connected)
47 REFP_RGB Positive Reference Voltage for RGB ADCs
48 REFM_RGB Negative Reference Voltage for RGB ADCs
51 R_CR R Input for RGB Insertion. Cr Input for Analog YCrCb mode.
52 G G Input for RGB Insertion.
53 B_CB B Input for RGB Insertion. Cb Input for Analog YCrCb mode.
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STV2310 Pin Allocation and Description
Table 2: Analog Pins (page 2 of 2)
58 ADCIN CVBS ADC Input (To be connected to Anti-Aliasing Filter output)
59 VIDEOCOMM CVBS Anti-Aliasing Filter Reference Voltage
60 VIDEO_OUT Video Analog Front-end Multiplexer Output for external filtering
61 REFP_CVBS Positive Reference Voltage for CVBS and Chroma ADCs
62 REFM_CVBS Ground CVBS and Chroma ADCs
63 CVBS1_Y CVBS or Y Input 1 (Selected by programming)
Table 3: Output Pins
Pin Pin Name Type Pin Description
19 YCRCB7 O Digital Video Output 7

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28 YCRCB0 O
o
Digital Video Output 0
s
31 CLK_DATA O
b
Output Pixel Clock, active edge is programmable
O
-
32 PLLLOCK/IRQ O Output PLL Lock Signal
)
Alternate Function 1: OUTBUS[0] Bus extension
s
Alternate Function 2: Interrrupt Request (IRQ)
(
33 HSYNC O
u ct Horizontal Synchronization Pulse Output

Alternate Function: OUTBUS[1] Bus extension
34 VSYNC
o d
O Vertical Synchronization Pulse Output
35 FIELD Pr O
Alternate Function: OUTBUS[2] Bus extension
Field (Parity) Output Signal
et e Alternate Function: OUTBUS[3] Bus extension
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bs
Table 4: Clock Signal Pins
OPin
41
Pin Name
XTALOUT Crystal Pad Oscillator Output

Pin Description
42 XTALIN_CLKXTP Crystal Pad Oscillator Input

Alternate Function: Differential Clock input
43 CLKXTM Differential Clock input (To be used in conjunction with CLKXTP)
44 CLKSEL OV: Differential Clock input active (CLKXTM, CLKXTP

3.3V: Crystal Pad Oscillator active (XTALOUT, XTALIN)
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Pin Allocation and Description STV2310
Table 5: Configuration Pins
Pin Pin Name Type Pin Description
6 TST_MODE I To be Connected to Ground
9 SDA I/O I²C Bus Data
10 SCL I/O I²C Bus Clock
13 NRESET I Active Low Reset
16 I2CADD I 0V: 86h/87h and output pad active at Reset

3.3V: 8Eh/8Fh and output pad high impedance state at Reset
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STV2310 Default Setup At Reset
3 Default Setup At Reset
The default configuration at reset is:

● CVBS1_ input active
● Fast Blanking input for RGB insertion enable
● Automatic Standard Recognition of NTSC/PAL/SECAM
● Comb filter enable
● Data slicer enable
● Output ITU_R BT. 656/601
● Output clock CLK_DATA rising edge active
● PLL lock, HSYNC, VSYNC, FIELD primary functions enable
● Output pads active when Pin 16 connected to ground
● Output pads high impedance state when pin 16 connected to 3.3V
● Automatic HPLL time constant selection
s)
For more detailed reset configuration descriptions, refer to Chapter 5: Register List.
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3.1 System Clock Generation
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The STV2310 clock is either provided by an internal 27-MHz crystal oscillator connected to pins
XTALIN_CLKXTP and XTALOUT, or imported in Differential mode from an external device such as
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the STV3500 and connected to the XTALIN_CLKXTP and CLKXTM pins.
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Functional Description STV2310
4 Functional Description
4.1 Analog Input Stage
4.1.1 General Description

The Analog Input Stage provides the interface between the incoming video signals and the Analog-
to-Digital Converters (ADC) using Clamp and Automatic Gain Control (AGC) stages to fit the analog
signals to the ADC range.
Several video sources are processed in this stage:
● CVBS signals from a broadcast signal or the SCART connector.
● S-Video (Y/C) signals coming from an external video source (VCR, DVD, STB).
● RGB signals with Fast Blanking (FB) input coming from the SCART connector.
● Analog YCrCb signals coming from a DVD player (1H interlaced).
Figure 5: Analog Input Stage Functional Block Diagram

s)
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u
Anti-Aliasing Filter
d
r o
CVBS1/Y Analog
CVBS Clamp
Control
e P
ADC Bias 1
CVBS2/Y Switch
le t PGA
10-bit
ADC
s o ±6 dB
b
Composite and Luminance Input Channels
O
-
(s)
Chroma Bias
8-bit
C
c t
Chrominance Input Channel
ADC
d u
r o ADC Bias 2
Controller R_CR Clamp Control 8-bit
R_CR
e P ADC
G
l et Controller G Clamp Control 8-bit
ADC
o
bs
Controller B_CB Clamp Control 8-bit
B_CB ADC
O 6-bit
FB
Interpolator
RGB and Fast Blanking Input Channels
The CVBS/Y signal from the selected input channel goes through an automatic clamp and a
Programmable Gain Amplifier (PGA) circuit. The clamping circuit automatically adjusts the black
level to a programmable A/D output digital code. The clamp voltage is stored on the input coupling
capacitor (22 nF, external to the STV2310). The PGA automatically adjusts the input signal
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STV2310 Functional Description
magnitude by ±6 dB in 63 logarithmic steps to the optimal range of the A/D Converter. The video
signal then goes through an external anti-aliasing filter before reaching the A/D Converter. The A/D
Converter dedicated to the CVBS/Y channel has a 10-bit resolution. The A/D Converters dedicated
to the C, R_Cr, G and B_Cb channels have an 8-bit resolution.
Figure 6: Anti-Aliasing FIlter for CVBS Input Signals
150 Ω
VIDEOOUT ADC
470 Ω
VIDEOCOMM
s)
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Two independent CVBS sources can be connected to the STV2310. To process S-Video signals,
the luma signal is connected to one of the CVBS inputs and the chroma signal is connected to the
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C input. RGB signals are directly connected to the three separate inputs (R_Cr, G and B_Cb). For
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Analog YCrCb signals, the luma signal is connected to one of the CVBS inputs, the Cr signal is
connected to the R_CR input and the Cb signal is connected to the B_CB input.
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For S-Video signals, the Y (luminance) signal is connected to the selected CVBS input. The analog
o
C (chrominance) input includes a bias and fixed gain circuit. The C signal is digitized by an 8-bit A/
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D Converter. It is recommended that an external anti-aliasing filter be added before the C input.
Figure 7: Anti-Aliasing FIlter for Chroma Input Signals
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Analog R_PR, G and B_PB signals are clamped to the black level during the back porch period.
These signals are digitized by a triple 8-bit A/D converter. It is recommended that an external anti-
aliasing filter be added before each channel input.
Figure 8: Anti-Aliasing FIlter for R_PR, G and B_PB Input Signals
R/Cr R_PR
G G
B/Cb B_PB
22 nF
The analog insertion (Fast Blanking) signal is sliced and sent to a shaper, controlling the soft
switching between the analog R, G and B signals and the decoded main picture CVBS stream.
s)
All reference voltages required by the A/D Converter are internally generated. Only two pairs of
reference levels, REFP and REFM must be decoupled externally (REFP_CVBS and REFM_CVBS,
REFP_RGB and REFM_RGB ).
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4.1.2 Programming
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P
The channel for the desired CVBS signal source is selected by the CVBSMUX bit in the
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t
DDECCONT0 register. The AGC and clamp mechanisms are described in Section 4.2.
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4.2 Synchronization and Monitoring Unit
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4.2.1 General Description Ob
) -
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The STV2310 system clock sampling frequency is provided by a free-running embedded crystal
(
ct
oscillator or an external clock generator. The nominal value of this sampling frequency is 27 MHz
and is independent of any input TV standard.
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Synchronization data (horizontal and vertical sync signals) is extracted from the video signal. After
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a low pass stage removing all high frequency information and noise, the video signal is sent to a
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synchronization slicer. Then the horizontal and vertical pulses are separated to generate the Hsync
and Vsync pulses. The extracted Hsync pulses are sent to the horizontal PLL (HPLL) in order to
l et
filter the jitter. The HPLL has an adaptive time constant with noise level and other operating
conditions. It provides an easy lock even in difficult conditions and performs the skew extraction.
s o
Using this data, skew correction on the data stream is performed by the output scaler. This PLL can
O b hold a frequency range of ±8% of the H frequency. A second PLL, associated with the output FIFO,
is used to perform the line-locked clock generation from which the output HSYNC and VSYNC
pulses are obtained by synchronous division.
A vertical sync processor is used to generate the output Vsync pulse, synchronous to the incoming
CVBS signal. This processor is able to automatically detect 50 Hz/60 Hz standards. In the event of
missing pulses, the Vsync processor replaces the missing pulse by inserting a V-pulse at the end of
the 50 Hz or 60 Hz windows.
If an input video signal (CVBS or S-Video) is not detected, the sync processor operates in Free-
running mode.
16/113
The Output Sync Pulse (H, V and F) can be embedded in the digital output stream, according to the
ITU_R BT_656/601 format, using the EAV and SAV codes. The Output Sync Pulse can also be
delivered on dedicated external pins (33, 34, 35). These pins can be used specifically if the output
sync pulses are no longer compliant with the ITU_R BT_656/601 format, as non-interlaced pictures
or signals from a non-standard source (VCR). See Section 4.12.2.1 and Section for more
information.
4.2.2 Programming
The circuit can function in Automatic mode or use a programmable HPLL time constant. Automatic
mode is selected by default. In this case the STV2310 automatically adapts the time constant to the
reception conditions. In the case of unstable sources (such as VCRs) the circuit uses a special
user-programmable VCR time constant. This HPLL time constant's proportional gain is selected in
the HSYN_GP[7:0] bits in the DDECCONT26 register. The value for the integral gain is selected in
the HSYN_GI[7:0] bits in the DDECCONT27 register. These bits also define the programmable time
constant when the HTIMECSTSEL bit is reset in the DDECCONT22 register (Automatic mode
disabled).
To be automatically selected, the VCR time constant requires that the noise level be below the noise
threshold selected by the NOISE_THRESHOLD[2:0] bits in the DDECCONT25 register.
s)
DDECCONT0 register.
c t(
The Vsync search and initial Free-running modes are selected by the 5060MODE[1:0] bits in the
d u
The (fluctuating) average sync bottom and blanking level values, based on the Hsync Pulse Bottom
r o
Period and Composite Video Burst Period identification data, are necessary in turn to perform the
e
programmed by the BLANKMODE[1:0] bits in the DDECCONT1 register. P
clamp correction on the CVBS signal in the analog domain. (See Figure 9.) The clamp level is
le t
The Active Input Video Period and small amplitude signals for the Active Input Video Period levels
o
which control the gain level of the AGC are programmed in the ACTITH[1:0] and SMHITH[1:0] bits
s
(respectively) in the DDECCONT16 register.
Ob
The CVBS saturation threshold is programmed in the SATLMTPT[1:0] and SATLMTLN[1:0] bits of
-
the DDECCONT16 register in the event of a high level of chroma demodulation. It is expressed as
)
s
a number of samples per field (when, according to the algorithm, the number of samples is reached,
(
ct
the gain is decreased).
register.
d u
Output mode can be forced to 50 Hz or 60 Hz by 5060MODE[1:0] bits in the the DDECCONT00
r o
To output a non-interlaced image, the chip must be set in direct parity mode by the DIRECTPARITY
P
bit in the DDECCONT1F register.
e
l et
s o
O b
17/113
The external HSync pulse can be synchronised to the End of Active Video (EAV) and the Start of
Active Video (SAV) pulses, or initialized according to the usual analog H/V pulse using the
HSYNC_SAV bit in the DDECCONT25 register.
Figure 9: AGC Flowchart
Points/Line Line
Code Threshold Threshold
CVBS Saturation Threshold

1020 0 to 65
Luma Saturation Threshold 807 + 8x 32 9
Luma Low Signal Detection Threshold 772 + 8x 8 5
s)
c t(
d u
r o
e P
le t
s o
Ob
256/244
Small Amplitude Signal

) -
( s
for Hsync Pulse Bottom Period
ct
30 108 220
du
Hsync Pulse Bottom Period 18 16 9
r o 0
e P
4.3
et
Input Sample Rate Conversion
l
4.3.1s o
General Description
O b An Input Sample Rate Converter (ISRC) converts the acquisition pixel rate to a clock domain
virtually locked to the color subcarrier. This ISRC is controlled by a subcarrier phased-locked loop
(Chroma PLL). This enables comb filtering and chroma demodulation to be carried out on various
subcarrier frequencies using the same system clock sampling frequency.
The Input SRC uses the data provided by the front-end ADCs to process both the CVBS and C
flows (in the event of separated Y/C inputs, the CVBS flow = Y flow). The same processing is
applied to the CVBS and C data.
When the input video standard has been identified, its subcarrier frequency (fSC) is known and the
Chroma PLL is locked. The Input SRC transforms the input data captured at the 27-MHz system
clock sampling frequency (fS) to the subcarrier clock domain frequency (4 x fSC).
18/113
The practical value of the 4 x fSC frequency depends on the actual input TV standard.
4.4 Luminance and Chrominance Separation

The Y/C Separator separates the chrominance (C) component from the composite signal which
also includes the luminance (Y), synchronization and color burst (subcarrier) components. In
normal operation (NTSC and PAL standards), this is done through comb or notch filtering which
relies on the correlation of consecutive lines. For SECAM inputs, a Chroma Bandpass/Trap filter
system is required. If an S-Video input is selected, Y/C separation is not required and the Y/C
Separator operates in Bypass mode. Y/C delay adjustment can be done with both pixel and sub-
pixel accuracy.
4.4.2 Programming
Once the samples processed by the input SRC have been stored in RAM, the type of input signal
(Y/C or CVBS) must be specified before the chroma component can be separated from the CVBS
input signal. This is done by setting the SVIDEOSEL bit in the DDECCONT0 register.
s)
t(
The Y/C separator block can either operate in auto-adaptive mode (Default mode) or Forced
c
DDECCONT18 register:
d u
Separation mode (notch). This operating mode is selected by the COMB_MODE bit in the
● Chroma Bandpass/Trap filtering is forced

r o
●
e P
Adaptative Comb Filtering mode is forced. (This applies to PAL/NTSC signals only. SECAM
le t
signals remain processed by Chroma Bandpass/Trap filter)
Figure 10: SECAM Trap Filter Frequency Response
s o
Ob
) -
( s
u ct
o d
Pr
et e
o l
b s
O
19/113
The notch filter width used in the Y/C separation can be adjusted from narrow to wide by the
BW_SEL[2:0] bits in the DDECCONT18 register. Luma Chroma delay can be adjusted by the
DEM_YC_DELAY[3:0] bits in the DDECCONT15 register and DDECCONT1A register, bit [5:0].
Figure 11: Notch Filter - Narrow Group
s)
c t(
d u
r o
e P
le t
s o
Ob
) -
( s
u ct
o d
Pr
et e
o l
b s
O
20/113
Figure 12: Notch Filter - Wide Group
s)
c t(
d u
r o
e P
le t
s o
Ob
4.5 )
Standard Research Sequence Programming -
( s
u ct
The chroma signal is sent to the Standard Identifier and Chroma Demodulator. The Standard
Identifier performs an automatic recognition sequence for one of the following standards.
o d
Pr Table 6: TV Standards
et e Chroma Standard Subcarrier Frequency Standard Code
o l PAL B,D,G,H,I 4.4336 MHz 000
bs
SECAM 4.406 MHz (foR) 001
4.250 MHz (foB)
O NTSC M
PAL M
3.5795 MHz
3.5756 MHz
010
011
PAL N 3.5820 MHz 100
NTSC 4.43 4.4336 MHz 101
No Standard1 n/a 110
No Standard1 n/a 111
21/113
Note 1: Codes 110 and 111 are associated with “No Standard”.
From this list of possible standards, the user must complete the Automatic Standard Recognition
table required for the automatic search. Identification will be restricted to the table entries and the
first entry will be tried first. Entering code 110 or 111 in the Automatic Standard Recognition table
terminates the standard sequence search. It is possible to enter several times the same code. The
Automatic Standard Recognition table and its default values are presented in Table 7.
Table 7: Automatic Standard Recognition Table
Standard Code
Register
Entries (Default values)
Standard 1 000 DDECCONT4[5:0]

Standard 2 001

Standard 4 111
s)
t(
Standard 6 001

u c
Standard 8 111
o d
P r
te
If the default values are used, code 111 (no standard) is the fourth entry and the standard
identification will be restricted to the first three standards (in order PAL BGDHI, SECAM and
NTSC M).
o le
b s
Each standard recognition trial period lasts 2 fields. All trials corresponding to table entries are
performed. The identification decision is based on the results of the trials and a single table entry
O
should be identified. If two entries are identified by error, the standard recognition sequence will re-
-
( s )
start from the beginning of the table and no standard will be identified.
ct
The DDECCONT4[5:0], DDECCONT3[5:0], DDECCONT2[5:0], and DDECCONT1[5:0] registers
are used to program the Automatic Standard Recognition table.
d u
After the sequence search, a second step (also called a confirmation step) is performed by the
r o
algorithm. It is performed on the single identified Automatic Standard Recognition table entry. It is
e P
possible to program the number of fields where the standard identification must be confirmed before
the status flags are modified. The confirmation code is described in Table 8.
l et Table 8: Confirmation Codes
s o
O b Confirmation
Code
Number of Successive Fields
with Correct Identification
000 1
001 3 (Default)
010 7
011 10
The confirmation code is programmed in the STI_NB_FIELDS_CONFIRM[2:0] bits of the

DDECCONT17 register.
22/113
After the confirmation step has been successful, the standard is considered as identified. The
TVSTID flag is set in the DDECSTAT2 register and the code of the identified standard is set in the
TVSTD[2:0] bits of the DDECSTAT2 register.
4.6 Standard Identification

The input signal standard is automatically recognized using a proprietary ST patented algorithm. It
avoids false identification and ensures a good recognition of the color standard, even in bad signal
conditions.
4.7 Chroma Demodulation

The Chroma PLL and the Input SRC are the main hardware blocks involved in chroma
demodulation. The Chroma PLL is locked to the input video burst signal in frequency and phase.
Demodulation is performed on the chroma samples positioned in the virtual 4 x fSC clock domain.
s)
t(
Dedicated demodulation hardware is used for SECAM demodulation (frequency modulated
signals). Demodulated chroma components are low pass filtered and matrixed into Cr and Cb
components.
u c
o d
The Chroma Demodulator also includes an Automatic Chroma Control (ACC) which rescales the
P r
chroma components from -20 dB to +6 dB. The color is killed (output Cr Cb components to 80h
value) until the standard is identified. ACC is disabled (fixed gain) in SECAM standard.
te
If NTSC M or NTSC 4.43 standards are identified, the Chroma Demodulator also incorporates a
le
Hue Control mechanism and a Flesh Tone Correction mechanism. The Hue Control is a
o
b s
programmable fixed offset in the demodulation angle and is only operational in the active line.
The Flesh Tone Correction mechanism operates with a programmable reference axis. It performs
- O
an on-the-fly change of demodulation axis for any color with a phase of approximately ± 39.4°
( s )
around the reference axis. It is only operational in the active video line.
ct
Flesh Tone Correction (cϕ) is up to a maximum of ±10°.
u
Cr and Cb amplitudes can be adjusted separately. (See Section 4.12.1 .)
d
4.7.2 Programming
r o
P
For NTSC standards, there are several ways to improve the video input. The hue value is controlled
e
l et
by the HUECTRL[5:0] bits in the DDECCONT2 register. The hue control value is defined in 63 steps
of approximately 1.4 degrees each, which provide an offset between -45.0° and +43.6°. When
s o
00000, the hue angle is 0, otherwise the value of the hue angle is coded in 2’s complement.
O b An Automatic Flesh Control is also available with the STV2310. This mode is enabled by setting the
FLESH_EN bit in the DDECCONT10 register. For the Automatic Flesh Control Phase Shift
selection, the Flesh Tone Reference Angle in the [B-Y, R-Y] axis system is either 123° or 117°. This
value is selected in the FLESHPH_SEL bit of the DDECCONT10 register.
The Color Kil control mode can be automatic, depending on the standard identification, or forced On
or Off by the DEM_CKILL_CTRL[1:0] bits in the DDECCONTD register. In PAL/NTSC mode, it can
also depend on burst amplitude by setting the in the DDECCONTF register.
A pedestal can be removed from the luminance input signal by the video standard using the
PEDESTAL_REMOVE bit in the DDECCONT2 register.
23/113
Figure 13: Phase Correction when Automatic Flesh Control Enabled
Phase Correction (cϕ)

ϕ0 = 123° or 117°
+10
ϕ0 + 39.4°
ϕ0
Input Subcarrier Phase
ϕ0 - 29.5° (degrees)
ϕ0 - 39.4°
-10
ϕ0 + 29.5°
4.8 Soft Mixer

s)
c t(
d u
The Soft Mixer is used to mix the Y, Cr and Cb data flows (respectively) from the CVBS source and
r o
the RGB Insertion block. The mixing of the data flows is controlled by Fast Blanking mode. A forced
CVBS or RGB flow mode can also be programmed. In this case, the mixer acts as a multiplexer. A
static mixing (also called alpha blending) mode is also programmable.
e P
le t
When the normal mixing mode is programmed, the CVBS and RGB flows are blending according to
the Fast Blanking (FB) signal. The FB signal is sampled with subpixel accuracy to ensure correct
mixing. The mixing slope between flows is programmable.
s o
4.8.2 Programming
Ob
) -
Fast Blanking mode is selected by the FBLANKMODE[2:0] bits in the DDECCONT5 register.
( s
ct
Table 9: Fast Blanking Modes
Bit Value
d u
Mixing Mode Description
00x
r o
Normal Mixing mode FB active during active line. Soft Mixing between 0 and 1. (Default mode)
01x
e P
Dynamic Mixer mode FB active and Soft Mixing from 0 to MIXSLOPE[7:0]
100
l et Static Mixer or Alpha FB inactive. YOUT = alpha x YCVBS + (1-alpha) x YRGB
s o Blending 1 mode with alpha = MIXSLOPE[7:0] (same for Cr and Cb signals)
O b 101 Static Mixer or Alpha

Blending 2 mode
FB inactive. YOUT = alpha x YRGB + (1- alpha) x YCVBS
with alpha = MIXSLOPE[7:0] (same for Cr and Cb signals)
110 Forced CVBS mode FB inactive. YOUT = YCVBS (same for Cr and Cb signals)
111 Forced RGB mode FB inactive. YOUT = YRGB (same for Cr and Cb signals)
Note: The FBLANKMODE value is only applied when the STV2310 is not in Analog YCrCb mode
The soft mixing slope or the Alpha Blending value, depending on the Fast Blanking mode, is set in
the MIX_SLOPE[7:0] bits in the DDECCONT6 register. When the blanking mode is in Forced RGB
or Forced CVBS mode, this value is ignored.
24/113
When one of the Alpha Blending modes is used for mixing, the alpha value is set in the
MIX_SLOPE[7:0] bits.
When the STV2310 is in normal RGB and CVBS mixing mode, the MIX_SLOPE[3:0] bits indicate
the mixing slope (duration of mixing). The MIX_SLOPE[7:4] bits must be set to 0000. The
MIX_SLOPE[3:0] bits code the soft mixing slope from 0000 to 1111, with 0000 corresponding to a
slope of 1 clock cycle (virtual 4 x fSC clock domain) and 1111 corresponding to a transition from one
signal to the other spanned on 16 clock cycles.
4.9 Output Scaler and Format Converter

An Output Sample Rate Converter (OSRC) is used to transpose the subcarrier locked virtual clock
domain to the output sample rate domain. This converter is used to provide a fixed number of pixels
per active line (i.e. 720 for ITU-R BT.601 format) independently of the input video standard and line
length.
● Upsampling is required for zoom-in functions.
Downsampling is required for zoom-out functions.
s)
t(
●
u c
The Output Sample Rate Converter compensates for line length variations. At this level, a skew
correction is applied on each pixel in order to compensate for the shift of the asynchronous
od
acquisition with respect to the current line horizontal sync pulse. New sample rate and skew
r
correction factors are computed at every line, taking into account the line length variation.
P
te
The Output Sample Rate Converter is also used to perform an horizontal format conversion to
support zoom in/out functions. For linear scaling, the scaling factor can be programmed in linear
le
steps from 0.25 to 4. Non-linear scaling is also available for Panorama mode. Region borders are
o
b s
fully programmable as well as the associated scaling factors (in the 0.25 to 4 range).
At the sample rate converter output, an active line is transposed into a fixed number of skew
O
corrected pixels, according to the selected output format (ITU-R BT.601 or square pixel). This is
-
converter.
( s )
used for the orthogonal display or field storage for the field-rate up-conversion, using an external up-
4.9.1.1 Square Pixel Mode

u ct
d
When a standard TV screen is used to display computer-generated images, Square Pixel mode is
o
Pr
required to ensure the correct aspect ratio in relation to the required sampling frequency of the TV
display format.
et e Table 10: TV Display Formats
o l
bs
Luma Sampling Frequency Format Pixels/Line
13.5 MHz ITU-R BT.601 (NTSC/PAL) 720

O 12.27 MHz NTSC Square Pixel 640
14.75 MHz PAL Square Pixel 768
25/113
The output formatting can be performed with Normal or Square Pixel modes. For Square Pixel
mode, the number of required samples per line depends on the input standard.
Table 11: Required Samples per Line for Square Pixel Mode
Samples per Line

Standard
Y SIgnal Cr Signal Cb Signal
625 Lines/50 Hz 768 384 384
525 Lines/60 Hz 640 320 320
4.9.1.2 Zoom-In Mode

In Zoom-In mode, a portion of the TV scan line is expanded to take all the available output samples
for that line.The zoom-in factor ranges from 1 (no zoom) to 4 (large zoom). The Zoom-In mode start
position is programmable.
s)
Figure 14: Zoom-In Mode
c t(
Programmable Offset
d u
r o
Input Line
e P
le t
Output Line
s o
after zoom
Ob
720 Samples (Y Normal Pixel Mode)
) -
2 Examples for Zoom In Action
( s
4.9.1.3 Zoom-Out Mode
u ct
o d
In Zoom-Out mode, the entire input TV scan line is compressed to take only a part of the output line.
Pr
The active samples are positionned in the center of the output line and the rest of the line is blacked
out. The zoom-out factor ranges from 0.25 (large zoom) to 1 (no zoom).
et e
o l Figure 15: Zoom-Out Mode
b s Input Line
O
Output Line
Black Level Black Level
after zoom
720 Samples (Y Normal Pixel Mode)
26/113
4.9.1.4 Panorama Mode (Non-Linear Scaling)

To better display wider TV screen aspect ratios, Panorama mode applies a different zoom factor to
the center of the image in relation to the edges; i.e. a Non-Linear Scaling mode must be
implemented. This implies that the compression/expansion factor will vary on the edges and remain
stable at the center. Note in Figure 16 that the resulting TV image is symetrical (right and left edges
are equal).
Figure 16: Non-Linear Scaling
Zoom Factor
Zoom-Out
Left Edge Center Right Edge
1
Zoom-In
Horizontal Axis
s)
c t(
d u
4.9.2 Programming
r o
4.9.2.1 Square Pixel Mode
e P
t
Square Pixel mode is enabled by setting the PIXMODE bit in the DDECCONT0 register.
le
4.9.2.2 Zoom-In Mode
s o
b
To enable Zoom-In mode, the ZOOMIN_EN bit in the DDECCONTB register must be set.
O
) -
The zoom-in value must be between 256 and 1023. A value of 512 will zoom-in the picture by a
factor of 2.0; i.e. pixels are twice as large. The zoom-in factor is programmed in the
( s
ZOOMIN_FACT[9:0] bits in the DDECCONT6 and DDECCONTB registers. The default value is 256
(No Zoom).
u ct
o d
The position where the zoom-in operation starts is programmed in the ZOOMIN_OFFSET[9:0] bits
in the DDECCONTA and DDECCONTB registers. If the value is 0, the zoom-in starts at the
Pr
beginning of the TV scan line (first left pixel). The number of pixels per line is based on the vertical
frequency and the pixel mode. For more information, refer to Table 10. The default value is 0; i.e. the
t e
first left pixel of the active line is the first pixel of zoom.
e
o l
4.9.2.3 Zoom-Out Mode
b s To enable Zoom-Out mode, the ZOOMOUT_EN bit in the DDECCONTB register must be set.
O The zoom-out value must be between 256 and 1023. A value of 512 will zoom-out the picture by a
factor of 0.5; i.e. pixels are twice as small. The zoom-out factor is programmed in the
ZOOMOUT_FACT[9:0] bits in the DDECCONT9 and DDECCONTB registers.
4.9.2.4 Panorama Mode

Panorama mode is enabled when both the ZOOMIN_EN bit in the DDECCONTB register and the
ZOOMOUT_EN bit in the DDECCONTB register are set to 1.
In Panorama mode, the ZOOMIN_FACT, the ZOOMOUT_FACT and the ZOOMIN_OFFSET values
are used (see Figure 16).
27/113
● The ZOOMIN_FACT bits determine the zoom-in factor at the left and right edges of the picture
● The ZOOMOUT_FACT bits determine the zoom-out factor at the center of the picture
● The ZOOMIN_OFFSET bits determine the border width where the zoom factor increases from
the zoom-in factor to the zoom-out factor, starting from the left edge (resp. the border width
finishing on the right edge where the zoom factor decreases from the zoom-out factor to the
zoom-in factor)
For correct programming the following formula must be checked:
Zt x (Zout - Zin) = N x (Zout -1)
where Zin = ZOOMIN_FACT ; Zout = ZOOMOUT_FACT ; Zt = ZOOMIN_OFFSET ; N number of Y
pixels per line (720 in Normal Pixel mode, 640 or 768 in Square Pixel mode).
4.10 RGB Insertion

The RGB signals are captured by three 8-bit A/D converters and should be synchronous to the
s)
t(
selected CVBS or Y/C sources. The RGB signals are also adjusted in the analog domain by clamp
circuits used for sourcing and sinking charges on the front end capacitor.
u c
A digital adjustable gain can be applied to the RGB data flow, in order to adapt to the CVBS
dynamic range.
o d
P r
The RGB signals are YCrCb formatted and mixed with the YCrCb signals from the main picture.
te
Soft mixing is driven by the FB signal. The rising and falling edges of the FB signal are measured
with subpixel accuracy to perform correct insertion. (For more information, refer to Section 4.8: Soft
Mixer on page 24).
o le
b s
The RGB insertion block also provides a Cr Cb overload mechanism. This mechanism is used to
avoid clipping YCrCb signals (i.e when the input RGB signals are too large). The Cr Cb overload
- O
mechanism measures the chroma signal during the video line in order to compute the correcting
scale factor.
( s )
ct
Figure 17: RGB Capture and Mixing with Main Picture
d u
r oR Clamp
Main Picture
e P G Clamp (YCrCb)
l et B Clamp
s o
O b R 8-bit
A/D
Y
Converter Conversion Cr 4:2:2

G Matrix Formatting
and
Cb Processing
B
Y
Soft
Cr
6-bit Mixer Cb
FB
Interpolator
28/113
4.10.2 Programming
To enable the CrCb overload mechanism, set the CRCBOVER_EN bit in the DDECCONTB register.
The automatic gain for the RGB is set in the DDECCONT35 register.
4.11 Analog YCrCb Mode

The STV2310 can be programmed in Analog YCrCb mode. This mode has specific input
connections:
● the Y analog input signal must be connected to the CVBS1_Y (or CVBS2_Y) pin
● the Cr and Cb analog input signals must be connected to the R_CR and B_CB input pins
(respectively).
A ±20 degree Tint Control mechanism is available to compensate for incorrect hue levels on the
input signals. When the Analog YCrCb mode is programmed, the various clamp circuits are
modified accordingly.
s)
t(
Note: The Fast Blanking (FB) signal is not relevant in Analog YCrCb mode. This mode is a full-page
display mode.
u c
4.11.2 Programming
o d
P r
The YCrCb Tint Angle Correction values are programmed in the TINTANGLE[4:0] bits in the
DDECCONT12 register. The tint angle is coded from -20° to +20° in steps of 1.33°. These bits are
coded in 2's complement. The default value is 0 (no correction).
te
o le
4.12 s
Output FIFO and Line-locked Ouput Pixel Clock Generator
b
- O
s )
The Output FIFO and Line-Locked Output Pixel Clock Generator block has two functions:
(
u ct
1 Handle the active line data received from the Output Scaler and Format Converter and the
ancillary data from the VBI slicer.
o d
The active video line data is provided on 3 buses: Y, Cr and Cb. The output flow is on 8 bit and
Pr
multiplexes the Y, Cr and Cb flows. Before being multiplexed, a programmable attenuation can
be applied to the Cr, Cb data. For every output line, digital preambles for synchronization and
t e
ancillary data (when available) are inserted in the output flow in compliance with standard ITU-
e
o lR BT 656.
2 Generate the Output Pixel Clock and associated signals.
b s A line-locked output pixel clock is generated. This output clock is a multiple of the input line
O ●
frequency. There are 4 possible multiples:
1716 or 1728 in Normal Pixel mode,
● 1560 or 1888 in Square Pixel mode.
When there is no input signal, the output data can be blanked in option.
When required the STV2310 is able to enlarge the vertical blanking area. On the other hand it
is possible to disable the blanking mode during the VBI, using the "pass through" mode. (The
"pass through" mode must not be selected when the TXT VBI slice is used).
29/113
4.12.2 Output Data

There are 4 data output standards which are a combination of 525/625 input standards and Normal/
Square pixel format. There are four possible multiples:
● 1716 or 1728 in Normal Pixel mode,
● 1560 or 1888 in Square Pixel mode.
For each output standard, the blanking code (Cb = 80h, Y = 10h, Cr = 80h, Y = 10h...) is used in the
active line section during the Vertical Blanking Interval (VBI). (See Figure 18.)
Table 12: Frame Output Standards
Output Standard Output Standard Output Standard Output Standard

1 2 3 4
Input Standard 525/60 Hz 625/50 Hz 625/50 Hz 525/60 Hz
Pixel Format Normal Normal Square Square
Blanking (bytes) 268 + 8 280 + 8 344 + 8 272 + 8
Active Video (bytes) 1440 1440 1536 1280

s)
Vertical Blanking
Interval1
Lines 1 to 19
Lines 264 to 282
Lines 1 to 22
Lines 311 to 335
Lines 1 to 22
Lines 311 to 335
c t(
Lines 1 to 19
Lines 264 to 282
Lines 624 and 625
d u
Lines 624 and 625
Vsync SIgnal Synchronized with the output pixel clock. See below.
r o
Hsync Signal Synchronized with the output pixel clock.
e P
Field Signal
t
Synchronized with the Hsync signal output pixel clock.
le
o
1. Lines are numbered in compliance with specification ITU-R BT470.
s
Ob
) -
( s
u ct
o d
Pr
et e
o l
b s
O
30/113
4.12.2.1 Vsync Output Pin Modes
Figure 18: Frame Output Standards
525 Line / 60 Hz Modes 625 Line / 50 Hz Modes
Field (F) Field F

Output Standard 1 Output Standard 2
1716 bytes 1728 bytes
line 525 line 625
line 3 line 1 line 1
line 4
(V = 1) (V = 1)
Blanking
Blanking
Field 1 line 19 Field 1 line 22
line 20 line 23
(F = 0) (F = 0)
Odd Odd Field 1
Field 1
Active Video
Normal Pixel Modes

Active Video (V = 0) (V = 0)
line 265 line 263 line 312 line 310

line 264 line 311
line 266 line 313 (V = 1)
(V = 1) Blanking
)
Blanking
s
line 282 line 335
t(
line 283 line 336
Field 2 Field 2
c
(F = 1) (F = 1) Field 2
Field 2 (V = 0)
Even Active Video (V = 0) Even Active Video
d u
line 625
r o line 623
P
line 525 (V = 0) line 624 (V = 1)
line 1 line 1
line 3 Blanking
line 4 H = 0 SAV
te
H = 0 SAV
le
H = 1 EAV H = 1 EAV
s o
Field (F)
Output Standard 4
1560 bytes
Ob
Field F
line 625
Output Standard 3
1888 bytes
-
line 525
line 3 line 1 line 1
line 4
Blanking
(V = 1)
( s ) Blanking
(V = 1)
line 22
ct
line 19 Field 1
Field 1 line 23
line 20 (F = 0)
(F = 0)
du
Odd Field 1
Odd Field 1
Active Video Square Pixel Modes
(V = 0)
r o
Active Video (V = 0)
line 265
e P line 263 line 312 line 310
t line 264 line 311

line 313
e
line 266 (V = 1)
Blanking
l
(V = 1)
Blanking
s
Field 2 o line 282
line 283 Field 2
line 335
line 336
O b (F = 1)
Even
Field 2
(F = 1)
Even
Field 2
line 623
line 625 line 624 (V = 1)
line 525 (V = 0)
line 1
line 1 Blanking
line 3
line 4 H = 0 SAV H = 0 SAV
H = 1 EAV H = 1 EAV
31/113
For all output standards, the Vsync output signal changes twice per frame. The Vsync signal (pin
34) can be generated at the output in one of two modes:
1 “Digital“ Vsync mode: The VSYNC signal always changes at the beginning of the line,
depending on the output standard.
2 “Analog” Vsync mode: The VSYNC signal changes either at the beginning or the middle of the
line, depending on the analog input signal.
➢ for Output Standard 1: Start of line 4 and middle of line 266
➢ for Output Standard 3: Start of line 1 and middle of line 313 (same as standard 2)
Note that the output standard depends on the input TV standard and the programmable Normal
Pixel or Square Pixel mode.
The VSYNC output mode is selected by the VSYNCTYPE bit in the DDECCONT0 register.
The V bit of the output flow always changes at the beginning of the line (in compliance with standard
ITU-R BT 656).
s)
t(
Non-Interlaced mode: When required, the STV2310 is able to interlace the output, even if the
source is non-interlaced (by default, the output Vsync follows the input Vsync).
u c
4.12.2.2 Hsync Output Pin Mode
o d
r
The Hsync output pulse can shifted, this is in comparision with the embedded Hsync pulse.
P
4.12.2.3 FIELD Output Pin Mode
te
o le
The FIELD output pulse represents the parity of the field and toggles either with the embedded
FIELD pulse, or is synchronous with the Vsync pin, when set in analog interlaced mode. To toggle in
b s
analog interlaced mode, the direct parity mode must be selected.
- O
( s )
u ct
o d
Pr
et e
o l
b s
O
32/113
4.12.2.4 Output Standard 1 : Normal Pixel mode / 525 lines / 60 Hz (NTSC)
EAV code Description of Different Sections of Output Standard 1

F 0 0 X
description of EAV code on 4 bytes
F 0 0 Y
4
Xand Y are computed as checksums
SAV code
F 0 0 X
description of SAV code on 4 bytes
F 0 0 Y
4
blanking code on 268 bytes
8 1 8 1 --- repeated pattern 8 1 8 1 --- repeated pattern

1
s)
t(
0 0 0 0 0 0 0 0 0
268 bytes
u c
o d
co-sited co-sited
P r co-sited
te
Cb Y Cr Y Cb Y Cr Y
o le Cb Y Cr Y
1440 bytes
b s
- O
( s )
u ct
Overview of output video line and corresponding H signal
EAV code Blanking

o d
SAV code Active Video line
Pr
et e
o l
b s
O
H
1716 bytes
33/113
Digital Output Frame Overview for Output Standard 1
1716 bytes
line 1 V=1
line 4
Blanking
Blanking code (80 10) also in active line section
Field 1 line 20 (V=0)
(F=0) Field 1
Odd Active Video
Active video in active line section
line 264 (V=1)

line 266
Blanking
s)
line 283 (V=0)

c t(
Field 2 Field 2
d u
(F=1)
Even
Active Video
r o
e P
le t
s o
line 525 (V=0)
line 3
Ob
H=0 SAV
) -
H=1 EAV
( s
u ct
o d
Note that the vertical blanking interval has been extended from line 1 to line 19 included (transition
from Field 2 to Field 1 of next Frame) and from line 264 to line 282 included (transition from Field 1 to
Field 2)
Pr
This encompasses the optional blanking lines described in the standard (lines 11 to 19 included and
et e
lines 273 to 282 included respectively)
o l
b s The V and H signals change synchronously with the output pixel clock.
O The F signal change synchronously with the H signal and the output pixel clock.
The V signal changes twice during one frame:
- either at the start of line 1 and at the start of line 264 (“digital Vsync mode”)
- or at the start of line 1 and in the middle of line 263 (“analog Vsync mode”)
34/113
4.12.2.5 Output Standard 2: Normal Pixel / 625 lines / 50 Hz (PAL & SECAM)
F 0 0 X
F 0 0 Y
4
SAV code
F 0 0 X
F 0 0 Y
4
1
8 8 1 --- repeated pattern 8 1 8 1
--- repeated pattern
1
s)
t(
0 0 0 0 0 0 0 0 0
280 bytes
u c
co-sited co-sited
o d co-sited
P r
Cb Y Cr Y Cb Y Cr Y
te Cb Y Cr Y
1440 bytes
o le
b s
- O
( s )
u ct
Overview of output video line and corresponding H signal
EAV code Blanking

o d
Pr
et e
o l
b s
O
H = c9oll_h
1728 bytes
35/113
1728 bytes
line 1 line 1 V=1
Blanking
(F=0) Field 1
Odd Active Video
line 313 line 311 (V=1)

Blanking
s)
line 336 (V=0)

c t(
Field 2 Field 2
d u
(F=1)
Even
Active Video
r o
e P
line 624 (V=1)
le t
line 625
s o
line 625 (V=1)
Blanking
Ob
H=0 SAV
) -
H=1 EAV
( s
u ct
o d
Field 2)
Pr
et e
o l
The V and H signals change synchronously with the output pixel clock.
b s The F signal is given as an indication. It is not output
36/113
4.12.2.6 Output Standard 3: square pixel / 625 lines / 50Hz (PAL SECAM)
F 0 0 X
F 0 0 Y
4
SAV code
F 0 0 X
F 0 0 Y
4
1
1
s)
t(
0 0 0 0 0 0 0 0 0
344 bytes (difference with normal pixel mode)

u c
o d
co-sited co-sited
P r co-sited
te
Cb Y Cr Y Cb Y Cr Y
o le Cb Y Cr Y
b s
- O
( s )
u ct
Overview of Output Video Line and Corresponding H Signal
EAV code Blanking

o d
Pr
et e
o l
b s
O H = c9oll_h
37/113
1888 bytes
line 1 line 1 V=1
Blanking
(F=0) Field 1
Odd Active Video
line 311 (V=1)

line 313
Blanking
s)
line 336 (V=0)

c t(
Field 2 Field 2
d u
(F=1)
Even
Active Video
r o
e P
le t
line 625
o
line 624 (V=1)
s
line 625 (V=1)
Blanking
Ob
H=0 SAV
) -
H=1 EAV
( s
u ct
o d
Pr
Field 2)
et e
o l
b s The V and H signals change synchronously with the output pixel clock.
The F signal is given as an indication. It is not output
O
38/113
4.12.2.7 Output Standard 4: Square Pixel / 525 lines / 60Hz (NTSC)
F 0 0 X
F 0 0 Y
4
SAV code
F 0 0 X
F 0 0 Y
4
1
1
s)
t(
0 0 0 0 0 0 0 0 0
u c
co-sited co-sited
o d co-sited
P r
Cb Y Cr Y Cb Y Cr Y
te Cb Y Cr Y
o le
b s
- O
( s )
u ct
Overview of Output Video Line and Corresponding H Signal
EAV code Blanking

o d
Pr
et e
o l
b s
O
H = c9oll_h
1560 bytes
39/113
1560 bytes
line 1 V=1
line 4
Blanking
(F=0) Field 1
Odd Active Video
line 266 line 264 (V=1)

Blanking
s)
line 283 (V=0)

c t(
Field 2 Field 2
d u
(F=1)
Even
Active Video
r o
e P
le t
line 3
s o
line 525 (V=0)
Ob
H=0 SAV
) -
H=1 EAV
( s
u ct
o d
Field 2)
Pr
t e
This encompasses the optional blanking lines described in the standard (lines 11 to 19 included and
lines 273 to 282 included respectively)
e
o l
b s
O The V and H signals change synchronously with the output pixel clock.
The F signal is given as an indication. It is not output
4.12.3 Insertion of Ancillary Data

Ancillary data is inserted in the output flow as it is received from the VBI slicer. No operation/
modification is performed on this data. No fixed prefix or suffix is added.
40/113
The ancillary data is always inserted between the EAV and SAV codes of each line.
The line number is provided by the VBI slicer.VBI data is inserted on the next possible output line.
The only lines where insertion cannot take place are the forbidden lines. The list of forbidden lines
depend on the standard:
● for the 525 lines (60 Hz): 9,10,11,272,273,274
● for the 625 lines (50 Hz): 5,6,7,318,319,320
Ancillary data is inserted starting just after the EAV code. Ancillary data will replace the blanking
data codes. Ancillary data is inserted in the same order as it is received from the VBI slicer.
VBI data belonging to the same line at reception is inserted in a single line.The maximum number of
ancillary data bytes to be inserted is 84.
4.12.4 Line-Locked Output Pixel Clock Generation

A phase-locked loop (PLL) generates a clock signal (CLK_DATA) that is used to read the output
FIFO and to output the YCrCb data in synchronization. This output pixel clock frequency is a
multiple of the input line frequency. Its value (1716, 1728, 1560 or 1888) depends on the input TV
standard and the programmable Normal Pixel or Square Pixel mode.
s)
c t(
Note that phase jumps detected in the input video are replicated in the output PLL. This is
equivalent to a temporary change of the number of samples per line, but no change in the output
u
clock frequency. This feature can be disabled. In this case, the output PLL then corrects the input
d
phase step by frequency modulation.
r o
4.12.5 Alternate Functions: Bus Extensions
e P
le t
Output data is issued synchronously to the CLK_DATA clock active edge. Either the rising or falling
edge of the CLK_DATA signal can be programmed as the active edge.
s o
The following pins can be used for bus extension purposes as programmable output pins:
PLLLOCK, HSYNC, VSYNC and FIELD.
Ob
) -
PLLLOCK has a second alternate function IRQ (Interrrupt Request). Interrupt can be generated by
several functions described in registers DDECCONT36 and DDECCONT3C.
( s
4.12.6 Output Code Clipping
u ct
d
To allow compatibility with other devices, output codes can be clipped to remain inside 0 to 100% of
o
r
luminance (16 to 235) and chrominance (16 to 240) components.
P
4.12.7 Programming
et e
o l
The Vsync Insertion mode for the output flow is selected in the VSYNCTYPE bit in the
DDECCONT0 register.
b s The PHSHFT_DIS bit in the DDECCONT5 register is used to disable the phase jump mechanism in
O the output PLL. By default, phase jumps are allowed when a phase shift in the video input is
transmitted in the data flow to the output PLL.
The active edge for the CLK_DATA signal is selected by the ACTEDGE bit in the DDECCONT0
register.
Data is output from the STV2310 on the FIELD, VSYNC, HSYNC, PLLLOCK and YCRCB[7:0] pins
which are synchronous to the CLK_DATA output clock on either the rising or falling edge (depending
on the selected option).
To force the Interlaced output mode, use the NONINTERLACED_EN bit in the DDECCONT18
register.
41/113
To force the pass through mode, use the PASSTHROUGH_EN bit in the DDECCONT38 register.
To shift the external Hsync pulse, use the HSYNCSHIFT_DEL[1:0] and HSYNCSHIFT_EN bits in
the DDECCONT22 register.
Cr Cb attenuation are controlled by the DDECCONT37 and the DDECCONT38 registers.
The output blanking modes are controlled by the OUTBEHAV_BLANK2 and OUTBEHAV_BLANK1
bits in the DDECCONT38 register.
Output clipping is controlled by the DDECCONT18 register bit [2].
The PLLLOCK, HSYNC, VSYNC and FIELD pins may have bus extension functions. This is done by
programming the OUTBUS [7:0] bits in the DDECCONT7 register.
Table 13: Output PLL Alternate Functions
Bitfield Description
OUTBUS[0] 0: Standard function.

1: PLLLOCK = OUTBUS[1]

1: FIELD = OUTBUS[7]
s)
c t(
1: VSYNC = OUTBUS[5]
d u
1: HSYNC = OUTBUS[3]
r o
e P
le t
The PLLLOCK pin has a second alternate IRQ (Interrupt Request) function, selected by the
o
PLLLOCKIT_EN bit in the DDECCONT35 register.
s
Note:
b
By default, the PLLLOCK, HSYNC, VSYNC, and FIELD pins are used for their primary functions.
O
4.13 VBI Data Slicing and Insertion-
( s )
t
The following standards are supported by the VBI Data Slicer (see Table 14). After slicing, VBI data
c
d u
is embedded in the output stream, using the intervals between the End of Active Video (EAV) and
the Start of Active Video (SAV) codes of each line and formatted according to the ancillary
r o
sequences in compliance with specification ITU-R BT.656. VBI data is inserted in the Output FIFO.
e P Table 14: VBI Slicing Standards
l et
VBI Standards
TV Systems
TV Lines1
Bit Rate
Modulation
Bytes per
s o (lines/freq.) (Mbit/s) Line
O b Teletext B WST
VPS
625/50
625/50
6 to 22
16
6.9375
2.5000
NRZ
Bi-phase
45
15
WSS 625/50 23 0.8333 Bi-phase 14 bits of data
Closed Caption 625/50 21/22 0.5035 NRZ 3
Teletext B-WST1 525/60 10 to 21 5.727272 NRZ 37
Closed Caption 525/60 21 0.5035 NRZ 3
Gemstar 525/60 21 1.007 NRZ 5
1. Lines are numbered in compliance with specification ITU-R BT.470.
42/113
Note: The WST - Teletext C and D (525 lines /60 Hz) formats (NATBS - MOJI) may be covered by the
WST - Teletext B (525 lines -60 Hz) format.
4.13.1 VBI Formatting Features

4.13.1.1 VPS Features
Video Programming System (VPS) data complies with ETSI specifications.
● Search of VPS data on TV line 16 of each field
● Optional Extended VPS data on three TV lines (15,16 and 17) of each field
● Search of VPS data regardless of the field information
● Recognition of Start code
● Sampling and decoding of bytes 5 and 11 to 14
● Bi-phase code check
● Generation of bi-phase correctness flags
4.13.1.2 WSS Features

Wide Screen Signaling (WSS) data complies with ETSI specifications.
s)
● Search of WSS data on TV line 23 of each field
c t(
●
d u
Optional Extended WSS data on four TV lines (21, 22, 23 and 24) of each field
● Search of WSS data regardless of the field information
r o
● Recognition of Start code
e P
●
●
Sampling and decoding of relevant 14 bits
Bi-phase code check
le t
● Generation of bi-phase correctness flags
s o
4.13.1.3 WST Features
Ob
-
World System Teletext (WST) data complies with ETSI specifications. The searched WST format is
)
s
unique at a given time and is programmed by software through register-based control bits (50 Hz or
(
ct
60 Hz, etc.).
●
broadcasts.
d u
Search of WST data starting at TV line 6 for 525-line broadcasts, or TV line 318 for 625-line
●
r o
Optional Extended WST data search starting at 2nd TV line (register-based control bit).
●
e P
Recognition and check of usual WST frame code (27h).
●
l et
Optional recognition and check of programmable extended frame code (register-based value -
but the three LSBs must be kept at ‘1’).
o
bs
● Recognition of all packets or recognition of only Service Packets X/30 and X/31 (register-based
control bit).
O ●
●
Hamming decode & check of Magazine and Page bytes for usual frame code.
Split of Magazine & Page data in two separate bytes (1st byte is for Magazine, 2nd for Page).
4.13.1.4 Closed Caption Features

● Search of CC data during line 21 (NTSC) or line 22 (PAL), regardless of the field information.
● Optional Extended slicing during all the VBI (line 5 to 25 /NTSC or 2 to 25 /PAL), regardless of
the field information.
● Recognition and check of usual CC Frame code (11000b).
● Recognition and check of tighter CC Frame code (C2h).
43/113
● Generation of Per-byte Parity check flags.
4.13.1.5 Gemstar Features

● Search of Gemstar data during the line 21 (NTSC) or line 22 (PAL), regardless of the field
information.
● Optional Extended slicing during all the VBI (line 5 to 25 /NTSC or 2 to 25 /PAL), regardless of
the field information.
● Recognition and check of usual Gemstar Frame code (x011x1x1b)
● Recognition and check of tighter Gemstar Frame code (10110111b)
4.13.2 Data Output Format (DOF)

The Data Output Format stage will add the following data items to those received from the VBI
Formatting unit:
● An ancillary preamble
● A User Data Word Count
● Filler Words
s)
t(
● A User Data Word checksum
It will then perform the following operations:
u c
● Byte-to-nibble Data conversion operations
o d
●
●
Calculation of word-wise parity control bits
User Data Word checksum calculation P r
te
The data output flow issued by the Data Output Format is inserted into an ITU-R BT.656-type
le
digitized stream which complies with specifications ITU-R BT.656, ITU-R BT.1364 and SMPTE
o
291M.
b s
In particular, the data flow follows the 8-bit data coding convention. Ancillary data is coded as “Type
- O
2" 8-bit data items (as defined in both ITU.1364 and SMPTE 291M specifications).
EAV
(
Blanking Interval
s ) SAV Video Digitalized Stream
u ct
d
A maximum of 100 bytes are used in the Blanking Interval for ancillary data. For more information,
o
Pr
refer to Table 12: Frame Output Standards.
The Data Output Format unit provides the following data on a TV line base:
●
t e
The Transport layer which consists of the Ancillary Data Flag (ADF), Data ID (DID), Secondary
e
o lData ID (SDID), Data Count (DC) and Checksum Word (CS).
bs
● The entire data flow generated by the Hardware Filtering, after having split each byte into
nibble format.
O ● The current TV Line value, from which the data was extracted.
44/113
Ancillary Data Flow

For each TV line, the following sequence is generated immediately after the EAV code:
ADF DID SDID DC UDWi CS
3 Bytes 1 Byte 1 Byte 1 Byte User Data 1 Byte

Words
00h - FFh - FFh 41h Format ID UDW Count Sliced Data in Checksum
nibble
DID & SDID Coding Convention

All VBI data formats recognized by the Slicer use the same Data ID value. This Data ID value is
programmed in the SLDID[5:0] bits in the VBICONT1 register. The default value of the DID register
is "000001" respecting an 8-bit format and coding for 8-bit applications, in compliance with SMPTE
291M specifications (the full default code is 41h when parity control bits are added). Bits 6 and 7 of
the DID value are hardware calculated (bit 6 is the even parity of bits 5 to 0, bit 7 is the binary
complement of bit 6).
s)
Note: All possible DID values are coded using a Type 2 ancillary data coding format.
c t(
The Secondary Data ID codes (SDID) identify the recognized data formats as follows:
d u
Table 15: Secondary ID Codes
r o
SDID1 SDID Byte
e P Comments
01 41h WSS (No field link)

le t
02 42h
s o (Not used)
03 83h VPS (No field link)

Ob
04 44h
-
Closed Caption - Field 2
)
05 85h
( s
Closed Caption - Field 1
06 86h
u ct
Gemstar - Field 2
07 47h
o d Gemstar - Field 1
08
Pr
48h Teletext B - 625 lines/50 Hz - Field 2 Frame Code: 27h - F = 6.9375 MHz
09
et e89h Teletext B - 625 lines/50 Hz - Field 1 Frame Code: 27h - F = 6.9375 MHz
0A
o l 8Ah Teletext B - 625 lines/50 Hz - Field 2 Frame Code: XXh2 - F = 6.9375 MHz
b s 0B
10
4Bh
50h
Teletext B - 625 lines/50 Hz - Field 1
Teletext B - 525 lines/60 Hz - Field 2

Frame Codecode: XXh2 - F = 6.9375 MHz
Frame Code: 27h - F = 5.727272 MHz

O 11 91h Teletext B - 525 lines/60 Hz - Field 1 Frame Code: 27h - F = 5.727272 MHz
12 92h Teletext B - 525 lines/60 Hz - Field 2 Frame Code: XXh2 - F = 5.727272 MHz
13 53h Teletext B - 525 lines/60 Hz - Field 1 Frame Code: XXh2 - F = 5.727272 MHz
1. 8-bit Format
2. A different Frame Code (from the usual one) has been validated for this data.
The field information can be recovered from the Data ID value.
45/113
Data Count (DC) Coding

The Data Count (DC) byte is coded according to the parity protection scheme defined in SMPTE
291M or ITU-R BT.1364 specifications, as applied to 8-bit coded data (i.e. bit 6 is the even parity
check of bits 0 to 5, bit 7 is bit 6 complement to 1). In 8-bit applications, the DC byte gives a value
as a 4-byte group.
The number of the group of 4 User Data Words (UDW) transferred for the corresponding TV line is
given in the DC byte using 6 bits.
Checksum (CS) Coding

The Checksum (CS) byte is coded according to the parity protection scheme defined in SMPTE
291M or ITU-R BT.1364 specifications, as applied to 8-bit coded data.
Bits 6 to 0 are the LSB bits of the result of the sum of the seven LSB bits of DID, SDID, DC and all
UDW bytes (any carry is dropped). Bit 7 is the complement of Bit 6.
User Data Word (UDW) Coding

As 00h and FFh codes are prohibited in ITU-R BT.656 specifications, each data byte is substituted
by a pair of bytes; these two bytes are respectively built with:
s)
● The lower data nibble for the lower nibble of the 1st byte.
c t(
● The upper data nibble for the lower nibble of the 2nd byte.
d u
o
Data is transmitted in the same temporal order as for the Hardware Filtering.
r
data flow is re-mixed with the video flow.
e P
The TV line value is also provided to the DOF block to prevent scrambling errors when the ancillary
User Data Word Filler

le t
s o
As data is coded according to the 8-bit application protocol described in SMPTE 291M and ITU-R
b
BT.1364 specifications, some extra bytes may be inserted into the User Data Word sequence.
O
) -
These bytes code the value 80h which is meaningless and is used only to maintain a 4-byte UDW
modularity (in compliance with the above specifications). These meaningless bytes are also used to
s
maintain the most adequate 4-byte wise data storing format handled by the microcontroller.
(
items.
u ct
When an application is running, it is important that these filler bytes are not processed as valid data
o d
Pr
UDW Coding for WST - Teletext B
For World System Teletext (WST) standards, the UDW coding scheme depends on the searched
t
frame code.
e e
o l
When the searched frame code is the usual code (27h), the two first UDW words code the
b s Magazine (3 bits) and the Page (5 bits) values. In this case, there is no need to perform a nibble split
on these two words.When the searched frame code is validated with a programmable value, a split
O of the two first words is applied (as they may not be necessarily Hamming 8/4 coded).
The above bytes are followed by 80 bytes (respectively 64 bytes in 525/60Hz) resulting of the nibble
split of the 40 bytes (respectively 32 bytes in 525/60Hz) decoded from the current TV ancillary data.
Table 16: Magazine and Page Coding
Bit 7 6 5 4 3 2 1 0
Magazine Bit 6 Even parity Always 0 Magazine value

Byte 1’s complement check for bits
Coding [5:0]
46/113
Table 16: Magazine and Page Coding
Bit 7 6 5 4 3 2 1 0
Page Byte Bit 6 Even parity Always 0 Page value

Coding 1’s complement check for bits
[5:0]
In both cases, two filler bytes are added immediately after the last meaningful User Data Word in
order to maintain a Data Count value that is a multiple of 4 bytes.
All UDW bytes are coded according to the parity protection scheme defined in SMPTE 291M or ITU-
R BT.1364 specifications, as applied to 8-bit coded data (i.e. bit 6 is the even parity check of bits 0
to 5 and bit 7 is bit 6 complement to1).
Table 17: UDW Coding for WST
Other
Frame Code ADF DID SDID DC MAG PAGE UDW FIL1 FIL2 CS
Bytes
s)
t(
WST - 625 lines/50 Hz 27h Byte.count 3 1 1 1 1 1 80 1 1 1
WST - 625 lines/50 Hz
WST - 525 lines/60 Hz
xxh
27h
Byte.count
Byte.count
3
3
1
1
1
1
1
1
0
1
0
1
84
64
u c0
1
0
1
1
1
WST - 525 lines/60 Hz xxh Byte.count 3 1 1 1 0 0
o
68
d 0 0 1
P r
Note: “FIL1” and “FIL2” stand for Filler Bytes 1 and 2.
te
Table 18: UDW Byte Contents
o le
Byt
625 lines / 50 Hz 625 lines / 50 Hz
b s Byt
525 lines / 60 Hz 525 lines / 60 Hz
e
Content
(Framing = 27h)
Content
(Custom Framing)
- O e
Content
(Framing = 27h)
Content
(Custom Framing)
(s)
1 Decoded Magazine value LSB of Raw sliced 1st 1 Decoded Magazine value LSB of Raw sliced 1st byte
byte
c t
2 Decoded Page value
d u
MSB of Raw sliced 1st
byte
2 Decoded Page value MSB of Raw sliced 1st
byte
3 st
r o LSB of Raw sliced 2nd 3 LSB of 1st data byte LSB of Raw sliced 2nd
LSB of 1 data byte
e P byte byte
4
et
MSB of 1st data byte
l
MSB of Raw sliced 2nd 4 MSB of 1st data byte MSB of Raw sliced 2nd
o
byte byte
bs
5 LSB of 2nd data byte LSB of Next raw byte 5 LSB of 2nd data byte LSB of Next raw byte
O
6
…
MSB of 2nd data byte
…
MSB of Next raw byte
…
6
…
MSB of 2nd data byte
…
MSB of Next raw byte
… … … 67 LSB of 32nd data byte LSB of Last raw byte
83 LSB of 40th data byte LSB of Last raw byte 68 MSB of 32nd data byte MSB of Last raw byte
84 MSB of 40th data byte MSB of Last raw byte … … …
47/113
UDW Coding for VPS

In Video Programming Systems (VPS), a nibble split algorithm is applied. In all bytes, bit 6 is the
even parity check of bits 5 to 0. Bit 7 is the complement of bit 6.
Table 19: UDW Coding for VPS

ADF DID SDID DC VPUD VPUD VPUD VPUD VPUD VPUD VPUD VPUD VPUD VPUD VPUD VPUD CS
00 01 10 11 20 21 30 31 40 41 S0 S1
The result of the VPS sliced information is providing 12 bytes of data, which are generated in the
following order:
● VPUD00: This byte provides the LSB contents of VPS byte 5.
bit 7 6 5 4 3 2 1 0
0 0 RX3 RX2 RX1 RX0
● VPUD01: This byte provides the MSB contents of VPS byte 5.

bit 7 6 5 4 3 2 1 0
s)
0 0 SD1 SD0 RR1
c t(
RR0
SD[1:0]Sound bits
RR[1:0]R-Rating bits for flagging material not suitable for children.
d u
RX[3:0]Reserved bits for future applications. Presently not defined.
r o
e P
bit 7 6 5 4 3
le t2 1 0
so
0 0 ADT2 ADT1 ADT0 AMT3
Ob
VPUD11: This byte provides the MSB contents of VPS byte 11.
bit 7 6 5
-
4 3 2 1 0
(t s)
0 0 ID1 ID0 ADT4 ADT3
u c
ID[1:0]Identification of the address for this VPS line.
ADT[4:0]Announced day of transmission.
o d
AMT[3]Announced month of transmission.
●
Pr
VPUD20: This byte provides the LSB contents of VPS byte 12.
et
bit 7
e 6 5 4 3 2 1 0
o l 0 0 ASH3 ASH2 ASH1 ASH0
b s ● VPUD21: This byte provides the MSB contents of VPS byte 12.
O bit 7 6 5
0
4
0
3
AMT2
2
AMT1
1
AMT0
0
ASH4
AMT[2:0]Announced month of transmission.

ASH[4]Announced start hour.
bit 7 6 5 4 3 2 1 0
0 0 ASM1 ASM0 NC3 NC2
48/113
bit 7 6 5 4 3 2 1 0
0 0 ASM5 ASM4 ASM3 ASM2
ASM[5:0]Announced start minute.

NC[3:0]Nationality code which is used to identify the source of the item.
bit 7 6 5 4 3 2 1 0
0 0 PSC3 PSC2 PSC1 PSC0
bit 7 6 5 4 3 2 1 0
0 0 NC1 NC0 PSC5 PSC4
NC[3:0]Nationality code which is used to identify the source of the item.

PSC[5:0]Program source code used to identify the source of the item inside the country
identified in the nationality code.
s)
● VPUDS0: This byte provides the result of data coding checks.
c t(
bit 7 6 5 4 3 2
d
1
u 0
●
0 0 VPSER4
VPUDS1: This byte provides the result of data coding checks.

P
VPSER3
roVPSER2 VPSER1
e
let
bit 7 6 5 4 3 2 1 0
so
0 0 0 0 VPSVDA VPSER5
Ob
VPSVDA:Valid VPS Data. This bit is set when the VPS Start code has been matched and a full
VPS data flow has been sliced. When this bit is reset, it indicates that at least part of the VPS
-
data flow has not been received (in case of a too short TV line, for example).
)
s
VPSER1:Bi-phase error in the 1st VPS Byte. Data is written but there was a bi-phase error.
(
u ct
VPSER2:Bi-phase error in the 2nd VPS Byte. Data is written but there was a bi-phase error.
VPSER3:Bi-phase error in the 3rd VPS Byte. Data is written but there was a bi-phase error.
o d
Pr
VPSER4:Bi-phase error in the 4th VPS Byte. Data is written but there was a bi-phase error.
VPSER5:Bi-phase error in the 5th VPS Byte. Data is written but there was a bi-phase error.
et e
l
UDW Coding for WSS
o
bs
In Wide Screen Signaling (WSS), a nibble split algorithm is applied. In all bytes, bit 6 is the even
parity check of bits 5 to 0. Bit 7 is the complement of bit 6.
O Table 20: UDW Coding for WSS

ADF DID SDID DC WSUD WSUD WSUD WSUD WSUD WSUD WSUD WSUD CS
00 01 10 11 20 21 30 31
● WSUD00: This byte provides the LSB contents of the WSS 1st group of data.
bit 7 6 5 4 3 2 1 0
0 0 WSS3 WSS2 WSS1 WSS0
49/113
● WSUD01: This byte provides the MSB contents of the WSS 1st group of data.
bit 7 6 5 4 3 2 1 0
0 0 0 0 0 WSSER1
WSSER1:WSS data group 1 error flag. This bit is set when any of the Group 1 bits (WSS[3:0])
is received with a bi-phase error.
WSS[3:0]:WSS Aspect Ratio Bits.
● WSUD10: This byte provides the LSB contents of the WSS 2nd group of data.
bit 7 6 5 4 3 2 1 0
0 0 WSS7 WSS6 WSS5 WSS4
● WSUD11: This byte provides the MSB contents of the WSS 2nd group of data.
bit 7 6 5 4 3 2 1 0
0 0 0 0 0 WSSER2
WSSER2:WSS data group 2 error flag. This bit is set when any of the Group 2 bits (WSS[7:4])
is received with a bi-phase error.
s)
WSS[7:4]: WSS Enhanced Services Bits.
WSUD20: This byte provides the LSB contents of the WSS 3rd group of data. c t(
●
d u
bit 7 6 5 4 3 2
r o 1 0
0 0 WSSER3
WSUD21: This byte is static and provides no information.

e P
WSS10 WSS9 WSS8
bit 7 6 5 4 3
le t 2 1 0
1 0 0
s
0 o 0 0 0 0
Ob
WSSER3:WSS data group 3 error flag. This bit is set when any of the Group 3 bits
WSS[10:8]: WSS Subtitle Bits.

) -
(WSS[10:8]) is received with a bi-phase error.
( s
ct
● WSUD30: This byte provides the LSB contents of the WSS 4th group of data.
du
bit 7 6 5 4 3 2 1 0
r o 0 0 WSSER4 WSS13 WSS12 WSS11
e P
WSUD31: This byte provides the MSB contents of the WSS 4th group of data.
l et
bit 7 6 5 4 3 2 1 0
s o 0 0 0 0 0 WSSVDA
O b WSSVDA:Valid WSS Data. This bit is set when the WSS Start code has been matched and a
full WSS data flow has been sliced. When this bit is reset, it indicates that at least part of the
WSS data flow has not been received (in case of a too short TV line, for example).
WSSER4:WSS Data Group 4 Error Flag. This bit is set when any of the Group 4 bits
(WSS[13:11]) is received with a bi-phase error.
WSS[13:11]: WSS reserved Bits.
50/113
UDW Coding for CC

In Closed Caption (CC) systems, a nibble split algorithm is applied. In all bytes, bit 6 is the even
parity check of bits 5 to 0. Bit 7 is the complement of bit 6.
Table 21: UDW Coding for CC
ADF DID SDID DC CCUD CCUD CCUD CCUD CCUD CCUD FIL0 FIL1 CS
00 01 10 11 L0 L1
● CCUD00: This byte provides the LSB contents of the CC 1st byte of data.
bit 7 6 5 4 3 2 1 0
0 0 CC3 CC2 CC1 CC0
● CCUD01: This byte provides the MSB contents of the CC 1st byte of data.
bit 7 6 5 4 3 2 1 0
s)
0 0 CC7 CC6 CC5 CC4
c t(
d u
● CCUD10: This byte provides the LSB contents of the CC 2nd byte of data.
r o
e P
bit 7 6 5
0
4
0 CC11
3
le t
CC10
2
CC9
1
CC8
0
s o
●
Ob
CCUD11: This byte provides the MSB contents of the CC 2nd byte of data.
-
(s)
bit 7 6 5 4 3 2 1 0
ct
0 0 CC15 CC14 CC13 CC12
d u
●
r o
CCUDL0: This byte provides the contents of the CC bytes parity check.
e P bit 7 6 5 4 3 2 1 0
l et 0 0 0 0 CCP1 CCP0
s o
O b ● CCUDL1: This byte is static and provide no information.
bit 7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0
CCP0:Closed Caption parity flag of the first byte

CCP1:Closed Caption parity flag of the second byte
51/113
UDW Coding for Gemstar

In US Gemstar systems, a nibble split algorithm is applied. In all bytes, bit 6 is the even parity check
of bits 5 to 0. Bit 7 is the complement of bit 6.
Table 22: UDW Coding for Gemstar

ADF DID SDID DC GMU GMU GMU GMU GMU GMU GMU GMU GMPF GMPF FIL0 FIL1 CS
D00 D01 D10 D11 D20 D21 D30 D31 L0 L1
● GMUD00: This byte provides the LSB contents of the Gemstar 1st byte of data.
bit 7 6 5 4 3 2 1 0
0 0 GM3 GM2 GM1 GM0
● GMUD01: This byte provides the MSB contents of the Gemstar 1st byte of data.
bit 7 6 5 4 3 2 1 0
s)
0 0 GM7 GM6 GM5 GM4
c t(
d u
●
r o
GMUD10: This byte provides the LSB contents of the Gemstar 2nd byte of data.
bit 7 6 5 4 3 2
e P 1 0
0 0 GM11
le t
GM10 GM9 GM8
s o
●
Ob
GMUD11: This byte provides the MSB contents of the Gemstar 2nd byte of data.
-
(s)
bit 7 6 5 4 3 2 1 0
ct
0 0 GM15 GM14 GM13 GM12
d u
●
r o
GMUD20: This byte provides the LSB contents of the Gemstar 3rd byte of data.
e P bit 7 6 5 4 3 2 1 0
l et 0 0 GM19 GM18 GM71 GM16
s o
O b ● GMUD21: This byte provides the MSB contents of the Gemstar 3rd byte of data.
bit 7 6 5 4 3 2 1 0
0 0 GM23 GM22 GM21 GM20
● GMUD30: This byte provides the LSB contents of the Gemstar 4th byte of data.
bit 7 6 5 4 3 2 1 0
0 0 GM27 GM26 GM25 GM24
52/113
● GMUD31: This byte provides the MSB contents of the Gemstar 4th byte of data.
bit 7 6 5 4 3 2 1 0
0 0 GM31 GM30 GM29 GM28
● GMUDL0: This byte provides the contents of the Gemstar bytes parity check.
bit 7 6 5 4 3 2 1 0
0 0 GMP3 GMP2 GMP1 GMP0
● GMUDL1: This byte is static and provide no information.
bit 7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0
s)
GMP0: Gemstar parity flag of the first byte
c t(
GMP1: Gemstar parity flag of the second byte
d u
GMP2: Gemstar parity flag of the third byte
r o
GMP3: Gemstar parity flag of the fourth byte
e P
4.14 I²C Bus Specifications
le t
s o
Data transfers follow the usual I²C format: after the start condition (S), a 7-bit slave address is sent,
b
followed by an eight-bit which is a data direction bit (W). An 8-bit sub-address is sent to select a
O
) -
register, followed by an 8-bit data word to be included in the register. The circuit operates at clock
frequencies of up to 400 kHz. The IC’s I²C bus decoder allows the automatic incrementation mode
in write mode.
( s
String Format
u ct
d
Write Only mode (S = Start Condition, P = Stop Condition, A = Acknowledge)
o
S
Pr
SLAVE ADDRESS 0 A REGISTER N A DATA N A P
et
Read Only mode e
o l
bs
S SLAVE ADDRESS 0 A REGISTER N A P
O S SLAVE ADDRESS 1 A DATA N A DATA N+1 A P
Slave Address
Address A7 A6 A5 A4 A3 A2 A1 A0
Value 1 0 0 0 I2CADD 1 1 R/W
53/113
Table 23: Alternate I²C Addresses
I2CADD = 0 I2CADD = 1
Write Address 86h Write Address 8Eh
Read Address 87h Read Address 8Fh
For the exact numerical values of the I²C timing characteristics, please refer to the I²C Bus
Characteristics on page 106.
s)
c t(
d u
r o
e P
le t
s o
Ob
) -
( s
u ct
o d
Pr
et e
o l
b s
O
54/113
STV2310 Register List
5 Register List
This section lists the Control and Status registers for the I²C interface. Registers are called as output
ports and are named as follows:
● DDECCONT[n][7:0] for non-VBI Control registers
● DDECSTAT[n][7:0] for Status registers (Read Only)
● VBICONT[n][7:0] for VBI Control registers
5.1 Register Map
Register Function and Description

Add. Reset Value
Name
(h) (Bin)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DDECCONT0 00h 0000 0100 VSYNC PIXMODE ACT CVBS OUTTRI SVIDEO 5060MODE[1:0]
TYPE EDGE MUX STATE SEL
s)
DDECCONT1 01h 0011 1111 BLANKMODE[1:0] AUTOSTD[5:0]
c t(
DDECCONT2 02h 0100 1001 PEDESTAL
_REMOVE
AUTOSTD[11:6]
d u
DDECCONT3 03h 0001 0111
r o
AUTOSTD[17:12]
DDECCONT4 04h 0000 0001
e P
AUTOSTD[23:18]
DDECCONT5 05h 0010 0000 CRCBOVE

le t FBLANKMODE[2:0] YCRCB_ PHSHFT_
R_EN
s o MODE DIS
DDECCONT6
b
06h 0000 0001 MIX_SLOPE[7:0]
DDECCONT7 07h 0000 0000
- O OUTBUS[7:0]
(s)
DDECCONT8 08h 1111 1111 ZOOMIN_FACT[9:2]
ct
DDECCONT9 09h 0100 0000 ZOOMOUT_FACT[9:2]
du
DDECCONTA 0Ah 0000 0000 ZOOMIN_OFFSET[9:2]
DDECCONTB 0Bh
r o
1100 0000 ZOOMIN_FACT[1:0] ZOOMOUT_FACT ZOOMIN_OFFSET ZOOMOUT ZOOMIN_
DDECCONTC 0Ch
e P
0000 0000 SPC_CORING[1:0]
[1:0] [1:0]
ALL_NTSC_HUE_VALUE[5:0]
_EN EN
DDECCONTD
l et
0Dh 0011 0100 STI_NB_FIELDS_FALS STI_OK_O DEM_CKILL_CTRL[1:0]
s o E
[1:0]
NCE_OR_
MORE
O b
DDECCONTE 0Eh 0010 0110
DDECCONTF 0Fh 0000 0000 DEM_CKILL_LVL[2:0] DEM_CKILL_LVL[4:0]
DDECCONT1 10h 0001 0000 SPC_NTS SPC_NTS

C_FLESH_ C_FLESH_
0 PH EN
DDECCONT1 11h 1000 1000 SYNC_SLICE_LEVEL[3:0]

1
DDECCONT1 12h 0000 0000 SPC_NTS TINTANGLE[4:0]
C_GREEN
2 _EN
55/113
Register List STV2310

Add. Reset Value
Name
(h) (Bin)
DDECCONT1 13h 0000 0000

3
DDECCONT1 14h 0000 0000
4
DDECCONT1 15h 0001 0000 DEM_YC_DELAY[3:0]
5
DDECCONT1 16h 0111 1010 SATLMTLN[1:0] SATLMTPT[1:0] SMHITH[1:0] ACTITH[1:0]
6
DDECCONT1 17h 0110 0100 STI_50_60 STI_NB_FIELDS_CONFIRM[2:0] SPC_OVE SPC_ACC
HZ_EN RLOAD_O _OFF
7 FF
DDECCONT1 18h 0101 1001 BW_SEL[2:0] NONINTE SATCODE COMB_MO

8 RLACED_
EN
_EN
s) DE[1:0]
DDECCONT1 19h 0100 0100

c t(
9
d u
DDECCONT1 1Ah 0010 0000
r o
A
e P
DDECCONT1
B
1Bh 1000 0100
le t
DDECCONT1 1Ch 1000 0100
s o
C
Ob
DDECCONT1
D
1Dh 1000 1000
) -
( s
ct
DDECCONT1 1Eh 1001 1001
E
DDECCONT1 1Fh 0001 1000
d u
DIRECTPA
F
r o RITY
DDECCONT2 20h P
0000 0100
e
0
l et
DDECCONT2
1
s o 21h 0010 1011 BLKLINE[1:0]
O b
DDECCONT2 22h 1110 1000 HTIMECST HSYNCSHIFT_DEL[1:0] HSYNCSHI
SEL FT_EN
2
DDECCONT2 23h 1010 1010
3
DDECCONT2 24h 1000 0111
4
DDECCONT2 25h 1001 0100 HSYNC_ NOISE_THRESHOLD[2:0]
SAV
5
56/113

Add. Reset Value
Name
(h) (Bin)
DDECCONT2 26h 0100 0100

6
DDECCONT2 27h 0110 0110
7
DDECCONT2 28h 1000 0010 HUNLOCK_LINE_NUM[3:0] HLOCK_LINE_NUM[3:0]
8
DDECCONT2 29h 0101 0101 HLOCK_PH_ER_TH[3:0]
9
DDECCONT2 2Ah 1000 0010 CLAM_PROP[1:0] CLAM_DER[1:0] CLAMP_INT[2:0]
A
DDECCONT2 2Bh 0110 0011
B
s)
DDECCONT2
C
2Ch 1000 0010
c t(
DDECCONT2 2Dh 0000 1010
d u
D
r o
DDECCONT2 2Eh 0000 0000
e P
E
le t
DDECCONT2
F
2Fh 0000 0000
s o OVERDRIV OVERDRIVE_SEL[1:0]
E_MODE
DDECCONT3 30h 0000 0000

Ob
0
-
DDECCONT3
(t s)
31h 0010 0000 AGC_DIS CVBSAGCGAIN[5:0]
1
u c
DDECCONT3
d
32h 0000 0000
2
r o
DDECCONT3
3
33h
P
0000 0000
e
DDECCONT3
l et
34h 0000 0000
4
s o
O
5
b
DDECCONT3 35h 0000 0000 PLLLOCKI RGBADJU
T_EN ST_EN
RGBADJUST[5:0]
DDECCONT3 36h 1111 0000 PLLLOCK_ VLOCK_M HLOCK_M TVSTDID_ FBDEL[3:0]

MASK ASK ASK MASK
6
DDECCONT3 37h 1111 1111 CB_SCALING[1:0] CR_SCALING[5:0]
7
DDECCONT3 38h 0010 1111 CB_SCALING[5:2]
8
57/113

Add. Reset Value
Name
(h) (Bin)
DDECCONT3 39h 0101 0101

9
DDECCONT3 3Ah 0101 0101
A
DDECCONT3 3Bh 0011 0101
B
DDECCONT3 3Ch 1111 1100 VSYNCNS TRICKDET INTERDET VCRDET_ INSERDET FBDET_M
TD_MASK _MASK _MASK MASK _MASK ASK
C
VBICONT1 3Dh xx00 0001 SLDID[5:0]
VBICONT2 3Eh xx00 0000 SLFIL[5:0]
VBICONT3 3Fh 1000 0001 SLICECO RAWFILTO WSTSLICI WSTCUST WSTEXTLI WSTALLPA
MP_EN FF_EN NG_EN OMFRAM NES
)
CKETS
s
VBICONT4 40h 0010 0111 FRAMINGCODE[7:0]
c t(
VBICONT5 41h 1100 0101 WSSF1ON VPS1ONLY
LY_EN _EN
VPSSLICI
NG_EN NES
d u
VPSEXTLI WSSSLICI WSSEXTLI
NG_EN NES
VBICONT6 42h 0000 0000 GMVBILIN GMRELAX GMSLICIN

r o CCVBILIN CCRELAX CCSLICIN
ES _EN G_EN
e P ES _EN G_EN
VBICONT7 43h 0000 1101
le t
VBICONT8 44h 0000 1000
s o
VBICONT9
VBICONT0A
45h
46h
0110 0011
0001 1100
Ob
VBICONT0B
) -
s
47h 0100 0110
VBICONT0C 48h 0000 0000
ct (
VBICONT0D 49h 0000 0000
d u
VBICONT0E 4Ah
r
0000 0000
o
VBICONT0F 4Bh
e P
1011 0011 CGSEW[2:0] CGNBS[1:0] CGNBI[2:0]
VBICONT10
l et
4Ch 0000 1000 CGESPF2 CGESPF1 CGVS[5:0]
o
bs
VBICONT11 4Dh 0111 0001
O
VBICONT12 4Eh 0000 1100
VBICONT13 4Fh 0000 0000 WSTH[7:0]
VBICONT14 50h 0000 0000 WSTH[9:8]
VBICONT15 51h 0001 0101
VBICONT16 52h 1010 0000 EQZPRGM EQZORDE EQZFLTMOD[4:0]

ODE RSEL
VBICONT17 53h 0101 0000 VBI_EQUALCOEFF[2:0]
VBICONT18 54h 0001 0010
58/113

Add. Reset Value
Name
(h) (Bin)
DDECCONTF 7Eh 0000 0000 INTERDET VCRDET_ INSERDET FBDET_AC PLLLOCK_ VLOCK_A HLOCK_A TVSTDID_
_ACK ACK _ACK K ACK CK CK ACK
E
DDECCONTF 7Fh 0000 0000 VSYNCNS TRICKDET
TD_ACK _ACK
F
DDECSTAT1 80h 0001 0000 STVDDECVERS[7:0]
DDECSTAT2 81h READ ONLY VLOCK HLOCK PLLLOCK 5060ID TVSTDID TVSTD[2:0]
DDECSTAT3 82h READ ONLY VSYNCLO BLANKLVL INTERLAC DVD_DET VCR_DET INSER_DE FB_DETE TRICKMO
C_NSTD _SHIFT_D ED_DETE ECTED ECTED TECTED CTED D_DETEC
ETECTED CTED TED
DDECSTAT4 83h READ ONLY NOISELVL[7:0]
DDECSTAT5 84h READ ONLY SLDID[7:0]
DDECSTAT6 85h READ ONLY SLFIL[7:0]

s)
DDECSTAT7 86h READ ONLY VBIERR_D GEM_DET CC_DETE VPS_DET
c t(
WST_DET WSS_DET OPENLOO
DDECSTAT8
ETECTED ECTED CTED ECTED
u
ECTED
d
ECTED P
r o
5.2 Non-VBI Control Register Descriptions
e P
le t
DDECCONT0 Register Description
s o
Address: 00h
Ob
Reset Value (bin): 0000 0100
) -
( s
ct
du
VSYNCTYP PIXMODE ACTEDGE CVBSMUX OUTTRISTA SVIDEOSEL 5060MODE[1:0]
E TE
r o
e P
Bit Name
VSYNCTYPE
l etVsync Insertion in Output Flow
Function
o
bs
The VSYNC output signal is always synchronous to the output clock (CLK_DATA). It will toggle twice per
frame either in Digital or Analog mode according to this option.
O 0: Analog mode (Interlaced): depends on the standard:

for Output Standard 1: start of line 1 and middle of line 263
for Output Standard 2: start of line 1 and middle of line 313
for Output Standard 3: start of line 1 and middle of line 313 (same as Standard 2)
for Output Standard 4: start of line 1 and middle of line 263 (Default)
1: Digital mode: start of line 1/624 or start of line 264/624 (Vsync at beginning of line)
Note that the analog mode is now split between an "analog output as input" mode and an "analog output
with forced interlaced" output mode. For more information, see bit 3 of register DDECCONT18.
59/113
Bit Name Function
PIXMODE Pixel Mode Selection

In Square Pixel mode, the number of Y, Cr and Cb components depends on the standard as shown in
Table 12. The output line locked frequency (CLK_DATA) will also change according to the standard.
0: Normal Pixel mode (Default)
1: Square Pixel mode
ACTEDGE Data is output from the STV2310 on the following pads: FIELD, VSYNC, HSYNC, PLLLOCK and
YCRCB[7:0]. It is synchronous to the CLK_DATA output clock either on the rising or falling edge depending
on this option.
0: Clock falling edge is active edge (Default)
1: Clock rising edge is active edge
CVBSMUX Y/CVBS Input Selection

0: Y/CVBS1 input (Default)
1: Y/CVBS2 input
OUTTRISTATE Pad Tristate Mode

The pad tristate mode depends on the chip I2C address.
If the I2C default chip address is chosen:
s)
0: Output digital pads in Output mode (Default)
1: Output digital pads in Tristate mode
c t(
If the I2C spare chip address is chosen:
d u
0: Output digital pads in Tristate mode (Default)
r o
1: Output digital pads in Output mode
e P
Note that only the following pads can be in Tristate mode: FIELD, VSYNC, HSYNC, PLLLOCK, CLK_DATA
and YCRCB[7:0]. The I2C pads are never in Tristate mode.
le t
SVIDEOSEL CVSB/S-Video Selection
s o
The S-video mode notifies the STV2310 that the chroma and luma signals are already separated.
0: S-Video Input
1: CVBS Input (Default)
Ob
5060MODE[1:0]
) -
Vsync Search Mode and initial Free-running Mode
( s
ct
These bits provide the starting point for the Vsync extraction mechanism. 50-Hz or 60-Hz input standards
are expected. The options are to look exclusively for 50-Hz or 60-Hz standards (Forced 50 or 60) or to
d u
search for all standards with a priority in the search mechanism (Auto 50 or 60).
00: Auto 50: Automatic search mode starting with 50-Hz standards. (Default)
r o
01: Forced 60: Search mode forced to 60-Hz standards only.
P
10: Forced 50: Search mode forced to 50-Hz standards only.
11: Auto 60: Automatic search mode starting with 60-Hz standards.
e
l et
s o
O b
Address (hex): 01h
BLANKMODE[1:0] AUTOSTD[5:0]
60/113
Bit Name Function
BLANKMODE Blanking Mode

[1:0] The blanking mode defines how the clamp mechanism will perform. The blanking code is the ADC output
code used by the clamp mechanism as target In the Auto mode and depends on the vertical sync
identification result (50 or 60 Hz). The blanking code is determined in the 2 other modes.
00: Auto (50 Hz = Code 256, 60 Hz = Code 244) (Default)
01: Blanking code 256 (Sync tip 43 IRE)
10: Blanking code 244 (Sync tip 40 IRE)
11: Auto (Same as 00)
AUTOSTD[5:0] Auto Identification Table (Seventh and Eighth Standards)

The STV2310 can search for one of the TV standards programmed in the Automatic Standard Identification
Table (split over several registers). The Automatic Standard Identification Table has 8 entries with an order
of priority for the search. Note that in the default configuration, "No Standard" is programmed in the seventh
and eigth entries.
000: PAL BGDHI100: PAL N
001: SECAM 101 NTSC 4.43
010: NTSC M110 or 111: No Standard
011: PAL M
s)
c t(
d u
Address (hex): 02h
r o
e P
Bit 7 Bit 6
PEDESTAL_
Bit 5 Bit 4 Bit 3
le t Bit 2
AUTOSTD[11:6]
Bit 1 Bit 0
REMOVE
s o
Ob
Bit Name
) - Function
( s
ct
Bit 7 Reserved: Must be set to 0.
PEDESTAL_
d u
Pedestal Remove in Input signal
REMOVE
r o
The PEDESTAL_REMOVE bit describes the input signal (whether a pedestal is present in the input signal
P
or not). This information is entered by the user. Gain and offset on the Y processing will be different
according to that bit. The pedestal remove function is active for all 50- and 60-Hz input standards. Note that
et e
by default, it is considered that there is no pedestal in NTSC M inputs.
o l The pedestal remove function operates both on the CVBS and RGB flows.
0: Pedestal is present in input signal.
b s 1: Pedestal is not present in input signal. (Default)
O
AUTOSTD[11:6] Auto Identification Table (Fifth and Sixth Standards)
Fifth and Sixth Standards of the Automatic Standard Identification Table. See register DDECCONT1.
001 001: SECAM (Default)
61/113
Address (hex): 03h
AUTOSTD[17:12]
Bit Name Function
Bits[7:6] Reserved: Must be set to 0.
AUTOSTD[17:12] Auto Identification Table (Third and Fourth Standards)

Third and Fourth Standards of the Automatic Standard Identification Table. See register DDECCONT1.
010 111: NTSC M and No Standard (Default)
s)
c t(
Address (hex): 04h
d u
r o
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
e P Bit 1 Bit 0
le t
AUTOSTD[23:18]
s o
Bit Name
Ob Function
Bits[7:6] Reserved: must be set to 0.

) -
( s
ct
AUTOSTD[23:18] Auto Identification Table (First and Second Standards)
u
First and Second Standards of the Automatic Standard Identification Table. See register DDECCONT1.
d
o
000 001: PAL BGDHI and SECAM (Default)
r
e P
l et
o
Address (hex): 05h
s
O b
SECAM_CHRTUNING[1:0] CRCBOVER FBLANKMODE[2:0] YCRCB_ PHSHFT_DIS

_EN MODE
Bit Name Function
SECAM_CHRTU Reserved: must be set to 0.

NING[1:0]
62/113
Bit Name Function
CRCBOVER_EN RGB enables the CRCB overload algorithm

This bit enables the RGB CrCb overload mechanism. This mechanism is used to prevent clipping on YCrCb
(when the input RGB signals are too large). The CrCb overload mechanism performs chroma measurement
during the video line to compute the correcting scale factor.
0: CRCB overload algorithm not active
1: CRCB overload algorithm active
FBLANKMODE Fast Blanking Mode Selection

[2:0] The Fast Blanking mode is only operational when the STV2310 is not in Analog YCrCb mode. It also
depends on the programmed mode and the FB input value. See register DDECCONT6.
00x: Normal mixing mode between CVBS and RGB (Default)
(FB active during active line; soft mixing between 0 and 1)
01x: Saturated mode (mixing mode between CVBS and RGB)
(FB active and soft mixing from 0 to MIXSLOPE[7:0])
100: Static Mixer or Alpha Blending Mode 1
(FB inactive) YOUT = alpha x YRGB + (1-alpha) x YCVBS
101: Static Mixer or Alpha Blending Mode 2
(FB inactive) YOUT = alpha x YCVBS + (1- alpha) x YRGB with alpha = MIXSLOPE[7:0]
s)
(Same relationship for Cr and Cb)
c t(
110: Forced CVBS (FB inactive) YOUT = YCVBS (idem for Cb, Cr)
111: Forced RGB (FB inactive) YOUT = YRGB (idem for Cb,Cr)
d u
r o
YCRCB_MODE YCrCb Mode Selection
e P
When the STV2310 is in Analog YCrCb mode, Fast Blanking Mode is disabled.
0: YCrCb signals all either from CVBS or RGB. (Default)
le t
1: YCrCb mode: Y from CVBS signal, Cr and Cb from RGB signal with priority over FB mode.
PHSHFT_DIS Phase Shift Option Disabled in Output PLL

s o
Ob
This bit disables the phase jumps mechanism in the output PLL. Phase jumps are allowed when a phase
shift in the video input is transmitted in the data flow to the output PLL.
)
0: Phase shifts are enabled. (Default) -
1: Phase shifts are disabled.
( s
u ct
DDECCONT6
o d Register Description
Address (hex): 06h

Pr
t e
e
Bit 7
o l Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
bs
MIX_SLOPE[7:0]
63/113
Bit Name Function
MIX_SLOPE[7:0] Soft Mixing Slope, Alpha Blending or Saturated Value

This bitfield provides the soft mixing slope or the alpha blending value depending on Fast Blanking mode.
When the blanking mode is in Forced RGB or Forced CVBS mode, this bitfield is irrelevant.
When the blanking mode is in one of the alpha blending modes, the MIX_SLOPE[7:0] register provides the
alpha value (an FF entry means full scale).
When the blanking mode is in the normal mixing mode between RGB and CVBS, the MIX_SLOPE[1:0] bits
indicate the mixing slope. The MIX_SLOPE[7:2] bits must be set to 000000.
The MIX_SLOPE[1:0] register codes the soft mixing slope from 00 to 11 with 00 corresponding to a slope of
1 clock cycle (4 x fSC clock domain) and 11 corresponding to a slope of 4 clock cycles.
The default entry is 01, corresponding to a slope of 2 clock cycles.
Address (hex): 07h
s)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
c t( Bit 0
OUTBUS[7:0]
d u
r o
Bit Name Function
e P
OUTBUS[7:2] Alternative values driven by OUTBUS
le t
s o
The OUTBUS[7:2] bits are linked to the HSYNC, VSYNC and FIELD pad control.
When OUTBUS[2] = 0: standard function on HSYNC; when = 1: HSYNC = OUTBUS[3]
Ob
When OUTBUS[4] = 0: standard function on VSYNC; when = 1: VSYNC = OUTBUS[5]
When OUTBUS[6] = 0: standard function on FIELD; when = 1: FIELD = OUTBUS[7]
OUTBUS[1:0]
)
Alternative values driven by OUTBUS -
( s
The OUTBUS[1:0] bits are linked to the PLLLOCK pad control.
ct
When OUTBUS[0] = 0: standard function; when = 1: PLLLOCK = OUTBUS[1]
u
o d
DDECCONT8
Pr Register Description
Address (hex): 08h
et e
l
o
bs
O ZOOMIN_FACT[9:2]
Bit Name Function
ZOOMIN_FACT Zoom-in Factor from 1 to 4 (MSBs)

[9:2]
The Zoom-in factor operates from 4 to 1 (No zoom). The LSBs of this value are in the DDECCONTB
register. This value must be between 256 (x4) and 1023 (x1).
3FFh: Zoom-in factor of 1 (No zoom) (Default value)
200h: Zoom-in factor of 2
100h: Zoom-in factor of 4 (Enlarged picture)
64/113
Address (hex): 09h
ZOOMOUT_FACT[9:2]
Bit Name Function
ZOOMOUT_ Zoom-out Factor from 1 to 0.25 (MSBs)

FACT [9:2] The Zoom-out factor operates from 1 (no zoom) to 0.25 (large zoom). The Zoom-out factor must be
between 256 (x1) and 1023 (x0.25). The LSBs of this value are in the DDECCONTB register.
3FFh: Zoom-out factor of 0.25 (Reduced picture)
100h: Zoom-out factor of 1.0 (No zoom) (Default value)
DDECCONTA Register Description

s)
c t(
Address (hex): 0Ah
d u
r o
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
e
Bit 2
P Bit 1 Bit 0
ZOOMIN_OFFSET[9:2]
le t
s o
Bit Name
Ob Function
ZOOMIN_
OFFSET[9:2]
Zoom-in Offset (Cropping) (MSBs)
) -
The Zoom-in offset determines the section of input line used for zooming in. The Zoom-in offset value must
( s
be between 0 and the maximum number of Y pixels per line.
u ct
Note that the number of pixels per line will depend on the standard and the pixel mode.
Note that the Zoom-out factor is coded on 10 bits in 2 registers. The Default value is 0 = first left pixel of the
d
active line is the first pixel of zoom.
o
Pr
DDECCONTB
et e Register Description
o l
Address (hex): 0Bh
b s
O Bit 7
ZOOMIN_FACT[1:0]
Bit 6 Bit 5
ZOOMOUT_FACT[1:0]
Bit 4 Bit 3
ZOOMIN_OFFSET[1:0]
Bit 2 Bit 1
ZOOMOUT_
Bit 0
ZOOMIN_EN
EN
Bit Name Function
ZOOMIN_FACT Zoom-in Factor (LSBs). See register DDECCONT8.

[1:0]
65/113
Bit Name Function
ZOOMOUT_FAC Zoom-out Factor (LSBs). See register DDECCONT9.

T
[1:0]
ZOOMIN_OFFSE Zoom-in Offset (LSBs). See register DDECCONTA.

T[1:0]
ZOOMOUT_EN Zoom-out Function Enable

When both Zoom-in and Zoom-out functions are enabled, the STV2310 is in Panorama mode. In Panorama
mode, the ZOOMIN_FACT, the ZOOMOUT_FACT and the ZOOMIN_OFFSET are used. The
ZOOMIN_FACT determines the zoom-in factor at the left and right edges of the picture. The
ZOOMOUT_FACT determines the zoom-out factor at the center of the picture. The ZOOMIN_OFFSET
determines the border width where the zoom factor increases from the zoom-in factor to the zoom-out
factor, starting from the left edge (respectively, the border width finishing on the right edge where the zoom
factor decreases from the zoom-out factor to the zoom-in factor).
Correct programming is left to the user without hardware check. For programming verification, the following
formula must be checked: Zt x (Zout - Zin) = N x (Zout -1)
where Zin = ZOOMIN_FACT; Zout = ZOOMOUT_FACT; Zt = ZOOMIN_OFFSET; N = Number of Y pixels
per line (720 in Normal Pixel mode, 640 or 768 in Square Pixel mode)
s)
t(
0: Zoom-out function is disabled. (Default)
1: Zoom-out function is enabled.
ZOOMIN_EN Zoom-in Function Enable

u c
0: Zoom-in function is disabled. (Default)
o d
1: Zoom-in function is enabled.
P r
te
le
DDECCONTC Register Description
Address (hex): 0Ch

s o
Ob
Bit 7 Bit 6 Bit 5
)
Bit 4
- Bit 3 Bit 2 Bit 1 Bit 0
SPC_CORING[1:0]
( s ALL_NTSC_HUE_VALUE[5:0]
u ct
Bit Name
o d Function
SPC_CORING
Pr
Coring Function for all standards
[1:0]
et e
The Coring function is operational for all standards. When activated, the demodulated color components (Cr
l
and Cb) close to 128 are replaced by 128.
s o 00: No action. (Default)

01: 127 to 129 rounded to 128 (dynamic range of ± 1 LSB)
O b 10: 125 to 131 rounded to 128 (dynamic range of ± 3 LSBs)

11: 123 to 133 rounded to 128 (dynamic range of ± 5 LSBs)
ALL_NTSC_HUE NTSC Hue Control Function

_VALUE[5:0] The Hue Control mechanism is only operational when the NTSC or NTSC M standard has been detected
(or being tried by the standard identification algorithm). The hue is a fixed offset in a demodulation angle.
The offset is only operational in the active line. There are 63 steps of approximately 1.4 degrees each,
allowing an offset of between -45° and +43.6°.
Coded in 2’s complement (0 = No Hue)
66/113
DDECCONTD Register Description
Address (hex): 0Dh
STI_NB_FIELDS_FALSE STI_OK_ON DEM_CKILL_CTRL[1:0]

[1:0] CE_OR_MO
RE
Bit Name Function
STI_NB_FIELDS Number of Fields where Identification is lost before declaring Loss of Identification
_FALSE[1:0] The STI_NB_FIELDS_FALSE bits are related to the standard identification algorithm. These bits are
)
operational on all standards. They operate in the tracking phase when a standard has been recognized.
the standard is no longer met: the standard is then considered as lost.

t( s
They determine the number of successive fields to reach when at least one of the criteria associated with
00: 1 field10: 7 fields

01: 3 fields11: 15 fields
u c
o d
Bit 4
STI_OK_ONCE_
Reserved. Must be set to 1.
Number of trials before standard is officially recognized

P r
OR_MORE
te
The STI_OK_ONCE_OR_MORE bit is related to the internal standard identification algorithm and provides
le
some flexibility in the standard identification. This bit is operational for all standards. As previously
s o
described, up to 8 standards can be entered in the Automatic Standard Identification table. One (or more)
standard can be written more than once in that table (e.g. 4 times SECAM and 4 times PAL BGDHI). The
Ob
complete standard identification table is screened and tried before a decision can be made on identification
(one trial per table entry, succesful or not).
) -
When a standard has been programmed more than once and when this bit is set, all trials for all entries of
that standard in the Automatic Standard Identification table must be successful before the standard is
declared identified.
( s
u ct
When a standard has been programmed more than once and when this bit is reset, the standard is declared
identified when at least one trial was successful.
d
(Note that the information presented here only refers to the STI_OK_ONCE_OR_MORE bit. It does not
o
Bit 2
Pr
represent the entire standard identification algorithm.)
DEM_CKILL_
et e
Color Kill Control
CTRL[1:0]
o l The Color Kill Control mode is operational for all TV standards. In Automatic mode, the color is killed until
the standard is identified.
b s 00: Automatic (Default)10: Color always killed
O 01: Color never killed 11: Automatic (Same as 00) with Burst Amplitude control (see DDECCONT0F)
DDECCONTE Register Description
Address (hex): 0Eh
67/113
Bit Name Function
Bits [5:0] Reserved. Must be set to 0.
Bit 6 Reserved. Must be set to 0.
DDECCONTF Register Description
Address (hex): 0Fh
DEM_CKILL_LVL[2:0] DEM_CKILL_LVL[4:0]
Bit Name Function

s)
DEM_CKILL_LVL
[2:0]
Reserved. Must be set to 000. Chroma Killer Hysteresis Level
c t(
d u
The chroma kill mechanism is by default in automatic mode (see ddeccontd[7:0] register). The color is killed
on the output when no chroma standard is recognised. This register offers an additional killer feature when
r o
in automatic mode. The chroma is killed when the burst amplitude is under the chroma killer automatic level.
The chroma is restaured when the chroma burst amplitude is above the threshold plus the programmed
e P
hysteresis. When the chroma burst amplitude < dem_ckill_lvl[4:0], the chroma is killed. When the chroma is
killed and the chroma burst amplitude > dem_ckill_lvl[4:0] + dem_ckill_lvl[7:5], the chroma is no longer
killed.
le t
DEM_CKILL_LVL
[4:0] o
Reserved. Must be set to 00000. Chroma Killer Automatic Threshold.
s
See above.
Ob
DDECCONT10
) -
Register Description
( s
Address (hex): 10h
u ct
o d
Bit 7
SPC_NTSC P
SPC_NTSC
r
_FLESH_PH
t e
_FLESH_EN
e
o l
b s
Bit Name Function
O
SPC_NTSC_FLE
SH_PH
Automatic Flesh Control Phase Reference Selection
The Flesh Tone Reference Angle in the [B-Y, R-Y] axis system is either 123° or 117°.
0: Reference Phase is 117° (Default)
1: Reference Phase is 123°
SPC_NTSC_FLE Automatic Flesh Control Mode Enable

SH_EN 0: Automatic Flesh Control is disabled. (Default)
1: Automatic Flesh Control is enabled.
Bits [5:0] Reserved/ Must be set to 01 0000
68/113
Address (hex): 11h
SYNC_SLICE_LEVEL[3:0]
Bit Name Function
SYNC_SLICE_LE Slicing Level Value

VEL[3:0] The horizontal PLL requires a slicing level . This bitfield indicates the slicing level as a fraction between the
blanking and the sync tip level. The blanking level is used as the reference level for the clamp mechanism.
(See also bit BLANKMODE[1:0] in register DDECCONT1). The sync tip level is computed from the input
video signal by the synchronization mechanism.
0000: Slicing Level = Blank Level
1111: Slicing Level = (Blank – sync tip )/16 + sync tip
s)
t(
Bits[3:0] Reserved. Must be set to 0000.
u c
o d
Address (hex): 12h
P r
te
le
so
SPC_NTSC
_GREEN_E
N
Ob TINTANGLE[4:0]
) -
( s
Bit Name
u ct Function
Bits[7:6]
d
o
SPC_NTSC_GRE
EN_EN
Pr
Green Enhancement Mode Enable
The Green Enhancement mechanism is applied to the CVBS flow only and is only valid for the NTSC M and
et e
the NTSC 4.43 standards. The green tone axis has been defined as flesh tone axis + 90 degrees in the
vectorscope representation (i.e. 213 or 207 degrees). Green enhancement is only performed during the
o l active line. Green enhancement operates through saturation increase. Saturation increase factor k is a
b s linear function of the color phase distance to green axis.

k = 1 for color phase - green axis = ± 22.5 degrees (minimum value)
O k = 1.2 for color phase = green axis (maximum value)

(k always 1 when color phase not at 22.5 degrees of green axis)
0: Green Enhancement mode is disabled.
1: Green Enhancement mode is enabled.
TINTANGLE[4:0] Tint Angle

The Tint Angle is applied to the Cr and Cb values of the RGB data flow after the RGB to YCrCb conversion.
The Tint Angle is coded from -20° to +20° in steps of 1.33°. The bitfield is coded in 2's complement.
69/113
Address (hex): 13h
Bit Name Function
Bits[7:0) Reserved: Must be set to 0000 0000.
Address (hex): 14h

s)
c t( Bit 0
d u
r o
Bit Name Function
e P
Bits [7:0] Reserved: Must be set to 0000 0000.
le t
s o
DDECCONT15 b
O
Address (hex): 15h
) -
( s
ct
du
r o DEM_YC_DELAY[3:0]
e P
Bit Name
l et Function
Bits[7:6]
s o Reserved. Must be set to 00.
O b
Bits[5:4]
DEM_YC_DELAY
Y vs. C Delay in Chroma Demodulator

[3:0] This bitfield provides a programmable Y path vs. C path delay in the Chroma Demodulator. The unit delay is
a quarter of the chroma sub-carrier period. Negative values mean that the luma is in advance compared to
the chroma. Bits are coded in 2’s complement.
1000: -8
0000: No shift between Chroma and Luma (Default)
0111: +7
70/113
Address (hex): 16h
SATLMTLN[1:0] SATLMTPT[1:0] SMHITH[1:0] ACTITH[1:0]
Bit Name Function
SATLMTLN[1:0] AGC Saturation Limit (Points/Lines)

SATLMTPT[1:0] The SATLMTPT[1:0] and SATLMTLN[1:0] bits are used to program the CVBS Saturation Threshold. It is
expressed as a number of samples per field (when, according to the algorithm, the number of samples is
reached, the gain is decreased). The formula for the threshold computation is the following:
Threshold = 1 + 4 x SATLMTPT[1:0] +16 x SATLMTLN[1:0]
SMHITH[1:0] AGC SMHI Threshold Value
)
This bitfield defines the Luma Low Signal Detection Threshold (when, according to the algorithm, the luma
s
t(
signal remains under that threshold, the gain is increased). The threshold is defined as an ADC (10 bit)
code output according to the following formula:
Threshold = 772 + 8 x SMHITH[1:0] (Default = 772 + 8 x 2)
u c
ACTITH[1:0] AGC ACTI Threshold Value
o d
P r
This bitfield defines the Luma Saturation Threshold (when, according to the algorithm, the luma signal
overtakes that threshold, the gain is decreased). The threshold is defined as an ADC (10 bit) code output
according to the following formula:
te
le
Threshold = 807 + 8 x ACTITH[1:0] (Default = 807 + 8 x 2)
o
DDECCONT17 b
s
- O
Address (hex): 17h
( s )
ct
du
r o STI_NB_FIELDS_CONFIRM[2:0]
e P
Bit Name
l et Function
Bit 7
s o Reserved. Must be set to 1. Recommended value: 1 (instead of 0 at reset).
O b
Bit 6
STI_50_60HZ_
Standard ID Enable
EN This bit modifies the standard identification algorithm. When this bit is set (default), the standard
identification algorithm disregards the auto identification table entries not corresponding to the 50 or 60Hz
detection performed by the synchronization block.
71/113
Bit Name Function
STI_NB_FIELDS Number of Fields to be Confirmed

_CONFIRM[2:0] This bitfield operates on the second stage of the standard identification algorithm: the confirmation stage. It
gives the number of consecutive fields where the standard criteria must be OK before the standard
identification is confirmed.
000: 1 field 100: 8 fields
001: 3 fields (default) 101: 32 fields
010: 7 fields 110: 45 fields
011: 10 fields 111: 63 fields
SPC_OVERLOA Cover coefficient forced to 1

D_OFF The SPC_ACC_OFF and SPC_OVERLOAD_OFF bits are related to the ACC and ACC Overload
mechanisms operating on the CVBS flow. These regulating algorithms are a complement to the AGC
operating on the CVBS and the Y amplitudes).
The ACC and ACC Overload mechanisms operate on the chroma (C) amplitude in the CVBS flow. The ACC
(automatic chroma control) operates with the Cburst burst scale factor. The ACC overload mechanism
operates with the Cover chroma correction factor. Both Cburst and Cover values are internal variables.
The Cover variable carries the maximum chroma value measured during the video line.
0: Cover coefficient is not forced to 1 (Overload mechanism).
s)
t(
1: Cover coefficient is forced to 1.
SPC_ACC_OFF Cburst coefficient forced to 1
u c
o d
The Cburst variable carries the input video burst amplitude. When that amplitude is different from the
standard, demodulated chroma components are scaled with Cburst. Cburst change rate and change steps
P r
are also programmable. See registers DDECCONT20[1:0] = SPC_ACC_KTHBURST[1:0] ,
DDECCONT20[5:4] = SPC_ACC_NB_LINEUP[1:0] , DDECCONT20[7:6] = SPC_ACC_NB_LINEDW[1:0].
0: Cburst coefficient is not forced to 1 (ACC. mechanism).
te
le
1: Cburst coefficient is forced to 1.
s o
Ob
Address (hex): 18h
) -
( s
Bit 7 Bit 6 Bit 5
u ct Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
o d
BW_SEL[2:0] NONINTER OUT_ COMB_
Pr LACED_EN RANGE MODE
Bit Name
et e Function
o l
bs
BW_SEL[2:0] Notch Width Select
O This register offers the possibility to select the notch width:

000: Notch filter the narrowest
111: Notch filter the widest
72/113
Bit Name Function
NONINTERLACE Analog Output as Input Bit

D_EN This bit enables the "analog output as input" mode. It is only operational when the o_vsynctype is set to the
analog mode (see register o_ddeccont0[7] bit) When the o_vsynctype is set to the digital mode, that bit is
irrelevant.
0: Analog Forced Interlaced Mode. The output is interlaced even if the video input is not. This is equivalent
to cut 1.0. It is required by TMM.
1: Analog Output as Input Mode. The output is interlaced when the input is interlaced. The output is not
interlaced when the input is not interlaced. (Default)
OUT_RANGE Output Range Control

0: Output code range is 1 to 254 on Y, Cr and Cb outputs (Default)
1: Output code range is 16 to 235 on Y; and 16 to 240 on Cr and Cb outputs
COMB_MODE Adaptive Comb or Notch Forced Mode

This register selects the Luma Chroma Separation mode. Luma Chroma Separation can be performed by
comb filtering or notch filtering.
0: Notch separation mode forced
1: Adaptive comb filter (Default)
s)
c t(
d u
Address (hex): 19h
r o
e P
le t Bit 2 Bit 1 Bit 0
s o
Ob
Bit Name
) - Function
Bits [7:0]
( s
Reserved: Must be set to 0100 0100
u ct
DDECCONT1A
Address (hex): 1Ah

Pr
t e
e
Bit 7
b s
O
Bit Name Function
Bits[7:6] Unused. Must be set to 00.
Bits [5:0] Reserved: Must be set to 10 0000
73/113
DDECCONT1B Register Description
Address (hex): 1Bh
Bit Name Function
Bits[7:4] Reserved: Must be set to 1000
DDECCONT1C Register Description
Address (hex): 1Ch

s)
c t(
d uBit 1 Bit 0
r o
e P
Bit Name Function
le t
s o
Ob
) -
DDECCONT1D
s
(
Address (hex): 1Dh
u ct
o d
Bit 7
Pr
et e
o l
b s
Bit Name Function
O
Bits[7:4]
Bits[3:0]
Reserved: Must be set to 1000
Reserved: Must be set to 1000
74/113
DDECCONT1E Register Description
Address (hex): 1Eh
Bit Name Function
DDECCONT1F Register Description
Address (hex): 1Fh

s)
c t(
u
Bit 1
d
Bit 0
DIRECTPAR
r o
P
ITY
te
Bit Name
o Function le
DIRECTPARITY Direct Parity Option
b s
- O
This bit selects the option of the direct parity on the F pad. This option is only operational when the stvddec
is in the analog output mode (see register DDECCONT0[[7]). The input video parity is detected on every
( s )
field. The parity issued on the FSYNC pad is normally not this direct parity but is filtered on several fields.
0: Normal parity is issued on the FSYNC pad (Default)
Bit 6
u ct
1: Direct parity is issued on the FSYNC pad
Reserved: Must be set to 0.
o d
Bit 5
Bit 4
Pr
Bit 3
et e
Bits [2:1]
o l Reserved: Must be set to 00.
b s
O DDECCONT20 Register Description
Address (hex): 20h
75/113
Bit Name Function
Bits [7:6] Reserved: Must be set to 00.
Address (hex): 21h
BLKLINE[1:0]
s)
Bit Name Function
c t(
d u
BLKLINE[1:0] Optional output blanking lines
r o
00: no additional blanking
e P
This register provides additional blanking on lines just before or just after the vertical blanking interval.
01: one line additional blanking

10: 2 lines additional blanking (Default)
le t
11: 3 lines additional blanking
s o
Bits[3:0] Reserved: Must be set to 1011.
Ob
) -
DDECCONT22
( s
Address (hex): 22h

u ct
o d
Bit 7
Pr
et e HTIMECSTS HSYNCSHIFT_DEL[1:0] HSYNCSHIFT
o l EL _EN
b s
O Bit Name

Function
HTIMECSTSEL HPLL Mode Selection

0: Fixed Time Constant mode 1: Automatic mode
76/113
Bit Name Function
HSYNCSHIFT_D This register allows a programmable delay of HSYNC output signal. This register is only active when
EL[1:0] o_hsyncshift_en is active (see register DDECCONT22[0]).
00: (no details yet)
HSYNCSHIFT_E Output Synchronisation shift enable

N 0: No delay (Default)
1: HSYNC is delayed with respect to the digital ouput.
Note that this feature has not been decided yet.
Address (hex): 23h
s)
c t(
Bit Name Function
d u
r o
e P
le t
s o
Address (hex): 24h
Ob
) -
( s
ct
du
MAX_PJ_AMP[3:0] ERR_THRESHOLD[2:0] PJ_EN
r o
Bit Name
e P Function
Bits [7:4]
l et Reserved. Must be set to 1000.
Bits [3:1]
s o Reserved. Must be set to 011.
O b
Address (hex): 25h
HSYNC_ NOISE_THRESHOLD[2:0]
SAV
77/113
Bit Name Function
HSYNC_SAV HSYNC / SAV

This option bit is active when set AND the output mode is an analog mode (see DDECCONT0[7] register).
0: the hsync signal is issued according to the analog mode description
1: the hsync signal coincidates with the SAV code in the digital flow (falling edge on SAV first byte and rising
edge on SAV last byte).
NOISE_THRESH HPLL Noise Threshold Selection

OLD[2:0] This bitfield provides a tuning mechanism for HPLL behavior using the detected level of noise as a
parameter.
This bitfield defines a high noise level. When that high noise level is reached some HPLL features are
disabled (phase jumps, copy protection detection).
The bitfield can be considered as a cursor where an entry of 000 means that the input signal is above the
high noise level, whatever the noise level detected internally. Conversely an entry of 111 means that the
input signal is under the high noise level in all circumstances. Between these 2 extremes, a proportion of the
detected level of noise (register DDECSTAT3) is the reference for the high noise level.
s)
c t(
Address (hex): 26h
d u
r o
e Bit 2 P Bit 1 Bit 0
le t
s o
Bit Name
Ob Function
Bits [7:0]
)
Reserved. Must be set to 0100 0100. -
( s
ct
du
Address (hex): 1Eh

r o
P
e
Bit 7
l et Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
s o
O b
Bit Name Function
Bits [7:0] Reserved. Must be set to 0110 0110.
78/113
Address (hex): 28h
HUNLOCK_LINE_NUM[3:0] HLOCK_LINE_NUM[3:0]
Bit Name Function
HUNLOCK_LINE HPLL number/4 of successive err>thresh for hunlock

_NUM[3:0] This register is used by the HPLL. It provides the number of successive lines divided by 4 where the phase
error must be above the required threshold to consider the hlock to be lost. The default value is 8 x 4 lines.
HLOCK_LINE_N HPLL number/4 of successive err<thresh for hlock

UM This register is used by the HPLL. Its entry is the number of successive lines divided by 4 where the phase
[3:0] error must be below the required threshold before the hlock is acquired (a value of 0001 h = 1 means 4
lines). The default value is 2 x 4 lines.
s)
c t(
d u
Address (hex): 29h
r o
e P
le t Bit 2 Bit 1 Bit 0
so
HLOCK_PH_ER_TH[3:0]
Ob
Bit Name
) - Function

( s
Bit 7
ct
u
Bits [5:4]
d
o
HLOCK_PH_ER_
TH[3:0]
Pr
HPLL phase error threshold / 8 for hlock / hunlock
This register provides the phase error threshold for the HPLL. The same value is used for the lock and
et e
unlock mechanism. The entry value is the number of samples multiplied by 8. The default value is 5 x 8
o l samples.
b s DDECCONT2A Register Description

O
Address (hex): 2Ah
CLAMP_PROP[1:0] CLAMP_DER[1:0] CLAMP_INT[2:0]
79/113
Bit Name Function
CLAMP_PROP[1: Proportional Gain Selection

0] This register is related to the CVBS clamp regulation algorithm where a PID filter is used. CLAMP_PROP
defines the Proportional Gain selection.
00: Proportional Gain divided by 64 10: Proportional Gain divided by 16
01: Proportional Gain divided by 32 11: Proportional Gain divided by 8
CLAMP_DER[1:0] Defines the Clamp Derivate selection.

00 : 1 10 : 1/4
01 : 1/2 11 : 0
CLAMP_INT[2:0] Clamp Integral Gain Configuration

This bitfield is related to the CVBS clamp regulation algorithm where a PID filter is used. This bitfield
provides the integral gain selection. The entry is coded as follows:
000: Divided by 64
111: Divided by 5192
s)
DDECCONT2B Register Description
c t(
Address (hex): 2Bh
d u
r o
e
Bit 2 P Bit 1 Bit 0
le t
s o
Bit Name
Ob Function
) -
( s
DDECCONT2C
u ct
o d
Address (hex): 2Ch
Pr
Bit 7
et e
o l
b s
O Bit Name Function
80/113
DDECCONT2D Register Description
Address (hex): 2Dh
Bit Name Function
DDECCONT2E Register Description
s)
Address (hex): 2Eh
c t(
d u
P ro
Bit 1 Bit 0
e
Bit Name
o let
Function

b s
- O
( s )
Bit 4
ct
u
Bit 3
d
o
Bit 2
Bit 1
Pr
Bit 0
et e
o l
b s DDECCONT2F Register Description
O
Address (hex): 2Fh
OVERDRIV OVERDRIVE_SEL[1:0]
E_MODE
81/113
Bit Name Function
OVERDRIVE_MO This bit is used for a special proprietary mode between the STV2310 and the STV3500. It is called
DE overdrive mode. Additional VBI data is stuffed between the EAV and the SAV to raise the output clock data.
0: Overdrive output mode disabled
1: Overdrive output mode enabled
OVERDRIVE_ Selection of frequency shift in the overdrive mode

SEL[1:0] It is only active when the overdrive mode has been selected.
The n value provided by the OVERDRIVE_SEL[1:0] register will determine the number of bytes added in
each preamble according to: number of bytes added = n x 32 bytes.

s)
Address (hex): 30h
c t(
d u
r o Bit 1 Bit 0
e P
le t
Bit Name
s oFunction

Ob
Bits [6:0]
)
Reserved: Must be set to 000 0000. -
( s
ct
du
Address (hex): 31h

r o
P
e
Bit 7
l et Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
s o AGC_DIS CVBSAGCGAIN[5:0]
O b
Bit Name Function
Bit 7 Reserved: Must be set to 0
AGC_DIS Disabling AGC

0: Normal mode (AGC is not disabled)
1: Test mode (AGC is disabled) Forced DAC command as specified by CVBSAGCGAIN.
CVBSAGCGAIN Forced value of CVBS AGC when in Forced Mode

[5:0]
82/113
Address (hex): 32h
Bit Name Function
Address (hex): 33h

s)
c t(
u
Bit 1
d
Bit 0
r o
e P
Bit Name Function
le t
s o
Bit [6:0] Reserved. Must be set to 0000 0000.
Ob
) -
DDECCONT34
s
(
Address (hex): 34h
u ct
o d
Bit 7
P
Bit 6r Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
et e
o l
b s
Bit Name Function
O
Bit [6:0] Reserved. Must be set to 0000 0000.
83/113
Address (hex): 35h
PLLLOCKIT RGBADJUS RGBADJUST[5:0]

_EN T_EN
Bit Name Function
PLLLOCKIT_EN PLLLOCK Pad IT Enable

0: The PLLLOCK pad use is determined by the DDECCONT7 register
1: The PLLLOCK pad is used as the IT pad (in this case, register DDECCONT7 is irrelevant)
RGBADJUST_EN RGB Gain Adjustment Enable

0: RGB Gain Adjustment mechanism is disabled (Default)
1: RGB Gain Adjustment enabled
s)
RGBADJUST[5:0] RGB Gain Adjustment Value
c t(
This adjusts the RGB channel with the CVBS channel. The adjustment gain is expressed as [1 +
u
RGBADJUST]. It is applied on Y, Cr and Cb when in RGB mode. It is applied on Cr and Cb in YCrCb
d
mode. RGBADJUST is coded in 2's complement (+31 to -32).
011111: Maximum positive value of approx. +0.25
r o
000000: RGBADJUST = 0 (Default)
100000: Maximum negative value of approx. -0.25
e P
le t
s o
Address (hex): 36h
Ob
) -
( s
ct
du
PLLLOCK_ VLOCK_MA HLOCK_MA TVSTDID_M FBDEL[3:0]
MASK SK SK ASK
r o
e P
Bit Name
l et Function
PLLLOCK_MASK
s o Mask for interruption on change of PLLLOCK status
O b
VLOCK_MASK
HLOCK_MASK
Mask for interruption on change of VLOCK status
Mask for interruption on change of HLOCK status
TVSTDID_MASK Mask for interruption on change of TVSTDID status

0: Interrupt is not masked
1: Interrupt is masked
FBDEL[3:0] delays the FB signal wrt the RGB flow

The delay is coded in 2's complement (from -16 to 15) The Default value is 0, expressed in 4 x fSC clock
periods.
84/113
Address (hex): 37h
CB_SCALING[1:0] CR_SCALING[5:0]
Bit Name Function
CB_SCALING 2 LSB for Scaling Factor for Cb data flow

[1:0] The Cb data flow in the COR block is multiplied by the CB_SCALING factor.
(Each LSB of scaling factor = 1/64)
when CB_SCALING = 11 1111, the scaling factor = 1
when CB_SCALING = 00 0000, the scaling factor = 1/64
CR_SCALING Scaling Factor for Cr data flow

[5:0] The Cr data flow in the COR block is multiplied by the CR_SCALING factor.
s)
t(
(Each LSB of scaling factor = 1/64)
when CR_SCALING = 11 1111, the scaling factor = 1
when CR_SCALING = 00 0000, the scaling factor = 1/64
u c
o d
P r
te
Address (hex): 38h
o le
Bit 7 Bit 6 Bit 5 Bit 4

b sBit 3 Bit 2 Bit 1 Bit 0
PASSTHRO OUTBEHAV OUTBEHAV OUTBEHAV

- O CB_SCALING[5:2]
UGH_EN _MOD1 _BLANK2
( )
_BLANK1
s
Bit Name
u ct Function
o d
PASSTHROUGH
_EN
Pr
Enable for the pass-through mode
The pass-through mode allows (test) lines that are sent during the Vertical Blanking interval to be sent
et e
captured by the line memory and reissued.
OUTBEHAV_MO
D1
o l The OUTBEHAV_MOD1 selection bit is used to block the free run mode on the output clock when there is
no input video (HLOCK = 0).
b s 0: Free run mode on the output clock when hlock = 0 (Default). The output data is blanked or not during the
no video state or the transient state according to the bits OUTBEHAV_BLANK1 and OUTBEHAV_BLANK2.
O (See above)
1: The output clock follows the search performed by the input PLL. (This mode is mainly used for debug
reasons.)
OUTBEHAV_ The OUTBEHAV_BLANK1 and OUTBEHAV_BLANK2 selection bits are used to program the STV2310
BLANK2 behaviour when there is no input video (HLOCK = 0) or when there is an input video (HLOCK = 1) but the
OUTBEHAV_ vertical synchronisation is not yet acquired (VLOCK = 0). They are only operational when
BLANK1 OUTBEHAV_MOD1 = 0. This is the normal default mode.
OUTBEHAV_BLANK1 = 0, the output FIFO is read when HLOCK = 0
OUTBEHAV_BLANK1 = 1, the output data is blanked when HLOCK = 0
OUTBEHAV_BLANK2 = 0, the output FIFO is read when HLOCK = 1 and VLOCK = 0
OUTBEHAV_BLANK2 = 1, the output data is blanked when HLOCK = 1 and VLOCK = 0
85/113
Bit Name Function
CB_SCALING 4 MSBs for Scaling Factor for Cb data flow

[5:2]
Address (hex): 39h
Bit Name Function
)
t( s
DDECCONT3A Register Description
u c
od
Address (hex): 3Ah

P r
te
Bit 2 Bit 1 Bit 0
o
FRC_CLK_GEN[15:8] le
b s
Bit Name
- O Function
Bits [7:0]
( s )
Reserved. Must be set to 0101 0101.
u ct
DDECCONT3B
Address (hex): 3Bh

Pr
t e
e
Bit 7
b s
O Bit Name Function
86/113
DDECCONT3C Register Description
Address (hex): 3Ch
VSYNCNST TRICKDET_ INTERDET_ VCRDET_M INSERDET_ FBDET_MA

D_MASK MASK MASK ASK MASK SK
Bit Name Function
VSYNCNSTD_ Mask for interruption on change of status on VSYNCLOC_NSTD.

MASK 0: Interrupt is not masked 1: Interrupt is masked
TRICKDET_ Mask for interruption on change of status on TRICKMODE_DETECTED.

MASK 0: Interrupt is not masked 1: Interrupt is masked
INTERDET_
MASK
Mask for interruption on change of status on INTERLACED_DETECTED.
s)
t(
0: Interrupt is not masked 1: Interrupt is masked
VCRDET_MASK Mask for interruption on change of status on VCR_DETECTED.
u c
o d
INSERDET_
MASK
Mask for interruption on change of status on INSER_DETECTED.
P r
FBDET_MASK Mask for interruption on change of status on FB_DETECTED.
te
0: Interrupt is not masked
o le
1: Interrupt is masked
Bits [1:0]
s
b
5.3 -
VBI Control Register Descriptions
O
( s )
VBICONT1
c t Register Description
d u
Address (hex): 3Dh
r o
P
e
Bit 7
l et Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
SLDID[5:0]
Bit 1 Bit 0
s o
O b
Bit Name Function
SLDID[5:0] Bitfield Description

DID value used by the STV2310 for coding ancillary packets. (The default value is type 2, first code
reserved for 8-bit applications).
87/113
VBICONT2 Register Description
Address (hex): 3Eh
SLFIL[5:0]
Bit Name Function
SLFIL[5:0] Bitfield Description

Filler value used by the STV2310 for coding the filler byte in the ancillary packets. The default value is 80.
s)
Address (hex): 3Fh
c t(
d u
ro
SLICECOM
P_EN
RAWFILTOF
F_EN
WSTSLICIN
G_EN
e P
WSTCUSTO
MFRAM
WSTEXTLIN
ES
WSTALLPACK
ETS
o let
Bit Name
b s Function
- O
SLICECOMP_EN
RAWFILTOFF_E
( s )
On the fly slicing level computation enable (only for TXT decoding)
Hamming filtering bypass in raw mode for TXT reception

N
ct
0: The filtering is active in raw mode (Default)
u
1: The filtering is bypassed in raw mode
WSTSLICING_E
o d
WST Slicing Enable
N
Pr
0: (WST) data slicing is disabled
1: (WST) data slicing is authorised
et e
Note that this bit is used at the top level to control the equalizer
WSTCUSTOMFR
o l WST search with new framing code enable
bs
AM 0: The new framing code is not enabled
1: The new framing code (provided in register VBICONT4[7:0] = SLCORE[15:8]) is enabled
O
WSTEXTLINES WST extended slicing window enable
0:
1: The WST search starts at line 2
WSTALLPACKET WST slicing of all packets enable

S 0: Only service packets X/30 and X/31 are sampled
1: all packets are sampled
88/113
Address (hex): 40h
FRAMINGCODE[7:0]
Bit Name Function
FRAMINGCODE[ New Frame Code Value

7:0]
Address (hex): 41h
s)
t(
uc
Bit 1 Bit 0
od
WSSF1ONL VPS1ONLY_ VPSSLICIN VPSEXTLIN WSSSLICIN WSSEXTLINE
Y_EN EN G_EN ES
P r G_EN S
te
Bit Name
o
Function
le
WSSF1ONLY_EN
b s
VPS1ONLY_EN
Bit 5 Reserved. Must be set to 0

- O
Bit 4 Reserved. Must be set to 0
( s )
VPSSLICING_EN VPS Slicing Enable
u ct
o d
0: (VPS) data slicing is disabled
1: (VPS) data slicing is enabled
VPSEXTLINES
Pr
VPS Extended Line
et e
0: VPS data is expected only in line 16
1: VPS data is expected in lines 15, 16, 17 (not necessarily all of them)
WSSSLICING_E
o l WSS Slicing Enable
bs
N 0: (WSS) data slicing is disabled
1: (WSS) data slicing is enabled
O
WSSEXTLINES WSS Extended Line
0: WSS data is expected only in line 23
1: WSS data is expected in lines 21, 22, 23, 24 (not necessarily all of them)
89/113
Address (hex): 42h
GMVBILINE GMRELAX_ GMSLICING CCVBILINE CCRELAX_ CCSLICING_

S EN _EN S EN EN
Bit Name Function
GMVBILINES GM VBI Slicing Enable

0: Data slicing is active on line 21 in 60Hz and line 22 in 50Hz
1: Data slicing is authorised during the whole VBI
GMRELAX_EN GEM-US Relaxed Frame Check Enable

0: Relaxed frame check is disabled 1: Relaxed frame check is enabled
GMSLICING_EN GEM-US Slicing Enable

s)
0: Data slicing is disabled (Gem = Gemstar) 1: Data slicing is enabled
c t(
CCVBILINES CC VBI Slicing Enable
d u
0: Data slicing is running only during the line 21 in 60Hz and line 22 in 50Hz.
1: Data slicing is authorised during the entire VBI
r o
CCRELAX_EN CC Relaxed Frame Check Enable
e P
0: Relaxed Framecheck is disabled
t
1: Relaxed Framecheck is enabled
le
CCSLICING_EN CC Slicing Enable
0: Data slicing is disabled
s o 1: Data slicing is enabled
Ob
VBICONT7
) -
( s
Address (hex): 43h
u ct
o d
Bit 7
Pr
et e
o l
bs
Bit Name Function

O
Address (hex): 44h
SLHY[9:8]
90/113
Bit Name Function
Address (hex): 45h
Bit Name Function

s)
c t(
d u
r o
VBICONT0A Register Description
e P
Address (hex): 46h
le t
s o
Ob
) -
( s
Bit Name
u ct Function
Bits [7:0]
o d
Pr
t
VBICONT0B
e e Register Description
o l
Address (hex): 47h
b s
O Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit Name Function
91/113
Bit Name Function
VBICONT0C Register Description
Address (hex): 48h
s)
Bit Name Function
c t(
Bits[7:0] Reserved. Must be set to 0001 1011.
d u
r o
VBICONT0D Register Description
e P
Address (hex): 49h
le t
s o
ObBit 3 Bit 2 Bit 1 Bit 0
) -
( s
Bit Name
u ct Function
Bits [7:0]
o d
Reserved: Must be set to 0001 1011.
Pr
t
VBICONT0E
e e Register Description
o l
Address (hex): 4Ah
b s
O Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit Name Function
92/113
VBICONT0F Register Description
Address (hex): 4Bh
CGSEW[2:0] CGNBS[1:0] CGNBI[2:0]
Bit Name Function
CGSEW[2:0] Interval width for the shift compansation
CGNBS[1:0] Number of sample rate for a bit

"10" for 1 sample keep every 3
CGNBI[2:0] Number of Run-in Bytes before to start CCP/GEM slice states machine

s)
c t(
Address (hex): 4Ch
d u
r o
e
Bit 2
P Bit 1 Bit 0
CGESPF2 CGESPF1
t
CGVS[5:0]
le
s o
Bit Name
Ob Function
CGESPF2 Enable the two pulse spike filter
) -
s
CGESPF1 Enable the one pulse spike filter
CGVS[5:0] Number of sample for a bit

ct (
d u
VBICONT11
r o Register Description
Address (hex): 4Dh

e P
l et
o
bs
O
Bit Name Function
93/113
Address (hex): 4Eh
Bit Name Function
s)
Address (hex): 4Fh
c t(
d u
WSTH[7:0]
Bit 2
P ro Bit 1 Bit 0
e
Bit Name
oFunctionlet
WSTH[7:0] Hysteresis value for Teletext Slicer
b s
- O
VBICONT14
s )
(
Address (hex): 50h
u ct
o d
Bit 7
Pr
et e WSTH[9:8]
o l
b s
Bit Name Function
O
Bits[7:2]
WSTH[9:8]
Hysteresis value for Teletext Slicer
94/113
Address (hex): 51h
Bit Name Function
Address (hex): 52h

s)
c t( Bit 0
EQZPRGM
ODE
EQZORDER
SEL
d u
r o
e P
Bit Name Function
le t
s o
EQZPRGMODE 0: Coefficients set not programmable
1: Coefficients set programmable.
Ob
VBI_EQUALCOEFF[2:0]
) -
When set, the table of coefficients can be programmed. The selection of each coefficients is done with
( s
ct
EQZORDERSEL 0: Second order filter is used
1: First order filter is used
Bits [4:0]
d u
r o
VBICONT17
e P Register Description
l
Address (hex): 53het
s o
O b Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
VBI_EQUALCOEFF[2:0]
95/113
Bit Name Function
VBI_EQUALCOE These bits select precomputed coefficients for the equaliser or let the equaliser select automatically the
FF[2:0] best set of coefficients or impose to the equaliser the sets of coefficients programmed
000: use set 1 of coefficients
010: use set 3 of coefficients (central or no equaliser)
100: equaliser in automatic mode
101: use set 5 of ceofficients
110: use programmed registers (see registers VBICONT0D and VBICONT0E) for the equaliser coefficients.
Address (hex): 54h

s)
t(
uc
o d
P r
Bit Name Function
e
o let
b s
Bit 5
Bit 4

- O
Bits [3:0]
(
s )
u ct
5.4 Acknowledge Registers
o d
Pr
The acknowledge registers are used to acknowledge the interruption source. When ACK = 1, the
et e
I²C master acknowledges the corresponding interrupt.
o l
Warning : These 2 registers can be written by the I2C but can't be read. Each bit is reset by the I2C
slave (stv2310) one clock period after an high level has been detected.
b s
O DDECCONTFE Register Description
Address (hex): 7Eh - Write Only
INTERDET_ VCRDET_A INSERDET_ FBDET_AC PLLLOCK_A VLOCK_AC HLOCK_AC TVSTDID_AC

ACK CK ACK K CK K K K
96/113
Bit Name Function
INTERDET_ACK Acknowledge for interrupt on INTERLACED_DETECTED status change
VCRDET_ACK Acknowledge for interrupt on VCR_DETECTED status change
INSERDET_ACK Acknowledge for interrupt on INSER_DETECTED status change
FBDET_ACK Acknowledge for interrupt on FB_DETECTED status change
PLLLOCK_ACK Acknowledge for interrupt on PLLLOCK status change
VLOCK_ACK Acknowledge for interrupt on VLOCK status change
HLOCK_ACK Acknowledge for interrupt on HLOCK status change
TVSTDID_ACK Acknowledge for interrupt on TVSTDID status change
DDECCONTFF Register Description
Address (hex): 7Eh - Write Only
s)
t(
uc
od
VSYNCNST TRICKDET_A
r
D_ACK CK
e P
Bit Name Function
le t
Bits[7:3] Reserved.
s o
Bit 2 Reserved
Ob
VSYNCNSTD_AC
K -
Acknowledge for interrupt on VSYNCLOCK_NOSTD status change
)
( s
ct
TRICKDET_ACK Acknowledge for interrupt on TRICKMODE_DETECTED status change
d u
5.5 Status Registers
r o
e P
l et
DDECSTAT1 Register Description
o
Address (hex): 80h - Read Only
s
O b
STVDDECVERS[7:0]
Bit Name Function
STVDDECVERS This block is hardwired in every STV2310 cut.

[7:0] [7:4]: for Full Layer cuts (0001 is Cut 1.0, 0010 is Cut 2.0)
[3:0]: for Metal Fix cuts
97/113
Reset Value (bin): Undefined
VLOCK HLOCK PLLLOCK 5060ID TVSTDID TVSTD[2:0]
Bit Name Function
VLOCK Flag used to signal Vertical Synchronization Signal Capture

0: Vsync is not captured 1: Vsync is captured
HLOCK Flag used to signal Horizontal PLL (detection) lock status

0: HPLL is out of lock 1: HPLL is in lock
PLLLOCK Flag used to signal Output PLL (line-locked) status

0: Output PLL is out of lock 1: Output PLL is in lock
s)
5060ID Flag used to signal detection of either 50 Hz or 60 Hz signal
0: 60 Hz signal is detected. 1: 50 Hz signal is detected.
c t(
TVSTDID Flag used to signal that standard is identified
d u
0: Standard is not identified. 1: Standard is identified.
r o
TVSTD[2:0] Identification (code) of Identified Standard
e P
See the AUTOSTD[5:0] bits in the DDECCONT1 register.
le t
s o
Ob
) -
( s
Bit 7 Bit 6 Bit 5
u ct Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
VSYNCLOC BLANKLVL_
o d
INTERLACE DVD_DETE VCR_DETE INSER_DET FB_DETEC TRICKMOD_
_NSTD
ECTED
Pr
SHIFT_DET D_DETECT
ED
CTED CTED ECTED TED DETECTED
et e
Bit Name
o l Function
b s
VSYNCLOC_ The synchronisation block normally detects the input video parity by detecting the Vsync position with
O
NSTD respect to the Hsync. The Vsync position is normally at the beginning of line (0%) or middle of line (50%).
The built-in thresholds for Vsync position are 25% and 75%. When the Vysnc is actually close to these
limits, a bad parity detection may take place. This is the reason for this status bit.
When set, the Vsync is positioned between 20% - 30% OR 70%-80% of input video line.
BLANKLVL_SHIF When set, this bit indicates that the input video blank level is shifted during the VBI. This detection only
T_DETECTED takes place when the shift is above a determined threshold and there is a low level of noise.
INTERLACED_ When set, this bit indicates that the input video is interlaced. When reset the input video is non interlaced.
DETECTED This bit can potentially change value at each input video field
DVD_DETECTED When set, this bit indicates that a DVD has been detected on the input.
VCR_DETECTED When set, this bit indicates that a VCR has been detected on the input.
98/113
Bit Name Function
INSER_ When set, this bit indicates that a transition on the FB signal has been detected inside an active line at least
DETECTED once in the field. This flag remains set for the next field.
FB_DETECTED When set, this bit indicates that the FB signal has been detected to 1 (level detection) at least once in the
field. This flag remains set for the next field.
TRICKMOD_ This status bit purpose is to detect special VCR playback modes where the number of lines is non standard.
DETECTED (note that it is not limited to VCR inputs).
The standard number of lines depend on the 50Hz/60Hz detection:
When in 50Hz mode, the number of lines is standard when >= 310 and <= 314
When in 60Hz mode, the number of lines is standard when >= 260 and <= 264
When this bit is set, the number of lines is non-standard.

s)
t(
uc
NOISELVL[7:0]
o d
P r
Bit Name Function
e
NOISELVL[7:0] Noise level computed by sync and monitoring block
o let
b s
- O
( s )
ct
du
r o SLDID[7:0]
e P
Bit Name
l et Function
o
bs
SLDID[7:0] Replica (read only) of bits SLDID[5:0] in register VBICONT1 with parity and checksum
O DDECSTAT6 Register Description
SLFIL[7:0]
99/113
Bit Name Function
SLFIL[7:0] Reserved.
GEM_DETE CC_DETEC VPS_DETE WST_DETE WSS_DETE OPENLOOP

CTED TED CTED CTED CTED
Bit Name Function
)
Bit 7 Reserved.
Bit 6 Reserved.
t( s
GEM_DETECTE
D
Detection of gemstar ancillary data
u c
o d
CC_DETECTED
VPS_DETECTED
Detection of close caption ancillary data
Detection of VPS ancillary data

P r
WST_DETECTE Detection of WST ancillary data
te
D
o le
WSS_DETECTE
D
Detection of WSS ancillary data
b s
OPENLOOP
O
This flag indicates that the output PLL uses phase jumps for phase error correction.
-
0: Phase jump inactive
1: Phase jump active
( s )
u ct
o d
Pr
et e
o l
b s
O
100/113
STV2310 Electrical Characteristics
6 Electrical Characteristics
6.1 Absolute Maximum Ratings
Symbol Parameter Min. Typ. Max. Unit
V3.3V 3.3 V Supply Voltage 3.8 V
V1.8V 1.8 V Supply Voltage 2.2 V
VESD Capacitor 100 pF discharged via 1.5 kΩ serial resistance ±4 kV

(Human Body Model)
TOPER Operating Temperature 0 +70 °C
TSTG Storage Temperature −55 +150 °C
6.2 Thermal Data

s)
t(
Symbol Parameter Min. Typ.
uc
Max. Unit
RthJA Junction-ambient Thermal Resistance (TQFP64, 14x14x1.4mm)

two layer PCB, one copper ground layer
r od
50 °C/W
RthJA Junction-ambient Thermal Resistance (TQFP64, 10x10x1.4mm)

e P 60 °C/W
two layer PCB, one copper ground layer
le t
s o
6.3 Operating Conditions
Ob
Symbol Parameter
) - Min. Typ. Max Unit
( s
ct
V1.8V 1.8 V Supply Voltage 1.6 1.8 2.0 V
du
V3.3V 3.3 V Supply Voltage 3.0 3.3 3.6 V
fMC
r o
Master Clock Frequency 27 MHz
ICC1.8V
e P
1.8V Supply Current 235 mA
ICC3.3V
l et
3.3V Supply Current 40 mA
o
sCVBS/Y/C Analog Inputs
6.4
O b TAMB = 25 °C, VCC33 = 3.3 V, VCC18 = 1.8 V
Symbol Parameter Min. Typ. Max Unit
VIN_CVBS/Y Y/CVBS Sync to Peak Chroma Input Voltage (Anti-Aliasing Filter .74 1.24 2.08 VPP
with Attenuation = 0.75, Standard Color bar 100%); AGC active
AGC AGC Range on Y/CVBS inputs ±6 dB
G_Step AGC Step 0.19 dB
101/113
Electrical Characteristics STV2310
VIN_Chroma C Full Scale Input Voltage (before external Anti-Aliasing Filter 0.6 0.88 1.25 VPP
with Attenuation = 0.55)
CIN_CVBS Input Coupling Capacitor for CVBS 22 nF
CIN_C Input Coupling Capacitor for C 1 nF
BWCVBS Input Bandwidth Analog Input 6 MHz
CLCVBS CVBS/Y Input Black Clamping Level 1.0 V
CBIAS C Input Bias Level 560 mV
ISOURCE Positive Clamp Current (CVBS/Y) +200 +400 µA
ISINK Negative Clamp Current (CVBS/Y) -400 -200 µA
I_Step I Step Clamp ±5 µA
ZIN C Input Impedance 10 kOhm
Crosstalk Channel Crosstalk 50

s) dB
c t(
6.5 R/G/B and Cr/Cb Inputs
d u
r o
Symbol Parameter Min.
e P Typ. Max Unit
VIN_RGB R/G/B Full Scale Input Voltage (before external Anti-Aliasing

Filter with Attenuation = 0.65)
le t
0.5 0.7 1.0 VPP
CLRGB R/G/B Input Clamp Level

s o 1.0 V
CIN_RGB Input Coupling Capacitor

Ob 22 nF
BWRGB_L Channel Bandwidth on Luma Component

) - 6 MHz
BWRGB_Chr
( s
Channel Bandwidth on CrCb Component 3 MHz
VIN_CrCb
u ct
Cr/Cb Full Scale Input Voltage (before external Anti-Aliasing 0.5 0.7 1.0 VPP
d
Filter with Attenuation = 0.65)
o
CLCrCb
ISOURCE Pr
Cr/Cb Clamp Level
Positive Clamp Current (RGB) +200

1.3
+400
V
µA
ISINK
et e
Negative Clamp Current (RGB) -400 -200 µA
o l
b s
Crosstalk
I Step Clamp
Crosstalk between Analog Inputs

±5
50
µA
dB
102/113
6.6 FB Input
VIL FB Input Voltage Low Level 0.4 V
VIH FB Input Voltage High Level 1.0 V
IL FB Input Leakage Current 1 µA
6.7 Analog-to-Digital Converter (ADC)
10-bit ADC for CVBS Input
B Analog Bandwidth 15 MHz
fCLK ADC Clock Frequency 27
s) MHz
ED Differential Linearity Error (DLE) 1
c t( LSB
EL Integral Linearity Error (ILE) 2
d u LSB
8-bit ADCs for RGB/C Inputs
r o
B Analog Bandwidth
e P 15 MHz
fCLK
ED
ADC Clock Frequency
Differential Linearity Error (DLE)

le t 27
1
MHz
LSB
s o
EL
Gmatch
Integral Linearity Error (ILE)
RGB Gain Matching

Ob 2
0.5 1.5
LSB
) -
( s
6.8 Analog Reference Levels
u ct
Symbol
o d Parameter Min. Typ. Max Unit
REFP_CVBS
Pr
REFP_CVBS Pin Level 750 mV
Videocomm
t e
Videocomm Pin Level
e
1.2 V
REFP_RGB
o l
REFP_RGB Pin Level 750 mV
bs
REFM_RGB REFM_RGB Pin Level 375 mV
O
6.9 YCrCb, Hsync, Vsync, Field and PLL Lock Outputs
VOL Low Level Output Voltage (IOUT = 2 mA) 0.4 V
VOH High Level Output Voltage (IOUT = 2 mA) 2.4 V
tr Rise Time 3 ns
103/113
tf Fall Time 3 ns
Maximum Capacitive Load 30 pf
6.10 Clock Data Output
VOL Low Level Output Voltage (IOUT = 4 mA) 0.4 V
VOH High Level Output Voltage (IOUT = 4 mA) 2.4 V
tr Rise Time 3 ns
tf Fall Time 3 ns
Maximum Capacitive Load 30 pf
s)
6.11 CLKSEL, TST_MODE, NRESET and I2CADD Inputs
c t(
d u
Symbol Parameter Min.
r o
Typ. Max Unit
CLKSEL Input
e P
VIL CLKSEL Input Voltage Low Level
le t 0.6 V
so
VIH CLKSEL Input Voltage High Level 1.2 V
IL CLKSEL Input Leakage Current
Ob 1 µA
TST_MODE, NRESET and I2CADD Inputs

-
(t s)
VIL Input Low Level 0.8 V
uc
VIH Input High Level 2.0 V
od
IL Input Leakage Current -1.0 1.0 µA
Pr
et e
6.12 Main Clock Characteristics
o l
b s
Differential Clock Input (CLKXTM, CLKXTP)
O
FS Nominal Frequency 27 MHz
FS_TOL Tolerance (including Temp. shift) ±50 ppm
Duty_cycle Clock Duty Cycle 45 50 %
VIL Input Voltage Low Level 0.6
VIH Input Voltage High Level 1.2
IL Input Leakage Current 1 µA
External Crystal Characteristics
104/113
fXTAL Crystal Frequency, Fundamental Mode 27 MHz
RBIAS Internal Bias Resistance 1.5 MΩ
Tolerance (including Temp. shift) ±60 ppm
s)
c t(
d u
r o
e P
le t
s o
Ob
) -
( s
u ct
o d
Pr
et e
o l
b s
O
105/113
6.13 Horizontal/Vertical Synchronization Block
Output Luma/Sync Misalignment ±2.5 ns
Output Chroma/Sync Misalignment ±20 ns
Line PLL Capture Range ±8 %
6.14 Chroma Block
ACC Control Range -6 +30 dB
Chroma PLL Capture Range 0.8 1 kHz
Total Chroma Phase Tracking Error ±0.5 ±1 deg.
Quadrature Error ±0.5 ±1

s) deg.
t(
uc
Hue Control Range ±40 deg
od
Hue Control Step 1.5 deg.
6.15 I²C Bus Characteristics P r

te
le
so
Symbol Parameter Test Conditions Min. Typ Max. Unit
SCL
Ob
VIL Low Level Input Voltage
- -0.3 1.5 V
(s)
VIH High Level Input Voltage 2.3 5.5 V
IIL Input Leakage Current
u ct VIN = 0 to 5.0 V -10 10 µA
fSCL Clock Frequency
o d 400 kHz
tR
Pr
Input Rise Time 1 V to 2 V 300 ns
tF
et e
Input Fall Time 2 V to 1 V 300 ns
CI
o lInput Capacitance 10 pF
SDA
b
VIL
s Low Level Input Voltage -0.3 1.5 V
O
VIH High Level Input Voltage 2.3 5.5 V
IIL Input Leakage Current VIN = 0 to 5.0 V -10 10 µA
tR Input Rise Time 1 V to 2 V 300 ns
tF Input Fall Time 2 V to 1 V 300 ns
VOL Low Level Output Voltage IOL = 3 mA 0.4 V
tF Output Fall Time 2 V to 1 V 250 ns
106/113
Symbol Parameter Test Conditions Min. Typ Max. Unit
CL Load Capacitance 400 pF
CI Input Capacitance 10 pF
I²C Timing
tLOW Clock Low period 1.3 µs
tHIGH Clock High period 0.6 µs
tSU,DAT Data Set-up Time 100 ns
tHD,DAT Data Hold Time 0 900 ns
tSU,STO Set-up Time from Clock High 0.6 µs

to Stop
tBUF Start Set-up Time following a 1.3 µs

Stop
tHD,STA Start Hold Time 0.6
s) µs
tSU,STA Start Set-up Time following

Clock Low to High Transition
0.6
c t( µs
d u
Figure 19: I²C Bus Timing
r o
e P
SDA
le t
tBUF
s o
tLOW
Ob tSU,DAT
SCL
) -
( s
tHD,STA
u ct tR tHD,DAT tHIGH tF tSU,STO
o d
SDA
Pr tSU,STA
et e
Note:
o l
The STV2310 device can be interfaced with +3.3 V or +5.0 V logic levels.
b s
O
107/113
Package Mechanical Data STV2310
7 Package Mechanical Data
7.1 TQFP64 14x14 Package
Figure 20: TQFP64 14x14 Package
s)
c t(
Figure 21: 64-Pin Thin Quad Flat Package
d u
r o
e P
Millimeters Inches
0.10mm
.004
seating plane
Dim.
A
le t
Min. Typ. Max.
1.60
Min. Typ. Max.
0.063
s o
A1 0.05 0.15 0.002 0.006
Ob A2
B
1.35 1.40 1.45 0.053 0.055
0.30 0.37 0.45 0.012 0.015
0.057
0.018
) - C 0.09 0.20 0.004 0.008
( s D 16.00 0.630
ct
D1 14.00 0.551
d u D3
E
12.00
16.00
0.472
0.630
r o E1 14.00 0.551
e P E3
e
12.00
0.80
0.472
0.031
l et K 0° 3.5° 7°
s o L1
L
L
L1
0.45 0.60 0.75 0.018 0.024
1.00 0.039
0.030
O b K N 64
Number of Pins
ND 16 NE 16
108/113
STV2310 Package Mechanical Data
7.2 TQFP64 10x10 Package
Figure 22: TQFP64 10x10 Package
Figure 23: 64-Pin Thin Quad Flat Package
s)
c t(
0.10mm
.004 Dim.
Millimeters
d u Inches
Min. Typ.
oMax. Min. Typ. Max.
seating plane
A
A1 0.05
P r 1.60
0.15 0.002
0.063
0.006
A2
t
1.35
e 1.40 1.45 0.053 0.055 0.057
le
b 0.17 0.22 0.27 0.007 0.009 0.011
C
s
D o 0.09
12.00
0.20 0.004
0.472
0.008
Ob D1
E
10.00
12.00
0.394
0.472
) - E1 10.00 0.394
( s e 0.50 0.020
ct
K 0° 3.5° 7° 0° 3.5° 7°
L 0.45 0.60 0.75 0.018 0.024 0.030
d u L1 1.00 0.039
r o L1
L
N
Number of Pins
64 ND 16 NE 16
e P
l et K
o
sLead-free Packaging
7.3
O b To meet environmental requirements, ST offers these devices in ECOPACK® packages. These
packages have a lead-free second level interconnect. The category of second level interconnect is
marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
109/113
Revision History STV2310
8 Revision History
The following table summarizes the modifications applied to this document.
Revision Description Date
1.0 First Issue N/A
1.1 Addition of Section 5.3: VBI Control Register Descriptions on page 87. March 2001
1.2 Addition of Chapter 7: Package Mechanical Data on page 108. March 2001
1.3 Addition of Section 4.5: Standard Research Sequence Programming on 9 May 2001
page 21, Section 4.9: Output Scaler and Format Converter on page 25,
Section 4.3: Input Sample Rate Conversion on page 18 and Section
6: Electrical Characteristics on page 101
1.4 Update of all register descriptions, general descriptions and programming information. Pin June 2001
description section reformatted. Addition of Anti-Aliasing Filter Diagrams.
s)
t(
1.5 Update of all register descriptions, general descriptions and programming information. July 2001
Update of Figure 9 and Analog Input Stage programming data.

uc
1.6 July 2001
1.7 Reset values corrected in Register Descriptions and register DDECCONT35 updated
r
with Cut 2 information. Section 6: Electrical Characteristics on page 101 updated. od November 2001
format.
e P
Figure 35 updated. Moved to Datasheet template 2.1 and converted from single file to book
1.8
le t
Updated Figure 18 on page 31 and Figure 3 on page 8, Zoom in/out function
o
characteristics clarified. Addition of ESD PERFORMANCES on page 80.
s
1.9
DDECCONTE modified.
Ob
SECAM filter is removed. Registers DDECCONT2A, DDECCONT17 and 12 February 2002
-
(s)
2.0 Update of Section 6: Electrical Characteristics on page 101. 25 March 2002
ct
2.1 ESD Section removed. 10 July 2002
du
2.2 Pin NRESET changed to NRESET. Updated register information for cut 3.0. 21 Nov 2002
2.3
r o
Updated Figure 3 on page 8 and Figure 6 on page 15.
2.4
e P
Updated Figure 3 on page 8 and Figure 4 on page 9. Update to VCC33OUT in
Section 2.2: Pin Descriptions. Update of Figure 6 on page 15. Ouput Sync Pulse
20 January 2003
et
information added to Section 4.2: Synchronization and Monitoring Unit on
l
s o page 16. Update of Section 4.4: Luminance and Chrominance Separation on
page 19. Update of Table 8: Confirmation Codes on page 22. New section added:
O b Section 4.6: Standard Identification on page 23. Update of Section

4.7: Chroma Demodulation on page 23. Update of Section 4.8: Soft Mixer on
page 24.Update of Section 4.12: Output FIFO and Line-locked Ouput Pixel
Clock Generator on page 29. GDIFF added to Section 6.7: Analog-to-Digital
Converter (ADC) on page 103. Updated Figure 35 and Figure 36.
3.0 Re-organisation and update of page 1 and page 2. Modification of text in Section 1: General July 2004
Description on page 6. Updated Figure 2 on page 7, Figure 3 on page 8 and Figure 4 on
page 9. Modification of pin descriptions in Section 2: Pin Allocation and Description on page
9. Addition of Section 3: Default Setup At Reset on page 13. Major updates to Chapter 5:
Register List on page 80. Major change to Figure 6 on page 15. Various modifications to
Chapter 6: Electrical Characteristics on page 134. Addition of TQFP64 10x10 package in
Chapter 8: Package Mechanical Data on page 143.
110/113
STV2310 Revision History
Revision Description Date
3.1 Minor updates to Register Description December 2004
4.0 Section 7.3 added, disclaimer updated. Technical content unaffected. 07-Nov-2008
s)
c t(
d u
r o
e P
le t
s o
Ob
) -
( s
u ct
o d
Pr
et e
o l
b s
O
111/113
STV2310
Index
A I
A/D Converter ................................................ 6, 15 I²C Bus Interface .................................................. 1
Adaptive Time Constant .................................... 16 Input Sample Rate Converter ............................ 18
Alpha Blending .................................................. 24
Anti-Aliasing Filter .............................................. 15 M
Automatic Flesh Control .................................... 23
Automatic Gain Control ...................................... 14 Mixing Slope ...................................................... 24
C O
CCIR Specification ................................... 6, 25, 42 Output Pixel Clock Frequency ........................... 41
Chroma Demodulator .................................. 21, 23 Output Sample Rate Converter ......................... 25
Clocks
Pixel ............................................................... 7 P
s)
System ..................................................... 6, 18
Clocks System ................................................... 16 c t(
Color Kill Control ................................................ 67
d u
Panorama Mode ................................................ 27
Programmable Gain Amplifier ............................ 14
So
Comb Filter .......................................................... 1
F P r
te
Skew Extraction ................................................. 16
Fast Blanking ..................................................... 24
Filtering le
Soft Mixer ........................................................... 24
o
Comb ........................................................... 19
b s
Square Pixel Mode ............................................ 27
Standard Identifier ............................................. 21
Notch ........................................................... 19
Flesh Tone Correction ....................................... 23
- O Synchronization Slicer ....................................... 16
(s)
Flesh Tone Reference Angle ............................. 68 T
Free-running Mode ............................................ 16
c t Tint Angle Correction ......................................... 29

G
d u Tint Control ........................................................ 29
r o
Green Enhancement ......................................... 69 V
P
eH
l et VBI Data Slicer .................................................. 42
Vertical Blanking Interval ................................... 30
s o
Horizontal PLL ................................................... 16
Hue Control ....................................................... 23
Vertical Sync Processor ..................................... 16
b
Hue Levels ......................................................... 29
O
XYZ
Zoom-In Mode ................................................... 27
Zoom-Out Mode ................................................. 27
112/113
STV2310
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
s)
All ST products are sold pursuant to ST’s terms and conditions of sale.
c t(
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
d u
o
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
P r
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
te
o le
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
b s
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
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DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
o
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
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et e ST and the ST logo are trademarks or registered trademarks of ST in various countries.
o l Information in this document supersedes and replaces all information previously supplied.
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® STV2310

Multistandard TV digital video decoder

■ Copy-Protection System compatible

November 2008 Rev 4 1/113

Clock Synchronizatio HSYNC

Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Chapter 2 Pin Allocation and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Chapter 3 Default Setup At Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Chapter 4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4.9 Output Scaler and Format Converter ................................................................................. 25

4.10 RGB Insertion ..................................................................................................................... 28

4.11 Analog YCrCb Mode .......................................................................................................... 29

4.11.1 General Description ............................................................................................................................. 29

4.13 VBI Data Slicing and Insertion ............................................................................................42

4.14 I²C Bus Specifications ........................................................................................................53

Chapter 5 Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

o lAnalog-to-Digital Converter (ADC) ..................................................................................103

Chapter 7 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

Chapter 8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

to the TV processor STV3550 for LCD-TVs.

Figure 2: Architectural Block Diagram

Figure 3: Application Block Diagram

1.8 VANA 1.8 VANA

r o Synchronization and Monitoring 33 HSYNC

o l 13 NRESET Digital Core 32 PLLLOCK

2 Pin Allocation and Description

2.1 Pinout Diagram

b s Table 1: Power Supply Pins (page 1 of 2)

O Pin Pin Name Pin Description

1 VCC18_CVBS 1.8 V Analog Voltage Supply for Analog Input Stage

37 GND_SUB Analog Ground Supply (Substrate Polarization)

39 VCC18_CLK 1.8 V Analog Voltage Supply for Clock Generator

Table 1: Power Supply Pins (page 2 of 2)

Pin Pin Name Pin Description

40 GND_CLK Analog Ground Supply for Clock Generator

49 VCC18_RGB 1.8 V Analog Voltage Supply (RGB)

50 GND_RGB Analog Ground Supply (RGB)

54 VCC18_DIG 1.8 V Analog Voltage Supply (Analog Input Stage)

55 GND_DIG Analog Ground Supply (Analog Input Stage)

56 GND_IO Analog Ground Supply (Analog Input Stage)

57 VCC33_IO 3.3 V Analog Voltage Supply (Analog Input Stage)

64 GND_CVBS Analog Ground Supply (Analog Input Stage)

4 VDD18_CORE 1.8 V Digital Voltage Supply (Digital Core)

3.3 V I/O Voltage Supply (Digital Core)

Pr Digital Ground Supply (Output Stage)

et e Table 2: Analog Pins (page 1 of 2)

Chroma Input (Y/C inputs used for S-Video) (Selected by programming)

47 REFP_RGB Positive Reference Voltage for RGB ADCs

48 REFM_RGB Negative Reference Voltage for RGB ADCs

52 G G Input for RGB Insertion.

Table 2: Analog Pins (page 2 of 2)

Pin Pin Name Pin Description

58 ADCIN CVBS ADC Input (To be connected to Anti-Aliasing Filter output)

59 VIDEOCOMM CVBS Anti-Aliasing Filter Reference Voltage

60 VIDEO_OUT Video Analog Front-end Multiplexer Output for external filtering

61 REFP_CVBS Positive Reference Voltage for CVBS and Chroma ADCs

62 REFM_CVBS Ground CVBS and Chroma ADCs

63 CVBS1_Y CVBS or Y Input 1 (Selected by programming)

Table 3: Output Pins