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    Vlsi Design Bec 401

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    Vlsi Design Bec 401

    Uploaded by

    akshayjaiswal273306
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    VLSI DESIGN BEC 401

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    5 views11 pages

    Vlsi Design Bec 401

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    akshayjaiswal273306

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    © All Rights Reserved
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    of 11

    VLSI DESIGN

    COURSE CODE: BEC-401


    FACULTY – KULDIP KANNAUJIYA
    BEC-401 B
    Contact hours/week : Lecture: 3, Tutorial: 1, Practical: 2
    Number of Credits : 5
    Course Assessment methods : Continuous assessment through
    tutorials, attendance, assignments, quizzes, practical work, record,
    viva voce, minor and major theory & practical Examination.
    Course Objectives : The objective of this course is to impart the
    knowledge on fundamentals of CMOS VLSI, associated technologies,
    their circuit level models with principles of operation, design of the
    fundamental blocks of VLSI circuits, and further to develop hands-on
    skills of using CAD tools in VLSI design.
    Course Outcomes : The students are expected to be able to demonstrate the
    following knowledge, skills and attitudes after completing this course.
    1. Able to understand the fundamentals of CMOS VLSI and associated technologies.
    2. Able to solve problems in the design of CMOS logic circuits, with particular
    reference to speed and power consumption.
    3. Able to acquire hands-on skills of using CAD tools in VLSI design.
    4. Able to appreciate the design process in VLSI through a mini-project on the
    design of a CMOS sub-system.
    5. Able to explain basic operation principles of diodes and MOS transistors and their
    circuits level models.
    6. Able to design the fundamental blocks of a VLSI circuits, both by circuit schematic
    and physical layout with performance.
    Topics Covered
    UNIT-I
    Introduction: Trends & Projections in VLSI Circuits, Flow
    diagram of VLSI Circuit Design, VLSI Design issues, Y-Chart,
    VLSI Design Styles, Full Custom and Semi Custom VLSI Design
    Electrical characterization of MOS transistor: Energy-band
    explanation for MOS structure, MOS Capacitors, C-V
    characteristics of MOS Capacitor, Long Channel and Short
    Channel MOSFETs, Short-Channel effects, SPICE parameters of
    MOS transistor.
    UNIT-II
    MOS Inverter Design: NMOS and CMOS inverter design, noise
    margin, VTC curve, Calculation of delay time, switching power
    dissipation in CMOS inverters, scaling in CMOS circuits,
    technology scaling and its impact on the inverter metrics,
    Super Buffer Design
    UNIT-III
    Stick Diagrams: Physical Design Rules; Layout Designing;
    Euler’s Rule for VLSI Physical Design, MOS logic circuits with
    depletion nMOS loads, CMOS logic circuits, complex logic
    circuits, Complementary CMOS, Ratioed Logic, CMOS Pass-
    Transistor Logic
    UNIT-IV
    Dynamic CMOS circuits: Basic Principles of pass transistor
    and transmission gate, CMOS Transmission-Gate and Pass-
    transistor logic circuits, Domino CMOS Logic, NORA CMOS
    Logic,Zipper CMOS circuits, Basic Bi-CMOS behaviour
    LIST OF EXPERIMENTS
    A) Compulsory Experiments:
    1. To design a CMOS inverter and perform the DC and transient
    analysis.
    2. To design a CMOS inverter [Wp/Lp:Wn/Ln = 3:1] and analyze the
    effect of following parameters on average power:
    i. VDD (Supply voltage)
    ii. CL (Output load capacitance)
    iii. Frequency
    3.To design XOR gate using transmission gate and perform its transient
    analysis.
    4. To design a 2:1 Multiplexer and analyze its transient analysis.
    5. Design the layout of XOR circuit using CMOS technology.
    6. To design CMOS based NAND gate and perform its transient analysis.
    7. To design CMOS based NOR gate and perform its transient analysis.
    8. To design XNOR gate using transmission gate and perform its
    transient analysis.
    9. Design the layout of CMOS inverter using CMOS technology.
    B) Optional Experiments
    1.Write a Verilog HDL code to design 4 to 2 Encoder and simulate on
    Questa simulator using Verilog test bench.
    2. Write a Verilog HDL code to design 4 to 2 Decoder and simulate on
    Questa simulator using Verilog test bench.
    3. Write a Verilog HDL code for binary to Gray Code Conversion and
    simulate on Questa simulator using Verilog test bench.
    4. Write a Verilog HDL code for 4-bit SIPO register and simulate on
    Questa simulator using Verilog test bench
    Text and Reference Books
    1. S.M. Kang & Y. Leblibici, “CMOS Digital Integrated Circuits-Analysis &
    Design”, TMH, 2nd Ed. 2003.
    2. B.G. Streetman & S. Banerjee, “Solid State Electronic Devices”, Pearson
    Education.
    3. Neil H. Weste& David Harris, “CMOS VLSI Design: A Circuit and
    Systems Perspective”, PHI.
    4. J.M. Rabaey, A. Chandrakasan& B. Nikolic “Digital Integrated Circuits-
    A Design Perspective”, Pearson.
    5. DoughlasPucknell& Kamran Eshragian, “Basic VLSI Design”, PHI.

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