Adxl350bcez RL7

3-Axis, ±1g/±2g/±4g/±8g
Digital Accelerometer
Data Sheet ADXL350
FEATURES GENERAL DESCRIPTION
Excellent zero-g bias accuracy and stability with The high performance ADXL350 is a small, thin, low power,
minimum/maximum specifications 3-axis accelerometer with high resolution (13-bit) and selectable
Ultralow power: as low as 45 μA in measurement mode and measurement ranges up to ±8 g. The ADXL350 offers industry-
0.1 μA in standby mode at VS = 2.5 V (typical) leading noise and temperature performance for application
Power consumption scales automatically with bandwidth robustness with minimal calibration. Digital output data is
User-selectable resolution formatted as 16-bit twos complement and is accessible through
Fixed 10-bit resolution either a SPI (3- or 4-wire) or I2C digital interface.
Full resolution, where resolution increases with g range,
The ADXL350 is well suited for high performance portable
up to 13-bit resolution at ±8 g (maintains 2 mg/LSB scale
applications. It measures the static acceleration of gravity in tilt-
factor in all g ranges)
sensing applications, as well as dynamic acceleration resulting
Embedded, 32-level FIFO buffer minimizes host processor
from motion or shock. Its high resolution (2 mg/LSB) enables
load
measurement of inclination changes of less than 1.0°.
Tap/double tap detection and free-fall detection
Activity/inactivity monitoring Several special sensing functions are provided. Activity and
Supply voltage range: 2.0 V to 3.6 V inactivity sensing detect the presence or lack of motion and if
I/O voltage range: 1.7 V to VS the acceleration on any axis exceeds a user-set level. Tap sensing
SPI (3- and 4-wire) and I2C digital interfaces detects single and double taps. Free-fall sensing detects if the
Flexible interrupt modes mappable to either interrupt pin device is falling. These functions can be mapped to one of two
Measurement ranges selectable via serial command interrupt output pins.
Bandwidth selectable via serial command Low power modes enable intelligent motion-based power
Wide temperature range (−40°C to +85°C) management with threshold sensing and active acceleration
10,000 g shock survival measurement at extremely low power dissipation.
Pb-free/RoHS compliant
The ADXL350 is supplied in a small, thin, 3 mm × 4 mm ×
Small and thin: 4 mm × 3 mm × 1.2 mm cavity LGA package
1.2 mm, 16-lead cavity laminate package.
APPLICATIONS
Portable consumer devices
High performance medical and industrial applications
FUNCTIONAL BLOCK DIAGRAM

VS VDD I/O
ADXL350 POWER
MANAGEMENT
CONTROL INT1
SENSE ADC AND
ELECTRONICS DIGITAL INTERRUPT
3-AXIS FILTER LOGIC INT2
SENSOR
SDA/SDI/SDIO
32 LEVEL SERIAL I/O
FIFO SDO/ALT
ADDRESS
SCL/SCLK
10271-001
GND CS
Figure 1.
Rev. 0 Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADXL350 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Interrupts ..................................................................................... 21
Applications ....................................................................................... 1 FIFO ............................................................................................. 21
General Description ......................................................................... 1 Self-Test ....................................................................................... 22
Functional Block Diagram .............................................................. 1 Register Map ................................................................................... 23
Revision History ............................................................................... 2 Register Definitions ................................................................... 24
Specifications..................................................................................... 3 Applications Information .............................................................. 28
Absolute Maximum Ratings ............................................................ 4 Power Supply Decoupling ......................................................... 28
Thermal Resistance ...................................................................... 4 Mechanical Considerations for Mounting .............................. 28
Package Information .................................................................... 4 Tap Detection .............................................................................. 28
ESD Caution .................................................................................. 4 Threshold .................................................................................... 29
Pin Configuration and Function Descriptions ............................. 5 Link Mode ................................................................................... 29
Typical Performance Characteristics ............................................. 6 Sleep Mode vs. Low Power Mode............................................. 29
Theory of Operation ...................................................................... 14 Offset Calibration ....................................................................... 29
Power Sequencing ...................................................................... 14 Using Self-Test ............................................................................ 30
Power Savings.............................................................................. 15 Axes of Acceleration Sensitivity ............................................... 32
Serial Communications ................................................................. 16 Layout and Design Recommendations ................................... 33
SPI ................................................................................................. 16 Outline Dimensions ....................................................................... 34
I2C ................................................................................................. 19 Ordering Guide .......................................................................... 34
REVISION HISTORY
9/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
Data Sheet ADXL350
SPECIFICATIONS
TA = 25°C, VS = 2.5 V, VDD I/O = 2.5 V, acceleration = 0 g, and CIO = 0.1 μF, unless otherwise noted. All minimum and maximum
specifications are guaranteed. Typical specifications are not guaranteed.
Table 1.
Parameter Test Conditions Min Typ Max Unit
SENSOR INPUT Each axis
Measurement Range User selectable ±1, ±2, ±4, ±8 g
Nonlinearity Percentage of full scale ±0.5 %
Inter-Axis Alignment Error ±0.1 Degrees
Cross-Axis Sensitivity 1 ±3 %
OUTPUT RESOLUTION Each axis
All g Ranges 10-bit resolution 10 Bits
±1 g Range Full resolution 10 Bits
SENSITIVITY Each axis
Sensitivity at XOUT, YOUT, ZOUT Any g-range, full resolution 473.6 512 550.4 LSB/g
Scale Factor at XOUT, YOUT, ZOUT Any g-range, full resolution 1.80 1.95 2.10 mg/LSB
Sensitivity at XOUT, YOUT, ZOUT ±1 g, 10-bit resolution 473.6 512 550.4 LSB/g
Scale Factor at XOUT, YOUT, ZOUT ±1 g, 10-bit resolution 1.80 1.95 2.10 mg/LSB
Sensitivity Change Due to Temperature ±0.01 %/°C
0 g BIAS LEVEL Each axis
0 g Output for XOUT, YOUT −150 ±50 +150 Mg
0 g Output for ZOUT −250 ±75 +250 Mg
0 g Offset vs. Temperature (X Axis and Y Axis) 2 −0.31 ±0.17 +0.31 mg/°C
0 g Offset vs. Temperature (Z Axis)2 −0.49 ±0.24 +0.49 mg/°C
NOISE PERFORMANCE
Noise (X-Axis and Y-Axis) 100 Hz data rate, full resolution 1.1 LSB rms
Noise (Z-Axis) 100 Hz data rate, full resolution 1.7 LSB rms
OUTPUT DATA RATE AND BANDWIDTH User selectable
Measurement Rate 3 6.25 3200 Hz
SELF-TEST 4 Data rate ≥ 100 Hz, 2.0 V ≤ VS ≤ 3.6 V
Output Change in X-Axis 0.2 2.1 g
Output Change in Y-Axis −2.1 −0.2 g
Output Change in Z-Axis 0.3 3.4 g
POWER SUPPLY
Operating Voltage Range (VS) 2.0 2.5 3.6 V
Interface Voltage Range (VDD I/O) 1.7 1.8 VS V
Supply Current Data rate > 100 Hz 166 µA
Data rate < 10 Hz 45 µA
Standby Mode Leakage Current 0.1 2 µA
Turn-On Time 5 Data rate = 3200 Hz 1.4 ms
o
OPERATING TEMPERATURE RANGE −40 +85 C
1
Cross-axis sensitivity is defined as coupling between any two axes.
2
Offset vs. temperature minimum/maximum specifications are guaranteed by characterization and represent a mean ±3σ distribution.
3
Bandwidth is half the output data rate.
4
Self-test change is defined as the output (g) when the SELF_TEST bit = 1 (in the DATA_FORMAT register) minus the output (g) when the SELF_TEST bit = 0 (in the
DATA_FORMAT register). Due to device filtering, the output reaches its final value after 4 × τ when enabling or disabling self-test, where τ = 1/(data rate).
5
Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rate, the turn-on and wake-up times are each approximately 11.1 ms.
For other data rates, the turn-on and wake-up times are each approximately τ + 1.1 in milliseconds, where τ = 1/(data rate).
ADXL350 Data Sheet
ABSOLUTE MAXIMUM RATINGS

Table 2.
PACKAGE INFORMATION
Parameter Rating The information in Figure 2 and Table 4 provide details about
Acceleration the package branding for the ADXL350. For a complete listing
Any Axis, Unpowered 10,000 g of product availability, see the Ordering Guide section.
Any Axis, Powered 10,000 g
VS −0.3 V to +3.6 V
VDD I/O
Digital Pins
−0.3 V to +3.6 V
−0.3 V to VDD I/O + 0.3 V or
XL350B
3.6 V, whichever is less
All Other Pins −0.3 V to +3.6 V ywVVVV
10271-202
Output Short-Circuit Duration Indefinite
(Any Pin to Ground) Figure 2. Product Information on Package (Top View)
Temperature Range
Table 4. Package Branding Information
Powered −40°C to +105°C
Storage −40°C to +105°C Branding Key Field Description
XL350B Part identifier for ADXL350
yw Date code
Stresses above those listed under Absolute Maximum Ratings VVVV Factory lot code
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
ESD CAUTION
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 3. Package Characteristics
Package Type θJA θJC Device Weight
16-Terminal LGA_CAV 150°C/W 85°C/W 20 mg
Data Sheet ADXL350
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RESERVED
GND
VS
16 15 14
VDD I/O 1 13 GND
ADXL350
NC 2 12 RESERVED
+X
NC 3 11 INT1
SCL/SCLK 4 +Y 10 RESERVED
+Z
NC 5 9 INT2
6 7 8
SDA/SDI/SDIO
SDO/
CS
ALT ADDRESS
NC = NO INTERNAL
CONNECTION
10271-002
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions

Pin No. Mnemonic Description
1 VDD I/O Digital Interface Supply Voltage.
2 NC Not Internally Connected.
4 SCL/SCLK Serial Communications Clock.
6 SDA/SDI/SDIO Serial Data (I2C)/Serial Data Input (SPI 4-Wire)/Serial Data Input and Output (SPI 3-Wire).
7 SDO/ALT ADDRESS Serial Data Output/Alternate I2C Address Select.
8 CS Chip Select.
9 INT2 Interrupt 2 Output.
10 RESERVED Reserved. This pin must be connected to ground or left open.
11 INT1 Interrupt 1 Output.
12 RESERVED Reserved. This pin must be connected to ground.
13 GND This pin must be connected to ground.
14 VS Supply Voltage.
15 RESERVED Reserved. This pin must be connected to VS or left open.
16 GND This pin must be connected to ground.
ADXL350 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS

N = 460 for all typical performance characteristics plots, unless otherwise noted.
40 30
PERCENT OF POPULATION (%)

30
20
20
10
10
0 0
10271-106
10271-103
–100 –80 –60 –40 –20 0 20 40 60 80 100 –100 –80 –60 –40 –20 0 20 40 60 80 100
ZERO g OFFSET (mg) ZERO g OFFSET (mg)
Figure 4. X-Axis Zero g Offset at 25°C, VS = 2.5 V Figure 7. X-Axis Zero g Offset at 25°C, VS = 3.0 V
40 30
30
20
20
10
10
0 0
10271-104
10271-107
–100 –80 –60 –40 –20 0 20 40 60 80 100 –100 –80 –60 –40 –20 0 20 40 60 80 100
Figure 5. Y-Axis Zero g Offset at 25°C, VS = 2.5 V Figure 8. Y-Axis Zero g Offset at 25°C, VS = 3.0 V
30 30
20 20
10 10
0 0
–5
15
35
55
75
95
115
–85
–65
–45
–25
–125
–105
–110
10
30
50
70
–90
–70
–50
–30
–10
–230
–210
–190
–170
–150
–130
10271-108
10271-105
Figure 6. Z-Axis Zero g Offset at 25°C, VS = 2.5 V Figure 9. Z-Axis Zero g Offset at 25°C, VS = 3.0 V
Data Sheet ADXL350
30 100
–40°C TO +25°C N = 16
75 VS = VDD I/O = 2.5V
+25°C TO +85°C
50
20
OUTPUT (mg)
25
–25
10
–50
–75
0 –100
10271-112
0
0.1
0.2
0.3
0.4
0.5
–0.5
–0.4
–0.3
–0.2
–0.1
–60 –40 –20 0 20 40 60 80 100
10271-109
TEMPERATURE (°C)
ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/°C)
Figure 10. X-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V Figure 13. X-Axis Zero g Offset vs. Temperature—
16 Parts Soldered to PCB, VS = 2.5 V
30 100
N = 16
–40°C TO +25°C VS = VDD I/O = 2.5V
75
+25°C TO +85°C
50
20
OUTPUT (mg) 25
–25
10
–50
–75
0 –100
10271-113
–60 –40 –20 0 20 40 60 80 100
0
0.1
0.2
0.3
0.4
0.5
–0.5
–0.4
–0.3
–0.2
–0.1
10271-110
TEMPERATURE (°C)
Figure 11. Y-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V Figure 14. Y-Axis Zero g Offset vs. Temperature—
20 150
N = 16
–40°C TO +25°C VS = VDD I/O = 2.5V
+25°C TO +85°C 100
15
50
OUTPUT (mg)
10 0
–50
5
–100
0 –150
10271-114
–60 –40 –20 0 20 40 60 80 100

0
0.1
0.2
0.3
0.4
0.5
–0.5
–0.4
–0.3
–0.2
–0.1
10271-111
TEMPERATURE (°C)
Figure 12. Z-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V Figure 15. Z-Axis Zero g Offset vs. Temperature—
ADXL350 Data Sheet
30 100
–40°C TO +25°C N = 16
75 VS = VDD I/O = 3.0V
+25°C TO +85°C
50
20
OUTPUT (mg)
25
–25
10
–50
–75
0 –100
10271-118
0
0.1
0.2
0.3
0.4
0.5
0.6
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
–60 –40 –20 0 20 40 60 80 100
10271-115
TEMPERATURE (°C)
Figure 16. X-Axis Zero g Offset Temperature Coefficient, VS = 3.0 V Figure 19. X-Axis Zero g Offset vs. Temperature—
30 100
–40°C TO +25°C N = 16
75 VS = VDD I/O = 3.0V
+25°C TO +85°C
50
20
OUTPUT (mg)
25
–25
10
–50
–75
0 –100
10271-119
–60 –40 –20 0 20 40 60 80 100
0
0.1
0.2
0.3
0.4
0.5
0.6
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
10271-116
TEMPERATURE (°C)
Figure 17. Y-Axis Zero g Offset Temperature Coefficient, VS = 3.0 V Figure 20. Y-Axis Zero g Offset vs. Temperature—
20 150
N = 16
–40°C TO +25°C VS = VDD I/O = 3.0V
+25°C TO +85°C 100
15
50
OUTPUT (mg)
10 0
–50
5
–100
0 –150
10271-120
0
0.1
0.2
0.3
0.4
0.5
0.6
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
–60 –40 –20 0 20 40 60 80

10271-117
TEMPERATURE (°C)
Figure 18. Z-Axis Zero g Offset Temperature Coefficient, VS = 3.0 V Figure 21. Z-Axis Zero g Offset vs. Temperature—
Data Sheet ADXL350
60 80
–40°C TO +25°C
+25°C TO +85°C

60
40
40
20
20
0 0
0.002
0.004
0.006
0.008
0.010
–0.010
–0.008
–0.006
–0.004
–0.002
470
475
480
485
490
495
500
505
510
515
520
525
530
535
540
545
550
10721-121
10271-124
SENSITIVITY (LSB/g)
SENSITIVITY TEMPERATURE COEFFICIENT (%/°C)
Figure 22. X-Axis Sensitivity at 25°C, VS = 2.5 V, Full Resolution Figure 25. X-Axis Sensitivity Temperature Coefficient, VS = 2.5 V
60 80
–40°C TO +25°C
+25°C TO +85°C

60
40
40
20
20
10721-122
0 0
0.002
0.004
0.006
0.008
0.010
–0.010
–0.008
–0.006
–0.004
–0.002
470
475
480
485
490
495
500
505
510
515
520
525
530
535
540
545
550
10271-125
SENSITIVITY (LSB/g)
Figure 23. Y-Axis Sensitivity at 25°C, VS = 2.5 V, Full Resolution Figure 26. Y-Axis Sensitivity Temperature Coefficient, VS = 2.5 V
60 40
–40°C TO +25°C
+25°C TO +85°C
30
40
20
20
10
0 0
0
0.002
0.004
0.006
0.008
0.010
–0.010
–0.008
–0.006
–0.004
–0.002
470
475
480
485
490
495
500
505
510
515
520
525
530
535
540
545
550
10721-123
10271-126
SENSITIVITY (LSB/g)
Figure 24. Z-Axis Sensitivity at 25°C, VS = 2.5 V, Full Resolution Figure 27. Z-Axis Sensitivity Temperature Coefficient, VS = 2.5 V
ADXL350 Data Sheet
40 80
–40°C TO +25°C
+25°C TO +85°C

30 60
20 40
10 20
0 0
0.002
0.004
0.006
0.008
0.010
–0.010
–0.008
–0.006
–0.004
–0.002
495
500
505
510
515
520
525
530
535
540
545
550
555
560
565
570
575
10721-127
10271-130
SENSITIVITY (LSB/g)
Figure 28. X-Axis Sensitivity, VS = 3.0 V, Full Resolution Figure 31. X-Axis Sensitivity Temperature Coefficient, VS = 3.0 V
60 70
–40°C TO +25°C
60 +25°C TO +85°C

50
40
40
30
20
20
10
0 0 0
0.002
0.004
0.006
0.008
0.010
–0.010
–0.008
–0.006
–0.004
–0.002
495
500
505
510
515
520
525
530
535
540
545
550
555
560
565
570
575
10721-128
10271-131
SENSITIVITY (LSB/g)
Figure 29. Y-Axis Sensitivity, VS = 3.0 V, Full Resolution Figure 32. Y-Axis Sensitivity Temperature Coefficient, VS = 3.0 V
60 50
–40°C TO +25°C
+25°C TO +85°C
40
40
30
20
20
10
0 0
0
0.002
0.004
0.006
0.008
0.010
–0.010
–0.008
–0.006
–0.004
–0.002
470
475
480
485
490
495
500
505
510
515
520
525
530
535
540
545
550
10721-129
10271-132
SENSITIVITY (LSB/g)
Figure 30. Z-Axis Sensitivity, VS = 3.0 V, Full Resolution Figure 33. Z-Axis Sensitivity Temperature Coefficient, VS = 3.0 V
Data Sheet ADXL350
540 550
N = 16
535 VS = VDD I/O = 2.5V 545
530 540
525 535
SENSITIVITY (LSB/g)
SENSITIVITY (LSB/g)
520 530
515 525
510 520
505 515
N = 16
500 510
VS = VDD I/O = 3.0V
495 505
490 500
10271-133
10271-136
–60 –40 –20 0 20 40 60 80 100 –60 –40 –20 0 20 40 60 80 100
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 34. X-Axis Sensitivity vs. Temperature— Figure 37. X-Axis Sensitivity vs. Temperature—
16 Parts Soldered to PCB, VS = 2.5 V, Full Resolution 16 Parts Soldered to PCB, VS = 3.0 V, Full Resolution
540 550
N = 16
535 VS = VDD I/O = 2.5V 545
530 540
525
SENSITIVITY (LSB/g)
535
SENSITIVITY (LSB/g)
520 530
515 525
510 520
505 515
500 N = 16
510
VS = VDD I/O = 3.0V
495 505
490 500
10271-134
10271-137
–60 –40 –20 0 20 40 60 80 100 –60 –40 –20 0 20 40 60 80 100
Figure 35. Y-Axis Sensitivity vs. Temperature— Figure 38. Y-Axis Sensitivity vs. Temperature—
540 550
N = 16
535 545
VS = VDD I/O = 2.5V
540
530
535
525
SENSITIVITY (LSB/g)
SENSITIVITY (LSB/g)
530
520
525
515 520
510 515
510
505
505
500
500
495 N = 16
495
VS = VDD I/O = 3.0V
490 490
10271-135
10271-138
–60 –40 –20 0 20 40 60 80 100 –60 –40 –20 0 20 40 60 80 100

Figure 36. Z-Axis Sensitivity vs. Temperature— Figure 39. Z-Axis Sensitivity vs. Temperature—
ADXL350 Data Sheet
80 80

60 60
40 40
20 20
0 0
10271-139
10271-142
0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20
OUTPUT (g) OUTPUT (g)
Figure 40. X-Axis Self-Test Response at 25°C, VS = 2.5 V Figure 43. X-Axis Self-Test Response at 25°C, VS = 3.0 V
60 100
PERCENTAGE OF POPULATION (%)

80
40
60
40
20
20
0 0
10271-140
10271-143
–1.00 –0.95 –0.90 –0.85 –0.80 –0.75 –0.70 –0.65 –0.60
–1.20 –1.15 –1.10 –1.05 –1.00 –0.95 –0.90 –0.85 –0.80
Figure 41. Y-Axis Self-Test Response at 25°C, VS = 2.5 V Figure 44. Y-Axis Self-Test Response at 25°C, VS = 3.0 V
60 50
40
40
30
20
20
10
0 0
10271-141
10271-144
1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20
Figure 42. Z-Axis Self-Test Response at 25°C, VS = 2.5 V Figure 45. Z-Axis Self-Test Response at 25°C, VS = 3.0 V
Data Sheet ADXL350
60 220
200
40 180
CURRENT (µA)
160
20 140
120
0 100
10271-145
10271-147
100 110 120 130 140 150 160 170 180 190 200 2 3 4
CURRENT CONSUMPTION (µA) SUPPLY VOLTAGE (V)
Figure 46. Current Consumption at 25°C, 100 Hz Output Data Rate, Figure 48. Supply Current vs. Supply Voltage, VS at 25°C, 10 Parts
VS = 2.5 V, 31 Parts
180
160
140
120
CURRENT (µA)
100
80
60
40
20
0
10271-146
1 10 100 1k 10k
OUTPUT DATA RATE (Hz)
Figure 47. Current Consumption vs. Output Data Rate at 25°C

VS = 2.5 V, 10 Parts
ADXL350 Data Sheet
THEORY OF OPERATION
The ADXL350 is a complete 3-axis acceleration measurement POWER SEQUENCING
system with a selectable measurement range of ±1 g, ±2 g, ±4 g, Power can be applied to VS or VDD I/O in any sequence without
or ±8 g. It measures both dynamic acceleration resulting from damaging the ADXL350. All possible power-on modes are
motion or shock and static acceleration, such as gravity, which summarized in Table 6.
allows the device to be used as a tilt sensor.
The interface voltage level is set with the interface supply volt-
The sensor is a polysilicon surface-micromachined structure age, VDD I/O, which must be present to ensure that the ADXL350
built on top of a silicon wafer. Polysilicon springs suspend the does not create a conflict on the communication bus. For
structure over the surface of the wafer and provide a resistance single-supply operation, VDD I/O can be the same as the main
against acceleration forces. supply, VS. In a dual-supply application, however, VDD I/O can
Deflection of the structure is measured using differential capacitors differ from VS to accommodate the desired interface voltage, as
that consist of independent fixed plates and plates attached to the long as VS is greater than VDD I/O.
moving mass. Acceleration deflects the beam and unbalances the After VS is applied, the device enters standby mode, where power
differential capacitor, resulting in a sensor output whose amplitude consumption is minimized and the device waits for VDD I/O to be
is proportional to acceleration. Phase-sensitive demodulation is applied and for the command to enter measurement mode to be
used to determine the magnitude and polarity of the acceleration. received. (This command can be initiated by setting the measure
bit in the POWER_CTL register (Address 0x2D).) In addition, any
register can be written to or read from to configure the part while
the device is in standby mode. It is recommended to configure the
device in standby mode and then to enable measurement mode.
Clearing the measure bit returns the device to the standby mode.
Table 6. Power Sequencing

Condition VS VDD I/O Description
Power Off Off Off The device is completely off, but there is the potential for a communication
bus conflict.
Bus Disabled On Off The device is on in standby mode, but communication is unavailable and
creates a conflict on the communication bus. The duration of this state should
be minimized during power-up to prevent a conflict.
Bus Enabled Off On No functions are available, but the device does not create a conflict on the
communication bus.
Standby or Measurement On On At power-up, the device is in standby mode, awaiting a command to enter
measurement mode, and all sensor functions are off. After the device is
instructed to enter measurement mode, all sensor functions are available.
Data Sheet ADXL350
POWER SAVINGS Table 8. Current Consumption vs. Data Rate, Low Power
Mode (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)
Power Modes
Output Data
The ADXL350 automatically modulates its power consumption Rate (Hz) Bandwidth (Hz) Rate Code IDD (µA)
in proportion to its output data rate, as outlined in Table 7. If 400 200 1100 100
additional power savings is desired, a lower power mode is 200 100 1011 65
available. In this mode, the internal sampling rate is reduced, 100 50 1010 55
allowing for power savings in the 12.5 Hz to 400 Hz data rate 50 25 1001 50
range but at the expense of slightly greater noise. 25 12.5 1000 40
To enter lower power mode, set the LOW_POWER bit (Bit 4) in 12.5 6.25 0111 40
the BW_RATE register (Address 0x2C). The current consumption Auto Sleep Mode
in low power mode is shown in Table 8 for cases where there is
Additional power can be saved if the ADXL350 automatically
an advantage for using low power mode. The current consump-
switches to sleep mode during periods of inactivity. To enable
tion values shown in Table 7 and Table 8 are for a VS of 2.5 V.
this feature, set the THRESH_INACT register (Address 0x25)
Current scales linearly with VS.
and the TIME_INACT register (Address 0x26) each to a value
Table 7. Current Consumption vs. Data Rate that signifies inactivity (the appropriate value depends on the
(TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V) application), and then set the AUTO_SLEEP bit and the link bit in
Output Data the POWER_CTL register (Address 0x2D). Current consumption
Rate (Hz) Bandwidth (Hz) Rate Code IDD (µA) at the sub-8 Hz data rates used in this mode is typically 40 µA
3200 1600 1111 145 for a VS of 2.5 V.
1600 800 1110 100 Standby Mode
800 400 1101 145
For even lower power operation, standby mode can be used. In
400 200 1100 145
standby mode, current consumption is reduced to 0.1 µA (typical).
200 100 1011 145
In this mode, no measurements are made. Standby mode is entered
100 50 1010 145
by clearing the measure bit (Bit 3) in the POWER_CTL register
50 25 1001 100
(Address 0x2D). Placing the device into standby mode preserves
25 12.5 1000 65
the contents of FIFO.
12.5 6.25 0111 55
6.25 3.125 0110 40
ADXL350 Data Sheet
SERIAL COMMUNICATIONS
I2C and SPI digital communications are possible and regardless, To read or write multiple bytes in a single transmission, the
the ADXL350 always operates as a slave. I2C mode is enabled if multiple-byte bit, located after the R/W bit in the first byte
the CS pin is tied high to VDD I/O. The CS pin should always be transfer (MB in Figure 52 to Figure 54), must be set. After the
tied high to VDD I/O or be driven by an external controller register addressing and the first byte of data, each subsequent
because there is no default mode if the CS pin is left set of clock pulses (eight clock pulses) causes the ADXL350 to
unconnected. Not taking this precaution may result in an inability point to the next register for a read or write. This shifting continues
to communicate with the part. In SPI mode, the CS pin is until the clock pulses cease and CS is deasserted. To perform
controlled by the bus master. reads or writes on different, nonsequential registers, CS must
In both SPI and I2C modes of operation, data transmitted from the be deasserted between transmissions and the new register must
ADXL350 to the master device should be ignored during writes to be addressed separately. The timing diagram for 3-wire SPI
the ADXL350. reads or writes is shown in Figure 54. The 4-wire equivalents
for SPI writes and reads are shown in Figure 52 and Figure 53,
SPI
respectively.
For SPI, either 3- or 4-wire configuration is possible, as shown
in the connection diagrams in Figure 49 and Figure 50. Clearing Preventing Bus Traffic Errors
the SPI bit in the DATA_FORMAT register (Address 0x31) selects The ADXL350 CS pin is used both for initiating SPI transact-
4-wire mode, whereas setting the SPI bit selects 3-wire mode. tions, and for enabling I2C mode. When the ADXL350 is used
The maximum SPI clock speed is 5 MHz with 100 pF maximum on an SPI bus with multiple devices, its CS pin is held high
loading, and the timing scheme follows clock polarity (CPOL) = 1 while the master communicates with the other devices. There
and clock phase (CPHA) = 1. may be conditions where an SPI command transmitted to
CS is the serial port enable line and is controlled by the SPI master. another device looks like a valid I2C command. In this case, the
This line must go low at the start of a transmission and high at ADXL350 would interpret this as an attempt to communicate in
the end of a transmission, as shown in Figure 52. SCLK is the I2C mode, and could interfere with other bus traffic. Unless bus
serial port clock and is supplied by the SPI master. It is stopped traffic can be adequately controlled to assure such a condition
never occurs, it is recommended to add a logic gate in front of
high when CS is high during a period of no transmission. SDI
the SDI pin as shown in Figure 51. This OR gate will hold the
and SDO are the serial data input and output, respectively. Data
should be sampled at the rising edge of SCLK. SDA line high when CS is high to prevent SPI bus traffic at the
ADXL350 from appearing as an I2C start command.
ADXL350
ADXL350 PROCESSOR
ADXL350
ADXL350 PROCESSOR
CS D OUT
SDIO D IN/OUT CS D OUT
SDIO D IN/OUT
SDO
10271-004
SDO
10271-151
SCLK D OUT
SCLK D OUT
Figure 49. 3-Wire SPI Connection Diagram
Figure 51. Recommended SPI Connection Diagram when Using Multiple SPI
ADXL350 PROCESSOR Devices on a Single Bus
ADXL350
CS D OUT
SDI D OUT
SDO D IN
10271-003
SCLK D OUT
Figure 50. 4-Wire SPI Connection Diagram
Data Sheet ADXL350
Table 9. SPI Digital Input/Output Voltage

Limit 1
Parameter Test Conditions Min Max Unit
Digital Input
Low Level Input Voltage (VIL) 0.3 × VDD I/O V
High Level Input Voltage (VIH) 0.7 × VDD I/O V
Low Level Input Current (IIL) VIN = VDD I/O 0.1 µA
High Level Input Current (IIH) VIN = 0 V −0.1 µA
Digital Output
Low Level Output Voltage (VOL) IOL = 10 mA 0.2 × VDD I/O V
High Level Output Voltage (VOH) IOH = −4 mA 0.8 × VDD I/O V
Low Level Output Current (IOL) VOL = VOL, max 10 mA
High Level Output Current (IOH) VOH = VOH, min −4 mA
Pin Capacitance fIN = 1 MHz, VIN = 2.5 V 8 pF
1
Limits based on characterization results, not production tested.
Table 10. SPI Timing (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V) 1
Limit 2, 3
Parameter Min Max Unit Description
fSCLK 5 MHz SPI clock frequency
tSCLK 200 ns 1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40
tDELAY 10 ns CS falling edge to SCLK falling edge
tQUIET 10 ns SCLK rising edge to CS rising edge
tDIS 100 ns CS rising edge to SDO disabled
tCS,DIS 250 ns CS deassertion between SPI communications
tS 0.4 × tSCLK ns SCLK low pulse width (space)
tM 0.4 × tSCLK ns SCLK high pulse width (mark)
tSDO 95 ns SCLK falling edge to SDO transition
tSETUP 10 ns SDI valid before SCLK rising edge
tHOLD 10 ns SDI valid after SCLK rising edge
1
The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation.
2
Limits are based on characterization results, characterized with fSCLK = 5 MHz and bus load capacitance of 100 pF; not production tested.
3
The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 9.
ADXL350 Data Sheet
CS
tSCLK tM tS tQUIET tCS,DIS

tDELAY
SCLK
tHOLD
tSETUP
SDI W MB A5 A0 D7 D0
tSDO ADDRESS BITS DATA BITS tDIS
10271-017
SDO X X X X X X
Figure 52. SPI 4-Wire Write
CS
tSCLK tM tS tQUIET tCS,DIS

tDELAY
SCLK
tHOLD
tSETUP
SDI R MB A5 A0 X X
tSDO ADDRESS BITS tDIS
SDO X X X X D7 D0
10271-018
DATA BITS
Figure 53. SPI 4-Wire Read
CS
tDELAY tSCLK tM tS
tQUIET tCS,DIS
SCLK
tSETUP tHOLD tSDO
SDIO R/W MB A5 A0 D7 D0
ADDRESS BITS DATA BITS
SDO
10271-019
NOTES
1. tSDO IS ONLY PRESENT DURING READS.
Figure 54. SPI 3-Wire Read/Write
Data Sheet ADXL350
I2C If other devices are connected to the same I2C bus, the nominal
operating voltage level of these other devices cannot exceed VDD I/O
With CS tied high to VDD I/O, the ADXL350 is in I2C mode,
by more than 0.3 V. External pull-up resistors, RP, are necessary
requiring a simple 2-wire connection as shown in Figure 55.
for proper I2C operation. Refer to the UM10204 I2C-Bus
The ADXL350 conforms to the UM10204 I2C-Bus Specification
Specification and User Manual, Rev. 03—19 June 2007, when
and User Manual, Rev. 03—19 June 2007, available from NXP
selecting pull-up resistor values to ensure proper operation.
Semiconductor. It supports standard (100 kHz) and fast (400 kHz)
data transfer modes if the timing parameters given in Table 12 Table 11. I2C Digital Input/Output Voltage
and Figure 57 are met. Parameter Limit 1 Unit
Single-byte or multiple-byte reads/writes are supported, Digital Input Voltage
as shown in Figure 56. With the SDO/ALT ADDRESS pin Low Level Input Voltage (VIL) 0.25 × VDD I/O V max
(Pin 7) high, the 7-bit I2C address for the device is 0x1D, followed High Level Input Voltage (VIH) 0.75 × VDD I/O V min
by the R/W bit. This translates to 0x3A for a write and 0x3B for a Digital Output Voltage
read. An alternate I2C address of 0x53 (followed by the R/W bit) Low Level Output Voltage (VOL) 2 0.2 × VDD I/O V max
can be chosen by grounding the SDO/ALT ADDRESS pin 1
Limits are based on characterization results; not production tested.
(Pin 7). This translates to 0xA6 for a write and 0xA7 for a read. 2
The limit given is only for VDD I/O < 2 V. When VDD I/O > 2 V, the limit is 0.4 V maximum.
VDD I/O
ADXL350
ADXL350
RP RP PROCESSOR
CS
SDA D IN/OUT
ALT ADDRESS
SCL D OUT
10271-008
Figure 55. I2C Connection Diagram (Address 0x53)
SINGLE-BYTE WRITE
MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS DATA STOP
SLAVE ACK ACK ACK
MULTIPLE-BYTE WRITE
MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS DATA DATA STOP
SLAVE ACK ACK ACK ACK
SINGLE-BYTE READ
MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS START1 SLAVE ADDRESS + READ NACK STOP
SLAVE ACK ACK ACK DATA
MULTIPLE-BYTE READ
MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS START1 SLAVE ADDRESS + READ ACK NACK STOP
SLAVE ACK ACK ACK DATA DATA
NOTES
1. THIS START IS EITHER A RESTART OR A STOP FOLLOWED BY A START. 10271-009
2. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING.
Figure 56. I2C Device Addressing
ADXL350 Data Sheet
Table 12. I2C Timing (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)
Limit 1, 2
Parameter Min Max Unit Description
fSCL 400 kHz SCL clock frequency
t1 2.5 µs SCL cycle time
t2 0.6 µs tHIGH, SCL high time
t3 1.3 µs tLOW, SCL low time
t4 0.6 µs tHD, STA, start/repeated start condition hold time
t5 350 ns tSU, DAT, data setup time
t6 3, 4, 5, 6 0 0.65 µs tHD, DAT, data hold time
t7 0.6 µs tSU, STA, setup time for repeated start
t8 0.6 µs tSU, STO, stop condition setup time
t9 1.3 µs tBUF, bus-free time between a stop condition and a start condition
t10 300 ns tR, rise time of both SCL and SDA when receiving
0 ns tR, rise time of both SCL and SDA when receiving or transmitting
t11 250 ns tF, fall time of SDA when receiving
300 ns tF, fall time of both SCL and SDA when transmitting
20 + 0.1 Cb 7 ns tF, fall time of both SCL and SDA when transmitting or receiveing
Cb 400 pF Capacitive load for each bus line
1
Limits are based on characterization results, with fSCL = 400 kHz and a 3 mA sink current; not production tested.
2
All values are referred to the VIH and the VIL levels given in Table 11.
3
t6 is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge times.
4
A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to VIH(min) of the SCL signal) to bridge the undefined region of
the falling edge of SCL.
5
The maximum t6 value must be met only if the device does not stretch the low period (t3) of the SCL signal.
6
The maximum value for t6 is a function of the clock low time (t3), the clock rise time (t10), and the minimum data setup time (t5(min)). This value is calculated as t6(max) = t3 − t10 − t5(min).
7
Cb is the total capacitance of one bus line in picofarads.
SDA
t9 t3 t4
t10 t11
SCL
t4 t6 t2 t5 t7 t1 t8
10271-020
START REPEATED STOP
CONDITION START CONDITION
CONDITION
Figure 57. I2C Timing Diagram
Data Sheet ADXL350
INTERRUPTS register (Address 0x29). The FREE_FALL interrupt differs from

the inactivity interrupt as follows: all axes always participate, the
The ADXL350 provides two output pins for driving interrupts: timer period is much smaller (1.28 sec maximum), and the mode
INT1 and INT2. Each interrupt function is described in detail of operation is always dc-coupled.
in this section. All functions can be used simultaneously, with
the only limiting feature being that some functions may need Watermark
to share interrupt pins. Interrupts are enabled by setting the The watermark bit is set when the number of samples in FIFO
appropriate bit in the INT_ENABLE register (Address 0x2E) equals the value stored in the samples bits (Register FIFO_CTL,
and are mapped to either the INT1 or INT2 pin based on the Address 0x38). The watermark bit is cleared automatically when
contents of the INT_MAP register (Address 0x2F). It is recom- FIFO is read, and the content returns to a value below the value
mended that interrupt bits be configured with the interrupts stored in the samples bits.
disabled, preventing interrupts from being accidentally triggered Overrun
during configuration. This can be done by writing a value of 0x00
The overrun bit is set when new data replaces unread data.
to the INT_ENABLE register.
The precise operation of the overrun function depends on the
Clearing interrupts is performed either by reading the data FIFO mode. In bypass mode, the overrun bit is set when new data
registers (Address 0x32 to Address 0x37) until the interrupt replaces unread data in the DATAX, DATAY, and DATAZ registers
condition is no longer valid for the data-related interrupts or by (Address 0x32 to Address 0x37). In all other modes, the overrun
reading the INT_SOURCE register (Address 0x30) for the bit is set when FIFO is filled. The overrun bit is automatically
remaining interrupts. This section describes the interrupts that can cleared when the contents of FIFO are read.
be set in the INT_ENABLE register and monitored in the
INT_SOURCE register. FIFO
DATA_READY The ADXL350 contains patent pending technology for an
embedded 32-level FIFO that can be used to minimize host
The DATA_READY bit is set when new data is available and is processor burden. This buffer has four modes: bypass, FIFO,
cleared when no new data is available. stream, and trigger (see Table 20). Each mode is selected by
SINGLE_TAP the settings of the FIFO_MODE bits in the FIFO_CTL register
The SINGLE_TAP bit is set when a single acceleration event (Address 0x38).
that is greater than the value in the THRESH_TAP register Bypass Mode
(Address 0x1D) occurs for less time than is specified in In bypass mode, FIFO is not operational and, therefore,
the DUR register (Address 0x21). remains empty.
DOUBLE_TAP FIFO Mode
The DOUBLE_TAP bit is set when two acceleration events In FIFO mode, data from measurements of the x-, y-, and z-
that are greater than the value in the THRESH_TAP register axes are stored in FIFO. When the number of samples in FIFO
(Address 0x1D) occur for less time than is specified in the equals the level specified in the samples bits of the FIFO_CTL
DUR register (Address 0x21), with the second tap starting after register (Address 0x38), the watermark interrupt is set. FIFO
the time specified by the latent register (Address 0x22) but within continues accumulating samples until it is full (32 samples from
the time specified in the window register (Address 0x23). See measurements of the x-, y-, and z-axes) and then stops collecting
the Tap Detection section for more details. data. After FIFO stops collecting data, the device continues to
Activity operate; therefore, features such as tap detection can be used
The activity bit is set when acceleration greater than the value after FIFO is full. The watermark interrupt continues to occur
stored in the THRESH_ACT register (Address 0x24) is until the number of samples in FIFO is less than the value
experienced. stored in the samples bits of the FIFO_CTL register.
Inactivity Stream Mode

The inactivity bit is set when acceleration of less than the value In stream mode, data from measurements of the x-, y-, and
stored in the THRESH_INACT register (Address 0x25) is experi- z-axes are stored in FIFO. When the number of samples in FIFO
enced for more time than is specified in the TIME_INACT equals the level specified in the samples bits of the FIFO_CTL
register (Address 0x26). The maximum value for TIME_INACT register (Address 0x38), the watermark interrupt is set. FIFO
is 255 sec. continues accumulating samples and holds the latest 32 samples
from measurements of the x-, y-, and z-axes, discarding older
FREE_FALL
data as new data arrives. The watermark interrupt continues
The FREE_FALL bit is set when acceleration of less than the occurring until the number of samples in FIFO is less than the
value stored in the THRESH_FF register (Address 0x28) is value stored in the samples bits of the FIFO_CTL register.
experienced for more time than is specified in the TIME_FF
ADXL350 Data Sheet
Trigger Mode SELF-TEST
In trigger mode, FIFO accumulates samples, holding the latest The ADXL350 incorporates a self-test feature that effectively
32 samples from measurements of the x-, y-, and z-axes. After tests its mechanical and electronic systems simultaneously.
a trigger event occurs and an interrupt is sent to the INT1 or When the self-test function is enabled (via the SELF_TEST bit
INT2 pin (determined by the trigger bit in the FIFO_CTL register), in the DATA_FORMAT register, Address 0x31), an electrostatic
FIFO keeps the last n samples (where n is the value specified by force is exerted on the mechanical sensor. This electrostatic force
the samples bits in the FIFO_CTL register) and then operates in moves the mechanical sensing element in the same manner as
FIFO mode, collecting new samples only when FIFO is not full. acceleration, and it is additive to the acceleration experienced
A delay of at least 5 μs should be present between the trigger event by the device. This added electrostatic force results in an output
occurring and the start of reading data from the FIFO to allow change in the x-, y-, and z-axes. Because the electrostatic force
the FIFO to discard and retain the necessary samples. Additional is proportional to VS2, the output change varies with VS.
trigger events cannot be recognized until the trigger mode is The self-test feature of the ADXL350 also exhibits a bimodal
reset. To reset the trigger mode, set the device to bypass mode behavior that depends on which phase of the clock self-test is
and then set the device back to trigger mode. Note that the enabled. However, the limits shown in Table 1 and Table 13
FIFO data should be read first because placing the device into to Table 16 are valid for all potential self-test values across the
bypass mode clears FIFO. entire allowable voltage range. Use of the self-test feature at data
Retrieving Data from FIFO rates less than 100 Hz may yield values outside these limits.
Therefore, the part should be placed into a data rate of 100 Hz
The FIFO data is read through the DATAX, DATAY, and DATAZ
or greater when using self-test.
registers (Address 0x32 to Address 0x37). When the FIFO is in
FIFO, stream, or trigger mode, reads to the DATAX, DATAY, Table 13. Self-Test Output in LSB for ±1 g, 10-bit Resolution
and DATAZ registers read data stored in the FIFO. Each time or any g-Range, Full Resolution
data is read from the FIFO, the oldest x-, y-, and z-axes data are Axis Min Max Unit
placed into the DATAX, DATAY, and DATAZ registers. X 100 1180 LSB
If a single-byte read operation is performed, the remaining Y −1180 −100 LSB
bytes of data for the current FIFO sample are lost. Therefore, all Z 150 1850 LSB
axes of interest should be read in a burst (or multiple-byte) read
operation. To ensure that the FIFO has completely popped (that Table 14. Self-Test Output in LSB for ±2 g, 10-Bit Resolution
is, that new data has completely moved into the DATAX, DATAY, Axis Min Max Unit
and DATAZ registers), there must be at least 5 μs between the X 50 590 LSB
end of reading the data registers and the start of a new read of Y −590 −50 LSB
the FIFO or a read of the FIFO_STATUS register (Address 0x39). Z 75 925 LSB
The end of reading a data register is signified by the transition
Table 15. Self-Test Output in LSB for ±4 g, 10-Bit Resolution
from Register 0x37 to Register 0x38 or by the CS pin going high.
Axis Min Max Unit
For SPI operation at 1.6 MHz or less, the register addressing X 25 295 LSB
portion of the transmission is a sufficient delay to ensure that Y −295 −25 LSB
the FIFO has completely popped. For SPI operation greater than Z 38 463 LSB
1.6 MHz, it is necessary to deassert the CS pin to ensure a total
delay of 5 μs; otherwise, the delay will not be sufficient. The total Table 16. Self-Test Output in LSB for ±8 g, 10-Bit Resolution
delay necessary for 5 MHz operation is at most 3.4 μs. This is Axis Min Max Unit
not a concern when using I2C mode because the communication
X 12 148 LSB
rate is low enough to ensure a sufficient delay between FIFO reads.
Y −148 −12 LSB
Z 19 232 LSB
Data Sheet ADXL350
REGISTER MAP
Table 17. Register Map
Address
Hex Dec Name Type Reset Value Description
0x00 0 DEVID R 11100101 Device ID.
0x01 to 0x01C 1 to 28 Reserved Reserved. Do not access.
0x1D 29 THRESH_TAP R/W 00000000 Tap threshold.
0x1E 30 OFSX R/W 00000000 X-axis offset.
0x1F 31 OFSY R/W 00000000 Y-axis offset.
0x20 32 OFSZ R/W 00000000 Z-axis offset.
0x21 33 DUR R/W 00000000 Tap duration.
0x22 34 Latent R/W 00000000 Tap latency.
0x23 35 Window R/W 00000000 Tap window.
0x24 36 THRESH_ACT R/W 00000000 Activity threshold.
0x25 37 THRESH_INACT R/W 00000000 Inactivity threshold.
0x26 38 TIME_INACT R/W 00000000 Inactivity time.
0x27 39 ACT_INACT_CTL R/W 00000000 Axis enable control for activity and inactivity detection.
0x28 40 THRESH_FF R/W 00000000 Free-fall threshold.
0x29 41 TIME_FF R/W 00000000 Free-fall time.
0x2A 42 TAP_AXES R/W 00000000 Axis control for tap/double tap.
0x2B 43 ACT_TAP_STATUS R 00000000 Source of tap/double tap.
0x2C 44 BW_RATE R/W 00001010 Data rate and power mode control.
0x2D 45 POWER_CTL R/W 00000000 Power-saving features control.
0x2E 46 INT_ENABLE R/W 00000000 Interrupt enable control.
0x2F 47 INT_MAP R/W 00000000 Interrupt mapping control.
0x30 48 INT_SOURCE R 00000010 Source of interrupts.
0x31 49 DATA_FORMAT R/W 00000000 Data format control.
0x32 50 DATAX0 R 00000000 X-Axis Data 0.
0x33 51 DATAX1 R 00000000 X-Axis Data 1.
0x34 52 DATAY0 R 00000000 Y-Axis Data 0.
0x35 53 DATAY1 R 00000000 Y-Axis Data 1.
0x36 54 DATAZ0 R 00000000 Z-Axis Data 0.
0x37 55 DATAZ1 R 00000000 Z-Axis Data 1.
0x38 56 FIFO_CTL R/W 00000000 FIFO control.
0x39 57 FIFO_STATUS R 00000000 FIFO status.
ADXL350 Data Sheet
REGISTER DEFINITIONS A value of 0 mg may result in undesirable behavior if the inactivity
Register 0x00—DEVID (Read Only) interrupt is enabled.
D7 D6 D5 D4 D3 D2 D1 D0 Register 0x26—TIME_INACT (Read/Write)
1 1 1 0 0 1 0 1 The TIME_INACT register is eight bits and contains an unsigned
The DEVID register holds a fixed device ID code of 0xE5 time value representing the amount of time that acceleration
(345 octal). must be less than the value in the THRESH_INACT register for
inactivity to be declared. The scale factor is 1 sec/LSB. Unlike
Register 0x1D—THRESH_TAP (Read/Write) the other interrupt functions, which use unfiltered data (see the
The THRESH_TAP register is eight bits and holds the threshold Threshold section), the inactivity function uses filtered output
value for tap interrupts. The data format is unsigned, so the data. At least one output sample must be generated for the
magnitude of the tap event is compared with the value in inactivity interrupt to be triggered. This results in the function
THRESH_TAP. The scale factor is 31.2 mg/LSB (that is, 0xFF appearing unresponsive if the TIME_INACT register is set to a
= +8 g). A value of 0 may result in undesirable behavior if tap/ value less than the time constant of the output data rate. A value
double tap interrupts are enabled. of 0 results in an interrupt when the output data is less than the
Register 0x1E, Register 0x1F, Register 0x20—OFSX, value in the THRESH_INACT register.
OFSY, OFSZ (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write)
The OFSX, OFSY, and OFSZ registers are each eight bits and D7 D6 D5 D4
offer user-set offset adjustments in twos complement format ACT ac/dc ACT_X enable ACT_Y enable ACT_Z enable
with a scale factor of 7.8 mg/LSB (that is, 0x7F = +1 g). D3 D2 D1 D0
INACT ac/dc INACT_X enable INACT_Y enable INACT_Z enable
Register 0x21—DUR (Read/Write)
The DUR register is eight bits and contains an unsigned time ACT AC/DC and INACT AC/DC Bits
value representing the maximum time that an event must be A setting of 0 selects dc-coupled operation, and a setting of
above the THRESH_TAP threshold to qualify as a tap event. The 1 enables ac-coupled operation. In dc-coupled operation, the
scale factor is 625 µs/LSB. A value of 0 disables the tap/double current acceleration magnitude is compared directly with
tap functions. THRESH_ACT and THRESH_INACT to determine whether
Register 0x22—Latent (Read/Write) activity or inactivity is detected.
The latent register is eight bits and contains an unsigned time In ac-coupled operation for activity detection, the acceleration
value representing the wait time from the detection of a tap event value at the start of activity detection is taken as a reference
to the start of the time window (defined by the window register) value. New samples of acceleration are then compared to this
during which a possible second tap event can be detected. The scale reference value, and if the magnitude of the difference exceeds
factor is 1.25 ms/LSB. A value of 0 disables the double tap function. the THRESH_ACT value, the device triggers an activity
interrupt.
Register 0x23—Window (Read/Write)
Similarly, in ac-coupled operation for inactivity detection, a
The window register is eight bits and contains an unsigned time
reference value is used for comparison and is updated whenever
value representing the amount of time after the expiration of the
the device exceeds the inactivity threshold. After the reference
latency time (determined by the latent register) during which a
value is selected, the device compares the magnitude of the
second valid tap can begin. The scale factor is 1.25 ms/LSB. A
difference between the reference value and the current accel-
value of 0 disables the double tap function.
eration with THRESH_INACT. If the difference is less than the
Register 0x24—THRESH_ACT (Read/Write) value in THRESH_INACT for the time in TIME_INACT, the
The THRESH_ACT register is eight bits and holds the threshold device is considered inactive and the inactivity interrupt is
value for detecting activity. The data format is unsigned, so the triggered.
magnitude of the activity event is compared with the value in ACT_x Enable Bits and INACT_x Enable Bits
the THRESH_ACT register. The scale factor is 31.2 mg/LSB.
A setting of 1 enables x-, y-, or z-axis participation in detecting
A value of 0 may result in undesirable behavior if the activity
activity or inactivity. A setting of 0 excludes the selected axis from
interrupt is enabled.
participation. If all axes are excluded, the function is disabled.
Register 0x25—THRESH_INACT (Read/Write)
Register 0x28—THRESH_FF (Read/Write)
The THRESH_INACT register is eight bits and holds the threshold
The THRESH_FF register is eight bits and holds the threshold
value for detecting inactivity. The data format is unsigned, so
value, in unsigned format, for free-fall detection. The root-sum-
the magnitude of the inactivity event is compared with the value
square (RSS) value of all axes is calculated and compared with
in the THRESH_INACT register. The scale factor is 31.2 mg/LSB.
the value in THRESH_FF to determine if a free-fall event occurred.
The scale factor is 31.2 mg/LSB. Note that a value of 0 mg may
Data Sheet ADXL350
result in undesirable behavior if the free-fall interrupt is enabled. Rate Bits
Values between 300 mg and 600 mg (0x0A to 0x13) are These bits select the device bandwidth and output data rate (see
recommended. Table 7 and Table 8 for details). The default value is 0x0A, which
Register 0x29—TIME_FF (Read/Write) translates to a 100 Hz output data rate. An output data rate
The TIME_FF register is eight bits and stores an unsigned time should be selected that is appropriate for the communication
value representing the minimum time that the RSS value of all axes protocol and frequency selected. Selecting too high of an output
must be less than THRESH_FF to generate a free-fall interrupt. data rate with a low communication speed results in samples
The scale factor is 5 ms/LSB. A value of 0 may result in undesirable being discarded.
behavior if the free-fall interrupt is enabled. Values between 100 ms Register 0x2D—POWER_CTL (Read/Write)
and 350 ms (0x14 to 0x46) are recommended. D7 D6 D5 D4 D3 D2 D1 D0
Register 0x2A—TAP_AXES (Read/Write) 0 0 Link AUTO_SLEEP Measure Sleep Wakeup
D7 D6 D5 D4 D3 D2 D1 D0
Link Bit
0 0 0 0 Suppress TAP_X TAP_Y TAP_Z
enable enable enable A setting of 1 in the link bit with both the activity and inactivity
functions enabled delays the start of the activity function until
Suppress Bit inactivity is detected. After activity is detected, inactivity detection
Setting the suppress bit suppresses double tap detection if begins, preventing the detection of activity. This bit serially links
acceleration greater than the value in THRESH_TAP is present the activity and inactivity functions. When this bit is set to 0,
between taps. See the Tap Detection section for more details. the inactivity and activity functions are concurrent. Additional
information can be found in the Link Mode section.
TAP_x Enable Bits
When clearing the link bit, it is recommended that the part be
A setting of 1 in the TAP_X enable, TAP_Y enable, or TAP_Z
placed into standby mode and then set back to measurement
enable bit enables x-, y-, or z-axis participation in tap detection.
mode with a subsequent write. This is done to ensure that the
A setting of 0 excludes the selected axis from participation in
device is properly biased if sleep mode is manually disabled;
tap detection.
otherwise, the first few samples of data after the link bit is cleared
Register 0x2B—ACT_TAP_STATUS (Read Only) may have additional noise, especially if the device was asleep
D7 D6 D5 D4 D3 D2 D1 D0 when the bit was cleared.
0 ACT_X ACT_Y ACT_Z Asleep TAP_X TAP_Y TAP_Z
source source source source source source AUTO_SLEEP Bit
ACT_x Source and TAP_x Source Bits If the link bit is set, a setting of 1 in the AUTO_SLEEP bit sets
the ADXL350 to switch to sleep mode when inactivity is detected
These bits indicate the first axis involved in a tap or activity
(that is, when acceleration has been below the THRESH_INACT
event. A setting of 1 corresponds to involvement in the event,
value for at least the time indicated by TIME_INACT). A setting
and a setting of 0 corresponds to no involvement. When new
of 0 disables automatic switching to sleep mode. See the description
data is available, these bits are not cleared but are overwritten by
of the sleep bit in this section for more information.
the new data. The ACT_TAP_STATUS register should be read
before clearing the interrupt. Disabling an axis from participation When clearing the AUTO_SLEEP bit, it is recommended that the
clears the corresponding source bit when the next activity or part be placed into standby mode and then set back to measure-
tap/double tap event occurs. ment mode with a subsequent write. This is done to ensure that
the device is properly biased if sleep mode is manually disabled;
Asleep Bit otherwise, the first few samples of data after the AUTO_SLEEP
A setting of 1 in the asleep bit indicates that the part is asleep, bit is cleared may have additional noise, especially if the device
and a setting of 0 indicates that the part is not asleep. See the was asleep when the bit was cleared.
Register 0x2D—POWER_CTL (Read/Write) section for more Measure Bit
information on autosleep mode.
A setting of 0 in the measure bit places the part into standby mode,
Register 0x2C—BW_RATE (Read/Write) and a setting of 1 places the part into measurement mode. The
D7 D6 D5 D4 D3 D2 D1 D0
ADXL350 powers up in standby mode with minimum power
0 0 0 LOW_POWER Rate consumption.
LOW_POWER Bit Sleep Bit
A setting of 0 in the LOW_POWER bit selects normal operation, A setting of 0 in the sleep bit puts the part into the normal mode
and a setting of 1 selects reduced power operation, which has of operation, and a setting of 1 places the part into sleep mode.
somewhat higher noise (see the Power Modes section for details). Sleep mode suppresses DATA_READY, stops transmission of data
ADXL350 Data Sheet
to FIFO, and switches the sampling rate to one specified by the Bits set to 1 in this register indicate that their respective functions
wakeup bits. In sleep mode, only the activity function can be used. have triggered an event, whereas a value of 0 indicates that the
When clearing the sleep bit, it is recommended that the part be corresponding event has not occurred. The DATA_READY,
placed into standby mode and then set back to measurement watermark, and overrun bits are always set if the corresponding
mode with a subsequent write. This is done to ensure that the events occur, regardless of the INT_ENABLE register settings,
device is properly biased if sleep mode is manually disabled; and are cleared by reading data from the DATAX, DATAY, and
otherwise, the first few samples of data after the sleep bit is DATAZ registers. The DATA_READY and watermark bits may
cleared may have additional noise, especially if the device was require multiple reads, as indicated in the FIFO mode descriptions
asleep when the bit was cleared. in the FIFO section. Other bits, and the corresponding interrupts,
are cleared by reading the INT_SOURCE register.
Wakeup Bits
Register 0x31—DATA_FORMAT (Read/Write)
These bits control the frequency of readings in sleep mode as
D7 D6 D5 D4 D3 D2 D1 D0
described in Table 18.
SELF_TEST SPI INT_INVERT 0 FULL_RES Justify Range
Table 18. Frequency of Readings in Sleep Mode The DATA_FORMAT register controls the presentation of data
Setting to Register 0x32 through Register 0x37. All data, except that for
D1 D0 Frequency (Hz) the ±8 g range, is clipped internally to avoid rollover.
0 0 8
SELF_TEST Bit
0 1 4
1 0 2 A setting of 1 in the SELF_TEST bit applies a self-test force to
1 1 1 the sensor, causing a shift in the output data. A value of 0 disables
the self-test force.
Register 0x2E—INT_ENABLE (Read/Write)
D7 D6 D5 D4 SPI Bit
DATA_READY SINGLE_TAP DOUBLE_TAP Activity A value of 1 in the SPI bit sets the device to 3-wire SPI mode,
D3 D2 D1 D0 and a value of 0 sets the device to 4-wire SPI mode.
Inactivity FREE_FALL Watermark Overrun INT_INVERT Bit
Setting bits in this register to a value of 1 enables their respective A value of 0 in the INT_INVERT bit sets the interrupts to active
functions to generate interrupts, whereas a value of 0 prevents high, and a value of 1 sets the interrupts to active low.
the functions from generating interrupts. The DATA_READY,
FULL_RES Bit
watermark, and overrun bits enable only the interrupt output;
the functions are always enabled. It is recommended that interrupts When this bit is set to a value of 1, the device is in full resolution
be configured before enabling their outputs. mode, where the output resolution increases with the g range
set by the range bits to maintain a 2 mg/LSB scale factor. When
Register 0x2F—INT_MAP (Read/Write)
the FULL_RES bit is set to 0, the device is in 10-bit mode, and
D7 D6 D5 D4
the range bits determine the maximum g range and scale factor.
DATA_READY SINGLE_TAP DOUBLE_TAP Activity
D3 D2 D1 D0 Justify Bit
Inactivity FREE_FALL Watermark Overrun A setting of 1 in the Justify bit selects left (MSB) justified mode,
and a setting of 0 selects right justified mode with sign extension.
Any bits set to 0 in this register send their respective interrupts to
the INT1 pin, whereas bits set to 1 send their respective interrupts Range Bits
to the INT2 pin. All selected interrupts for a given pin are OR’ed. These bits set the g range as described in Table 19.
Register 0x30—INT_SOURCE (Read Only)
Table 19. g Range Setting
D7 D6 D5 D4
Setting
DATA_READY SINGLE_TAP DOUBLE_TAP Activity
D1 D0 g Range
D3 D2 D1 D0
0 0 ±1 g
Inactivity FREE_FALL Watermark Overrun
0 1 ±2 g
1 0 ±4 g
1 1 ±8 g
Data Sheet ADXL350
Register 0x32 to Register 0x37—DATAX0, DATAX1, Samples Bits
DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only)
The function of these bits depends on the FIFO mode selected
These six bytes (Register 0x32 to Register 0x37) are eight bits (see Table 21). Entering a value of 0 in the samples bits immediately
each and hold the output data for each axis. Register 0x32 and sets the watermark status bit in the INT_SOURCE register,
Register 0x33 hold the output data for the x-axis, Register 0x34 and regardless of which FIFO mode is selected. Undesirable operation
Register 0x35 hold the output data for the y-axis, and Register 0x36 may occur if a value of 0 is used for the samples bits when trigger
and Register 0x37 hold the output data for the z-axis. The output mode is used.
data is twos complement, with DATAx0 as the least significant
byte and DATAx1 as the most significant byte, where x represent X, Table 21. Samples Bits Functions
Y, or Z. The DATA_FORMAT register (Address 0x31) controls FIFO Mode Samples Bits Function
the format of the data. It is recommended that a multiple-byte Bypass None.
read of all registers be performed to prevent a change in data FIFO Specifies how many FIFO entries are needed to
between reads of sequential registers. trigger a watermark interrupt.
Stream Specifies how many FIFO entries are needed to
Register 0x38—FIFO_CTL (Read/Write) trigger a watermark interrupt.
D7 D6 D5 D4 D3 D2 D1 D0 Trigger Specifies how many FIFO samples are retained in
FIFO_MODE Trigger Samples the FIFO buffer before a trigger event.
FIFO_MODE Bits
0x39—FIFO_STATUS (Read Only)
These bits set the FIFO mode, as described in Table 20. D7 D6 D5 D4 D3 D2 D1 D0
Table 20. FIFO Modes FIFO_TRIG 0 Entries
Setting FIFO_TRIG Bit
D7 D6 Mode Function
A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring,
0 0 Bypass FIFO is bypassed.
and a 0 means that a FIFO trigger event has not occurred.
0 1 FIFO FIFO collects up to 32 values and then
stops collecting data, collecting new data Entries Bits
only when FIFO is not full.
These bits report how many data values are stored in FIFO.
1 0 Stream FIFO holds the last 32 data values. When
FIFO is full, the oldest data is overwritten Access to collect the data from FIFO is provided through the
with newer data. DATAX, DATAY, and DATAZ registers. FIFO reads must be
1 1 Trigger When triggered by the trigger bit, FIFO done in burst or multiple-byte mode because each FIFO level is
holds the last data samples before the cleared after any read (single- or multiple-byte) of FIFO. FIFO
trigger event and then continues to collect stores a maximum of 32 entries, which equates to a maximum
data until full. New data is collected only of 33 entries available at any given time because an additional
when FIFO is not full.
entry is available at the output filter of the device.
Trigger Bit
A value of 0 in the trigger bit links the trigger event of trigger mode
to INT1, and a value of 1 links the trigger event to INT2.
ADXL350 Data Sheet
APPLICATIONS INFORMATION
POWER SUPPLY DECOUPLING • The maximum tap duration time is defined by the DUR
register (Address 0x21).
A 1 μF tantalum capacitor (CS) at VS and a 0.1 μF ceramic capacitor
• The tap latency time is defined by the latent register
(CIO) at VDD I/O placed close to the ADXL350 supply pins is used
(Address 0x22) and is the waiting period from the end of
for testing and is recommended to adequately decouple the
the first tap until the start of the time window, when a
accelerometer from noise on the power supply. If additional
second tap can be detected, which is determined by the
decoupling is necessary, a resistor or ferrite bead, no larger than
value in the window register (Address 0x23).
100 Ω, in series with VS may be helpful. Additionally, increasing
• The interval after the latency time (set by the latent register) is
the bypass capacitance on VS to a 10 μF tantalum capacitor in
defined by the window register. Although a second tap must
parallel with a 0.1 μF ceramic capacitor may also improve noise.
begin after the latency time has expired, it need not finish
Care should be taken to ensure that the connection from the before the end of the time defined by the window register.
ADXL350 ground to the power supply ground has low impedance
because noise transmitted through ground has an effect similar
FIRST TAP SECOND TAP
to noise transmitted through VS. It is recommended that VS and
VDD I/O be separate supplies to minimize digital clocking noise
on the VS supply. If this is not possible, additional filtering of
XHI BW
THRESHOLD
(THRESH_TAP)
the supplies as previously mentioned may be necessary.
VS VDD I/O
TIME LIMIT FOR
CS CIO TAPS (DUR)
LATENCY TIME WINDOW FOR

VS VDD I/O TIME SECOND TAP (WINDOW)
(LATENT)
ADXL350
INTERRUPTS
SDA/SDI/SDIO
3- OR 4-WIRE
INTERRUPT INT1 SDO/ALT ADDRESS SINGLE TAP DOUBLE TAP
SPI OR I2C
10271-011
CONTROL SCL/SCLK INTERRUPT INTERRUPT
INT2 INTERFACE
GND CS
10271-016
Figure 60. Tap Interrupt Function with Valid Single and Double Taps
Figure 58. Application Diagram If only the single tap function is in use, the single tap interrupt
MECHANICAL CONSIDERATIONS FOR MOUNTING is triggered when the acceleration goes below the threshold, as
long as DUR has not been exceeded. If both single and double
The ADXL350 should be mounted on the PCB in a location tap functions are in use, the single tap interrupt is triggered when
close to a hard mounting point of the PCB to the case. Mounting the double tap event has been either validated or invalidated.
the ADXL350 at an unsupported PCB location, as shown in
Figure 59, may result in large, apparent measurement errors due Several events can occur to invalidate the second tap of a double
to undampened PCB vibration. Locating the accelerometer near tap event. First, if the suppress bit in the TAP_AXES register
a hard mounting point ensures that any PCB vibration at the (Address 0x2A) is set, any acceleration spike above the threshold
accelerometer is above the accelerometer’s mechanical sensor during the latency time (set by the latent register) invalidates
resonant frequency and, therefore, effectively invisible to the the double tap detection, as shown in Figure 61.
accelerometer. INVALIDATES DOUBLE TAP IF
SUPRESS BIT SET
ACCELEROMETERS
PCB
XHI BW
10271-010
MOUNTING POINTS
Figure 59. Incorrectly Placed Accelerometers

10271-012
TIME LIMIT
FOR TAPS LATENCY TIME WINDOW FOR SECOND
TAP DETECTION (DUR) TIME (LATENT) TAP (WINDOW)
The tap interrupt function is capable of detecting either single Figure 61. Double Tap Event Invalid Due to High g Event
When the Suppress Bit Is Set
or double taps. The following parameters are shown in Figure 60
for a valid single and valid double tap event:
• The tap detection threshold is defined by the THRESH_TAP
register (Address 0x1D).
Data Sheet ADXL350
A double tap event can also be invalidated if acceleration above THRESHOLD
the threshold is detected at the start of the time window for the The lower output data rates are achieved by decimating a
second tap (set by the window register). This results in an invalid common sampling frequency inside the device. The activity,
double tap at the start of this window, as shown in Figure 62. free-fall, and single tap/double tap detection functions are
Additionally, a double tap event can be invalidated if an accel- performed using unfiltered data. Since the output data is
eration exceeds the time limit for taps (set by the DUR register), filtered, the high frequency and high g data that is used to
resulting in an invalid double tap at the end of the DUR time determine activity, free-fall, and single tap/double tap events may
limit for the second tap event, also shown in Figure 62. not be present if the output of the accelerometer is examined.
This may result in trigger events being detected when acceleration
INVALIDATES DOUBLE TAP
AT START OF WINDOW does not appear to trigger an event because the unfiltered data
may have exceeded a threshold or remained below a threshold
for a certain period of time while the filtered output data has
not exceeded such a threshold.
XHI BW
LINK MODE
The function of the link bit is to reduce the number of activity
TIME LIMIT
interrupts that the processor must service by setting the device
FOR TAPS
(DUR)
to look for activity only after inactivity. For proper operation of
TIME LIMIT
this feature, the processor must still respond to the activity and
FOR TAPS
(DUR)
LATENCY TIME WINDOW FOR inactivity interrupts by reading the INT_SOURCE register
TIME SECOND TAP (WINDOW)
(LATENT) (Address 0x30) and, therefore, clearing the interrupts. If an activity
TIME LIMIT interrupt is not cleared, the part cannot go into autosleep mode.
FOR TAPS
(DUR) The asleep bit in the ACT_TAP_STATUS register (Address 0x2B)
indicates if the part is asleep.
SLEEP MODE VS. LOW POWER MODE
XHI BW
In applications where a low data rate is sufficient and low power

INVALIDATES
DOUBLE TAP AT
consumption is desired, it is recommended that the low power
mode be used in conjunction with the FIFO. The sleep mode, while
10271-013
END OF DUR
offering a low data rate and low average current consumption,

Figure 62. Tap Interrupt Function with Invalid Double Taps suppresses the DATA_READY interrupt, preventing the accelero-
Single taps, double taps, or both can be detected by setting the meter from sending an interrupt signal to the host processor
respective bits in the INT_ENABLE register (Address 0x2E). when data is ready to be collected. In this application, setting
Control over participation of each of the three axes in single tap/ the part into low power mode (by setting the LOW_POWER bit
double tap detection is exerted by setting the appropriate bits in in the BW_RATE register) and enabling the FIFO in FIFO mode to
the TAP_AXES register (Address 0x2A). For the double tap collect a large value of samples reduces the power consumption
function to operate, both the latent and window registers must of the ADXL350 and allows the host processor to go to sleep
be set to a nonzero value. while the FIFO is filling up.
Every mechanical system has somewhat different single tap/double OFFSET CALIBRATION
tap responses based on the mechanical characteristics of the Accelerometers are mechanical structures containing elements
system. Therefore, some experimentation with values for the that are free to move. These moving parts can be very sensitive
latent, window, and THRESH_TAP registers is required. In to mechanical stresses, much more so than solid-state electronics.
general, a good starting point is to set the latent register to a The 0 g bias or offset is an important accelerometer metric because
value greater than 0x10, to set the window register to a value it defines the baseline for measuring acceleration. Additional
greater than 0x10, and to set the THRESH_TAP register to be stresses can be applied during assembly of a system containing
greater than 3 g. Setting a very low value in the latent, window, or an accelerometer. These stresses can come from, but are not
THRESH_TAP register may result in an unpredictable response limited to, component soldering, board stress during mounting,
due to the accelerometer picking up echoes of the tap inputs. and application of any compounds on or over the component. If
After a tap interrupt has been received, the first axis to exceed calibration is deemed necessary, it is recommended that calibration
the THRESH_TAP level is reported in the ACT_TAP_STATUS be performed after system assembly to compensate for these effects.
register (Address 0x2B). This register is never cleared, but is A simple method of calibration is to measure the offset while
overwritten with new data. assuming that the sensitivity of the ADXL350 is as specified in
Table 1. The offset can then be automatically accounted for by
ADXL350 Data Sheet
using the built-in offset registers. This results in the data acquired registers in the ADXL350, the offset registers do not retain the
from the DATA registers already compensating for any offset. value written into them when power is removed from the part.
In a no-turn or single-point calibration scheme, the part is oriented Power cycling the ADXL350 returns the offset registers to their
such that one axis, typically the z-axis, is in the 1 g field of gravity default value of 0x00.
and the remaining axes, typically the x-axis and y-axis, are in a Because the no-turn or single-point calibration method assumes an
0 g field. The output is then measured by taking the average of a ideal sensitivity in the z-axis, any error in the sensitivity results in
series of samples. The number of samples averaged is a choice of offset error. To help minimize this error, an additional measure-
the system designer, but a recommended starting point is 0.1 sec ment point can be used with the z-axis in a 0 g field and the 0 g
worth of data for data rates of 100 Hz or greater. This corresponds measurement can be used in the ZACTUAL equation.
to 10 samples at the 100 Hz data rate. For data rates less than
USING SELF-TEST
100 Hz, it is recommended that at least 10 samples be averaged
together. These values are stored as X0g, Y0g, and Z+1g for the 0 g The self-test change is defined as the difference between the
measurements on the x-axis and y-axis and the 1 g measure- acceleration output of an axis with self-test enabled and the
ment on the z-axis, respectively. acceleration output of the same axis with self-test disabled (see
Endnote 4 of Table 1). This definition assumes that the sensor
The values measured for X0g and Y0g correspond to the x- and y-axis does not move between these two measurements, because if the
offset, and compensation is done by subtracting those values from sensor moves, a non-self-test related shift corrupts the test.
the output of the accelerometer to obtain the actual acceleration.
Proper configuration of the ADXL350 is also necessary for an
XACTUAL = XMEAS − X0g accurate self-test measurement. The part should be set with a
YACTUAL = YMEAS − Y0g data rate that is greater than or equal to 100 Hz. This is done by
Because the z-axis measurement was done in a +1 g field, a no-turn ensuring that a value greater than or equal to 0x0A is written
or single-point calibration scheme assumes an ideal sensitivity, into the rate bits (Bit D3 through Bit D0) in the BW_RATE
SZ for the z-axis. This is subtracted from Z+1g to attain the z-axis register (Address 0x2C).
offset, which is then subtracted from future measured values to It is also recommended that the part be set to ±8 g mode to
obtain the actual value: ensure that there is sufficient dynamic range for the entire self-test
Z0g = Z+1g − SZ shift. This is done by setting Bit D3 of the DATA_FORMAT
register (Address 0x31) and writing a value of 0x03 to the range
ZACTUAL = ZMEAS − Z0g bits (Bit D1 and Bit D0) of the DATA_FORMAT register (Address
The ADXL350 can automatically compensate the output for offset 0x31). This results in a high dynamic range for measurement and
by using the offset registers (Register 0x1E, Register 0x1F, and a 2 mg/LSB scale factor.
Register 0x20). These registers contain an 8-bit, twos complement After the part is configured for accurate self-test measurement,
value that is automatically added to all measured acceleration several samples of x-, y-, and z-axis acceleration data should be
values, and the result is then placed into the DATA registers. retrieved from the sensor and averaged together. The number of
Because the value placed in an offset register is additive, a negative samples averaged is a choice of the system designer, but a recom-
value is placed into the register to eliminate a positive offset and mended starting point is 0.1 sec worth of data, which corresponds
vice versa for a negative offset. The register has a scale factor of to 10 samples at 100 Hz data rate. The averaged values should
7.8 mg/LSB and is independent of the selected g-range. be stored and labeled appropriately as the self-test disabled data,
As an example, assume that the ADXL350 is placed into full- that is, XST_OFF, YST_OFF, and ZST_OFF.
resolution mode with a sensitivity of typically 512 LSB/g. The Next, self-test should be enabled by setting Bit D7 of the
part is oriented such that the z-axis is in the field of gravity and DATA_FORMAT register (Address 0x31). The output needs
x-, y-, and z-axis outputs are measured as +10 LSB, −13 LSB, some time (about four samples) to settle after enabling self-test.
and +9 LSB, respectively. Using the previous equations, X0g is After allowing the output to settle, several samples of the x-, y-,
+10 LSB, Y0g is −13 LSB, and Z0g is +9 LSB. Each LSB of output and z-axis acceleration data should be taken again and averaged. It
in full-resolution is 1.95 mg or one-quarter of an LSB of the is recommended that the same number of samples be taken for
offset register. Because the offset register is additive, the 0 g this average as was previously taken. These averaged values should
values are negated and rounded to the nearest LSB of the offset again be stored and labeled appropriately as the value with self-
register: test enabled, that is, XST_ON, YST_ON, and ZST_ON. Self-test can then
XOFFSET = −Round(10/4) = −3 LSB be disabled by clearing Bit D7 of the DATA_FORMAT register
YOFFSET = −Round(−13/4) = 3 LSB (Address 0x31).
ZOFFSET = −Round(9/4) = −2 LSB

These values are programmed into the OFSX, OFSY, and OFXZ
registers, respectively, as 0xFD, 0x03, and 0xFE. As with all
Data Sheet ADXL350
With the stored values for self-test enabled and disabled, the Although the fixed 10-bit mode or a range other than 8 g can be
self-test change is as follows: used, a different set of values, as indicated in Table 14 through
XST = XST_ON − XST_OFF Table 16, would need to be used. Using a range below 8 g may
result in insufficient dynamic range and should be considered
YST = YST_ON − YST_OFF when selecting the range of operation for measuring self-test. In
ZST = ZST_ON − ZST_OFF addition, note that the range in Table 1 and the values in Table 13
Because the measured output for each axis is expressed in LSBs, through Table 16 take into account all possible supply voltages, VS,
XST, YST, and ZST are also expressed in LSBs. These values can be and no additional conversion due to VS is necessary.
converted to g’s of acceleration by multiplying each value by the If the self-test change is within the valid range, the test is considered
2 mg/LSB scale factor, if configured for full-resolution, 8 g mode. successful. Generally, a part is considered to pass if the minimum
Additionally, Table 13 through Table 16 correspond to the self- magnitude of change is achieved. However, a part that changes
test range converted to LSBs and can be compared with the by more than the maximum magnitude is not necessarily a failure.
measured self-test change. If the part was placed into full-
resolution, 8 g mode, the values listed in Table 13 should be used.
ADXL350 Data Sheet
AXES OF ACCELERATION SENSITIVITY
AZ
AY
10271-021
AX
Figure 63. Axes of Acceleration Sensitivity (Corresponding Output Voltage Increases When Accelerated Along the Sensitive Axis)
XOUT = 0g
YOUT = 1g
ZOUT = 0g
GRAVITY
XOUT = 1g XOUT = –1g
YOUT = 0g YOUT = 0g
ZOUT = 0g ZOUT = 0g
XOUT = 0g
YOUT = –1g
ZOUT = 0g XOUT = 0g XOUT = 0g
10271-022
YOUT = 0g YOUT = 0g
ZOUT = 1g ZOUT = –1g
Figure 64. Output Response vs. Orientation to Gravity
Data Sheet ADXL350
LAYOUT AND DESIGN RECOMMENDATIONS
Figure 65 shows the recommended printed wiring board land pattern. Figure 66 and Table 22 provide details about the recommended
soldering profile.
0.3mm
0.8mm
3.35mm
0.5mm
10271-044
3.53mm
Figure 65. Recommended Printed Wiring Board Land Pattern

(Dimensions shown in millimeters)
CRITICAL ZONE
tP TL TO TP
TP
RAMP-UP
TL
TEMPERATURE
TSMAX tL
TSMIN
tS
PREHEAT RAMP-DOWN
10271-015
t25°C TO PEAK
TIME
Figure 66. Recommended Soldering Profile
Table 22. Recommended Soldering Profile 1, 2

Condition
Profile Feature Sn63/Pb37 Pb-Free
Average Ramp Rate from Liquid Temperature (TL) to Peak Temperature (TP) 3°C/sec max 3°C/sec max
Preheat
Minimum Temperature (TSMIN) 100°C 150°C
Maximum Temperature (TSMAX) 150°C 200°C
Time from TSMIN to TSMAX (tS) 60 sec to 120 sec 60 sec to 180 sec
TSMAX to TL Ramp-Up Rate 3°C/sec max 3°C/sec max
Liquid Temperature (TL) 183°C 217°C
Time Maintained Above TL (tL) 60 sec to 150 sec 60 sec to 150 sec
Peak Temperature (TP) 240 + 0/−5°C 260 + 0/−5°C
Time of Actual TP − 5°C (tP) 10 sec to 30 sec 20 sec to 40 sec
Ramp-Down Rate 6°C/sec max 6°C/sec max
Time 25°C to Peak Temperature 6 minutes max 8 minutes max
1
Based on JEDEC Standard J-STD-020D.1.
2
For best results, the soldering profile should be in accordance with the recommendations of the manufacturer of the solder paste used.
ADXL350 Data Sheet
OUTLINE DIMENSIONS
4.10
4.00 0.25 REF
3.90
3.40 REF 0.86 0.50 BSC
REFERENCE R 0.10 BSC
CORNER REF
0.22 BSC
0.62 × 0.25 13 14
(PINS 1-5, 9-13) 16 1 0.50
3.10 BSC
3.00
2.90
0.25
2.40 0.10 DIA. REF
REF (Vent Hole)
9 8 6 5
0.50
REF
R 0.60
REF TOP VIEW BOTTOM VIEW 0.64
0.25 × 0.35 0.13 REF
R 0.18 REF (PINS 6-8, 14-16)
1.30
1.20
1.10
07-13-2012-B
SIDE VIEW
0.24 REF
Figure 67. 16-Terminal Chip Array, Small Outline, No Lead Cavity [LGA_CAV]
4.00 mm × 3.00 mm × 1.2 mm Body
(CE-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Measurement Specified Temperature Package
Model 1 Range (g) Voltage (V) Range Package Description Option
ADXL350BCEZ-RL ±1, ±2, ±4, ±8 2.5 −40°C to +85°C 16-Terminal [LGA_CAV] CE-16-3
ADXL350BCEZ-RL7 ±1, ±2, ±4, ±8 2.5 −40°C to +85°C 16-Terminal [LGA_CAV] CE-16-3
EVAL-ADXL350Z Evaluation Board
EVAL-ADXL350Z-M Analog Devices Inertial Sensor Evaluation
System, Includes ADXL350 Satellite
EVAL-ADXL350Z-S ADXL350 Satellite, Standalone
1
Z = RoHS Compliant Part.
Data Sheet ADXL350
NOTES
ADXL350 Data Sheet
NOTES
©2012 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D10271-0-9/12(0)

Adxl350bcez RL7

Uploaded by

Copyright:

Available Formats

Adxl350bcez RL7

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Adxl350bcez RL7

Uploaded by

Copyright:

Available Formats

3-Axis, ±1g/±2g/±4g/±8g

FUNCTIONAL BLOCK DIAGRAM

Rev. 0 Document Feedback

Applications ....................................................................................... 1 FIFO ............................................................................................. 21

General Description ......................................................................... 1 Self-Test ....................................................................................... 22

Functional Block Diagram .............................................................. 1 Register Map ................................................................................... 23

Revision History ............................................................................... 2 Register Definitions ................................................................... 24

Specifications..................................................................................... 3 Applications Information .............................................................. 28

Absolute Maximum Ratings ............................................................ 4 Power Supply Decoupling ......................................................... 28

Thermal Resistance ...................................................................... 4 Mechanical Considerations for Mounting .............................. 28

Package Information .................................................................... 4 Tap Detection .............................................................................. 28

ESD Caution .................................................................................. 4 Threshold .................................................................................... 29

Pin Configuration and Function Descriptions ............................. 5 Link Mode ................................................................................... 29

Theory of Operation ...................................................................... 14 Offset Calibration ....................................................................... 29

Power Sequencing ...................................................................... 14 Using Self-Test ............................................................................ 30

Power Savings.............................................................................. 15 Axes of Acceleration Sensitivity ............................................... 32

Serial Communications ................................................................. 16 Layout and Design Recommendations ................................... 33

SPI ................................................................................................. 16 Outline Dimensions ....................................................................... 34

I2C ................................................................................................. 19 Ordering Guide .......................................................................... 34

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

TYPICAL PERFORMANCE CHARACTERISTICS

PERCENT OF POPULATION (%)

PERCENT OF POPULATION (%)

PERCENT OF POPULATION (%)

ZERO g OFFSET (mg) ZERO g OFFSET (mg)

–60 –40 –20 0 20 40 60 80 100

–60 –40 –20 0 20 40 60 80 100

–60 –40 –20 0 20 40 60 80 100

–60 –40 –20 0 20 40 60 80

PERCENT OF POPULATION (%)

PERCENT OF POPULATION (%)

PERCENT OF POPULATION (%)

PERCENT OF POPULATION (%)

–60 –40 –20 0 20 40 60 80 100 –60 –40 –20 0 20 40 60 80 100

PERCENT OF POPULATION (%)

PERCENT OF POPULATION (%)

PERCENT OF POPULATION (%)

Figure 47. Current Consumption vs. Output Data Rate at 25°C

Table 6. Power Sequencing

Figure 50. 4-Wire SPI Connection Diagram

Table 9. SPI Digital Input/Output Voltage

tSCLK tM tS tQUIET tCS,DIS

tSDO ADDRESS BITS DATA BITS tDIS

Figure 52. SPI 4-Wire Write

tSCLK tM tS tQUIET tCS,DIS

tSDO ADDRESS BITS tDIS

Figure 53. SPI 4-Wire Read

tSETUP tHOLD tSDO

ADDRESS BITS DATA BITS

Figure 54. SPI 3-Wire Read/Write

Figure 55. I2C Connection Diagram (Address 0x53)

Figure 56. I2C Device Addressing

Figure 57. I2C Timing Diagram

INTERRUPTS register (Address 0x29). The FREE_FALL interrupt differs from

Inactivity Stream Mode

LATENCY TIME WINDOW FOR