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HIGH-VOLTAGE MIXED-SIGNAL IC
65x132 STN Controller-Driver
MP Specifications November 7, 2008

Revision 1.0
ULTRACHIP
The Coolest LCD Driver, Ever!
UC1701X
65x132 STN Controller-Drivers
Table of Content
INTRODUCTION .................................................................................................................3
MAIN APPLICATIONS .........................................................................................................3
FEATURE HIGHLIGHTS .......................................................................................................3
ORDERING INFORMATION ..................................................................................................4
BLOCK DIAGRAM ..............................................................................................................5
PIN DESCRIPTION .............................................................................................................6
RECOMMENDED COG LAYOUT ..........................................................................................9
CONTROL REGISTERS .....................................................................................................10
COMMAND TABLE ...........................................................................................................12
COMMAND DESCRIPTION .................................................................................................13
LCD VOLTAGE SETTING..................................................................................................18
VLCD QUICK REFERENCE .................................................................................................19
LCD DISPLAY CONTROLS ...............................................................................................21
ITO LAYOUT AND LC SELECTION ....................................................................................22
HOST INTERFACE ............................................................................................................25
DISPLAY DATA RAM (DDRAM) ......................................................................................29
RESET & POWER MANAGEMENT ......................................................................................31
ESD CONSIDERATION .....................................................................................................36
ABSOLUTE MAXIMUM RATINGS ........................................................................................37
SPECIFICATIONS .............................................................................................................38
AC CHARACTERISTICS ....................................................................................................39
PHYSICAL DIMENSIONS ...................................................................................................43
ALIGNMENT MARK INFORMATION .....................................................................................44
PAD COORDINATES.........................................................................................................45
TRAY INFORMATION ........................................................................................................47
REVISION HISTORY .........................................................................................................48
Revision A1.0 2
UC1701X
UC1701x
Single-Chip, Ultra-Low Power
65COM by 132SEG
Passive Matrix LCD Controller-Driver
INTRODUCTION
UC1701x is an advanced high-voltage mixed- • Support industry standard 8-bit parallel bus
signal CMOS IC, especially designed for the (8080 or 6800 mode) and 4-wire serial bus
display needs of ultra-low power hand-held (S8) interface.
devices.
• Ultra-low power consumption under all
This chip employs UltraChip’s unique DCC display patterns.
(Direct Capacitor Coupling) driver architecture to
achieve near crosstalk free images. • Fully programmable Mux Rate and Bias
Ratio allow many flexible power
In addition to low power column and row drivers, management options.
the IC contains all necessary circuits for high-V
LCD power supply, bias voltage generation, • 7-x internal charge pump with on-chip
timing generation and graphics data memory. pumping capacitor requires only 3 external
capacitors to operate.
Advanced circuit design techniques are
employed to minimize external component counts • On-chip Power-ON Reset and Software
and reduce connector size while achieving RESET commands, make RST pin optional.
extremely low power consumption.
• Very low pin count (10-pin) allows
exceptional image quality in COG format on
conventional ITO glass.
MAIN APPLICATIONS
• Flexible data addressing/mapping schemes
• Cellular Phones, Smart Phones, PDA, and to support wide ranges of software models
other battery operated palm top devices or
and LCD layout placements.
portable Instruments
• VDD range (Typ.): 1.8V ~ 3.3V
VDD2/3 range(Typ.): 2.5V ~ 3.3V
FEATURE HIGHLIGHTS LCD VOP range: 3.9V ~ 11.5V
• Single chip controller-driver support 65x132 • Available in gold bump dies
graphics STN LCD panels.
• COM/SEG bump information
• Support both row ordered and column Bump pitch: 27 µM
ordered display buffer RAM access. Bump gap: 12 µM
2
Bump surface: 2077.5 µM
Revision A1.0 3
ULTRACHIP
High-Voltage Mixed-Signal IC ©1999~2008
ORDERING INFORMATION
2
Part Number IC Description
UC1701xGAA No Gold Bumped Die
General Notes
APPLICATION INFORMATION
For improved readability, the specification contains many application data points. When application information is given, it
is advisory and does not form part of the specification for the device.
BARE DIE DISCLAIMER

All die are tested and are guaranteed to comply with all data sheet limits up to the point of. There is no post waffle
saw/pack testing performed on individual die. Although the latest modern processes are utilized for wafer sawing and die
pick-&-place into waffle pack carriers, UltraChip has no control of third party procedures in the handling, packing or
assembly of the die. Accordingly, it is the responsibility of the customer to test and qualify their application in which the die
is to be used. UltraChip assumes no liability for device functionality or performance of the die or systems after handling,
packing or assembly of the die.
LIFE SUPPORT APPLICATIONS

These devices are not designed for use in life support appliances, or systems where malfunction of these products can
reasonably be expected to result in personal injuries. Customer using or selling these products for use in such
applications do so at their own risk.
CONTENT DISCLAIMER
UltraChip believes the information contained in this document to be accurate and reliable. However, it is subject to change
without notice. No responsibility is assumed by UltraChip for its use, nor for infringement of patents or other rights of third
parties. No part of this publication may be reproduced, or transmitted in any form or by any means without the prior
consent of UltraChip Inc. UltraChip's terms and conditions of sale apply at all times.
CONTACT DETAILS
UltraChip Inc. (Headquarter) Tel: +886 (2) 8797-8947
2F, No. 70, Chowtze Street, Fax: +886 (2) 8797-8910
Nei Hu District, Taipei 114, Sales e-mail: [email protected]
Taiwan, R. O. C. Web site: http://www.ultrachip.com
4 MP Specifications
UC1701X
BLOCK DIAGRAM
COLUMN ADDRESS
GENERATOR
POWER ON &
PAGE ADDRESS GENERATOR
ROW ADDRESS GENERATOR

RESET
DATA RAM I/O BUFFER

CONTROL
LEVEL SHIFTER
COM DRIVERS
CLOCK & DISPLAY DATA RAM
TIMING
GENERATOR
CONTROL &
STATUS
REGISTER
DISPLAY DATA LATCHES
COMMAND LEVEL SHIFTERS VLCD & BIAS CL

GENERATOR
HOST INTERFACE SEG DRIVERS
CB0 CB1
Revision A1.0 5
ULTRACHIP
PIN DESCRIPTION
Name Type Pins Description
MAIN POWER SUPPLY
VDD supplies for Display Data RAM and digital logic, VDD2 supplies for
VLCD and VD generator, VDD3 supplies for VBIAS and other analog circuits.
VDD 3 VDD2/VDD3 should be connected to the same power source. But VDD can
VDD2 PWR 4 be connected to a source voltage no higher than VDD2/VDD3.
VDD3 2 Please maintain the following relationship:
VDD+1.3V VDD2/3 VDD
ITO trace resistance needs to be minimized for VDD2/VDD3.
VSS 2 Ground. Connect VSS and VSS2 to the shared GND pin. In COG
GND
VSS2 4 applications, minimize the ITO resistance for both VSS and VSS2.
LCD POWER SUPPLY & VOLTAGE CONTROL
LCD Bias Voltages. These are the voltage sources to provide SEG
VB0+ 2 driving currents. These voltages are generated internally. Connect
VB0– 2 capacitors of CBX value between VBX+ and VBX–.
PWR
VB1+ 4 In COG application, the resistance of these ITO traces directly affects the
VB1– 2 SEG driving strength of the resulting LCD module. Minimize these trace
resistance is critical in achieving high quality image.
Main LCD Power Supply. When VLCD is used, connect these pins
VLCDIN 2 together.
PWR
VLCDOUT 2 By-pass capacitor CL is optional. It can be connected between VLCD and
VSS. When CL is used, keep the ITO trace resistance around 70~100 Ω.
NOTE
• Recommended capacitor values:
CB: 2.2µF/5V or 100~250x(LCD load capacitance).
CL: 330nF/25V is appropriate for most applications.
6 MP Specifications
UC1701X

HOST INTERFACE
Bus mode: The interface bus mode is determined by BM[1:0] and
{D7, D6} by the following relationship:
BM[1:0] {D7, D6} Mode
BM0 1
I 11 Data 6800/8-bit
BM1 1
10 Data 8080/8-bit
4-wire SPI w/ 8-bit token
0x SDA, SCK
(S8: conventional)
Chip Select. Chip is selected when CS0 = “L”. When the chip is not
CS0 I 1
selected, D[7:0] will be of high impedance.
When RST=”L”, all control registers are re-initialized by their default states.
Since UC1701x has built-in Power-On Reset and Software Reset command,
RST I 1 RST pin is not required for proper chip operation.
An RC Filter has been included on-chip. There is no need for external RC
noise filter. When RST is not used, connect the pin to VDD.
Select Control data or Display data for read/write operation.
CD I 1
”L”: Control data ”H”: Display data
WR [1:0] controls the read/write operation of the host interface. See Host
Interface section for details.
WR0 1
I In parallel mode, the meaning of WR[1:0] depends on which interface it is in,
WR1 1
6800 or 8080 mode. In serial interface modes, these two pins are not used,
Connect them to VSS or VDD.
Duty selection.
DT2 DT1 Duty
DT1 1 0 0 1/65
I
DT2 1 0 1 1/49
1 0 1/33
1 1 1/55
Bi-directional bus for both serial and parallel host interfaces.
In serial modes, connect D[7] to SDA, D[6] to SCK.
D7 D6 D5 D4 D3 D2 D1 D0
D7~D0 I/O 8
BM=1x (8-bit) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BM=0x (S8) SDA SCK -- -- -- -- -- --
Always connect unused pins to either VSS or VDD.
HIGH VOLTAGE LCD DRIVER OUTPUT
SEG1 ~ SEG (column) driver outputs. Support up to 132 pixels.
HV 132
SEG132 Leave unused SEG drivers open-circuit.
COM (row) driver outputs. Support up to 64 rows.
COM1 ~ When designing LCM, always start from COM1. If the LCM has N pixel
HV 64
COM64 rows and N is less than 64, set CEN to be N-1, and leave COM drivers
[N+1 ~ 64] open-circuit.
CIC HV 2 Icon driver outputs. Leave it open if not used.
Revision A1.0 7
ULTRACHIP

MISC. PINS
Auxiliary VDD. This pin is connected to the main VDD bus within the IC. It’s
provided to facilitate chip configurations in COG application.
VDDX 4
There’s no need to connect VDDX to main VDD externally and it should NOT
be used to provide VDD power to the chip.
Test control. There’s an on-chip pull-up resistor for TST4. Leave it open
TST4 I 1
during normal use.
TST2 I/O 1 Test I/O pins. Leave these pins open during normal use.
Dummy 11 Dummy pins are NOT connected inside the IC.
Note: Several control registers will specify “0 based index” for COM and SEG electrodes. In those
situations, COMX or SEGX will correspond to index X-1, and the value range for those index register will be
0~63 for COM and 0~131 for SEG.
8 MP Specifications
UC1701X
RECOMMENDED COG LAYOUT
CS0
RST
CD COM<54> COM<53>
COM<55> COM<52>
COM<56>
WR0
COM<51>
COM<57> COM<50>
COM<58> COM<49>
COM<59> COM<48>
COM<60> COM<47>
WR1
COM<61> COM<46>
COM<62> COM<45>
COM<63> COM<44>
COM<64> COM<43>
CIC COM<42>
D0
COM<41>
COM<40>
COM<39>
TST4
COM<38>
UC1701x Bump View

COM<37>
D1
CS0
COM<36>
COM<35>
RST COM<34>
COM<33>
D2
CD
SEG<132>
SEG<131>
WR0 SEG<130>
SEG<129>
D3
SEG<128>
WR1
SEG<127>
SEG<126>
VDDX SEG<125>
SEG<124>
D4
D0 SEG<123>
SEG<122>
SEG<121>
D1
SEG<120>
SEG<119>
D5
D2 SEG<118>
SEG<117>
SEG<116>
D3
SEG<115>
SEG<114>
D6
D4 SEG<113>
SEG<112>
SEG<111>
D5
SEG<110>
SEG<109>
D7
D6
SEG<108>
SEG<107>
D7 SEG<106>
SEG<105>
SEG<104>
VDD1
SEG<103>
SEG<102>
VDD1 SEG<101>
SEG<100>
SEG<99>
VDD
VDD2
SEG<98>
SEG<97>
VDD2
SEG<96>
SEG<95>
VDD2 SEG<94>
SEG<93>
SEG<92>
VDD3
SEG<91>
SEG<90>
VSS1 SEG<89>
SEG<88>
SEG<87>
VSS1
SEG<86>
SEG<85>
VSS2
VSS
SEG<84>
SEG<83>
VSS2 SEG<82>
SEG<81>
SEG<80>
VSS2
SEG<79>
SEG<78>
VSS2 SEG<77>
SEG<76>
SEG<75>
VB1+
SEG<74>
SEG<73>
VB1+
SEG<72>
SEG<71>
DUMMY SEG<70>
SEG<69>
SEG<68>
VB0+
VB0+
SEG<67>
SEG<66>
VB0+ SEG<65>
SEG<64>
SEG<63>
VB0-
VB0-
SEG<62>
SEG<61>
VB0- SEG<60>
SEG<59>
DUMMY SEG<58>
SEG<57>
SEG<56>
VB1-
VB1-
SEG<55>
SEG<54>
VB1- SEG<53>
SEG<52>
SEG<51>
VB1+
VB1+
SEG<50>
SEG<49>
VB1+ SEG<48>
SEG<47>
SEG<46>
VLCDIN
VLCDIN
SEG<45>
SEG<44>
VLCDIN
SEG<43>
SEG<42>
VLCDOUT SEG<41>
VLCDOUT
SEG<40>
SEG<39>
VLCDOUT
SEG<38>
SEG<37>
DUMMY
SEG<36>
SEG<35>
DUMMY
SEG<34>
SEG<33>
DUMMY
SEG<32>
SEG<31>
DUMMY SEG<30>
SEG<29>
DUMMY SEG<28>
SEG<27>
DUMMY SEG<26>
SEG<25>
DUMMY SEG<24>
SEG<23>
DUMMY SEG<22>
SEG<21>
DUMMY SEG<20>
SEG<19>
TST2 SEG<18>
SEG<17>
BM0 VSSX
SEG<16>
SEG<15>
SEG<14>
VDDX SEG<13>
BM1
SEG<12>
SEG<11>
BM0
SEG<10>
SEG<9>
BM1 SEG<8>
DT1
SEG<7>
SEG<6>
DT1
SEG<5>
SEG<4>
VSSX
SEG<3>
DT2
SEG<2>
DT2 SEG<1>
CIC
VDD1
COM<1>
COM<2>
VDD2 COM<3>
COM<4>
COM<5>
VDD3
COM<6>
COM<7>
COM<8>
COM<32> COM<9>
COM<31> COM<10>
COM<30> COM<11>
COM<29> COM<12>
COM<28> COM<13>
COM<27> COM<14>
COM<26> COM<15>
COM<25> COM<16>
COM<24> COM<17>
COM<23> COM<18>
COM<22> COM<19>
COM<21> COM<20>
NOTES FOR VDD WITH COG:

The operation condition, VDD=1.8V (typical), should be satisfied under all operating conditions. UC1701x’s
peak current (IDD) can be up to ~15mA during high speed data-write to UC1701x’s on-chip SRAM. Such high
pulsing current mandates very careful design of VDD and VSS ITO trances in COG modules. When VDD and
VSS trace resistance is not low enough, the pulsing IDD current can cause the actual on-chip VDD to drop to
below 1.65V and cause the IC to malfunction.
Revision A1.0 9
ULTRACHIP
CONTROL REGISTERS
UC1701x contains registers, which control the chip operation. The following table is a summary of these
control registers, a brief description and the default values. These registers can be modified by commands,
which will be described in the next two sections, Command Table and Command Description.
Name: The Symbolic reference of the register.
Note that, some symbol name refers to bits (flags) within another register.
Default: Numbers shown in Bold font are default values after Power-Up-Reset and System-Reset.
Name Bits Default Description

SL 6 00H Scroll Line. Scroll the displayed image up by SL rows. The valid SL value is
between 0 (for no scrolling) and 63. Setting SL outside of this range causes
undefined effects on the displayed image. This register does not affect icon
output CIC.
CA 8 00H Column Address of DDRAM (Display Data RAM). Value range is 0~131.
(Used in Host to access DDRAM)
PA 4 0H Page Address of DDRAM. Value range 0~8.
(Used in Host to access DDRAM)
BR 1 0H Bias Ratio.
The ratio between VLCD and VBIAS varies according to Duty selected:
BR=0 BR=1
Duty=1/65 1/9 1/7
Duty=1/49 1/8 1/6
Duty=1/33 1/6 1/5
Duty=1/55 1/8 1/6
PM 6 20H Adjust contrast of LCD panel display.
PC 6 20H Power Control.
PC [0] : Voltage Follower. (Default 0: OFF)
PC [1] : Voltage Regular. (Default 0: OFF)
PC [2] : Booster Ratio. (Default 0: OFF)
PC [5:3]: Resistor Ratio for VLCD. (Default 100b)
000b~111b : Rb/Ra ratio setting
CR 8 0H Return Column Address. Useful for cursor implementation.
AC3 1 0H Address Control.
AC3: CUM: Cursor update mode, (Default 0: OFF)
When CUM=1, CA increment on write only, wrap around suspended
DC 3 0H Display Control:
DC[0]: PXV: Pixels Inverse (bit-wise data inversion. Default 0: OFF)
DC[1]: APO: All Pixels ON (Default 0: OFF)
DC[2]: Display ON/OFF (Default 0: OFF)
When DC[2] is set to 0, the IC will enter Sleep Mode
LC 2 0H LCD Control:
LC[0]: MX, Mirror X SEG/Column sequence inversion (Default: OFF)
LC[1]: MY, Mirror Y COM/Row sequence inversion (Default: OFF)
10 MP Specifications
UC1701X
Name Bits Default Description

Advanced Program Control. For UltraChip only. Do NOT use.
o
APC0 [7] : TC, VBIAS temperature compensation coefficient (%-per- C)
o
0b : TC curve definition = -0.05% / C
o
APC0 8 90H 1b : TC curve definition = -0.11% / C
APC1 8 -- APC0 [1:0] : WA, automatic column/row Wrap Around.
WA[0] : 0: PA wrap around disable 1: PA wrap around enable.
WA[1] : 0: CA wrap around disable 1: CA wrap around enable.
APC1[7:0] : For UltraChip’s use only.
Status Registers
BZ, 1 0 BZ : Set to 1 when system is busy. Commands can only be accepted when
MX, BZ=0.
DE, MX : Mirror X-axle (i.e. SEG or column)
RST DE : Set to 1 when display enabled.
RST : Reset flag. RST=1 when reset is in progress.
Revision A1.0 11
ULTRACHIP
COMMAND TABLE
The following is a list of host commands supported by UC1701x
C/D: 0: Control, 1: Data
W/R: 0: Write Cycle, 1: Read Cycle
# Useful Data bits – Don’t Care
Command C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Action Default
1. Write Data Byte 1 0 # # # # # # # # Write 1 byte N/A
2. Read Data Byte 1 1 # # # # # # # # Read 1 byte N/A
3. Get Status 0 1 BZ MX DE RST 0 0 0 0 Get Status --
Set Column Address LSB 0 0 0 0 # # # # Set CA [3:0] 0
4. 0 0
Set Column Address MSB 0 0 0 1 # # # # Set CA [7:4] 0
5. Set Power Control 0 0 0 0 1 0 1 # # # Set PC[2:0] 000b
6. Set Scroll Line 0 0 0 1 # # # # # # Set SL[5:0] 0
7. Set Page Address 0 0 1 0 1 1 # # # # Set PA[3:0] 0
8. Set VLCD Resistor Ratio 0 0 0 0 1 0 0 # # # Set PC[5:3] 100b
Set Electronic Volume 1 0 0 0 0 0 0 1
9. 0 0
(double-byte command) 0 0 # # # # # # Set PM[5:0] 20H
10. Set All-Pixel-ON 0 0 1 0 1 0 0 1 0 # Set DC[1] 0b
11. Set Inverse Display 0 0 1 0 1 0 0 1 1 # Set DC[0] 0b
12. Set Display Enable 0 0 1 0 1 0 1 1 1 # Set DC[2] 0b
13. Set SEG Direction 0 0 1 0 1 0 0 0 0 # Set LC[0] 0b
14. Set COM Direction 0 0 1 1 0 0 # - - - Set LC[1] 0b
15. System Reset 0 0 1 1 1 0 0 0 1 0 System Reset N/A
16. NOP 0 0 1 1 1 0 0 0 1 1 No operation N/A
17. Set LCD Bias Ratio 0 0 1 0 1 0 0 0 1 # Set BR 0b
18. Set Cursor Update Mode 0 0 1 1 1 0 0 0 0 0 AC3=1, CR=CA N/A
19. Reset Cursor Update Mode 0 0 1 1 1 0 1 1 1 0 AC3=0, CA=CR. N/A
20. Set Static Indicator OFF 0 0 1 0 1 0 1 1 0 0 NOP N/A
Set Static Indicator ON 1 0 1 0 1 1 0 1
21. 0 0 NOP N/A
Set Static Indicator - - - - - - - -
Set Booster Ratio 1 1 1 1 1 0 0 0
22. 0 0 NOP 00b
(double-byte command) 0 0 0 0 0 0 # #
Set Power Save Display OFF &
23. 0 0 # # # # # # # # N/A
(compound command) All Pixel ON
Set Test Control 1 1 1 1 1 1 TT For UCI only
24. 0 0 N/A
(double-byte command) - # # # # # # # Do NOT use
25. Set Adv. Program Control 0 1 1 1 1 1 0 1 0
0 0
(double-byte command) # 0 0 1 0 0 # # Set TC, WA[1:0] 90H
26. Set Adv. Program Control 1 1 1 1 1 1 0 1 1 For UCI only
0 0
(double-byte command) # # # # # # # # Set APC1 N/A
* Other than commands listed above, all other bit patterns result in NOP (No Operation).
UC1701X
COMMAND DESCRIPTION
1. Write Data Byte to Memory
Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Write data 1 0 8-bit data write to SRAM
2. Read Data Byte from Memory

Read data 1 1 8-bit data read from SRAM
Write/Read Data Byte (Command 1,2) access Display Data RAM based on Page Address (PA) register and
Column Address (CA) register. PA and CA can also be programmed directly by issuing Set Page Address
and Set Column Address commands.
3. Get Status

Get Status 0 1 BZ MX DE RST 0 0 0 0
BZ: BZ=1 when busy. The system accepts commands only when BZ=0.
MX: Mirror X. Status of register LC[0]
DE: Display Enable flag. DE=1 when display is enabled.
RST: RST flag. RST=1 when reset is in progress.
4. Set Column Address

Set Column Address LSB, CA[3:0] 0 0 0 0 0 0 CA3 CA2 CA1 CA0
Set Column Address MSB, CA[7:4] 0 0 0 0 0 1 CA7 CA6 CA5 CA4
Set the SRAM column address before Write/Read memory from host interface.
CA value range: 0~131
5. Set Power Control

Set Power Control, PC[2:0] 0 0 0 0 1 0 1 PC2 PC1 PC0
Set PC[2:0] to enable the built-in charge pump.
PC[2] : 0 – Boost OFF 1 – Boost ON
PC[1] : 0 – Voltage Regular OFF 1 – Voltage Regular ON
PC[0] : 0 – Voltage Follower OFF 1 – Voltage Follower ON
Revision A1.0 13
ULTRACHIP
6. Set Scroll Line

Set Scroll Line, SL[5:0] 0 0 0 1 SL5 SL4 SL3 SL2 SL1 SL0
Set the scroll line number. Range : 0~63
Scroll line setting will scroll the displayed image up by SL rows. Icon output CIC will not be affected by Set
Scroll Line command.
Image row 0 row 0 Image row N row 0
: : : :
Image row N-1 : : :
Image row N Image row 63
: Image row 0
: :
Image row 63 row 63 Image row N-1 row 63
SL=0 SL=N
7. Set Page Address

Set Page Address, PA[3:0] 0 0 1 0 1 1 PA3 PA2 PA1 PA0
Set the SRAM page address before write/read memory from host interface. Each page of SRAM
corresponds to 8 COM lines on LCD panel, except for the last page. The last page corresponds to the icon
output CIC.
Possible value = 0~8.
8. Set VLCD Resistor Ratio

Set VLCD Resistor Ratio, PC[5:3] 0 0 0 0 1 0 0 PC5 PC4 PC3
Configure PC[5:3] to set internal Resistor Ratio, Rb/Ra, for the VLCD Voltage regulator to adjust the contrast
of the display panel:
PC[5:3] : 000b~111b – 1+Rb/Ra ratio. Default : 100b. Refer to VLCD Quick Reference for “1+Rb/Ra” ratio.
VLCD=((1+Rb/Ra) x Vev) x (1+(T-25)xCT%) Vev=(1-(63-PM)/162)xVREF
where Rb and Ra are internal resistors,
VREF is on-chip contrast voltage, and
PM is a vaule of electronic volume
9. Set Electronic Volume

1 0 0 0 0 0 0 1
Set Electronic Volume, PM[5:0] 0 0
0 0 PM5 PM4 PM3 PM2 PM1 PM0
Set PM[5:0] for electronic volume “PM” for VLCD voltage regulator to adjust contrast of LCD panel display
Effective range : 0~63. Default : 32
UC1701X
10. Set All Pixel ON

Set All Pixel ON, DC [1] 0 0 1 0 1 0 0 1 0 DC1
Set DC[1] to force all SEG drivers to output ON signals. This function has no effect on the existing data
stored in display RAM. Default : 0
11. Set Inverse Display

Set Inverse Display, DC [0] 0 0 1 0 1 0 0 1 1 DC0
Set DC[0] to force all SEG drivers to output the inverse of the data (bit-wise) stored in display RAM. This
function has no effect on the existing data stored in display RAM.
12. Set Display Enable

Set Display Enable, DC[2] 0 0 1 0 1 0 1 1 1 DC2
This command is for programming register DC[2]. When DC[2] is set to 1, UC1701x will first exit from sleep
mode, restore the power and then turn on COM drivers and SEG drivers.
13. Set SEG Direction

Set Segment Direction, LC[0] 0 0 1 0 1 0 0 0 0 MX
Set LC[0] for SEG (column) mirror (MX). Default : 0
MX is implemented by reversing the mapping order between RAM and SEG (column) electrodes. The data
stored in RAM is not affected by MX command. Yet, MX has immediate effect on the display image.
14. Set COM Direction

Set Common Direction, LC[1] 0 0 1 1 0 0 MY - - -
Set LC[1] for COM (row) mirror (MY).
MY is implemented by reversing the mapping between RAM and COM (row) electrodes. The data stored in
RAM is not affected by MY command. Yet, MY has immediate effect on the display image.
15. System Reset

System Reset 0 0 1 1 1 0 0 0 1 0
This command will activate the system reset.
Control register values will be reset to their default values. Data store in RAM will not be affected.
16. NOP

No Operation 0 0 1 1 1 0 0 0 1 1
This command is used for “no operation”.
Revision A1.0 15
ULTRACHIP
17. Set LCD Bias Ratio

Set Bias Ratio, BR 0 0 1 0 1 0 0 0 1 BR
Select voltage bias ratio required for LCD. Default : 0
The setting of Bias ratio varies according to Duty:
DUTY BR = 0 BR = 1
1/65 1/9 1/7
1/49 1/8 1/6
1/33 1/6 1/5
1/55 1/8 1/6
18. Set Cursor Update Mode

Set Cursor Update Mode 0 0 1 1 1 0 0 0 0 0
This command is used for set cursor update mode function. When cursor update mode sets, UC1701x will
update register CR with the value of register CA. The column address CA will increment with write RAM
data operation but the address wraps around will be suspended no matter what WA setting is. However, the
column address will not increment in read RAM data operation. The set cursor update mode can be used to
implement “write after read RAM” function. The column address (CA) will be restored to the value, which is
before the set cursor update mode command, when reset cursor update mode.
The purpose of this pair commands and their feature is to support “write after read” function for cursor
implementation.
19. Reset Cursor Update Mode

Reset Cursor Update Mode 0 0 1 1 1 0 1 1 1 0
Set AC3=0 and CA=CR.
20. Set Static Indicator OFF

Turn OFF Static Indicator 0 0 1 0 1 0 1 1 0 0
No Operation.
21. Set Static Indicator ON

0 0 1 0 1 0 1 1 0 1
Turn ON Static Indicator
0 0 - - - - - - - -
No Operation.
UC1701X
22. Set Booster Ratio

Set Booster Ratio 1 1 1 1 1 0 0 0
0 1
(Double-byte command) 0 0 0 0 0 0 - -
This command is used for “No Operation”.
23. Set Power Save

Power Save
0 0 # # # # # # # #
(Compound Command)
24. Set Test Control

Set TT 1 1 1 1 1 1 TT
0 1
(Double-byte command) - # # # # # # #
This command is for UltraChip’s Test only. Do NOT use.
25. Set Advanced Program Control 0

Set Adv. Program Control, APC0 [7:0] 1 1 1 1 1 0 1 0
0 0
(Double-byte command) TC 0 0 1 0 0 WA1 WA0
TC : APC0 [7], VBIAS temperature compensation coefficient (%-per-degree-C)
Temperature compensation curve definition:
o o
TC : 0b = -0.05%/ C, 1b = -0.11%/ C
WA : APC0 [1:0], Automatic column/row wrap around.
WA[0] : 0: PA WA disable 1: PA WA enable.
WA[1] : 0: CA WA disable 1: CA WA enable.
26. Set Advanced Program Control 1

Set Adv. Program Control, APC1 [7:0] 1 1 1 1 1 0 1 1
0 0
(Double-byte command) APC1 register parameter
For UltraChip only. Please Do NOT use.
Revision A1.0 17
ULTRACHIP
LCD VOLTAGE SETTING

MULTIPLEX RATES VLCD GENERATION
Multiplex Rate is completely software VLCD is supplied by internal charge pump. The
programmable in UC1701x via registers CEN, source of VLCD is controlled by PC[2:0]. For good
DST, DEN, and partial display control flags LC[4]. product reliability, it is recommended to keep
VLCD under 11.5V for all temperature conditions.
Combined with low power partial display mode
and a low bias ratio of 6, UC1701x can support When VLCD is generated internally, the voltage
wide variety of display control options. For level of VLCD is determined by three control
example, when a system goes into stand-by registers: BR (Bias Ratio), PM (Potentiometer),
mode, a large portion of LCD screen can be and PC[5:3] (VLCD Resistor Ratio) with the
turned off to conserve power. following relationship:
VLCD=((1+Rb/Ra) x Vev) x (1+(T-25)xCT%)
BIAS RATIO SELECTION
Vev=(1-(63-PM)/162)xVREF
Bias Ratio (BR) is defined as the ratio between
VLCD and VBIAS, i.e. where
BR = VLCD /VBIAS, Ra and Rb are two design constants, whose
value depends on the setting of BR register,
where VBIAS = VB1+ – VB1– = VB0+ – VB0–. as illustrated in the table on the next page,
The theoretical optimum Bias Ratio can be PM is value of electronic volume,
estimated by Mux + 1 . BR of value 15~20%
lower/higher than the optimum value calculated VREG is on-chip contrast voltage,
above will not cause significant visible change in O
T is the ambient temperature in C, and
image quality.
CT is temperature compensation coefficient.
UC1701x supports four BR as listed below. BR
can be selected by software program.
VLCD FINE TUNING
Bias Ratio Black-and-white STN LCD is sensitive to even a
Duty BR=0 BR=1 1% mismatch between IC driving voltage and the
1/65 1/9 1/7 VOP of LCD. However, it is difficult for LCD
makers to guarantee such high precision
1/49 1/8 1/6 matching of parts from different venders. It is
1/33 1/6 1/5 therefore necessary to adjust VLCD to match the
1/55 1/8 1/6 actual VOP of the LCD.
Table 1: Bias Ratios For the best result, software based approach for
VLCD adjustment is the recommended method for
TEMPERATURE COMPENSATION VLCD fine-tuning. System designers should
always consider the contrast fine tuning
The temperature compensation coefficients is requirement before finalizing on the LEM design
o
–0.11% per C.
LOAD DRIVING STRENGTH
The power supply circuit of UC1701x is designed
to handle LCD panels with loading up to ~24nF
using 20-Ω/Sq ITO glass with VDD2/3 2.4V. For
larger LCD panels, use lower resistance ITO
glass packaging.
UC1701X
VLCD QUICK REFERENCE
11.0
10.0
9.0
8.0
VLCD
7.0
6.0
5.0
4.0
3.0
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
PM
VLCD Programming Curve.
PC[5:3] 1+Rb/Ra VREF PM VLCD Range (V)

0 3.87
000b 3.769 1.68
63 6.33
0 4.51
001b 4.396 1.68
63 7.38
0 5.15
010b 5.020 1.68
63 8.43
0 5.79
011b 5.643 1.68
63 9.48
0 6.43
100b 6.266 1.68
63 10.53
0 7.08
101b 6.891 1.68
62 11.51
0 7.72
110b 7.517 1.68
48 11.46
0 8.36
111b 8.143 1.68
37 11.48
Note: For good product reliability, keep VLCD under 11.5V over all temperature.
Revision A1.0 19
ULTRACHIP
HI-V GENERATOR AND BIAS REFERENCE CIRCUIT

VDD
VB0+
VDD CB0
VB0-
VDD2/VDD3
VB1+
VDD2 CB1
VDD3 VB1-
UC1701
VLCDOUT
VLCDIN
VSS CL
VSS2 RL
(OPTIONAL)
FIGURE 1: Reference circuit using internal Hi-V generator circuit

Note
Sample component values: (The illustrated circuit and component values are for reference only. Please
optimize for specific requirements of each application.)
CBx : 2.2 µF/5V or 100~250x LCD load capacitance.
CL : 330nF(25V) is appropriate for most applications.
RL: 3.3M~10M Ω to act as a draining circuit when VDD is shut down abruptly.
UC1701X
LCD DISPLAY CONTROLS

CLOCK & TIMING GENERATOR DRIVER ENABLE (DE)
UC1701x contains a built-in system clock. All Driver Enable is controlled by the value of DC[2]
required components for the clock oscillator are via Set Display Enable command. When DC[2] is
built-in. No external parts are required. set to OFF (logic “0”), both COM and SEG drivers
will become idle and UC1701x will put itself into
4 different frame rates are provided based on Sleep Mode to conserve power.
different Mux-Rate for system design flexibility.
When DC[2] is set to ON, the DE flag will become
DRIVER MODES “1”,and UC1701x will first exit from Sleep Mode,
restore the power (VLCD, VD etc.) and then turn on
COM and SEG drivers can be in either Idle mode
COM and SEG drivers.
or Active mode, controlled by Display Enable flag
(DC[2]). When SEG and COM drivers are in idle
mode, they will be connected together to ensure ALL PIXELS ON (APO)
zero DC condition on the LCD. When set, this flag will force all SEG drivers to
output ON signals, disregarding the data stored
DRIVER ARRANGEMENTS in the display buffer.
The naming conventions are: COMx, where x = This flag has no effect when Display Enable is
1~64, refers to the row driver for the x-th row of OFF and it has no effect on data stored in RAM.
pixels on the LCD panel.
The mapping of COM(x) to LCD pixel rows is INVERSE (PXV)
fixed and it is not affected by SL, MX or MY When this flag set to ON, SEG drivers will output
settings. the inverse of the value it received from the
display buffer RAM (bit-wise inversion). This flag
DISPLAY CONTROLS has no impact on data stored in RAM.
There are three groups of display control flags in
the control register DC: Driver Enable (DE), All-
Pixel-ON (APO) and Inverse (PXV). DE has the
overriding effect over PXV and APO.
Revision A1.0 21
ULTRACHIP
ITO LAYOUT AND LC SELECTION

Since COM scanning pulses of UC1701x can be as For good image quality, please minimize SEG ITO
short as 153µS, it is critical to control the RC delay trace resistance and limit the worst case of SEG
of COM and SEG signal to minimize crosstalk and signal RC delay as calculated below.
maintain good mass production consistency.
(RCOL / 2.7 + RSEG) x CCOL < 6.30µS
COM TRACES where
Excessive COM scanning pulse RC decay can CCOL: LCD loading capacitance of one pixel
cause fluctuation of contrast and increase COM column. It can be calculated by CLCD / (#
direction crosstalk. of column), where CLCD is the LCD panel
Please limit the worst case of COM signals RC capacitance.
delay (RCMAX) as calculated below RCOL: ITO resistance over one column of
(RROW / 2.7 + RCOM) x CROW < 9.23µS pixels within the active area
where RSEG: SEG routing resistance from IC to the

active area + SEG driver output
CROW: LCD loading capacitance of one row of impedance.
pixels. It can be calculated by CLCD/Mux-
Rate, where CLCD is the LCD panel (Use worst case values for all calculations)
capacitance.
SELECTING LIQUID CRYSTAL
RROW: ITO resistance over one row of pixels
within the active area The selection of LC material is crucial to achieve
the optimum image quality of finished LCM.
RCOM: COM routing resistance from IC to the
active area + COM driver output When (V90-V10)/V10 is too large, image contrast will
impedance. deteriorate, and images will look murky and dull.
In addition, please limit the min-max spread of RC When (V90-V10)/V10 is too small, image contrast will
decay to be: become too strong, and crosstalk will increase.
For the best result, it is recommended the LC
| RCMAX – RCMIN | < 2.76µS
material has the following characteristics:
so that the COM distortions on the top of the
(V90-V10)/V10 = (VON-VOFF)/VOFF x 0.72~0.80
screen to the bottom of the screen are uniform.
where V90 and V10 are the LC characteristics, and
(Use worst case values for all calculations)
VON and VOFF are the ON and OFF VRMS voltage
produced by LCD driver IC at the specific Mux-rate.
SEG TRACES
Example:
Excessive SEG signal RC decay can cause image
dependent changes of medium gray shades and Duty Bias VON/VOFF -1 x0.80 x0.72
sharply increase the crosstalk of SEG direction.
1/65 1/9 10.6% 9.6% 7.5%
UC1701X
RAM
W/R
POL
COM1
COM2
COM3
SEG1
SEG2
FIGURE 2: COM and SEG Electrode Driving Waveform
Revision A1.0 23
ULTRACHIP
THE COMMON OUTPUT STATUS SELECT CIRCUIT

In the UC1701x chips, the COM output scan direction can be selected by the common output status select
command. (See the table below for details.) Consequently, the constraints in IC layout at the time of LCD
module assembly can be minimized.
COM COM COM COM COM
Duty Direction COM[1:16] COM[49:64] COMS
[17:24] [25:27] [28:37] [38:40] [41:48]
0 COM [1:64]
1/65 COMS
1 COM [64:1]
0 COM[1:24] NC COM [25:48]
1/49 COMS
1 COM[48:25] NC COM [24:1]
0 COM[1:16] NC COM[17:32]
1/33 COMS
1 COM[32:17] NC COM[16:1]
0 COM [1:27] NC COM [28:54]
1/55 COMS
1 COM [54:28] NC COM [27:1]
Table 2: Duty Layout
UC1701X
HOST INTERFACE
As summarized in the table below, UC1701x supports two 8-bit parallel bus protocols and one serial bus
protocol. Designers can choose either the 8-bit parallel bus to achieve high data transfer rate, or use serial
bus to create compact LCD modules and minimize connector pins.
Bus Type
8080 6800 S8 (4-wire)
Width 8-bit 8-bit Serial
Access Read / Write Write only
BM[1:0] 10 11 00
Control & Data Pins
CS0 Chip Select

CD Control/Data
___ __ _ _
WR0 WR R/W –
___ __
WR1 RD EN –
DB[5:0] Data –
DB[7:6] Data DB[6]=SCK, DB[7]=SDA
* Connect unused control pins and data bus pins to VDD or VSS
CS CS RESET
Disable Bus Interface Init. Bus State Init. Bus State
8-bit 9 – 9
S8 9 9 9
• CS disable bus interface – CS can be used to disable Bus Interface Write / Read Access.
• RESET can be pin reset / soft reset / power on reset.
Table 3: Host interfaces Summary
Revision A1.0 25
ULTRACHIP
PARALLEL INTERFACE
The timing relationship between UC1701x internal Set PA command, a dummy read cycle need to be
control signal RD, WR and their associated bus performed before the actual data can propagate
actions are shown in the figure below. through the pipeline and be read from data port
D[7:0].
The Display RAM read interface is implemented as
a two-stage pipeline. This architecture requires that, There is no pipeline in write interface of Display
every time memory address is modified, either in RAM. Data is transferred directly from bus buffer to
parallel mode or serial mode, by either Set CA or internal RAM on the rising edges of write pulses.
External
CD
___
WR
__
RD
D[7:0] LLSB DL DL+K CMSB CLSB Dummy DC DC+1 MMSB MLSB
Internal
Write
Read
Data
DL DL+K Dummy DC DC+1 DC+2
Latch
Column
Address L L+K L+K+1 C C+1 C+2 C+3 M
Figure 3: Parallel Interface & Related Internal Signals
SERIAL INTERFACE
UC1701x supports 1 serial modes: 4-wire SPI mode (S8). Bus interface mode is determined by the wiring of
the BM[1:0]. See table in last page for more detail.
S8 (4-WIRE) INTERFACE
Only write operations are supported in 4-wire serial If CD=0, the data byte will be decoded as
mode. Pin CS[1:0] are used for chip select and bus command. If CD=1, this 8-bit will be treated as data
cycle reset. Pin CD is used to determine the and transferred to proper address in the Display
content of the data been transferred. During each Data RAM on the rising edge of the last SCK pulse.
write cycle, 8 bits of data, MSB first, are latched on
eight rising SCK edges into an 8-bit data holder. Pin CD is examined when SCK is pulled low for the
LSB (D0) of each token.
CS0
SDI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5
SCK
CD
Figure 4: 4-wire Serial Interface (S8)
UC1701X
HOST INTERFACE REFERENCE CIRCUIT

VDD
VCC VDD
D7~D0 D7~D0
CD CD
WR WR0(WR)
RD WR1(RD)
ADDRESS CS0
MPU UC1701
IORQ DECODER
VDD
RST
VDD
BM1
BM0
GND VSS
FIGURE 5: 8080/8bit parallel mode reference circuit

VDD
VCC VDD
D7~D0 D7~D0
CD CD
R/W WR0(R/W)
E WR1(E)
ADDRESS CS0
MPU UC1701
IORQ DECODER
VDD
RST
VDD
BM1
BM0
GND VSS
FIGURE 6: 6800/8bit parallel mode reference circuit
Revision A1.0 27
ULTRACHIP
VDD
VCC VDD
D5~D0 D5~D0
SCK SCK(D6)
SDA SDA(D7)
CD CD
WR0
WR1
ADDRESS CS0
MPU UC1701
IORQ DECODER
VDD
RST
BM1
BM0
GND VSS
FIGURE 7: Serial-8 serial mode reference circuit

Note
• The ID pins are for production control. The connection will affect the content of D[7] of the 1st byte of
the Get Status command. Connect to VDD for “H” or VSS for “L”.
• RST pin is optional. When the RST pin is not used, connect it to VDD.
2
• When using I C serial mode, CS1/0 are user configurable and affect A[3:2] of device address.
• R1, R2: 2k ~ 10k Ω, use lower resistor for bus speed up to 3.6MHz, use higher resistor for lower power.
UC1701X
DISPLAY DATA RAM (DDRAM)

a non-zero value is equivalent to scrolling the
DATA ORGANIZATION LCD display up or down (depends on MY) by SL
The input display data is stored to a dual port rows.
static DDRAM (DDRAM, for Display Data RAM)
organized as 65x132. RAM ADDRESS GENERATION
After setting CA and RA, the subsequent data The mapping of the data stored in the display
write cycle will store the data for the specified SRAM and the scanning electrodes can be
pixel to the proper memory location. obtained by combining the fixed Rm scanning
sequence and the following RAM address
Please refer to the map in the following page generation formula.
between the relation of COM, SEG, SRAM, and
various memory control registers. During the display operation, the RAM line
address generation can be mathematically
DISPLAY DATA RAM ACCESS represented as following:
The Display RAM is a special purpose dual port For the 1st line period of each field
RAM which allows asynchronous access to both Line = SL
its column and row data. Thus, RAM can be Otherwise
independently accessed both for Host Interface Line = Mod(Line+1, 64)
and for display operations.
Where Mod is the modular operator, and Line is
the bit slice line address of RAM to be outputted
DISPLAY DATA RAM ADDRESSING
to column drivers. Line 0 corresponds to the first
A Host Interface (HI) memory access operation bit-slice of data in RAM.
starts with specifying Row Address (RA) and
The above Line generation formula produce the
Column Address (CA) by issuing Set Row
“loop around” effect as it effectively resets Line to
Address and Set Column Address commands.
0 when Line+1 reaches 64.
MX IMPLEMENTATION
MY IMPLEMENTATION
Column Mirroring (MX) is implemented by
Row Mirroring (MY) is implemented by reversing
selecting either (CA) or (131–CA) as the RAM
the mapping order between row electrodes and
column address. Changing MX affects the data
RAM, i.e. the mathematical address generation
written to the RAM.
formula becomes:
Since MX has no effect of the data already stored st
For the 1 line period of each field
in RAM, changing MX does not have immediate
Line = Mod(SL + MR -1, 64)
effect on the displayed pattern. To refresh the
Otherwise
display, refresh the data stored in RAM after
Line = Mod(Line-1 , 64)
setting MX.
Visually, the effect of MY is equivalent to flipping
ROW MAPPING the display upside down. The data stored in
display RAM is not affected by MY.
COM electrode scanning orders are not affected
by Start Line (SL), Fixed Line (FLT & FLB) or
Mirror Y (MY, LC[3]). Visually, register SL having
Revision A1.0 29
ULTRACHIP
Line MY=0 MY=1

PA[3:0] 0 AddeCss SL=0 SL=16 SL=0 SL=0 SL=25 SL=25
D0 00H C1 C49 C64 C48 C25 C9
D1 01H C2 C50 C63 C47 C24 C8
D2 02H C3 C51 C62 C46 C23 C7
D3 03H C4 C52 C61 C45 C22 C6
0000 Page 0
D4 04H C5 C53 C60 C44 C21 C5
D5 05H C6 C54 C59 C43 C20 C4
D6 06H C7 C55 C58 C42 C19 C3
D7 07H C8 C56 C57 C41 C18 C2
D0 08H C9 C57 C56 C40 C17 C1
D1 09H C10 C58 C55 C39 C16 ---
D2 0AH C11 C59 C54 C38 C15 ---
D3 0BH C12 C60 C53 C37 C14 ---
0001 Page 1
D4 0CH C13 C61 C52 C36 C13 ---
D5 0DH C14 C62 C51 C35 C12 ---
D6 0EH C15 C63 C50 C34 C11 ---
D7 0FH C16 C64 C49 C33 C10 ---
D0 10H C17 C1 C48 C32 C9 ---
D1 11H C18 C2 C47 C31 C8 ---
D2 12H C19 C3 C46 C30 C7 ---
D3 13H C20 C4 C45 C29 C6 ---
0010 Page 2
D4 14H C21 C5 C44 C28 C5 ---
D5 15H C22 C6 C43 C27 C4 ---
D6 16H C23 C7 C42 C26 C3 ---
D7 17H C24 C8 C41 C25 C2 ---
D0 18H C25 C9 C40 C24 C1 ---
D1 19H C26 C10 C39 C23 C64 C48*
D2 1AH C27 C11 C38 C22 C63 C47
D3 1BH C28 C12 C37 C21 C62 C46
0011 Page 3
D4 1CH C29 C13 C36 C20 C61 C45
D5 1DH C30 C14 C35 C19 C60 C44
D6 1EH C31 C15 C34 C18 C59 C43
D7 1FH C32 C16 C33 C17 C58 C42
D0 20H C33 C17 C32 C16 C57 C41
D1 21H C34 C18 C31 C15 C56 C40
D2 22H C35 C19 C30 C14 C55 C39
D3 23H C36 C20 C29 C13 C54 C38
0100 Page 4
D4 24H C37 C21 C28 C12 C53 C37
D5 25H C38 C22 C27 C11 C52 C36
D6 26H C39 C23 C26 C10 C51 C35
D7 27H C40 C24 C25 C9 C50 C34
D0 28H C41 C25 C24 C8 C49 C33
D1 29H C42 C26 C23 C7 C48 C32
D2 2AH C43 C27 C22 C6 C47 C31
D3 2BH C44 C28 C21 C5 C46 C30
0101 Page 5
D4 2CH C45 C29 C20 C4 C45 C29
D5 2DH C46 C30 C19 C3 C44 C28
D6 2EH C47 C31 C18 C2 C43 C27
D7 2FH C48 C32 C17 C1 C42 C26
D0 30H C49 C33 C16 --- C41 C25
D1 31H C50 C34 C15 --- C40 C24
D2 32H C51 C35 C14 --- C39 C23
D3 33H C52 C36 C13 --- C38 C22
0110 Page 6
D4 34H C53 C37 C12 --- C37 C21
D5 35H C54 C38 C11 --- C36 C20
D6 36H C55 C39 C10 --- C35 C19
D7 37H C56 C40 C9 --- C34 C18
D0 38H C57 C41 C8 --- C33 C17
D1 39H C58 C42 C7 --- C32 C16
D2 3AH C59 C43 C6 --- C31 C15
D3 3BH C60 C44 C5 --- C30 C14
0111 Page 7
D4 3CH C61 C45 C4 --- C29 C13
D5 3DH C62 C46 C3 --- C28 C12
D6 3EH C63 C47 C2 --- C27 C11
D7 3FH C64 C48 C1 --- C26 C10
1000 D0 40H Page 8 CIC CIC CIC CIC CIC CIC
65 49 65 49
MUX
SEG128
SEG129
SEG130
SEG131
SEG132
SEG132 SEG1
SEG131 SEG2
SEG130 SEG3
SEG129 SEG4
SEG128 SEG5
SEG127 SEG6
SEG126 SEG7
SEG125 SEG8
0
MX
SEG5
SEG4
SEG3
SEG2
SEG1
1
Example for memory mapping: let MX = 0, MY = 0, SL = 0, according to the data shown in the above table:
⇒ Page 0 SEG 1 (D7-D0) : 11100000b
⇒ Page 0 SEG 2 (D7-D0) : 00110011b
UC1701X
RESET & POWER MANAGEMENT

required for VDD to stabilize, and then trigger the
TYPES OF RESET System Reset.
UC1701x has two different types of Reset:
Power-ON-Reset and System-Reset. System Reset can also be activated by software
command or by connecting RST pin to ground.
Power-ON-Reset is performed right after VDD is
connected to power. Power-On-Reset will first In the following discussions, Reset means
wait for about ~5mS, depending on the time System Reset.
The differences between hardware reset and software reset are

Hardware Software
Procedure
Reset Reset
Display OFF: DC[2]=0, all SEGs/COMs output at VSS V X
Normal Display: DC[0]=0, DC[1]=0 V X
SEG Normal Direction: MX=0 V X
Clear Serial Counter and Shift Register (if using Serial Interface) V X
Bias Selection: BR=0 V X
Booster Level BL[1:0]=0 V X
Exit Power Saving Mode V X
Power Control OFF: PC[2:0]=000b V X
Exit Cursor Update mode V V
Scroll Line SL[5:0]=0 V V
Column Address CA[7:0]=0 V V
Page Address PA[3:0]=0 V V
COM Normal Direction: MY=0 V V
VLCD Regulation Ratio PC[5:3]=100b V V
PM[5:0]=10 0000b V V
Exit Test Mode V V
For each mode, the related statuses are as below:

RESET STATUS
When UC1701x enters RESET sequence: Mode Reset Sleep Normal
OM 00 10 11
• Operation mode will be “Reset”
Host Interface Active Active Active
• All control registers are reset to default values. Clock OFF OFF ON
Refer to Control Registers for details of their
default values. LCD Drivers OFF OFF ON
Charge Pump OFF OFF ON
OPERATION MODES Draining Circuit ON ON OFF
UC1701x has three operating modes (OM): Table 4: Operating Modes
Reset, Sleep, Normal.
Revision A1.0 31
ULTRACHIP
Even though UC1701x consumes very little

CHANGING OPERATION MODE
energy in Sleep mode (typically under 2µA);
In addition to Power-ON-Reset, two commands however, since all capacitors are still charged,
will initiate OM transitions: the leakage through COM drivers may damage
Set Display Enable, and System Reset. the LCD over the long term. It is therefore
recommended to use Sleep mode only for brief
When DC[2] is modified by Set Display Enable,
Display OFF operations, such as full-frame
OM will be updated automatically. There is no
screen updates, and to use RESET for extended
other action required to enter power saving mode.
screen OFF operations.
For maximum energy utilization, Sleep mode is
designed to retain charges stored in external EXITING SLEEP MODE
capacitors CB0, CB1, and CL. To drain these
UC1701x contains internal logic to check whether
capacitors, use Reset command to activate the
VLCD and VBIAS are ready before releasing COM
on-chip draining circuit..
and SEG drivers from their idle states. When
Action Mode OM exiting Sleep or Reset mode, COM and SEG
drivers will not be activated until UC1701x
Reset command internal voltage sources are restored to their
RST_ pin pulled “L” Reset 00 proper values.
Power ON reset
Set Driver Enable to “0” Sleep 10
Set Driver Enable to “1” Normal 11
Table 5: OM changes
UC1701X
POWER-UP SEQUENCE ENTER/EXIT SLEEP MODE SEQUENCE

UC1701x power-up sequence is simplified by UC1503t enters Sleep mode from Display mode
built-in “Power Ready” flags and by the automatic by issuing Set Display Disable command and
invocation of System-Reset command after setting all-pixel-ON.
Power-ON-Reset.
To exit Sleep mode, set All-pixel-OFF.
System programmer is required to wait for only
5 ~ 10 mS before starting to issue commands to
UC1701x. No additional commands or waits are
required between enabling of the charge pump, Display Mode
turning on the display drivers, writing to RAM or
any other commands.
There’s no delay needed while turning on VDD Set Display OFF (AEH)
and VDD2/3, and either one can be turned on first. Set All-pixel-ON (A5H)
Turn on the Power
Sleep Mode
Set RST Low
Set All-pixel-OFF (A4H)

Wait 1 mS
Set Display Enable (AFH)
Set RST High

Display Mode
Wait 5 mS
FIGURE 6: Reference Enter/Exit Sleep Mode
Sequence
(Issue commands)
Wait for MTP-READ 120mS
Set LCD Bias Ratio (BR)
Set Electronic Volume (PM)
Set Display Enable (AFH)
FIGURE 8: Reference Power-Up Sequence
Revision A1.0 33
ULTRACHIP
POWER-DOWN SEQUENCE
To prevent the charge stored in capacitor CL Reset command
causing abnormal residue horizontal line on
display when VDD is switched off, use Reset
mode to enable the built-in charge draining circuit
to discharge these external capacitors.
Wait ~1 mS
Turn OFF the power
FIGURE 9: Reference Power-Down Sequence
Either VDD or VDD2/3

may be turned on first.
VDD2/3 ≥ 2.5V
VDD ≥ 1.8V
TWait > 10mS
VDD < 0.1V VDD2/3 ≥ VDD
Tf < 10 mS 10µS < T1< 10 mS
Figure 10: Power Off-On Sequence
UC1701X
SAMPLE COMMAND SEQUENCES FOR POWER MANAGEMENT

The following tables are examples of command sequence for power-up, power-down and display ON/OFF
operations. These are only to demonstrate some “typical, generic” scenarios. Designers are encouraged to
study related sections of the datasheet and find out what the best parameters and control sequences are for
their specific design needs.
C/D The type of the interface cycle. It can be either Command (0) or Data (1)
W/R The direction of data flow of the cycle. It can be either Write (0) or Read (1).
Type Required: These items are required
Customized: These items are not necessary if customer parameters are the same as default
Advanced: We recommend new users to skip these commands and use default values.
Optional: These commands depend on what users want to do.
POWER-UP
Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Chip action Comments
R – – – – – – – – – – Automatic Power-ON Reset. Wait ~5mS after VDD is ON
1 1 1 1 1 0 1 0
A 0 0 Set Adv. Program Control 0
1 0 0 1 0 0 1 1 Set Wrap Around Enable
C 0 0 1 0 1 0 0 0 0 # Set SEG Direction Set up LCD format specific
C 0 0 1 1 0 0 # – – – Set COM Direction parameters, MX, MY, etc.
C 0 0 1 0 1 0 0 0 1 # Set LCD Bias Ratio
LCD specific operating
0 0 1 0 0 0 0 0 0 1 voltage setting
R Set Electronic Volume
0 0 0 0 # # # # # #
1 0 # # # # # # # #
. . . . . . . . . .
O Write display RAM Set up display image
. . . . . . . . . .
1 0 # # # # # # # #
R 0 0 1 0 1 0 1 1 1 1 Set Display Enable
POWER-DOWN
R 0 0 1 1 1 0 0 0 1 0 System Reset
R – – – – – – – – – – Draining capacitor Wait ~3mS before VDD OFF
DISPLAY-OFF
R 0 0 1 0 1 0 1 1 1 0 Set Display Disable
C 1 0 # # # # # # # # Write display RAM Set up display image (Image
. . . . . . . . . . update is optional. Data in
. . . . . . . . . . the RAM is retained through
the SLEEP state.)
1 0 # # # # # # # #
R 0 0 1 0 1 0 1 1 1 1 Set Display Enable
Revision A1.0 35
ULTRACHIP
ESD CONSIDERATION
UC1700 series products usually are provided in bare die format to customers. This makes the product
particularly sensitive to ESD damage during handling and manufacturing process. It is, therefore, highly
recommended that LCM makers strictly follow the "JESD 625-A Requirements for Handling Electrostatic-
Discharge-Sensitive (ESDS) Devices" when manufacturing LCM.
The following pins in UC1701x require special "ESD Sensitivity" consideration in particular:
Test Mode Machine Mode Human Body Mode

Pins VDD VSS VDD VSS
LCD Driver 150V 150V 2000V 1500V
LCM Digital Interface 300V 250V 3000V 3000V
TST1/2/4 300V 300V 3000V 3000V
LCM HV CB pins 300V 300V 3000V 3000V

Interface VLCDIN 250V 300V 3000V 3000V
VLCDOUT 300V 300V 3000V 3000V
PWR/GND -- 300V -- 3000V
According to UltraChip's Mass Production experiences, the ESD tolerance conditions are believed to be very
stable and can produce high yield in multiple customer sites. However, special care is still required during
handling and manufacturing process to avoid unnecessary yield loss due to ESD damages.
UC1701X
ABSOLUTE MAXIMUM RATINGS

In accordance with IEC134 - notes 1, 2 and 3.
Symbol Parameter Min. Max. Unit

VDD Logic Supply voltage -0.3 +4.0 V
VDD2 LCD Generator Supply voltage -0.3 +4.0 V
VDD3 Analog Circuit Supply voltage -0.3 +4.0 V
VDD2/3-VDD Voltage difference between VDD and VDD2/3 -- 1.2 V
VLCD LCD Generated voltage -0.3 +13.2 V
VIN / VOUT Any input/output -0.4 VDD + 0.3 V
o
TOPR Operating temperature range -30 +85 C
o
TSTR Storage temperature -55 +125 C
Notes
1. VDD is based on VSS = 0V
2. Stress values listed above may cause permanent damages to the device.
Revision A1.0 37
ULTRACHIP
SPECIFICATIONS
DC CHARACTERISTICS
Symbol Parameter Conditions Min. Typ. Max. Unit
VDD Supply for digital circuit 1.65 1.8~3.3 3.6 V
VDD2/3 Supply for bias & pump 2.4 2.5~3.3 3.6 V
O
VLCD Charge pump output VDD2/3 2.4V, 25 C 11.5 V
O
VD LCD data voltage VDD2/3 2.4V, 25 C 0.80 1.32 V
VIL Input logic LOW 0.2VDD V
VIH Input logic HIGH 0.8VDD V
VOL Output logic LOW 0.2VDD V
VOH Output logic HIGH 0.8VDD V
IIL Input leakage current 1.5 µA
VDD = VDD2/3 = 3.3V,
ISB Standby current o 50 µA
Temp = 85 C
CIN Input capacitance 5 10 PF
COUT Output capacitance 5 10 PF
R0(SEG) SEG output impedance VLCD = 11V 2000 3000 Ω
R0(COM) COM output impedance VLCD = 11V 2000 3000 Ω
Duty=1/65 77
Duty=1/49 153
FFR Average Frame Rate -10% +10% Hz
Duty=1/33 76
Duty=1/55 136
POWER CONSUMPTION
VDD = 2.7 V, Bias Ratio = 0b, PM = 32,
VLCD = 8.49 V Frame Rate = 77Hz, CL = 330 nF,
Mux Rate = 65, Bus mode = 6800, All outputs are open circuit.
o
CB = 2.2 µF Temperature = 25 C
Display Pattern Conditions Typ. Max.
All-OFF Bus = idle 190 304
2-pixel checker Bus = idle 192 308
1-pixel checker Bus = idle 203 325
- Bus = idle (standby current) - 5
UC1701X
AC CHARACTERISTICS
CD
tAS80 tAH80
CS0
CS1
tCSSA80 tCY80 tCSH80
tPWR80, tPWW80 tHPW80
WR0
WR1
tDS80 tDH80
Write
D[7:0]
tACC80 tOD80
Read
D[7:0]
FIGURE 11: Parallel Bus Timing Characteristics (for 8080 MCU)
o
(2.5V VDD < 3.3V, Ta= –30 to +85 C)
Symbol Signal Description Condition Min. Max. Units

tAS80 setup time 0
CD Address 5 – nS
tAH80 hold time
tCSSA80 setup time 5
CS1/CS0 Chip select 5 – nS
tCSH80 hold time
read 120
tCY80 Cycle time – nS
write 80
tPWR80 WR1 read 60
Pulse width – nS
tPWW80 WR0 write 40
High pulse read 60
tHPW80 WR0, WR1 – nS
width write 40
tDS80 setup time 30
D7~D0 Data – nS
tDH80 hold time 0
tACC80 Read access time CL = 100pF – 60
nS
tOD80 Output disable time 20 –
o
(1.65V VDD < 2.5V, Ta= –30 to +85 C)

tAS80 setup time 0
CD Address 0 – nS
tAH80 hold time
CS1/CS0 Chip select 5 – nS
tCSH80 hold time
System read 240
tCY80 160 – nS
cycle time write
tPWR80 WR1 read 120
Pulse width – nS
tPWW80 WR0 write 80
High pulse read 120
tHPW80 WR0, WR1 80 – nS
width write
tDS80 setup time 60
D7~D0 Data – nS
tDH80 hold time 0
tACC80 Read access time CL = 100pF – 100
nS
Revision A1.0 39
ULTRACHIP
CD
tAS68 tAH68
CS0
CS1
tCSSA68 tCY68 tCSH68
tPWR68, tPWW68 tHPW68
WR1
tDS68 tDH68
Write
D[7:0]
tACC68 tOD68
Read
D[7:0]
FIGURE 12: Parallel Bus Timing Characteristics (for 6800 MCU)

o
(2.5V VDD < 3.3V, Ta= –30 to +85 C)

tAS68 setup time 0
CD Address – nS
tAH68 hold time 0
CS1/CS0 Chip select – nS
tCSH68 hold time 5
System read 120
tCY68 – nS
cycle time write 80
tPWR68 read 60
WR1 Pulse width – nS
tPWW68 write 40
High pulse read 60
tHPW68 – nS
width write 40
tDS68 setup time 30
D7~D0 Data – nS
tDH68 hold time 0
tACC68 Read access time – 60
CL = 100pF nS
o
(1.65V VDD < 2.5V, Ta= –30 to +85 C)

tAS68 setup time 0
CD Address – nS
tAH68 hold time 0
CS1/CS0 Chip select nS
tCSH68 hold time 5
read 240
tCY68 cycle time – nS
write 160
tPWR68 read 120
WR1 Pulse width – nS
tPWW68 write 80
High pulse read 120
tHPW68 – nS
width write 80
tDS68 setup time 60
D7~D0 Data – nS
tDH68 hold time 0
tACC68 Read access time – 100
CL = 100pF nS
UC1701X
CD
tASS8 tAHS8
CS0
CS1
tCSSAS8 tCYS8 tCSHS8

tLPWS8 tHPWS8
SCK
tDSS8 tDHS8
SDA
Write
FIGURE 13: Serial Bus Timing Characteristics (for S8)
o
(2.5V VDD < 3.3V, Ta= –30 to +85 C)

tASS8 setup time 0
CD Address – nS
tAHS8 hold time 0
tCSSAS8 setup time 5
tCSHS8 hold time 5
read 100
tCYS8 Cycle time – nS
write 30
Low pulse read 50
tLPWS8 SCK – nS
width write 15
High pulse read 50
tHPWS8 – nS
width write 15
tDSS8 setup time 12
SDA Data – nS
tDHS8 hold time 0
o
(1.65V VDD < 2.5V, Ta= –30 to +85 C)

tASS8 setup time 0
CD Address – nS
tAHS8 hold time 0
tCSSAS8 setup time 10
tCSHS8 hold time 10
read 130
tCYS8 Cycle time – nS
write 60
Low pulse read 65
tLPWS8 SCK – nS
width write 30
High pulse read 65
tHPWS8 – nS
width write 30
tDSS8 setup time 24
SDA Data – nS
tDHS8 hold time 0
Revision A1.0 41
ULTRACHIP
tRW
RST
tRD
WR[1:0]
FIGURE 14: Reset Characteristics
o
(1.65V VDD < 3.3V, Ta= –30 to +85 C)

tRW RST Reset low pulse width 3 – µS
tRD RST, WR Reset to WR pulse delay 6 – mS
UC1701X
PHYSICAL DIMENSIONS
DIE SIZE:
4850 µM x 660 µM ±40 µM
DIE THICKNESS:
400 µM±20 µM
BUMP HEIGHT:
15 µM ±3 µM
(HMAX – HMIN) within die 2 µM
BUMP SIZE:
15 µM x 138.5 µM ± 2 µM (Typ.)
BUMP PITCH:
27 µM
BUMP GAP:
12 µM
COORDINATE ORIGIN:
Chip center
PAD REFERENCE:
Pad center
(Drawing and coordinates are for the

Circuit/Bump view.)
Revision A1.0 43
ULTRACHIP
ALIGNMENT MARK INFORMATION
(0,0)
D-Left D-Right
Mark Mark
SHAPE OF THE ALIGNMENT MARK:

1
3 NOTE:
C
4 Alignment mark is on Metal3 under Passivation.
2 The “+” mark is symmetric both horizontally and vertically.
COORDINATES:
D-Left Mark (+) D-Right Mark (+)

X Y X Y
1 -1984.5 -149.5 1969.5 -149.5
2 -1969.5 -184.5 1984.5 -184.5
3 -1994.5 -159.5 1959.5 -159.5
4 -1959.5 -174.5 1994.5 -174.5
C -1977 -167 1977 -167
TOP METAL AND PASSIVATION:
SiN / 7KÅ
SiO2 / 5KÅ
Metal3 / 9KÅ
FOR PROCESS CROSS-SECTION
UC1701X
PAD COORDINATES
# Pad X Y W H # Pad X Y W H # Pad X Y W H
1 COM54 -2363 -227.75 15 138.5 59 DUMMY 985 -274.5 45 45 117 SEG9 1552.5 227.75 15 138.5
2 COM55 -2336 -227.75 15 138.5 60 DUMMY 1040 -274.5 45 45 118 SEG10 1525.5 227.75 15 138.5
3 COM56 -2309 -227.75 15 138.5 61 DUMMY 1095 -274.5 45 45 119 SEG11 1498.5 227.75 15 138.5
4 COM57 -2282 -227.75 15 138.5 62 DUMMY 1150 -274.5 45 45 120 SEG12 1471.5 227.75 15 138.5
5 COM58 -2255 -227.75 15 138.5 63 DUMMY 1205 -274.5 45 45 121 SEG13 1444.5 227.75 15 138.5
6 COM59 -2228 -227.75 15 138.5 64 DUMMY 1260 -274.5 45 45 122 SEG14 1417.5 227.75 15 138.5
7 COM60 -2201 -227.75 15 138.5 65 TST2 1320 -274.5 50 45 123 SEG15 1390.5 227.75 15 138.5
8 COM61 -2174 -227.75 15 138.5 66 VSSL 1385 -274.5 50 45 124 SEG16 1363.5 227.75 15 138.5
9 COM62 -2147 -227.75 15 138.5 67 VDDX 1450 -274.5 50 45 125 SEG17 1336.5 227.75 15 138.5
10 COM63 -2120 -227.75 15 138.5 68 BM0 1515 -274.5 50 45 126 SEG18 1309.5 227.75 15 138.5
11 COM64 -2093 -227.75 15 138.5 69 BM1 1580 -274.5 50 45 127 SEG19 1282.5 227.75 15 138.5
12 CIC -2066 -227.75 15 138.5 70 DT1 1645 -274.5 50 45 128 SEG20 1255.5 227.75 15 138.5
13 TST4 -1970 -274.5 50 45 71 VSSX 1710 -274.5 50 45 129 SEG21 1228.5 227.75 15 138.5
14 CS0 -1905 -274.5 50 45 72 DT2 1775 -274.5 50 45 130 SEG22 1201.5 227.75 15 138.5
15 RST -1840 -274.5 50 45 73 VDD1 1840 -274.5 50 45 131 SEG23 1174.5 227.75 15 138.5
16 CD -1775 -274.5 50 45 74 VDD2 1905 -274.5 50 45 132 SEG24 1147.5 227.75 15 138.5
17 WR0 -1710 -274.5 50 45 75 VDD3 1970 -274.5 50 45 133 SEG25 1120.5 227.75 15 138.5
18 WR1 -1645 -274.5 50 45 76 COM32 2066 -227.75 15 138.5 134 SEG26 1093.5 227.75 15 138.5
19 VDDX -1580 -274.5 50 45 77 COM31 2093 -227.75 15 138.5 135 SEG27 1066.5 227.75 15 138.5
20 D0 -1515 -274.5 50 45 78 COM30 2120 -227.75 15 138.5 136 SEG28 1039.5 227.75 15 138.5
21 D1 -1450 -274.5 50 45 79 COM29 2147 -227.75 15 138.5 137 SEG29 1012.5 227.75 15 138.5
22 D2 -1385 -274.5 50 45 80 COM28 2174 -227.75 15 138.5 138 SEG30 985.5 227.75 15 138.5
23 D3 -1320 -274.5 50 45 81 COM27 2201 -227.75 15 138.5 139 SEG31 958.5 227.75 15 138.5
24 D4 -1255 -274.5 50 45 82 COM26 2228 -227.75 15 138.5 140 SEG32 931.5 227.75 15 138.5
25 D5 -1190 -274.5 50 45 83 COM25 2255 -227.75 15 138.5 141 SEG33 904.5 227.75 15 138.5
26 D6 -1125 -274.5 50 45 84 COM24 2282 -227.75 15 138.5 142 SEG34 877.5 227.75 15 138.5
27 D7 -1060 -274.5 50 45 85 COM23 2309 -227.75 15 138.5 143 SEG35 850.5 227.75 15 138.5
28 VDD1 -995 -274.5 50 45 86 COM22 2336 -227.75 15 138.5 144 SEG36 823.5 227.75 15 138.5
29 VDD1 -930 -274.5 50 45 87 COM21 2363 -227.75 15 138.5 145 SEG37 796.5 227.75 15 138.5
30 VDD2 -865 -274.5 50 45 88 COM20 2363 227.75 15 138.5 146 SEG38 769.5 227.75 15 138.5
31 VDD2 -800 -274.5 50 45 89 COM19 2336 227.75 15 138.5 147 SEG39 742.5 227.75 15 138.5
32 VDD2 -735 -274.5 50 45 90 COM18 2309 227.75 15 138.5 148 SEG40 715.5 227.75 15 138.5
33 VDD3 -670 -274.5 50 45 91 COM17 2282 227.75 15 138.5 149 SEG41 688.5 227.75 15 138.5
34 VSS1 -605 -274.5 50 45 92 COM16 2255 227.75 15 138.5 150 SEG42 661.5 227.75 15 138.5
35 VSS1 -540 -274.5 50 45 93 COM15 2228 227.75 15 138.5 151 SEG43 634.5 227.75 15 138.5
36 VSS2 -475 -274.5 50 45 94 COM14 2201 227.75 15 138.5 152 SEG44 607.5 227.75 15 138.5
37 VSS2 -410 -274.5 50 45 95 COM13 2174 227.75 15 138.5 153 SEG45 580.5 227.75 15 138.5
38 VSS2 -345 -274.5 50 45 96 COM12 2147 227.75 15 138.5 154 SEG46 553.5 227.75 15 138.5
39 VSS2 -280 -274.5 50 45 97 COM11 2120 227.75 15 138.5 155 SEG47 526.5 227.75 15 138.5
40 VB1+ -215 -274.5 50 45 98 COM10 2093 227.75 15 138.5 156 SEG48 499.5 227.75 15 138.5
41 VB1+ -150 -274.5 50 45 99 COM9 2066 227.75 15 138.5 157 SEG49 472.5 227.75 15 138.5
42 DUMMY -85 -274.5 50 45 100 COM8 2039 227.75 15 138.5 158 SEG50 445.5 227.75 15 138.5
43 VB0+ -20 -274.5 50 45 101 COM7 2012 227.75 15 138.5 159 SEG51 418.5 227.75 15 138.5
44 VB0+ 45 -274.5 50 45 102 COM6 1985 227.75 15 138.5 160 SEG52 391.5 227.75 15 138.5
45 VB0- 110 -274.5 50 45 103 COM5 1958 227.75 15 138.5 161 SEG53 364.5 227.75 15 138.5
46 VB0- 175 -274.5 50 45 104 COM4 1931 227.75 15 138.5 162 SEG54 337.5 227.75 15 138.5
47 DUMMY 240 -274.5 50 45 105 COM3 1904 227.75 15 138.5 163 SEG55 310.5 227.75 15 138.5
48 VB1- 305 -274.5 50 45 106 COM2 1877 227.75 15 138.5 164 SEG56 283.5 227.75 15 138.5
49 VB1- 370 -274.5 50 45 107 COM1 1850 227.75 15 138.5 165 SEG57 256.5 227.75 15 138.5
50 VB1+ 435 -274.5 50 45 108 CIC 1823 227.75 15 138.5 166 SEG58 229.5 227.75 15 138.5
51 VB1+ 500 -274.5 50 45 109 SEG1 1768.5 227.75 15 138.5 167 SEG59 202.5 227.75 15 138.5
52 VLCDIN 565 -274.5 50 45 110 SEG2 1741.5 227.75 15 138.5 168 SEG60 175.5 227.75 15 138.5
53 VLCDIN 630 -274.5 50 45 111 SEG3 1714.5 227.75 15 138.5 169 SEG61 148.5 227.75 15 138.5
54 VLCDOUT 695 -274.5 50 45 112 SEG4 1687.5 227.75 15 138.5 170 SEG62 121.5 227.75 15 138.5
55 VLCDOUT 760 -274.5 50 45 113 SEG5 1660.5 227.75 15 138.5 171 SEG63 94.5 227.75 15 138.5
56 DUMMY 820 -274.5 45 45 114 SEG6 1633.5 227.75 15 138.5 172 SEG64 67.5 227.75 15 138.5
57 DUMMY 875 -274.5 45 45 115 SEG7 1606.5 227.75 15 138.5 173 SEG65 40.5 227.75 15 138.5
58 DUMMY 930 -274.5 45 45 116 SEG8 1579.5 227.75 15 138.5 174 SEG66 13.5 227.75 15 138.5
Revision A1.0 45
ULTRACHIP
# Pad X Y W H # Pad X Y W H
175 SEG67 -13.5 227.75 15 138.5 235 SEG127 -1633.5 227.75 15 138.5
176 SEG68 -40.5 227.75 15 138.5 236 SEG128 -1660.5 227.75 15 138.5
177 SEG69 -67.5 227.75 15 138.5 237 SEG129 -1687.5 227.75 15 138.5
178 SEG70 -94.5 227.75 15 138.5 238 SEG130 -1714.5 227.75 15 138.5
179 SEG71 -121.5 227.75 15 138.5 239 SEG131 -1741.5 227.75 15 138.5
180 SEG72 -148.5 227.75 15 138.5 240 SEG132 -1768.5 227.75 15 138.5
181 SEG73 -175.5 227.75 15 138.5 241 COM33 -1823 227.75 15 138.5
182 SEG74 -202.5 227.75 15 138.5 242 COM34 -1850 227.75 15 138.5
183 SEG75 -229.5 227.75 15 138.5 243 COM35 -1877 227.75 15 138.5
184 SEG76 -256.5 227.75 15 138.5 244 COM36 -1904 227.75 15 138.5
185 SEG77 -283.5 227.75 15 138.5 245 COM37 -1931 227.75 15 138.5
186 SEG78 -310.5 227.75 15 138.5 246 COM38 -1958 227.75 15 138.5
187 SEG79 -337.5 227.75 15 138.5 247 COM39 -1985 227.75 15 138.5
188 SEG80 -364.5 227.75 15 138.5 248 COM40 -2012 227.75 15 138.5
189 SEG81 -391.5 227.75 15 138.5 249 COM41 -2039 227.75 15 138.5
190 SEG82 -418.5 227.75 15 138.5 250 COM42 -2066 227.75 15 138.5
191 SEG83 -445.5 227.75 15 138.5 251 COM43 -2093 227.75 15 138.5
192 SEG84 -472.5 227.75 15 138.5 252 COM44 -2120 227.75 15 138.5
193 SEG85 -499.5 227.75 15 138.5 253 COM45 -2147 227.75 15 138.5
194 SEG86 -526.5 227.75 15 138.5 254 COM46 -2174 227.75 15 138.5
195 SEG87 -553.5 227.75 15 138.5 255 COM47 -2201 227.75 15 138.5
196 SEG88 -580.5 227.75 15 138.5 256 COM48 -2228 227.75 15 138.5
197 SEG89 -607.5 227.75 15 138.5 257 COM49 -2255 227.75 15 138.5
198 SEG90 -634.5 227.75 15 138.5 258 COM50 -2282 227.75 15 138.5
199 SEG91 -661.5 227.75 15 138.5 259 COM51 -2309 227.75 15 138.5
200 SEG92 -688.5 227.75 15 138.5 260 COM52 -2336 227.75 15 138.5
201 SEG93 -715.5 227.75 15 138.5 261 COM53 -2363 227.75 15 138.5
202 SEG94 -742.5 227.75 15 138.5
203 SEG95 -769.5 227.75 15 138.5
204 SEG96 -796.5 227.75 15 138.5
205 SEG97 -823.5 227.75 15 138.5
206 SEG98 -850.5 227.75 15 138.5
207 SEG99 -877.5 227.75 15 138.5
208 SEG100 -904.5 227.75 15 138.5
209 SEG101 -931.5 227.75 15 138.5
210 SEG102 -958.5 227.75 15 138.5
211 SEG103 -985.5 227.75 15 138.5
212 SEG104 -1012.5 227.75 15 138.5
213 SEG105 -1039.5 227.75 15 138.5
214 SEG106 -1066.5 227.75 15 138.5
215 SEG107 -1093.5 227.75 15 138.5
216 SEG108 -1120.5 227.75 15 138.5
217 SEG109 -1147.5 227.75 15 138.5
218 SEG110 -1174.5 227.75 15 138.5
219 SEG111 -1201.5 227.75 15 138.5
220 SEG112 -1228.5 227.75 15 138.5
221 SEG113 -1255.5 227.75 15 138.5
222 SEG114 -1282.5 227.75 15 138.5
223 SEG115 -1309.5 227.75 15 138.5
224 SEG116 -1336.5 227.75 15 138.5
225 SEG117 -1363.5 227.75 15 138.5
226 SEG118 -1390.5 227.75 15 138.5
227 SEG119 -1417.5 227.75 15 138.5
228 SEG120 -1444.5 227.75 15 138.5
229 SEG121 -1471.5 227.75 15 138.5
230 SEG122 -1498.5 227.75 15 138.5
231 SEG123 -1525.5 227.75 15 138.5
232 SEG124 -1552.5 227.75 15 138.5
233 SEG125 -1579.5 227.75 15 138.5
234 SEG126 -1606.5 227.75 15 138.5
UC1701X
47
1.94 Z
7x22=154
1.77
10Y
°
L1
L3
L2
Py
Sy
20-199x34-24
P1
P2
S
Sx
L2
P1
T
10°
P2
X Px
T
L3
L1
TRAY INFORMATION
Unless Otherwise
Specified
Unit mm
General N/A
Roughness
Revision A1.0
Tolerance
Dimension +/-0.1
Angle N/A
ULTRACHIP
REVISION HISTORY
Revision Contents Date of Rev.
0.6 First release Jul. 29, 2008
(1) A new register, APC, is added.
(Section “Control Registers”, page 10)
(2) Command “Set Advanced Program Control” is split into 2 commands.
(Section “Command Table”, - (25)(26), page 12;
0.7 “Command Description“ – (25)(26), page 17) Aug. 8, 2008
(3) The sample codes for Power-Up are updated.
(Section “Sample Command Sequences for Power Management”, page 34)
(4) The tray drawing is updated.
(Section “Tray Information”, page 46)
(1) VLCD data are updated.
(Section “VLCD Quick Reference”, page 19)
(2) The description on Mux-Rate is updated.
(Section “LCD Display Controls” – Clock & Timing Generator, page 21)
0.8 Aug. 27, 2008
(3) Power consumption data present.
(Section “Specifications” – Power Consumption, page 37)
(4) Some AC timings are adjusted.
(Section “AC Characteristics”, Pp 38~40)
(1) The setting of WR[1:0] in S8 mode is updated: 0 Æ –
(Section “Pin Description” – WR1~0, page 7;
“Host Interface”, page 25)
1.0 (2) Power Up and Enter/Exit Sleep Mode sequences are updated. Nov. 7, 2008
(Section “Reset & Power Management”, page 32)
(3) ESD data are corrected.
(Section “ESD Consideration”, page 36)

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Cr

65x132 STN Controller-Driver

MP Specifications November 7, 2008

BARE DIE DISCLAIMER

LIFE SUPPORT APPLICATIONS

PAGE ADDRESS GENERATOR

ROW ADDRESS GENERATOR

DATA RAM I/O BUFFER

DISPLAY DATA LATCHES

COMMAND LEVEL SHIFTERS VLCD & BIAS CL

Name Type Pins Description

Name Type Pins Description

RECOMMENDED COG LAYOUT

UC1701x Bump View

NOTES FOR VDD WITH COG:

Name Bits Default Description

Name Bits Default Description

1. Write Data Byte to Memory

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

2. Read Data Byte from Memory

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

4. Set Column Address

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

5. Set Power Control

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

6. Set Scroll Line

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

7. Set Page Address

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

8. Set VLCD Resistor Ratio

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

9. Set Electronic Volume

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

10. Set All Pixel ON

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

11. Set Inverse Display

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

12. Set Display Enable

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

13. Set SEG Direction

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

14. Set COM Direction

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

15. System Reset

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

17. Set LCD Bias Ratio

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

18. Set Cursor Update Mode

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

19. Reset Cursor Update Mode

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set AC3=0 and CA=CR.

20. Set Static Indicator OFF

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

21. Set Static Indicator ON

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

22. Set Booster Ratio