ASIC design of Pulpino

Contents:
1- RTL editing ………………………………………………………………………………………………………………..........
2- RTL simulation …………………………………………………………………………………………………………………..
3- Logic synthesis …………………………………………………………………………………………………………………..
4- Formality checking …………………………………………………………………………………………………………….
5- Placement and route ………………………………………………………………………………………………………...
- Data setup …………………………………………………………………………………………………………………..
- Floorplanning ………………………………………………………………………………………………………………
- Power network ……………………………………………………………………………………………………………
- Placement …………………………………………………………………………………………………………………..
- Clock tree synthesis …………………………………………………………………………………………………….
- Routing ……………………………………………………………………………………………………………………….
- STD filling …………………………………………………………………………………………………………………...
- Metal filling …………………………………………………………………………………………………………………
- Writing output data …………………………………………………………………………………………………….
6- Physical verification …………………………………………………………………………………………………………..
- DRC checking ………………………………………………………………………………………………………………
- LVS checking ……………………………………………………………………………………………………………….
7- Formality checking ….…………………………………………………………………………………………………………
8- Static timing analysis …………………………………………………………………………………………………………
9- Problems and solutions …………………………………………………………………………………………………….
Placement and Route
 Data setup

- Preparing macro cells:

We used TSMC memory compiler to generate our macro cells.

First, we have a problem in memory macro cells that are generated from TSMC memory compiler.

We tried to design a memory cell with TSMC memory compiler that is 1K * 8 bit memory block with
disabling M5 from power mesh.

After generating all files of memory cell, we found that the metal stack of this cell in gds file (using gds
viewer “Klayout”) is from M1 to M4 (as expected), as M4 is power straps of memory macro cell.

But we found in generated .Lef file, blockage on M5 for all macro area that immunes router from
connecting any shapes (nets or vias) on M4, that makes power and ground pins are not connecting with
chip power network.

We tried to modify in .Lef file (hack generated .Lef file from memory compiler) and remove this blockage
on M5 manually.

After doing this we found that, power and ground pins on macros are connected to whole design power
network and everything is ok without DRC violations.

- Generating ndm library format:

We used library manager tool (provided by synopsis) to generate ndm library format of standard cells,
macros, and IO pads.

Figure-1 shows library manager inputs and output

Library manager generates ndm library format of standard cells, macro cells, IO pads, and physical only
cells depending on timing model in .db file and frame view in .lef file.

We use generate ndm from library manager to create our design libraries.
- Reading different RC models:
We have different models of RC parasitics of tluplus files that are typical, worst C, best C, worst RC, and
best RC.

That are used as per length delay model of wires.

We read different RC models and create different scenarios of delay modeling.

Optimization tool uses different scenarios to optimize the design to meet all scenarios without any
timing violations.

- Reading design files:

Finally in this step, we read synthesis netlist and design constraints and linking netlist with ndm library
formats.
 Floorplanning
- Choosing dimensions:
According to TSMC 65nm taping out, the height of chip must be multiple of 0.5X mm.

So, our chip dimensions is as shown in figure-2.

Please note that our design is memory and pad limited.

Figure-2 shows dimensions of both height and width for core and die dimensions also offset between
die and core areas (all dimensions in um)

The following table shows important notes when choosing dimensions of layout:

Dimension note
Core width = 1350.4 Must be multiple of 0.2 (cell site)
Core height = 1275.4 Must be multiple of 1.4 (site row)

When you don’t respect the above dimension rules, you will get a lot of DRC violations that are not
solvable manually.

The following table shows DRC violations and their reasons when you don’t respect dimension rules:

Dimension reason
NW, OD spacing
NW enclosure Because of misalignment of top pads.
P+ active extension Because of empty areas of standard cells.
Overlap of PP and OD
Important note that you must take into account is NW and OD layers must be continuous to avoid the
above problems plus another problems like LUP.

- Macro placement:
We place macros in the lower area of chip, after more tries this gets good result according to congestion
analysis.

We also flip macros to 180 degree, as macro pins is on bottom site of block that also get good results, as
shown in figure-3.

Figure-3 shows macro placement in lower core area

- IO pad placement:
According to IO pads there are IO pads plus special power pads, the following table shows IO pads plus
special pads we use in our design.

Pad name Pad usage

PDDW0408SCDG Input/ output pad
PVDD1CDG Core power
PVSS1CDG Core ground
PVDD2CDG IO ring power
PVSS2CDG IO ring ground
PVDD2POC IO ring POC
IO pad placement is important thing to do, you can follow flylines using ICC synopsis tool to get shortest
and less congestion routing wires.

Also good choosing of core to die offset, will help to get more good results.

These methods are done with trying and debugging to get good results, figure-4 shows IO pad
placement.

Figure-4 shows IO pad placement of our design

The following table shows the function of each IO pad:

Pin name Usage

uart_rx_pad_A
UART_1
uart_tx_pad_A
(payment sensor)
gpio_out_pad_10
uart_rx_pad_B
UART_2
uart_tx_pad_B
(RF communication)
gpio_out_pad_11
uart_rx_pad_C UART_3
uart_tx_pad_C (IR communication)
gpio_in_pad_0
gpio_in_pad_1
5-pins interrupts
gpio_in_pad_2
(Hall effect sensor)
gpio_in_pad_3
gpio_in_pad_4
gpio_in_pad_5 Pin interrupt (Touch)
gpio_out_pad_9 Led output
gpio_in_pad_6 Pin interrupt (Meter cover)
gpio_in_pad_7 2-pin interrupt
gpio_in_pad_8 (Feedback from valve)
gpio_out_pad_5
3 output pins
gpio_out_pad_6
(To valve driver)
gpio_out_pad_7
gpio_in_pad_9 Pin interrupt (Fraud)
PAD_rst Pin interrupt (Reset)
gpio_out_pad_0
gpio_out_pad_1
5 output pins
gpio_out_pad_2
(LCD driver)
gpio_out_pad_3
gpio_out_pad_4
gpio_out_pad_8 Out pin (back light)
tck
trstn
JTAG
tms
(downloading and debugging)
tdi
tdo
fetch_enable
testmode
poc
spi_master_clk
spi_master_csn0
Master SPI
spi_master_sdo0_pad
spi_master_sdi0_pad
I2C_da_i
I2C_da_o
I2C
I2C_cl_i
I2C_cl_o
pwr_io1
pwr_io2
IO power and ground
grd_io1
grd_io2
pwr_core1
pwr_core2
pwr_core3
pwr_core4
Core power and ground
grd_core1
grd_core2
grd_core3
grd_core4
PAD_CLK Input clk (crystal oscillator)
ADC_in Analog ADC input
Total number of pins 59
As we said before, you must take into account the continuity of NW, power ring straps, and also PO and
OD continuity.

So, corner pads and filler pads must be added to guarantee continuity of all layers in pads.

PFILLxx and PCORNER pads are used as filling and corner pads.

- Adding boundary cells:

We add boundary cells around all sides of chip to guard standard cells against manufacturing damage to
a regular cells that is located close to the boundaries.

DCAPxx cells are used as boundary cells.

- Performing floorplanning placement:

In this step, we do an initial placement of standard cells.

Here, we tell the tool to not care about hierarchy in placing standard cells, to use ultra-effort congestion
analysis, and to use high effort timing driven placement.
 Powerplanning

- Adding TAP cells:

First we add TAP cells with respecting minimum distance between two TAP cells as described in rule file
to prevent LUP problems.

Make sure that you make placement legalization to prevent standard cells overlapping.

- Creating core ring:

We change default metal width to our design of ring width and choosing suitable metal layers for it.

The following table shows our design of core power ring:

Attribute name value

Vertical metal layer M8
Horizontal metal layer M7
Vertical width 12 um
Horizontal width 12 um

- Creating core straps:

We change default metal width to our design of straps width and choosing suitable metal layers for it.

The following table shows our design of core power straps:

Attribute name value

Vertical metal layer 1 M8
Vertical metal layer 2 M6
Vertical width 1 9 um
Vertical width 2 1.5 um
Vertical pitch 1 30 um
Vertical pitch 2 25 um
Horizontal metal layer 1 M9
Horizontal metal layer 2 M5
Horizontal width 1 9 um
Horizontal width 2 1.5 um
Horizontal pitch 1 30 um
Horizontal pitch 2 25 um

- Creating core rails:

We use M1 to crating power rails for each site row, to connect power and ground of each standard cell
to core rails.
- Analyzing IR drop and congestion:
The above choosing of metal layers and metal width is after debugging to design a good power network
with low IR drop, to make sure that IR drop doesn’t effect on delay and also congestion due to tower
VIAs from higher layer to lower layers.

Problem Solution
- Using higher metal layers to build straps.
- Good distribution of metal straps.
High IR drop (from 55mv to 33mv)
- Using inner metal layers to break VIAs tower.
- Placing power pads in the middle order of each side.
Good distribution of metal straps helps us to reduce congestion
High routing congestion
before placement stage.
Some metal trunks are not Using M7 as horizontal ring instead of M9.
connected to power pad

As shown in figure-5, the maximum IR drop is 33.87 mv (about 2.82% of VDD).

Figure-5 shows power network voltage drop

Figure-6 shows metal trunks problem as these opens prevent short between VDD and VSS with vertical
strap, and figure-7 shows metal trunks after solving this problem.

Figure-6 Figure-7
 Placement

- Performing placement spacing rule:

We know that good design is specified as is standard cell placement is good or not.

Good placement deals with good congestion analysis and good timing of paths.

Figure-8 shows global route congestion map before placement.

As we show the maximum overflow is from 7 to 16 (this is actually a big value that will make DRC errors
in routing stage like shorts).

Figure-8 shows congestion analysis of standard cells

After debugging, we found that the most congested cell is AOI cell, as it has large number of input pins
as shown in figure-9.

Figure-9 shows number of pins of AOI cell

We create a placement spacing rule to standard cells that have bigger number of pins.

- Defining clock tree rules:

Defining clock tree rules before performing placement is a very important thing to do, this helps
placement engine to imagine clock tree and optimize results according to these imaginations.

- Performing placement:
We perform placement by using place_opt command in synopsis ICC tool.

The place_opt command consists of the following stages:

1. Initial placement (initial_place)

2. Initial DRC violation fixing (initial_drc)
3. Initial optimization (initial_opto)
4. Final placement (final_place)
5. Final optimization (final_opto)
6. Legalization

Figure-10 shows congestion map after placement.

Only 7 nets are overflow from 4 to 3, and 133 nets are from 2 to 1.

Figure-10 shows congestion map after making good placement

 Clock tree synthesis

- Defining clock tree non-default rules:

Defining non-default routing rules of clock roots helps use to get good results of clock skew and clock
transition.

Also using higher metal layer to build clock roots helps us to get good results.

- Adding clock tree cells:

Adding clock cells (like buffers or inverters) helps us to get good results of clock transition.

We choose a specific cells to be added during building clock tree.

For example: clock buffer is not look like normal buffer.

Clock buffer guarantee that rising transition and falling transition are equal.

That’s make clock buffer bigger than normal buffer.

- Building clock tree:

We perform CTS by using clock_opt command in synopsis ICC tool.

The clock_opt command consists of the following stages:

1. build_clock
2. route_clock
3. final_opto

- Performing Concurrent Clock and Data Optimization:

We can perform CTS optimization by using the following methods in synopsis tool:

1. Splitting Clock Cells

2. Using clock_opt -from final_opto to perform only optimization after clock tree building.
 Routing

- Choosing routing metal layers:

We use (M9, M8, M5, and M4) for power network, M6 and M7 for roots of clock, and M1 for power
rails.

We control the tool to route nets with remaining metal layers (from M2 to M7), and reach to cell pins by
metal contacts to M1.

- Performing routing:
We use route_opt command in synopsis ICC tool.

The route_opt command consists of the following stages:

1. Performs extraction and updates the timing.

2. Performs the enabled optimizations.
3. Legalizes the block.
4. Performs ECO routing.

- Analyzing and fixing shorts:

First we solve routing shorts, we use check_lvs command in synopsis tool to analyze short circuit nets.
We solve shorts by:

1. Performing route_eco command with increasing number of iterations.

2. Manually solve it.

- Analyzing and fixing initial DRC reports:

We check DRC first on ICC tool and solve initial DRC violations.

We solve DRC violations by:

1. Performing signoff_fix_drc command on ICC tool.

2. Manually solve it.
 STD filling

- Why STD filling:

To guarantee continuity of NW, avoid PO minimum density DRC rule, and avoid OD minimum density
DRC rule.

- Choosing filler cells:

First we add DCAP cells as filler cells, these cells act as filler cells and DCAP capacitor to reduce IR drop in
power network.

But here there is a problem, DCAP cells have metal shapes in different metal layers especially in metal1,
so we will get DRC violations with routed wires.

After adding filler cells, we remove STD cells with violations using remove_stdcell_fillers_with_violation
command in ICC tool.

After that we add normal filler cells that is have empty metal shapes inside these cells.

- Solving minimum OD density trick:

In our technology, smallest filler cells which are FILLBWP7T and FILL2BWP7T, there is no OD shapes
inside these cells.

And when we tell layout tool (IC compiler in our case), take this list of filler cells to be used during STD
filling, ICC start filling with smallest filler cell.

Using only smallest filler cells which have no OD shapes will make a minimum OD density violations.

So the good technique to use filler cells:

1. Use DCAP cells as filler cells.

2. Use bigger size filler cells first.
3. Remove violations related to STD filling.
4. Use medium size filler cells.
5. Finally use smallest size filler cells.

When you follow the above technique of STD filling, you will get your design free of PO minimum
density violations, OD minimum density violations, and LUP violations.
 Metal filling

- Types of metal filling:

There is two types of metal filling using layout tool:

1. Track based metal filling.

2. Pattern based metal filling.

- Track based metal filling:

This technique use design rules in technology file, and make metal filling on metal layers only.

- Pattern based metal filling:

In this technique, we need runsets to be used during metal filling.

There is two runsets for metal filling:

1. Dummy FEOL runset.

2. Dummy BEOL runset.

FEOL stands for Front End Of Line.

BEOL stands for Back End Of Line.

Figure-11 shows the difference between FEOL and BEOL.

Figure-11

After making metal filling using pattern base technique, we will get our design free of any minimum
density violations on metal layers, OD layer, PO layer, and dummy layers.
 DRC checking

- Pre-DRC checking:
1. Generate your layout GDS file from your layout tool.
2. For pattern based metal fill, use ICV or Calibre to generate separately filling files and
then merge all files using Calibre.
3. Active MIXED_SCHEME to define different datatypes.
4. Check your results using ICV or Calibre.

- Manually solve DRC:

The following DRC rules are solved manually:
1. Adjacent edge.
2. Minimum number of VIAS (VIA array size).
Other DRC rules can be solved using route_eco or signoff_fixed_drc commands, also tool can’t
solve all violations.

- Metal filling commands:

1. Open metal filling runset and put a complete path of your design and design top cell.
2. Write the following in linux terminal at the same runset location:
Calibre –drc “your runset file”
3. Do this for FEOL and BEOL runsets.

- Merging GDS files:

1. Put generated GDS files in one folder.
2. Put Pulpiuno GDS file in another folder.
3. Type the following in linux terminal:
Calibredrv -a layout filemerge -in “original_file.gds” -indir “directory of generated gds” -
out “name and directory of generated gds” -topcell “top module”
 LVS checking

- Pre-LVS settings:
1. Make sure that power and ground nets are physically connected not only logically.
2. Generate netlist with excluding physical only cells, nothing else.
3. Generate GDS file only with option “output_pin all”, there is no need to generate all text of all
nets and shapes, use default settings.
4. Modify layer map file for correctly map text on text layers not on metal layers.
5. Generate GDS after adding filler cells to make sure that N-well and P-substrate are connected to
VDD and VSS using TAP cells.

- Using pad cells:

1. It’s must to use IO power pads (special pads) that are:
PVDD1CDG
PVSS1CDG
PVDD2CDG
PVSS2CDG
PVDD2POC
2. Use filler pads and corner pads to get VDD, VSS, VDDPST, VSSPST, and POC continue for
all IO ring.
3. Add manually POC labels on M1 POC net.
Category Problem solution
Don’t care about DRC in ICC.
Keep out margin violation inside STD cells
Make your checks in an authentication tool
on M1 in ICC.
like calibre or ICV.
Forbidden data type for specific VIA and It’s recommended to active MIXED_SCHEME
metal layers. switch to show all data types.
NW spacing
Make sure that your core height is multiple of
NW enclosure
site row (1.4).
NW extension
Make sure that your core width is multiple of
OD spacing
cell site (0.2).
OD enclosure
No routes reach to M4 straps of macro Hack your LEF file and remove blockage on
cells. M5.
Make sure that your merged GDS file is
correct.
Macro cells are not mapped correctly.
Write a complete path of macro GDS in
merged files option.
DRC Use different VIA shape.
Adjacent on metal layers.
Manually add metal layers.
Remove wires and perform route_eco.
Unresolved short nets.
Reduce number of columns of VIAs.
Perform pattern based metal fill separately
Avoid minimum density violations.
using ICV or calibre, then merge all GDS files.
First use larger filler cells, then use smaller as
Minimum density of OD in STD area.
smaller filler cells has no OD shapes.
Use TAP cells with spacing less than 30 um
LUP violations between STD cells.
between each others.
Use placement blockage after placing macros
LUP violations between macros. to prevent STD cells to be placed between
macros.
LUP violations in top and bottom sides of First place TAP cells then place boundary
boundary cells. cells.
Make sure every cell is mapped correctly
STD cells floating gates
during writing GDS file, especially macro cells.
Ports are not mapped on text layers Hacking layer map and write it manually.
Manually add POC label on M1 that is
LVS POC port is not mapped correctly connected to POC strap on M3 using
calibrevdrv.
VDD missing nets in source netlist
Use lower metal layers (for example M7) as
Opens in power trancks
horizontal ring.
others Use ultra-effort of congestion optimization
A lot of congestion and shorts during placement stage.
Use placement spacing rule.