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DFT Workshop

Experiment Findings · January 2019

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 Three Day National Level Workshop on Vellore Institute of Technology
Vellore Institute of Technology (VIT) was founded in 1984 as Vellore Engineering College by
the Chancellor Dr. G.Viswanathan.VIT attracts students from all the 29 states of India and
DESIGN FOR TESTABILITY (DFT) more than 41 different countries because of its academic excellence. The credentials of VIT in
academics and research, has placed VIT in the 13th position among the engineering
In association with Entuple Technologies Private Limited, Bangalore institutions and VIT Business School has placed 17th position among the business schools in
India by NIRF, Govt. of India Ranking. The world ranking body namely the QS has given 4 STAR
1st to 3rd February 2019 rating to VIT, with that VIT becomes the first institution in India to have the 4 STAR rating. In
addition to this, the consortium of industries, FICCI has adjudged VIT as the “Excellence in
Faculty”. VIT has also completed 3 cycles of NAAC accreditation and has been rated as “A”
grade institution. VIT has introduced many innovations in academic processes which adds
value to every student. FFCS (Fully Flexible Credit System), PBL (Project Based Learning) for
better learning, fully digitized academic portals that assists students in equipping themselves
for 2020 market place.

School of Electronics Engineering

School of Electronics Engineering (SENSE) at VIT was established for imparting state-of-the-
art knowledge in Electronics and Communication Engineering and allied areas. B.Tech. ECE
program was accredited by the Engineering Accreditation Commission of ABET,
http://www.abet.org. Almost 100% of the students get job from the campus placement
and many of them are placed in core companies every year. The School has state-of-the art
laboratories in almost all the areas of Electronics, Communication, VLSI, Embedded, Sensors
and Nano Technology. The School has many industry sponsored advanced laboratories for
doing research. The School has signed MoUs with many foreign Universities, research
organizations and Industries from where students get benefits for their R&D Work / Projects
Coordinators from the MoUs.

Dr. S. Sivanantham & Prof. C. Prayline Rajabai Department of Micro and Nano Electronics
The department of Micro and Nano Electronics offers M.Tech programs on VLSI Design and
Organized by Nanotechnology. It has industrial standard laboratory catering the need for complete IC
design cycle. Laboratories are fully equipped with industry standard EDA Tools like Cadence
Department of Micro and Nano Electronics (60 Licences), Synopsys (60 Licences) and Mentor Graphics (120 licenses).
School of Electronics Engineering
Entuple Technologies
Entuple Technologies is a next generation solutions enabler in cutting edge technologies.
Entuple delivers world class simulation solutions in Applied Electromagnetics, VLSI, System
Design & Reliability, Mechanical, CFD and RF. Entuple offer R & D consulting, Simulation &
Design Services, Prototyping, Testing, IP services, . Entuple has developed its own range of
semiconductor based power drives and process control solutions. Entuple cater to corporate,
Vellore – 632014, Tamilnadu, India manufacturing, defense & aerospace and academia.
Objective of the Workshop Who can attend?
Design For Testability (DFT) is a specialization in the SOC design cycle, which facilitates a This course is designed for the Faculty members, Research scholars, UG/PG students and
design for detecting manufacturing defects. With increase in size & complexity of chips, working VLSI/ Electronics engineers who want to learn / enhance their knowledge on Design
facilitated by advancement of manufacturing technologies, it has evolved as a specialization For Testability (DFT) and become Skilled DFT engineers.
in itself over a period of time. DFT Engineers, works on introducing various test structures as
part of the design flow, to increase the testability of logic, pads, memories, interconnects. Pre-requisites
 Knowledge of digital design.
The course is designed and will be delivered by experts in DFT. Importance is given to cover  Knowledge of ASIC / SOC design flow.
the concepts, methodology thoroughly with good emphasis on hands-on training, using  At least 1 year of work experience in ASIC or SOC Design Flow.
Industry Standard DFT tools with at least 50 % time allocated to lab sessions.  Prior knowledge of DFT is not required

Resource Persons
Cadence EDA Tools used in this course  Mr. Sharath Kanth, Entuple Technologies Pvt. Limited, Bangalore
Genus (formerly RTL Compiler), Modus DFT Solution (formerly known as Encounter Test), and  Mr. Santhosh, Entuple Technologies Pvt. Limited, Bangalore
Xcelium™ Parallel Simulator, LBIST and PMBIST.  Dr.S.Sivanantham, Vellore Institute of Technology, Vellore
 Mr.Renold Sam Vedhamuthu, DFT Lead, Microsemi, Bangalore
Course Schedule
Registration Fee (including GST)
Student / Full Time Research Scholar : Rs. 1500/-
Day-1:
Faculty Members : Rs. 2000/-
 Session 1: Role of DFT in ASIC Design flow
Industry Persons : Rs. 3000/-
 Session 2: Logic Synthesis and DFT – Overview
 Session 3: Logic Synthesis and DFT flow (Lab) For registration please use the following link:
 Session 4: Logic Synthesis and DFT flow (Lab) https://tinyurl.com/dftworkshop

Day-2: Note: Accommodation will be provided based on availability on paid basis in Student’s Hostel.
Certificate and Working Lunch will be provided for all participants.
 Session 1: Concepts of LBIST, Scan & Insertion
 Session 2: LBIST insertion into a top level design (Lab) Important Dates
 Session 3: LBIST insertion with Test Points into Top-Level Design (Lab) Last date of Registration : 25th January 2019
 Session 4: Concepts of MBIST and flow Workshop Dates : February 1-3, 2019 (Time: 9.30 AM to 5.30 PM)

Day-3: Coordinators
 Session 1: Concepts of LBIST, Scan & Insertion Dr. S. Sivanantham ([email protected]; +91 98944 32359) &
 Session 2: MBIST Top down flow (Lab) Prof. C. Prayline Rajabai ([email protected]; +91 7200577872)
 Session 3: MBIST multi block bottom up flow Department of Micro and Nano Electronics, School of Electronics Engineering,
 Session 4: MBIST Diagnostics, Redundancy & Repair (Lab)
 Embedded Memory Test Bus (Lab)
For queries on Registration:
Mr. V. Karthikeyan, Technical Officer, VIT. E-mail: [email protected]; Mobile: +91 98949 72399
Mr. Damodara M S, Entuple. E-mail: [email protected]; Mobile: +91 96111 09555

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