Chapter 2 (Part-2)

By
Sanchari Guha
Contents
• Threshold Voltage Effects
• Leakage
• Temperature Dependance
• Geometry Dependence
• DC Transfer Characteristics
 2.4.3 Threshold Voltage Effects
• Vt increases with the source voltage, decreases with the body voltage, decreases
with the drain voltage, and increases with channel length.
• Body Effect: Vsb increases the amount of charge required to invert the channel,
hence, it increases the threshold voltage. The threshold voltage can be modeled
as when,

For small voltages applied to the source or body,

 Threshold Voltage Effects
• Drain-Induced Barrier Lowering: V ds creates an electric field that affects the
threshold voltage. This drain-induced barrier lowering (DIBL) effect is especially
pronounced in short-channel transistors. It can be modeled as
• Short Channel Effect: Threshold voltage typically increases with channel length.
This phenomenon is especially pronounced for small L where the source and
drain depletion regions extend into a significant portion of the channel, and
hence is called the short channel effect or Vt rolloff. In some processes, a reverse
short channel effect causes Vt to decrease with length. There is also a narrow
channel effect in which Vt varies with channel width; this effect tends to be less
significant because the minimum width is greater than the minimum length.
 2.4.4 Leakage
Leakage mechanisms include subthreshold conduction
between source and drain, gate leakage from the gate to body,
and junction leakage from source to body and drain to body.
Subthreshold conduction is caused by thermal emission of
carriers over the potential barrier set by the threshold.
Gate leakage is a quantum-mechanical effect caused by
tunneling through the extremely thin gate dielectric. Junction
leakage is caused by current through the p-n junction between
the source/drain diffusions and the body.
 Leakage
• Subthreshold Leakage: The long-channel transistor I-
V model assumes current only flows from source to
drain when Vgs > Vt. In real transistors, current does
not abruptly cut off below threshold, but rather
drops off exponentially. When the gate voltage is
high, the transistor is strongly ON. When the gate
falls below V t , the exponential decline in current
appears as a straight line on the logarithmic scale.
W h e n V g s < V t i s ca l l e d we a k i nve rs i o n . T h e
subthreshold leakage current increases significantly
with Vds because of drain-induced barrier lowering.
 Leakage
• Gate Leakage: There is a nonzero probability that an
electron in the gate will find itself on the wrong side of
the oxide, where it will get whisked away through the
channel. This effect of carriers crossing a thin barrier is
called tunneling, and results in leakage current through
the gate.
Two physical mechanisms for gate tunneling are called
Fowler-Nordheim (FN) tunneling and direct tunneling.
FN tunneling is most important at high voltage and
moderate oxide thickness and is used to program EEPROM
memories.
Direct tunneling is most important at lower voltage with
thin oxides and is the dominant leakage component. The
direct gate tunneling current can be estimated as
Plots gate leakage current density (current/area) JG against
voltage for various oxide thicknesses. Gate leakage
increases by a factor of 2.7 or more per angstrom
reduction in thickness
 Leakage
• Junction Leakage: Reverse-biased diodes still conduct a small amount of current
ID. IS depends on doping levels and on the area and perimeter of the diffusion
region and VD is the diode voltage.

• Heavily doped drains are subject to band-to-band tunneling (BTBT) and gate-
induced drain leakage (GIDL).
• BTBT occurs across the junction between the source or drain and the body when
the junction is reverse-biased. It is a function of the reverse bias and the doping
levels.

• GIDL occurs where the gate partially overlaps the drain. This effect is most
pronounced when the drain is at a high voltage and the gate is at a low voltage.
GIDL current is proportional to gate-drain overlap area and hence to transistor
width. It is a strong function of the electric field and hence increases rapidly with
the drain-to-gate voltage.
 2.4.5 Temperature Dependence
• Transistor characteristics are influenced by temperature. Carrier mobility
decreases with temperature. An approximate relation is

• BTBT increases slowly with temperature, and gate leakage is almost independent
of temperature. High Vgs, the current has a negative temperature coefficient.

• Two popular lab tools for

determining temperature
dependence in circuits are
a can of freeze spray and
a heat gun.
 2.4.6 Geometry Dependence
The layout designer draws transistors with width and length Wdrawn and Ldrawn. The
actual gate dimensions may differ by some factors XW and XL.
For example, the manufacturer may create masks with narrower polysilicon or may
overetch the polysilicon to provide shorter channels (negative XL) without changing
the overall design rules or metal pitch. The source and drain tend to diffuse
laterally under the gate by LD, producing a shorter effective channel length that the
carriers must traverse between source and drain. Similarly, WD accounts for other
effects that shrink the transistor width.
Putting these factors together, we can compute effective transistor lengths and
widths.
 DC Transfer Characteristics
• The DC transfer characteristics of a circuit relate the output voltage to the input
voltage. Specific ranges of input and output voltages are defined as valid 0 and 1
logic levels.
• Static CMOS Inverter: In this table, Vtn is the threshold voltage of the n-channel
device, and Vtp is the threshold voltage of the p-channel device. Note that Vtp is
negative. The equations are given both in terms of Vgs /Vds and Vin /Vout. As the
source of the nMOS transistor is grounded, V gsn = V in and V dsn = V out . As the
source of the pMOS transistor is tied to VDD, Vgsp = Vin – VDD and Vdsp = Vout – VDD.
DC Transfer Characteristics
(a) The plot shows Idsn and Idsp in
terms of Vdsn and Vdsp for various
values of Vgsn and Vgsp.
(b)The same plot of I d s n and
|I dsp | now in terms of Vout for
various values of Vin. The
possible operating points of the
inverter, marked with dots, are
the values of V o u t where I d s n
=|I dsp | for a given value of V in .
T h e s e o p e rat i n g p o i nt s a re
plotted on Vout vs Vin.
DC Transfer Characteristics
• V i n a xe s i n ( c ) t o s h o w t h e i nv e r t e r D C t ra n s fe r
characteristics. The supply current IDD = Idsn = |Idsp| is also
plotted against Vin. The state of each transistor in each
region is shown in Table

• (d) showing that both transistors are momentarily ON as

V in passes through voltages between GND and VDD,
resulting in a pulse of current drawn from the power
supply.
 Beta Ratio Effects
Inverters with different beta ratios r = βp /βn are called skewed inverters.
If r > 1, the inverter is HI-skewed. If r < 1, the inverter is LO-skewed. If r = 1,
the inverter has normal skew or is unskewed.
A HI-skew inverter has a stronger pMOS transistor. Therefore, if the
input is VDD /2, we would expect the output will be greater than VDD /2. In
other words, the input threshold must be higher than for an unskewed
inverter. Similarly, a LO-skew inverter has a weaker pMOS transistor and
thus a lower switching threshold.
Figure explores the impact of skewing the beta ratio on the DC
transfer characteristics. As the beta ratio is changed, the switching
threshold moves. However, the output voltage transition remains sharp.
Gates are usually skewed by adjusting the widths of transistors while
maintaining minimum length for speed. Transfer characteristics of Skewed
inverters
 Noise Margin
Noise margin is closely related to the DC voltage characteristics. This parameter
allows you to determine the allowable noise voltage on the input of a gate so that
the output will not be corrupted. The specification most commonly used to
describe noise margin (or noise immunity) uses two parameters: the LOW noise
margin, NML, and the HIGH noise margin, NMH.

CMOS inverter noise margins

 Pass Transistor DC Characteristics
(a)an nMOS transistor with the gate and drain tied to VDD.
Imagine that source is initially at Vs = 0. Vgs > Vtn, so the transistor is ON
and current flows. If the voltage on the source rises to Vs = VDD – Vtn, Vgs
falls to V tn and the transistor cuts itself OFF. Therefore, nMOS
transistors attempting to pass a 1 never pull the source above VDD – Vtn.
This loss is sometimes called a threshold drop.
(b) pMOS transistors pass 1s well but 0s poorly. If the pMOS source
drops below |Vtp|, the transistor cuts off. Hence, pMOS transistors only
pull down to within a threshold above GND.
(c) the source can rise to within a threshold voltage of the gate, the
output of several transistors in series is no more degraded than that of
a single transistor.
(d) a degraded output drives the gate of another transistor, the second
transistor can produce an even further degraded output.