Computer Hardware Lecturer - 4

Introduction
RISC stands for Reduced Instruction Set Computer Processor, and CISC stands for
Complex Instruction Set Computer Processor, both are used to increase CPU
performance.
RISC reduces the cycles per instruction at the cost of the number of instructions per
program.
CISC tries to minimize the number of instructions per program but at the cost of
increasing the number of cycles per instruction.
A few decades earlier, when the programming was done using assembly language,
a need was felt to make instruction do more tasks because programming in
assembly was tedious and error-prone; because of this, CISC architecture evolved
but with the uprise of high-level language dependency on assembly reduced the
RISC architecture prevailed.
Let’s understand both RISC and CISC concepts in-depth.
Recommended Topic, Microinstruction in Computer Architecture
Reduced Instruction Set Computer (RISC)
RISC is a microprocessor architecture that uses a simple set of instructions that can
be substantially modified. It is designed to reduce the time it takes for instructions to
execute by optimizing and reducing the number of instructions. It means that each
instruction cycle has only one clock per cycle, and each cycle consists of three
parameters: fetch, decode, and execute. The RISC processor can also combine
multiple complex instructions into a simple one. RISC chips require several
transistors, making them less expensive to develop and reducing instruction
execution time.
RISC Architecture:
Features of RISC Processor

Some of the crucial features of the RISC processor are:-
1.) RISC processors use one clock per cycle (CPI) to execute each instruction in a
computer. Each CPI also comprises the methods for fetching, decoding, and
executing computer instructions.
2.) Multiple registers in RISC processors allow them to hold instructions, reply fast to
the computer, and interact with computer memory as little as possible.
3.) The RISC processors use the pipelining technique to execute multiple parts or
stages of instructions to perform more efficiently.
4.) RISC has a simple addressing mode and fixed instruction length for the pipeline
execution.
5.) It uses LOAD and STORE instruction to access the memory location.
Also See, Shift Registers in Digital Electronics
Complex Instruction Set Computer (CISC)
Intel developed the CISC processor. It has an extensive collection of complex
instructions that range from simple to very complex and specializes in the assembly
language level, which takes a long time to execute the instructions. So, CISC
approaches reducing the number of instructions on each program and ignoring the
number of cycles per instruction. It emphasizes building complex instructions directly
in the hardware because the hardware is always faster than software. However,
CISC chips are relatively slower than RISC chips but use little instructions.
Examples of CISC processors are AMD, Intel x86, and the System/360.
CISC Architecture:
Features of CISC Processor

Some of the crucial features of the RISC processor are:-
1.) CISC may take longer than a single clock cycle to execute the code.
2.) The length of the code is short, so it requires minimal RAM.
3.) It provides more accessible programming in assembly language.
4.) It focuses on creating instructions on hardware rather than software because they
are faster to develop.
5.) It comprises fewer registers and more addressing nodes, typically 5 to 20.
Difference Between RISC And CISC
The major difference between RISC and CISC is listed below:-
Pipelining in Computer Architecture
Pipelining organizes the execution of the multiple instructions simultaneously.

Pipelining improves the throughput of the system. In pipelining the instruction is
divided into the subtasks. Each subtask performs the dedicated task.
The instruction is divided into 5 subtasks: instruction fetch, instruction

decode, operand fetch, instruction execution and operand store. The instruction
fetch subtask will only perform the instruction fetching operation, instruction
decode subtask will only be decoding the fetched instruction and so on the other
subtasks will do.
In this section, we will discuss the types of pipelining, pipelining hazards, its
advantage. So let us start.
Content: Pipelining in Computer Architecture

1. Introduction
2. Types of Pipelining
3. Pipelining Hazards
4. Advantages
5. Key Takeaways
Introduction
The output of the first pipeline becomes the input for the next pipeline. It is like a
set of data processing unit connected in series to utilize processor up to its
maximum.
An instruction in a process is divided into 5 subtasks likely,
1. In the first subtask, the instruction is fetched.

2. The fetched instruction is decoded in the second stage.
3. In the third stage, the operands of the instruction are fetched.
4. In the fourth, arithmetic and logical operation are performed on the operands
to execute the instruction.
5. In the fifth stage, the result is stored in memory.
Now, understanding the division of the instruction into subtasks. Let us

understand, how the n number of instructions in a process, are pipelined.
Look at the figure below the 5 instructions are pipelined. The first instruction gets
completed in 5 clock cycle. After the completion of first instruction, in every new
clock cycle, a new instruction completes its execution.
Observe that when the Instruction fetch operation of the first instruction is
completed in the next clock cycle the instruction fetch of second instruction gets
started. This way the hardware never sits idle it is always busy in performing some
or other operation. But, no two instructions can execute their same stage at
the same clock cycle.
Types of Pipelining
In 1977 Handler and Ramamoorthy classified pipeline processors depending on
their functionality.
1. Arithmetic Pipelining
It is designed to perform high-speed floating-point addition, multiplication and

division. Here, the multiple arithmetic logic units are built in the system to perform
the parallel arithmetic computation in various data format. Examples of the
arithmetic pipelined processor are Star-100, TI-ASC, Cray-1, Cyber-205.
2. Instruction Pipelining
Here, the number of instruction are pipelined and the execution of current
instruction is overlapped by the execution of the subsequent instruction. It is also
called instruction lookahead.
3. Processor Pipelining
Here, the processors are pipelined to process the same data stream. The data
stream is processed by the first processor and the result is stored in the memory
block. The result in the memory block is accessed by the second processor. The
second processor reprocesses the result obtained by the first processor and the
passes the refined result to the third processor and so on.
4. Unifunction Vs. Multifunction Pipelining
The pipeline performing the precise function every time is unifunctional pipeline.
On the other hand, the pipeline performing multiple functions at a different time or
multiple functions at the same time is multifunction pipeline.
5. Static vs Dynamic Pipelining
The static pipeline performs a fixed-function each time. The static pipeline is
unifunctional. The static pipeline executes the same type of instructions
continuously. Frequent change in the type of instruction may vary the performance
of the pipelining.
Dynamic pipeline performs several functions simultaneously. It is a multifunction

pipelining.
6. Scalar vs Vector Pipelining
Scalar pipelining processes the instructions with scalar operands. The vector
pipeline processes the instruction with vector operands.
Pipelining Hazards
Whenever a pipeline has to stall due to some reason it is called pipeline hazards.
Below we have discussed four pipelining hazards.
1. Data Dependency
Consider the following two instructions and their pipeline execution:

In the figure above, you can see that result of the Add instruction is stored in the
register R2 and we know that the final result is stored at the end of the execution of
the instruction which will happen at the clock cycle t4.
But the Sub instruction need the value of the register R2 at the cycle t3. So the Sub
instruction has to stall two clock cycles. If it doesn’t stall it will generate an
incorrect result. Thus depending of one instruction on other instruction for data
is data dependency.
2. Memory Delay
When an instruction or data is required, it is first searched in the cache memory if

not found then it is a cache miss. The data is further searched in the memory which
may take ten or more cycles. So, for that number of cycle the pipeline has to stall
and this is a memory delay hazard. The cache miss, also results in the delay of all
the subsequent instructions.
3. Branch Delay
Suppose the four instructions are pipelined I1, I2, I3, I4 in a sequence. The instruction
I1 is a branch instruction and its target instruction is Ik. Now, processing starts and
instruction I1 is fetched, decoded and the target address is computed at the 4th stage
in cycle t3.
But till then the instructions I2, I3, I4 are fetched in cycle 1, 2 & 3 before the target
branch address is computed. As I1 is found to be a branch instruction, the
instructions I2, I3, I4 has to be discarded because the instruction Ik has to be
processed next to I1. So, this delay of three cycles 1, 2, 3 is a branch delay.
Prefetching the target branch address will reduce the branch delay. Like if the
target branch is identified at the decode stage then the branch delay will reduce to 1
clock cycle.
4. Resource Limitation
If the two instructions request for accessing the same resource in the same clock
cycle, then one of the instruction has to stall and let the other instruction to use the
resource. This stalling is due to resource limitation. However, it can be prevented
by adding more hardware.
Advantages
1. Pipelining improves the throughput of the system.
2. In every clock cycle, a new instruction finishes its execution.
3. Allow multiple instructions to be executed concurrently.

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Introduction

Features of RISC Processor

Features of CISC Processor

Pipelining organizes the execution of the multiple instructions simultaneously.

The instruction is divided into 5 subtasks: instruction fetch, instruction

Content: Pipelining in Computer Architecture

An instruction in a process is divided into 5 subtasks likely,

1. In the first subtask, the instruction is fetched.

Now, understanding the division of the instruction into subtasks. Let us

It is designed to perform high-speed floating-point addition, multiplication and

4. Unifunction Vs. Multifunction Pipelining

5. Static vs Dynamic Pipelining

Dynamic pipeline performs several functions simultaneously. It is a multifunction

6. Scalar vs Vector Pipelining

Consider the following two instructions and their pipeline execution:

When an instruction or data is required, it is first searched in the cache memory if

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