Fourth International Conference on Electronics, Communication and Aerospace Technology (ICECA-2020)

IEEE Xplore Part Number: CFP20J88-ART; ISBN: 978-1-7281-6387-1

A Unique Design of Hybrid Full Adder for the

Application of Low Power VLSI Circuits
M d. Nasiruddin Shah Biraj Shougaijam
Salam Surjit Singh Dolly Leishangthem Dept. of ECE, MTU, Takyelpat, Deparment of Electronics &
Dept. of ECE, MTU, Takyelpat, Dept. of ECE, MTU, Takyelpat, Imphal-795004 M anipur, India Communication Engineering
Imphal-795004 M anipur, India Imphal-795004 M anipur, India [email protected] (ECE), Manipur Technical
[email protected] [email protected] University (MTU), Takyelpat,
Imphal-795004 M anipur, India
[email protected],
[email protected]

Abstract— In this research work, a unique Hybrid Full Adder and dynamic CMOS logic are the most widely used logic styles
(HFA) is developed by deploying Pass Transistor Logic (PTL), for the building of 1-bit FA [6]. A mong the logic styles, the
CMOS logic and transmission gate (TG) logic on the Cadence conventional CMOS logic style is widely preferred due to its
Virtuoso platform in 90-nm technology. Various modules, excellent driving capabilities and good output swing. But, the
namely the XOR module, the carry generator module, sum drawback of emp loying CM OS circuits is its higher power
generator module are implemented for realizing 1-bit HFA. An consumption due to high current switching time and leakage of
inverter logic is employed next to the XOR logic to obtain the current due to short circuit. Further, the design can be
logic of XNOR which is required for designing the proposed
implemented by using multiple logic which are known as
HFA. The propagation delay (tpd) and average power of the
circuit are turned out to be 20 ns and ~6.889 μW respectively, at
hybrid logic, to enhance the overall performance of the FA.
1V supply voltage. S o, the power delay product (PDP) is
Hybrid logic styles consist of two or more different logic styles
remarkably low with the value 137.78 fJ of the proposed HFA. Viz. CM OS-CPL, PTL-TGA , CMOS-TG, hybrid CMOS, etc.,
The area is also satisfyingly less because the proposed design for designing the circuits [7, 8, 9].
used only 13 transistors. Hence, the proposed design gives a
remarkable improvement in terms of PDP which may be
applicable for basic building blocks of VLS I circuits.

Keywords— Average power, Hybrid Full Adder (HFA), low

power, power delay product and VLSI

I. INT RODUCT ION

With the increasing demand for battery-powered electronic
devices like the personal computer, smart phones, bio-
electronics and PDA devices, etc., Very Large-scale
Integration (VLSI) designers are focused towards minimu m
power delay characteristics of the circuits [1]. One of the major Fig. 1. Basic structure of Full Adder.
concern for designers to achieve minimu m power delay is to
design energy efficient VLSI circuit [2, 3]. In order to develop The benefits of CMOS logic based FA used twenty-eight
a low power VLSI circuit, the designer need to consider the numbers of transistors. Also, the circuit can withstand against
transistors count, power consumption, heat transfer and area of variation in the device dimension and voltage scaling,
the circuit. The main goal is to keep the battery life longer with however, large capacitance and buffer requirement are the
reduced cost and area of packaging which is suitable for main drawbacks of these circuits [10, 11]. The number of
portable device applications [4]. So, researchers are developing transistor count is high in this logic style which co mpro mises
efficient basic circuits for the application of low-power circuits the size. Further, the FA designed using CPL logic with 32
by implementing hybrid technology. As a result, the number of transistors have good voltage swing restoration. On
performance of microelectronic circu its is improved in a the other side, CPL logic design is not fully accessible for low
tremendous manner. A one bit Full Adder (FA) is considered power VLSI circuit applications due to more number of
as a basic logic module of building arithmetic logic circuits like transistor counts and high switching power. The obstacle
binary addition, subtraction and multip lier, etc. [5]. Hence, encountered in CPL i.e., the voltage degeneration was
highly efficient basic FA blocks in the arithmetic logic unit successfully dealt with by Transmission Gate Adder (TGA ). In
(ALU) circuit is needed for large scale arith metic operation of TGA, only 20 transistors are used for the imp lementation of a
high resolution image and video processing, and many other 1-bit FA, still, it has high power consumption and slow speed.
microprocessor applications. Usually, static complementary In order to overcome all these disadvantages, researchers
metal-o xide semiconductor (CMOS), Transmission gate FA mainly focused on hybrid technology by improving the overall

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 Fourth International Conference on Electronics, Communication and Aerospace Technology (ICECA-2020)
IEEE Xplore Part Number: CFP20J88-ART; ISBN: 978-1-7281-6387-1

performance of the circuit [10]. Recently, Majid A.V. et.al has reported the design of hybrid

(a) (b)

Fig. 2. (a) Shows the XOR block, (b) Carry (Cout) generation block.

Fig. 3. Shows the proposed HFA Circuit design.

1-bit FA using 18 nu mbers of transistors by employing a new B. Modified XOR module

XOR-XNOR logic [12]. The XOR module is a major problem in the whole adder
In this work, an energy-efficient HFA is proposed using a circuit due to high power consumption. Therefore, we need to
hybrid style. In this proposed style, a new HFA using Pass design an XOR module that consumes less power [13, 14]. To
Transistor Logic (PTL), CM OS and TGA are designed in 90 - solve this problem, an XOR module shown in figure 2 (a) is
nm technology on cadence virtuoso design environment. This proposed for imp lementing the HFA circuit. The length and
HFA circuit is designed using only 13 transistors (13T) and width of the transistors are adjusted to get the desired current at
simulated to verify the truth table at 1V. The proposed hybrid the output. In the XOR module, the resistance of the PMOS
1-bit HFA shows enhance performance in power consumption (PM0) is reduced by adjusting the dimension of the device.
and PDP as compared to the ordinary CMOS design. Similarly, the sizing of the last NMOS transistor in the XOR
module is done. Table I shows the logic table of XOR.
II. DESIGN A PPROACH OF PROPOSED HFA CIRCUIT
C. Carry and Sum generation module
A. Methodology The result of the carry signal is produced by using TG logic
The block representation of the FA circuit is shown in Fig. in the proposed HFA circuit. Here, the dimension of the PMOS
1 (a). It shows the FA imp lementation which gives out Sum and NMOS transistors used in TG is kept at 120 n m and 100
and Carry logics as output by giving A, B, and Cin as input nm as length and width, respectively. The carry propagation
signal. Module 2 and module 3 gives the final output of the FA delay is lower by implementing the carry signal (Cin ) using the
circuit which is implemented using XOR and XNOR logic. transistor gates (NM2, PM3) [15]. The PMOS transistors
(PM5, PM 6) and NM OS transistors (NM4, NM 5) realized the
complete SUM output function after passing through the

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 Fourth International Conference on Electronics, Communication and Aerospace Technology (ICECA-2020)
IEEE Xplore Part Number: CFP20J88-ART; ISBN: 978-1-7281-6387-1

XNOR logic gates. The truth table showing the input and
output signal of the HFA circuit is verified as illustrated in
Table II. Therefore, the design HFA is unique in number of
transistor used as compared to conventional FA design. Again,
a unique PTL with 3T as XOR logic has been imp lemented in
designing low power HFA for the first time.

TABLE I. SHOWS THR TRUTH TABLE OF XOR LOGIC.

A B A XOR B

0 0 0

0 1 1
Fig. 4. Shows the proposed HFA block diagram.
1 0 1

1 1 0 TABLE III. T RANSISTOR SIZES USED IN THE P ROP OSED HFA AT 90 NM

TECHNOLOGY

Transistor Used Width (W) Length(L)

TABLE II. T RUTH T ABLE OF P ROP OSED 1- BIT HFA

XOR_PM0 120 nm 100 nm

A B C in Sum C out
XOR_PM1 10 μm 100 nm
0 0 0 0 0
XOR_NM0 120 nm 100 nm
0 0 1 1 0

0 1 0 1 0 Adder_PM0 240 nm 100 nm

0 1 1 0 1
Adder_PM1, PM2, 120 nm 100 nm
1 0 0 1 0 PM3, PM4

1 0 1 0 1
Adder_NM0, NM1, 120 nm 100 nm
NM2, NM3, NM4
1 1 0 0 1
TABLE IV. SIMULATION RESULTS FOR HFA CIRCUIT AT 90 NM
1 1 1 1 1 T ECHNOLOGY UNDER 1V

Power Delay PDP (fJ) No. of

Design transistors
III. SIMULAT ION RESULT S (μW) (ns)

The proposed HFA circuit is illustrated in Fig. 3. The Full adder [16]
output of the XOR logic is given to the weak inverter realized 28.591 11.512 329.13 16
by PM2 and NM1. Consequently, the result of the weak
Full adder [17]
inverter gives the XNOR logics. Further, the W/L ratio of the 25.507 6.482 165.33 27
inverter logic is kept at 120 n m and 100 n m to increase the
performance of HFA. The output of XNOR is applied in Full adder
[proposed] 6.889 20 137.78 13
between PM3 and NM 3 transistors of the Cout block in order to
complete the Cout module. Finally, the result of XNOR logic is
connected to NM4 and NM 5 transistors so as to complete the
SUM part. In this hybrid design, W/L ratio is arranged in such a way
that the overall power consumption is reduced. Further, the
The proposed 1-bit HFA designed was simulated using speed of the hybrid circuit can be increase by changing the
90-nm technology. The block diagram showing the input and
dimension of the transistors present in the TG between the Cin
output representation of designed HFA is shown in Fig. 4 and
to Cout paths. Correspondingly, the desire propagation delay is
5, respectively. The aim of this proposed HFA design is to
achieved by changing the dimension of the transistors used in
reduce the power consumption of the FA circuit as well as to
the TG.
the increase the speed of the circuit. As a result, the PDP of the
proposed designed is reduced.

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 Fourth International Conference on Electronics, Communication and Aerospace Technology (ICECA-2020)
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Fig. 5. Schematic design of 13T 1-bit HFA.

Fig. 6. Output waveform for 1-bit HFA.

The waveform results of the designed HFA is illustrated in Thus, the waveforms of the designed HFA verifies the logic
Fig. 6. Further, the waveform shows that the logic of the sum table of a FA.
and carry of the circuit is verified. The proposed sizing of the
transistors of HFA design in 90-n m technology is shown in The proposed HFA is co mpared with other HFA designs
reported in Ref. [16, 17] in the 90-nm process technology. The
table III. And, the simulation results for 1-bit HFA at 90-n m
proposed HFA used only 13 nu mber of transistors, however,
technology under 1V power supply are shown in Table IV. The
parameter such as delay value, power and PDP parameter of the existing HFA used 16 numbers of transistors [16]. The
average power of the circu it is remarkably lower than the other
the designed HFA are compared with the existing full adder.
reported hybrid FAs. The speed of the HFA is also bringing

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