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    8051 2018 Lec3

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    Aziz Ashraf

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    © All Rights Reserved
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    8051 2018 Lec3

    Uploaded by

    Aziz Ashraf
    5 views28 pages

    Original Title

    8051_2018_lec3

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    © © All Rights Reserved

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    5 views28 pages

    8051 2018 Lec3

    Uploaded by

    Aziz Ashraf

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 28

    LECTURE 3

    A.Prof.Dr/ Assem Badr


    1
    Microprocessor A.Prof.Dr/ Assem Badr
    DB
    Directive used by assembler to store the
    Internal Rate of the
    permanent data into the program Internal clock
    clock divider
    memory (during the burning process) pulses
    by12

    ORG 100h
    DB 50h, 90h ; Bytes

    0100h 50h
    0101h 90h

    Program M
    3/7/2024 2
    DB
    Internal Rate of the
    ORG 50h Internal clock
    clock divider
    DB “Microprocessor” ; String
    by12 pulses

    0050h M
    0051h i
    c
    r
    o
    p
    r
    o
    c
    e
    s
    s
    o
    005Dh r

    Program M
    3/7/2024 3
    The instruction types of MCS-51
    The ISA of MCS-51 family includes 5 types of
    instructions as following:
    a) Data transfer Instructions.
    b) Logical operation instructions.
    c) Bit-Oriented Instructions.
    d) Arithmetic operation Instructions.
    e) Branching Instructions.

    3/7/2024 4
    The Mnemonic of instructions
    ❑ Each instruction is known by the shortened of its
    operation and called “Mnemonic” alike:
    Instruction’s operation Mnemonic
    Move data MOV
    Increment data INC
    Adding 2 data ADD
    Division 2 data DIV
    No operation NOP
    Jump if carry is set JC
    Complement CPL
    3/7/2024 5
    Some terminologies of the assembly of MCS-51
    Instruction’s
    terminology
    Description Example
    A The Accumulator CPL A
    C The Carry flag CLR C
    Bit The addressable bit SETB P1.5
    Rn The Register R0 to R7 of the selected DEC R5
    bank
    Rx Address of any internal RAM location MOV PSW, 20H
    (from 00h to FFh) or (from 0 to 255)
    or the SFR’s names
    @Ri Indirect 8-bit address of internal or INC @R0
    external RAM location (i = 1 or 0 only)
    DEC @R1

    3/7/2024 6
    The terminologies of ISA for MCS-51
    Instruction’s
    terminology
    Description Example
    Rel The relative address in the Again:
    program memory within range -128

    (from –128 to +127) bytes SJMP again


    +127
    Again:
    #data The 8-bit immediate data MOV A, #50h
    (from 00h to FFh)
    #data 16 The immediate 16-bit data MOV DPTR, #1020h
    (from 0000h to FFFFh)
    Addr 16 The 16-bit branching address LJMP Label3
    within 64KB Label3:
    Addr 11 The 11-bit branching address Start:
    3/7/2024 within 2kB AJMP Start 7
    “MOV”

    3/7/2024 8
    Available MOV-instructions
    MOV R1, 8h

    MOV P3, A

    3/7/2024 10
    MOV 80h, #50h

    3/7/2024 11
    MOV A, @R1

    3/7/2024 12
    EXAMPLE

    Draw Memory block-diagram and write


    assembly sub-program to read 2 samples
    (digital data) from a digital sensor via port-2
    and store them into 2 successive internal RAM
    locations starting from address 77h using
    indirect addressing @Ri of MCS-51.

    3/7/2024 13
    The subprogram to indicate the indirect
    address

    3/7/2024 14
    @R0
    @R0

    First sample Second sample

    3/7/2024 15
    The 16-bit Data transfer
    Example MOV DPTR, #0EE44h

    3/7/2024 16
    The Stack
    The stack is part of the RAM

    In 8051, all RAM locations can be as stack

    The Stack Pointer (SP)


    One of the SFR points toward the top of the
    stack area

    It has initial value "07h“

    Microprocessor 2017-18 17
    The Stack is effected by
    1- Push & Pop instructions

    2- Call & Ret instructions

    3- The interrupts (automatic call)

    4- Reti instructions (ret from interrupt)

    Microprocessor 2017-18 18
    The data transfers from/to Stack

    Last input is first output

    Microprocessor 2017-18 19
    Pushing data-byte into the stack
    PUSH 60h Source address

    Bank 0

    Before PUSH After PUSH


    Microprocessor 2017-18 20
    Pushing other data-byte into the stack
    PUSH 80h Source address

    After PUSH 80h


    Microprocessor 2017-18 21
    After Pop data-byte from the stack
    POP 00H Destination address

    Before POP After POP 00H


    Microprocessor 2017-18 22
    CALL Effecting on PC

    Assembly code Stack

    Org 0
    Calling current address

    1
    CALL delay Return address

    Delay:
    -----
    -----
    2 -----
    -----
    RET
    Data memory

    Microprocessor 2021-22 23
    The calling
    address
    Return
    address

    Example of the
    execution of the
    instruction “call”
    (3 slides)

    Microprocessor 2017-18 24
    2
    Calling
    1
    Pushing
    return
    address
    Program
    memory

    RAM

    Microprocessor 2017-18 25
    Pop
    return
    address

    Microprocessor 2017-18 26
    Complete the following block diagram (specially the SP & PC)
    during the executions of both instructions CALL and RET
    sequentially.

    27
    28

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