Lab2 and Lab3

lOMoAR cPSD| 31103568
LAB-2
1. Write RTL description and testbench for an Arithmetic Logic Unit using arithmetic and logical operators.
DESIGN CODE:
module alu(input [7:0]a,b,

input [3:0]command_in,
input oe,
output [15:0]d_out);
parameter ADD = 4'b0000, // Add two 8 bit numbers a and b.

INC = 4'b0001, // Increment a by 1.
SUB = 4'b0010, // Subtracts b from a.
DEC = 4'b0011, // Decrement a by 1.
MUL = 4'b0100, // Multiply 4 bit numbers a and b.
DIV = 4'b0101, // Divide a by b.
SHL = 4'b0110, // Shift a to left side by 1 bit.
SHR = 4'b0111, // Shift a to right by 1 bit.
AND = 4'b1000, // Logical AND operation
OR = 4'b1001, // Logical OR operation
INV = 4'b1010, // Logical Negation
NAND = 4'b1011, // Bitwise NAND
NOR = 4'b1100, // Bitwise NOR
XOR = 4'b1101, // Bitwise XOR
XNOR = 4'b1110, // Bitwise XNOR
BUF = 4'b1111; // BUF
//Internal variable used during ALU operation

reg [15:0]out;
/*Step1 : Write down the functionality of ALU based on the commands given above.
*Use arithmetic and logical operators* */
always@(*)
begin
case(command_in)
//--------- write the functionality here -------
ADD : out = a + b;
INC : out = a + 1'b1;
SUB : out = a - b;
DEC : out = a - 1'b1;
MUL : out = a * b;
DIV : out = a/b;
SHL : out = a<<1;
SHR : out = a>>1;
AND : out = a&b;
OR : out = a|b;
INV : out = ~a;
NAND : out = ~(a&b);
NOR : out = ~(a|b);
XOR : out = a^b;
XNOR : out = a~^b;
BUF : out = a;
endcase
end
//Understand the tri-state logic for actual output

assign d_out = (oe) ? out : 16'hzzzz;
endmodule
STIMULATION CODE:
module alu_tb();
//Testbench global variables

reg [7:0]a,b;
reg [3:0]command;
reg enable;
wire [15:0]out;
//Variables for iteration of the loops

integer m,n,o;
//Parameter constants used for displaying the strings during operation

parameter ADD = 4'b0000, // Add two 8 bit numbers a and b.
INC = 4'b0001, // Increment a by 1.
SUB = 4'b0010, // Subtracts b from a.
DEC = 4'b0011, // Decrement a by 1.
MUL = 4'b0100, // Multiply 4 bit numbers a and b.
DIV = 4'b0101, // Divide a by b.
SHL = 4'b0110, // Shift a to left side by 1 bit.
SHR = 4'b0111, // Shift a to right by 1 bit.
AND = 4'b1000, // Logical AND operation
OR = 4'b1001, // Logical OR operation
INV = 4'b1010, // Logical Negation
NAND = 4'b1011, // Bitwise NAND
NOR = 4'b1100, // Bitwise NOR
XOR = 4'b1101, // Bitwise XOR
XNOR = 4'b1110, // Bitwise XNOR
BUF = 4'b1111; // BUF
//Internal register for storing the string values

reg [4*8:0]string_cmd;
//Step1 : Instantiate the design ALU

alu DUT(a,b,command,enable,out);
task initialise;
{a,b,command,enable}=0;
endtask
//Tasks used for generztask en_oe(input i)

task en_oe(input i);
begin
enable=i;
end
endtask
task inputs(input [7:0]j,k);

begin
a=j;
b=k;
end
endtask
task cmd (input [3:0]l);

begin
command=l;
end
endtask
task delay();
begin
#10;
end
endtask
//Process to hold the string values as per the commands.

always@(command)
begin
case(command)
ADD : string_cmd = "ADD";
INC : string_cmd = "INC";
SUB : string_cmd = "SUB";
DEC : string_cmd = "DEC";
MUL : string_cmd = "MUL";
DIV : string_cmd = "DIV";
SHL : string_cmd = "SHL";
SHR : string_cmd = "SHR";
INV : string_cmd = "INV";
AND : string_cmd = "AND";
OR : string_cmd = "OR";
NAND : string_cmd = "NAND";
NOR : string_cmd = "NOR";
XOR : string_cmd = "XOR";
XNOR : string_cmd = "XNOR";
BUF : string_cmd = "BUF";
endcase
end
//Process used for generating stimulus by calling tasks & passing values
initial
begin
/*initialize;
en_oe(1'b1);
for(m=0;m<16;m=m+1)
begin
for(n=0;n<16;n=n+1)
begin
inputs(m,n);
for(o=0;o<16;o=o+1)
begin
command=o;
delay;
end
end
end */
en_oe(0);
inputs(8'd20,8'd10);
cmd(ADD);
delay;
en_oe(1);
inputs(8'd25,8'd17);
cmd(ADD);
delay;
$finish;
end
//Process to monitor the changes in the variables

initial
$monitor("Input oe=%b, a=%b, b=%b, command=%s, Output out=%b",enable,a,b,string_cmd,out);
endmodule
STIMULATION WAVEFORM:
TRANSCRIPT:
SYNTHESIS CIRCUIT:
2. Write Verilog Code for verifying Operators.
DESIGN CODE:
module logical_op();
reg [2:0] a,b,c,d;
reg [3:0] g,h;
reg x,y,z,q,r,i,l,m,n,o,k;
reg [2:0]w,p;
initial
begin
a = 3'b010;
b = 3'b111;
c = 3'b00x;
d = 3'b11x;
g = 4'b10x0;
x = a && b;
y=!c;
z=!d;
w = a & c;
p = b & d;
q = & c;
r = & d;
h = g >> 1;
i= a > d;
l=a+b;
m=a-b;
n=a*b;
o=a/b;
k=a?b: c;
$display("x=%b, y=%b, z=%b, w=%b, p=%b, q=%b, r=%b, g=%b, h=%b, i=%d", x,y,z,w,p,q,r,g,h,i,l,m,n,o,k);
end
endmodule
OUTPUT:
LAB-3(Combinational Logic Design)

1. Write behavioral descrpition and test bench for 4:1 MUX.
DESIGN CODE:
module mux4x1_behavioural(input [3:0]i, input[1:0]s, output reg y);
always@( * )
begin
case(s)
2'b00:y=i[0];
2'b01:y=i[1];
2'b10:y=i[2];
2'b11:y=i[3]; //if not given for particular case //latchn will be inferred--not preferred for //combinational
ckts---so we have default construct default : y=1'bz;
endcase
end
endmodule
STIMULATION CODE:
module mux4x1_behavioural_tb();
reg [3:0]i;
reg [1:0]s;
wire y;
integer k;
mux4x1_behavioural DUT(i, s, y);

initial
begin
for(k=0;k<64;k=k+1)
begin
{i,s} = k;
#10;
end
end
endmodule
TRANSCRIPT:
SYNTHESIS CIRCUIT:
2. Write an behavioral description for a 3:8 decoder and verify using test bench.
DESIGN CODE:
module decoder3x8_behavioural( input [2:0] a, output reg[7:0] y);
always @(*)
begin
case(a)
3'b000 : y = 8'b00000001;
3'b001 : y = 8'b00000010;
3'b010 : y = 8'b00000100;
3'b011 : y = 8'b00001000;
3'b100 : y = 8'b00010000;
3'b101 : y = 8'b00100000;
3'b110 : y = 8'b01000000;
3'b111 : y = 8'b10000000;
default : y = 8'b00000000;
endcase
end
endmodule
STIMULATION CODE:
module tb_decoder3x8_behavioural;
reg [2:0]i;
wire[7:0]y; //wire idle;
decoder3x8_behavioural DUT( i, y );
initial
begin stimulus;
end
task stimulus;
integer k;
for( k=0; k<8; k=k+1 )
begin i = k;
#10;
end
endtask
initial
$monitor( $time,"i=%b,y=%b", i,y);
endmodule
TRANSCRIPT:
SYNTHESIS CIRCUIT:
3. Write an behavioral description and testbench 8:3 priority encoder.
DESIGN CODE:
module priority_encoder8x3_behavioural(input [7:0]i, output reg[2:0] y, output reg idle);
always@(*)
begin
if(i[7])
begin y=3'b111;
idle=0;
end
else if(i[6])
begin y=3'b110;
idle=0;
end
else if(i[5])
begin y=3'b101;
idle=0;
end
else if(i[4])
begin y=3'b100;
idle=0;
end
else if(i[3])
begin y=3'b011;
idle=0;
end
else if(i[2])
begin y=3'b010;
idle=0;
end
else if(i[1])
begin y=3'b001;
idle=0;
end
else if(i[0])
begin y=3'b000;
idle=0;
end
else
begin y=3'b000;
idle=1;
end
end
endmodule
STIMULATION CODE:
module tb_priority_encoder8x3_behavioural;
reg [7:0]i;
wire [2:0]y;
wire idle;
priority_encoder8x3_behavioural DUT( i, y, idle );
initial
begin stimulus;
end
task stimulus;
integer k;
for( k=0; k<256; k=k+1 )

begin i = k;
#10;
end
endtask
initial
$monitor( $time,"i=%b,y=%b,idle=%b", i,y,idle);
endmodule
TRANSCRIPT:
SYNTHESIS CIRCUIT:

Lab2 and Lab3

Uploaded by

Copyright:

Available Formats

Lab2 and Lab3

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Lab2 and Lab3

Uploaded by

Copyright:

Available Formats

lOMoAR cPSD| 31103568

module alu(input [7:0]a,b,

parameter ADD = 4'b0000, // Add two 8 bit numbers a and b.

//Internal variable used during ALU operation

//Understand the tri-state logic for actual output

//Testbench global variables

//Variables for iteration of the loops

//Parameter constants used for displaying the strings during operation

//Internal register for storing the string values

//Step1 : Instantiate the design ALU

//Tasks used for generztask en_oe(input i)

task inputs(input [7:0]j,k);

task cmd (input [3:0]l);

//Process to hold the string values as per the commands.

//Process to monitor the changes in the variables

reg [2:0] a,b,c,d;

reg [3:0] g,h;

LAB-3(Combinational Logic Design)

module mux4x1_behavioural(input [3:0]i, input[1:0]s, output reg y);

mux4x1_behavioural DUT(i, s, y);

module decoder3x8_behavioural( input [2:0] a, output reg[7:0] y);

wire[7:0]y; //wire idle;

for( k=0; k<8; k=k+1 )

$monitor( $time,"i=%b,y=%b", i,y);

3. Write an behavioral description and testbench 8:3 priority encoder.

module priority_encoder8x3_behavioural(input [7:0]i, output reg[2:0] y, output reg idle);

priority_encoder8x3_behavioural DUT( i, y, idle );

for( k=0; k<256; k=k+1 )

$monitor( $time,"i=%b,y=%b,idle=%b", i,y,idle);

You might also like