Features

• ARM7TDMI™ ARM® Thumb® Processor Core

– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-Circuit Emulation)
• 4K Bytes RAM
• 1M 16-bit Words Flash Memory
– Single Voltage Read/Write
– 100 ns Access Time
– Sector Erase Architecture
– Fast Word Program Time: 20 µs AT91
ARM® Thumb®
– Fast Sector Erase Time: 200 ms
– Dual Plane Organization allows Concurrent Read and Program/Erase
– Erase Suspend Capability
– Low-power Operation: 25 mA Active — 10 µA Standby
– Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection
Microcontrollers
– RESET Input for Device Initialization
– Sector Program Unlock Command
• Fully Programmable External Bus Interface (EBI)
– Maximum External Address Space of 64M Bytes
AT91F40416
– Up to 8 Chip Selects
– Software Programmable 8/16-bit External Data Bus
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 4 External Interrupts, including a High-priority Low-latency Interrupt Request
• 32 Programmable I/O Lines
• 3-channel 16-bit Timer/Counter
– 3 External Clock Inputs
– 2 Multi-purpose I/O Pins per Channel
• 2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
• Programmable Watchdog Timer
• Low-power Idle Mode
• Fully Static Operation: 0 Hz to 25 MHz
• 2.7V to 3.6V Operating Range
• -40°C to 85°C Operating Temperature Range
• Available in a 120-ball BGA Package

Description
The AT91F40416 is a member of the Atmel AT91 16/32-bit Microcontroller family
which is based on the ARM7TDMI processor core.
The processor has a high-performance 32-bit RISC architecture with a high-density
16-bit instruction set and very low power consumption. In addition, a large number of
internally banked registers result in very fast exception handling, making the device
ideal for real-time control applications. The eight-level priority-vectored interrupt con-
troller, together with the Peripheral Data Controller, significantly enhance real-time
device performance.
By combining the microcontroller, featuring on-chip RAM and a wide range of periph-
eral functions, with 16M bits of Flash memory in a single compact 120-ball BGA pack-
age, the Atmel AT91F40416 provides a powerful, flexible and cost-effective solution to
many compute-intensive embedded control applications and offers significant board
size and system cost reductions.
The Flash memory may be programmed while powered by the single device supply,
making the AT91F40416 ideal for in-system programmable applications.
Rev. 1317A–10/99

1
Pin Configuration
Figure 1. AT91F40416 Pinout (120-ball BGA, Top View)

K J H G F E D C B A

1
P26 P25 P22 P21/TXD1
GND NCS0 TCK TDO MCKI GND
NCS2 MCKO RXD1 NTRI
2
P27 NCS1 NWAIT TDI VDD GND VDD P18 P20 VDD
NCS3 SCK1
3
A0 P24 NWR1 P13 P15
TMS NWODVF P17 P16 P19
NLB BMS NUB SCK0 RXD0
4
VDD P23 NRST P12 P11 P14
FIQ IRQ2 TXD0
5
P10 P9 P8
GND GND VDD
IRQ1 IRQ0 TIOB2
6
VDD GND P30/A22 P6 P5 P7
CS5 TCLK2 TIOB1 TIOA2
7
GND P29/A21 P31/A23 P0 P4 P3
CS6 CS4 TCLK0 TIOA1 TCLK1
AT91F40416

8
A1 GND VDD VDD GND P2
TIOB0
9
NCSF NRD VDD GND VDD A2
NOE
10
P1
GND D0 D8 A3 A4
TIOA0
11
D2 D9 D1 A5 A6 A7

12
D11 D3 D10 A8 A18 VPP

13
P28/A20
D5 D12 D4 A19 NBUSY
CS7
14
D14 VDD NC D6 GND VDD NRSTF NWR0 A9 A10
NWE
15
GND D15 D7 NC D13 GND A11 A12 A13 VDD

16
VDD A17 GND VDD NC NC A14 A16 A15 GND

2 AT91F40416
 AT91F40416
Table 1. AT91F40416 Pin Description
Active
Module Name Function Type Level Comments
Valid after reset; do not reprogram A20 to
A0-A23 Address Bus Output — I/O, as it is MSB of Flash address
D0-D15 Data Bus I/O —
NCS0-NCS3 External Chip Select Output Low Used to select external devices
CS4-CS7 External Chip Select Output High A23-A20 after reset
NWR0 Lower Byte 0 Write Signal Output Low Used in Byte Write option
NWR1 Upper Byte 1 Write Signal Output Low Used in Byte Write option
EBI NRD Read Signal Output Low Used in Byte Write option
NWE Write Enable Output Low Used in Byte Select option
NOE Output Enable Output Low Used in Byte Select option
NUB Upper Byte Select Output Low Used in Byte Select option
NLB Lower Byte Select Output Low Used in Byte Select option
NWAIT Wait Input Input Low
Sampled during reset; must be low for
BMS Boot Mode Select Input — Flash to be used as boot memory
FIQ Fast Interrupt Request Input — PIO controlled after reset
AIC
IRQ0-IRQ2 External Interrupt Request Input — PIO controlled after reset
TCLK0-TCLK2 Timer External Clock Input — PIO controlled after reset
Timer TIOA0-TIOA2 Multipurpose Timer I/O Pin A I/O — PIO controlled after reset
TIOB0-TIOB2 Multipurpose Timer I/O Pin B I/O — PIO controlled after reset
SCK0-SCK1 External Serial Clock I/O — PIO controlled after reset
USART TXD0-TXD1 Transmit Data Output Output — PIO controlled after reset
RXD0-RXD1 Receive Data Input Input — PIO controlled after reset
PIO P0-P31 Parallel IO line I/O —
WD NWDOVF Watchdog Overflow Output Low Open drain
MCKI Master Clock Input Input — Schmidt trigger
Clock
MCKO Master Clock Output Output —
NRST Hardware Reset Input Input Low Schmidt trigger, internal pull-up
Reset
NTRI Tristate Mode Select Input Low Sampled during reset
TMS Test Mode Select Input — Schmidt trigger, internal pull-up
TDI Test Data Input Input — Schmidt trigger, internal pull-up
ICE
TDO Test Data Output Output —
TCK Test Clock Input — Schmidt trigger, internal pull-up
NCSF Flash Memory Select Input Low Enables Flash Memory when pulled low
Flash
NBUSY Flash Memory Busy Output Output Low Flash RDY/BUSY signal; open-drain
Memory
NRSTF Flash Memory Reset Input Input Low Resets Flash to standard operating mode
VDD Power Power — All VDD and all GND pins MUST be
connected to their respective supplies by
Power GND Ground Ground — the shortest route
VPP Faster Program/Erase Voltage Power — Contact Atmel

3
 Figure 1. AT91F40416

Block Diagram
4
AT91F40416

D0-D15
D0-D15
TMS
TDO Embedded A1-A20
TDI ICE
ARM7TDMI Core A1-A20
A0/NLB

EBI: External Bus Interface

TCK
VDD
GND ASB NWR1/NUB
RAM NWAIT
NRST Reset NCS0
4K bytes NCS1
NRD/NOE
NWR0/NWE
MCKI P26/NCS2
ASB
Clock P27/NCS3
P25/MCKO Controller P29/A21/CS6
P30/A22/CS5
AMBA Bridge P31/A23/CS4
P12/FIQ
P9/IRQ0 AIC: Advanced EBI User
P10/IRQ1 Interrupt Controller Interface
P11/IRQ2 OE WE
APB GND GND
VPP VPP
P13/SCK0 2 PDC VCC VDD
P14/TXD0 USART0
P15/RXD0
Channels MCU FLASH MEMORY VCCQ
BYTE
VDD
VDD
P20/SCK1 P
AT91M40400 P
AT49BV16X4 RESET NRSTF
P21/TXD1/NTRI 2 PDC I RDY/BUSY NBUSY
I USART1
P22/RXD1 Channels CE NCSF
O O
P16
P17
P18 TC: Timer P0/TCLK0
PS: Power Saving P3/TCLK1
P19 Counter
P23 P6/TCLK2
P1/TIOA0
P24/BMS TC0
Chip ID P2/TIOB0
P4/TIOA1
TC1
P5/TIOB1
P7/TIOA2
NWDOVF WD: Watchdog Timer TC2 P8/TIOB2

PIO: Parallel I/O Controller

Eamon Todd 08/99

 AT91F40416

Architectural Overview
The AT91F40416 integrates Atmel’s AT91M40400 ARM All the external signals associated with the on-chip periph-
Thumb MCU and its AT49BV16X4 16-Mbit Flash memory erals are under the control of the Parallel I/O controller. The
die in a single compact 120-ball BGA device. The address, PIO controller may be programmed to insert an input glitch
data and control signals, except the Flash memory enable, filter on any pin; generation of an interrupt on a input signal
are internally interconnected. level change may also be programmed for any PIO con-
The AT91F40416 is built around two main buses, the trolled pin. After reset, the user must carefully program the
Advanced System Bus (ASB) and the Advanced Peripheral PIO User Interface Registers in order to define which
Bus (APB). The ASB is designed for maximum perfor- peripheral signals are connected with I/O pins.
mance. It interfaces the processor with the on-chip 32-bit The ARM7TDMI processor operates in little-endian mode
memories, as well as with external memories and devices in the microcontroller. The Processor’s internal architecture
via the External Bus Interface (EBI). The APB is designed and the ARM and Thumb instruction sets are described in
for accesses to on-chip peripherals and is optimized for low the “ARM7TDMI (Thumb) Datasheet”, Literature No. 0673.
power consumption. The AMBA Bridge provides an Atmel- For further detailed information the user may also consult
enhanced interface between the ASB and the APB. the following Atmel documents:
The Flash memory is organized as 1M 16-bit words, • “AT91M40400 Datasheet”
accessed via the EBI. Its main intended function is as a Literature No. 0768
program memory. A 16-bit Thumb instruction can be • “AT91M40400 Electrical and Mechanical Characteristics”
loaded from Flash memory in a single clock cycle. Sepa- Literature No. 1078
rate MCU and Flash memory Reset inputs (NRST and
• AT49BV16x4 “16-megabit 3-volt Only Flash Memory”
NRSTF) are provided for maximum flexibility: the user is
Literature No. 0925
thus free to tailor reset operation to his application.
The ARM Standard In-Circuit-Emulation debug interface is
An on-chip Peripheral Data Controller (PDC) transfers data supported via the ICE port of the microcontroller. (This is
between the on-chip USARTs and the on and off-chip not a standard IEEE 1149.1 JTAG Boundary Scan inter-
memories without processor intervention. Most importantly, face).
the PDC removes the processor interrupt handling over-
head and significantly reduces the number of clock cycles PDC: Peripheral Data Controller
required for a data transfer. It can transfer up to 64k contig- The AT91F40416 has a 4-channel PDC dedicated to the
uous bytes without reprogramming the starting address. As two on-chip USARTs. One PDC channel is connected to
a result, the performance of the microcontroller is the receiving channel and one to the transmitting channel
enhanced and its power consumption reduced. of each USART.
The AT91F40416 peripherals are designed to be pro- A PDC channel user interface is integrated within the mem-
grammed with a minimum number of instructions. Each ory space of each USART channel: it contains a 32-bit
peripheral has a 16K-byte address space allocated in the address pointer register and a 16-bit byte count register.
upper 3M bytes of the 4G byte address space. Except for When the programmed number of bytes have been trans-
the interrupt controller, the peripheral base address is the ferred, an end-of-transfer interrupt is generated by the cor-
lowest address of its memory space. The peripheral regis- responding USART.
ter set is composed of control, mode, data, status and inter-
rupt registers.
To maximize the efficiency of bit manipulation, frequently
written registers are mapped into three memory locations.
The first address is used to set individual register bits, the
second resets the bits and the third address reads the
value stored in the register. A bit can be set or reset by writ-
ing a one to the corresponding bit position at the appropri-
ate register address. Writing a zero has no effect. Individual
bits can thus be modified without having to use lengthy
read-modify-write or complex bit manipulation instructions.

5
Flash Memory enabled, the data in that sector cannot be changed while
input levels lie between ground and VDD.
The 16-Mbit Flash memory is organized as 1,048,576 16-
bit words whose contents appear on D0-D15. The Flash An optional VPP pin is available to enhance program/erase
memory is addressed as 16-bit words via the EBI. It uses times. Please contact Atmel for more information regarding
address lines A1 to A20. Address line A20 must on no the use of this feature.
account be reprogrammed as an I/O pin or as a chip select, A 6-byte command sequence (Bypass Unlock) allows the
as it is the most significant bit of the Flash memory device to be written to directly, using single pulses on the
address. write control lines. This mode (Single Pulse Programming)
The address, data and control signals, except the Flash is exited by powering down the device or by pulsing the
memory enable, are internally interconnected. The user NRSTF pin low for a minimum of 50 ns and then bringing it
should connect the Flash memory enable (NCSF) to one of back to VDD.
the active-low chip selects on the EBI; NCS0 must be used The following hardware features protect against inadvert-
if the Flash memory is to be the boot memory device. In ent programming of the Flash memory:
addition, if the Flash memory is to be used as boot mem- • VDD Sense: if VDD is below 1.8V (typical), the program
ory, the BMS input must be pulled down externally in order function is inhibited.
for the processor to perform correct 16-bit fetches on reset. • VDD Power-on Delay: once VDD has reached the VDD
The user must ensure that all VDD and all GND pins are sense level, the device will automatically time out 10 ms
connected to their respective supplies by the shortest (typically) before programming.
route.
• Program Inhibit: holding any one of OE low, CE high or
The Flash memory powers-on in the read mode. Command WE high inhibits program cycles.
sequences are used to place the device in other operating • Noise Filter: pulses of less than 15 ns (typical) on the
modes, such as program and erase. WE or CE inputs will not initiate a program cycle.
A separate Flash memory reset input pin (NRSTF) is pro- Electrical Characteristics, Device Operation and Command
vided for maximum flexibility: the user is thus free to tailor Sequences are fully documented in the AT49BV16X4
reset operation to his application. When this input is at a Flash Memory Datasheet entitled “16-megabit 3-volt Only
logic high level, the memory is in its standard operating Flash Memory”, Literature No. 0925.
mode; a low level on this input halts the current memory
operation and puts its outputs in a high impedance state.
The Flash memory features data polling to detect the end
EBI: External Bus Interface
of a program cycle: while a program cycle is in progress, an The EBI generates the signals which control the access to
attempted read of the last word written will return the com- the external memory or peripheral devices. The EBI is fully
plement of the written data on I/O7. An open drain READY/ programmable and can address up to 64M bytes. It has
BUSY output pin provides another method of detecting the eight chip selects and a 24-bit address bus, the upper four
end of a program or erase cycle. This pin is pulled low bits of which are multiplexed with a chip select.
while program and erase cycles are in progress and is The 16-bit data bus can be configured to interface with 8-
released at the completion of the cycle. A toggle bit feature or 16-bit external devices. Separate read and write control
provides a third means of detecting the end of a program or signals allow for direct memory and peripheral interfacing.
erase cycle. The EBI supports different access protocols allowing single
The Flash memory is segmented into two memory planes. clock cycle memory accesses.
Reads from one memory plane may be performed even The main features are:
while program or erase functions are being executed in the
• External memory mapping
other memory plane. This feature enhances performance
• Up to eight chip select lines
by not requiring the system to wait for a program or erase
cycle to complete before a read may be performed. • 8- or 16-bit data bus

The Flash memory is divided into 40 sectors for erase • Byte-write or byte-select lines
operations. To further enhance device flexibility, an Erase • Remap of boot memory
Suspend feature is offered. This feature puts the erase • Two different read protocols
cycle on hold for an indefinite period and allows the user to • Programmable wait state generation
read data from, or to write data to, any other sector within
• External wait request
the same memory plane. There is no need to suspend an
erase cycle if the data to be read is in the other memory • Programmable data float time
plane. The device has the capability to protect data stored
in any sector. Once the data protection for a sector is

6 AT91F40416
 AT91F40416

AIC: Advanced Interrupt Controller TC: Timer Counter

The AT91F40416 has an 8-level priority, individually The AT91F40416 features a Timer Counter (TC) block
maskable, vectored interrupt controller. This feature sub- which includes three identical 16-bit timer counter chan-
stantially reduces the software and real time overhead in nels. Each channel can be independently programmed to
handling internal and external interrupts. perform a wide range of functions including frequency mea-
The interrupt controller is connected to the NFIQ (fast inter- surement, event counting, interval measurement, pulse
rupt request) and the NIRQ (standard interrupt request) generation, delay timing and pulse width modulation.
inputs of the ARM7TDMI processor. The processor’s NFIQ Each timer counter channel has three external clock inputs,
line can only be asserted by the external fast interrupt five internal clock inputs, and two multi-purpose input/out-
request input: FIQ. The NIRQ line can be asserted by the put signals which can be configured by the user. Each
interrupts generated by the on-chip peripherals and the channel drives an internal interrupt signal which can be
external interrupt request lines: IRQ0 to IRQ2. programmed to generate processor interrupts via the AIC
An 8-level priority encoder allows the customer to define (Advanced Interrupt Controller).
the priority between the different NIRQ interrupt sources. The Timer Counter block has two global registers which act
Internal sources are programmed to be level sensitive or upon all three TC channels. The Block Control Register
edge triggered. External sources can be programmed to be allows the three channels to be started simultaneously with
positive or negative edge triggered or high or low level sen- the same instruction. The Block Mode Register defines the
sitive. external clock inputs for each timer counter channel, allow-
ing them to be chained.
PIO: Parallel I/O Controller
The AT91F40416 has 32 programmable I/O lines. Five pins
WD: Watchdog Timer
on the AT91F40416 are available as general purpose I/O The AT91F40416 has an internal watchdog timer which
pins (P16, P17, P18, P19, and P23). Other I/O lines are can be used to reset the system if the software becomes
multiplexed with on-chip peripheral signals in order to opti- trapped in a deadlock. An active-low signal, NWDOVF, is
mize the use of available package pins. The PIO controller generated for external use, on watchdog overflow.
enables generation of a bit-maskable interrupt on input
level change as well as the insertion of bit-enablable input PS: Power Saving
glitch filter on any of the PIO pins.
The AT91F40416 Power Saving module provides a low-
power idle mode. In Idle mode, the CPU clock is deacti-
USART: Universal Synchronous/ vated while all on-chip peripherals and the RAM remain
Asynchronous Receiver/Transmitter active. The contents of the on-chip RAM and all the special
The AT91F40416 provides two identical, full-duplex, uni- function registers remain unchanged during this mode. The
versal synchronous/asynchronous receiver/transmitters Idle mode can be terminated by any enabled interrupt or by
which are connected to the Peripheral Data Controller. a hardware Reset.
The main features are:
• Programmable baud rate generator
SF: Special Function
• Parity, framing and overrun error detection The AT91F40416 provides registers which implement the
following special functions.
• Line break generation and detection
• Chip identification
• Automatic echo, local loopback and remote loopback
channel modes • RESET status

• Multi-drop mode: address detection and generation

• Interrupt generation
• Two dedicated peripheral data controller channels
• 5-, 6-, 7- and 8-bit character length

7
Emulation Functions
Tristate Mode ICE Debug Mode
The AT91F40416 features a tristate mode, which is used ARM standard embedded In-Circuit Emulation is supported
for debug purposes in order to connect an emulator probe via the ICE port. It is connected to a host computer via an
to an application board. external ICE Interface.
In ICE Debug Mode the ARM core responds with a non-
JTAG chip ID which identifies the core to the ICE system.
This is not JTAG IEEE 1149.1 compliant.

Ordering Information
Speed Power Supply Temperature
(MHz) Operating Range Ordering Code Package Operating Range
Commercial
AT91M40416-25CC BGA 120
(0°C to 70°C)
25 2.7V to 3.6V
Industrial
AT91M40416-25CI BGA 120
(-40°C to 85°C)

8 AT91F40416
 AT91F40416

Package Outline BGA 120

Figure 2. 120-ball Ball Grid Array Package

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A
B
C
D
E
TOP VIEW
F
AT91F40416
G
H
J
K

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

K
J
H

+ 0.15
+ 0.15
G
F
+ 0.15

11.00 −
9.00 −
BOTTOM VIEW
E
1.00 −

D
C
B
A

+ 0.15
1.00 − 0.51 (120)

+ 0.15
15.00 −
1.70 max

0.41 max

+ 0.15
17.00 −

All dimensions in mm

SIDE VIEW

9
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© Atmel Corporation 1999.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s website. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
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not authorized for use as critical components in life suppor t devices or systems.

ARM, Thumb and ARM Powered are registered trademarks of ARM Limited.
ARM7TDMI is a trademark of ARM Ltd. Printed on recycled paper.
All other marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation.
1317A–10/99/5M
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