Texas Instruments Incorporated Amplifiers: Op Amps

Interfacing op amps to high-speed DACs,

Part 2: Current-sourcing DACs
By Jim Karki
Member, Technical Staff, High-Performance Analog
Introduction Figure 11. Simplified PMOS current source
Most high-speed DACs are current-steering DACs that are
designed with complementary outputs that either source
PMOS
or sink current. Part 1 (see Reference 1) of this three-part
AVDD
article series discussed the interface between a current-
sinking DAC and an op amp. This article, Part 2, discusses
the interface between a current-sourcing DAC and an op
amp. This interface allows the designer to use the full
compliance voltage range of the DAC. Part 3, which will Current- Example Devices:
appear in a future issue of the Analog Applications Source DAC902, DAC2902,
Journal, will discuss interfacing a current-sourcing DAC Cascodes DAC5662, DAC5674
and an op amp by using the more popular configuration
that simply terminates to ground. This article series
focuses on using high-speed DACs in end equipment that
requires DC coupling, like signal generators with frequency
bandwidths of up to 100 MHz and a single-ended output. Switches
In these cases, high-speed op amps can provide a good
solution for converting the complementary-current output
from a high-speed DAC to a voltage that can drive the
Output
signal output. Compliance Voltage:
It is assumed that the reader is familiar with the opera- IOUT1 IOUT2 –1.0 V to +1.25 V
tion of complementary-current-steering DACs. If further
information is needed, please see Reference 1 for an over-
view. The design approach for Part 2 is the same as for voltages tend to shut down the outputs, and lower voltages
Part 1, except that a current-sourcing DAC was used to have the potential to cause breakdown. Both of these
derive the design equations instead of the current-sinking should be avoided to provide the best performance and
DAC used in Part 1. Because of this, about half of the long term-reliability.
equations are the same and about half are modified. Generally the output is terminated via some impedance
to ground. This impedance supplies a current path needed
Architecture and compliance voltage of current- for the array, and the voltage drop across the same imped-
sourcing DACs ance can be used as a voltage output. The impedance can
Figure 11 shows a simplified example of a PMOS current be constructed in various ways; it can be a simple resistor
source and lists a few devices that use it. The compliance divider, a transformer-coupled impedance, or an active cir-
voltage shown is the voltage range at the DAC outputs cuit like an op amp. This article focuses on the interface to
within which a device will perform as specified. Higher an op amp.

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 Amplifiers: Op Amps Texas Instruments Incorporated

Op amp interface Figure 12. Proposed circuit for an op amp interface

A proposed op amp interface is shown in
Figure 12. This circuit will provide biasing
of the DAC outputs, convert the DAC cur- AVDD
DAC Bias Network
rents to voltages, and provide a single- VREF
VDAC+
ended output voltage. The op amp is the IDAC+ Input Resistors
to Positive Input
active amplifier element for the circuit and RX R2
of Op Amp
is configured as a difference amplifier.
• IDAC+ and IDAC– are the current outputs ZDAC+ R1 VS+
R3 Vp
from the DAC. +
AVDD
• R2 and R3 are input resistors to the posi- Op Amp VOUT
VREF Vn
tive input of the op amp. I DAC – VDAC– –
• RG and RF are the main gain-setting resis- RY VS –
tors for the op amp.
• RX, R1, RY, and R4 provide bias and imped­ Current- R4 RG RF
ance termination for the DAC outputs. Sourcing ZDAC –
DAC
• VDAC+ and VDAC– are the voltages at the
Op Amp Gain Resistors
outputs of the DAC.
• Vp and Vn are the input terminals of the
op amp.
• VS+ and VS– are the power supplies to the op amp. crite­ria. The following assumptions are made in this article:
Proper component selection will provide the impedance 1. The DAC output current, IDAC+, and the voltage swing,
required to maintain voltage compliance with maximum VDAC+, are defined by the designer to set a target value
amplitude and balance for the best performance. The for ZDAC+.
analysis of this circuit follows from Part 1 with only minor 2. An existing circuit voltage or other known voltage is
changes due to the change in polarity of the DAC current used for VREF.
(sourcing versus sinking) and the change in compliance 3. In a difference amplifier, R3/R2 needs to equal RF/RG to
voltage range around ground instead of AVDD. The circuit balance the gain of the amplifier.*
in Figure 12 enables the designer to use the maximum 4. The equations will be solved for the condition where the
compliance voltage range of the DAC. DAC current on the positive side is zero (IDAC+ = 0 mA).
The motivation for this interface design is to balance the This in turn will set the DAC voltage on the positive side
input voltages to the difference-amplifier circuit to sup- to its minimum value, VDAC+ = VDAC+(min). Note that
press second-order harmonics, and little impact is expected this value is different from that of the current-sinking
on third-order harmonics. Also, because it allows higher DAC in Part 1, where setting IDAC+ = 0 mA led to
voltage swings at the DAC output than simple termination VDAC+ = VDAC+(max).
to ground, the gain of the op amp will be lower given the
same output-voltage requirement. * Note that in a voltage-feedback op amp, it is desirable to make the imped-
ance at Vp equal to that at Vn in order to cancel voltage offset caused by the
Analysis of positive side input bias current. In a current-feedback op amp, the input bias currents are
Figure 13 shows the analysis circuit for the positive side. not correlated; so it is acceptable not to balance these impedances, but it
The node equation at the VDAC+ output is the same as in may be desirable to minimize them.

Part 1 but with a change in the polarity of IDAC+:

VDAC + − VREF VDAC + VDAC + Figure 13. Positive side of analysis circuit
+ + −I =0 (20)
RX R1 R 2 + R3 DAC +
AVDD Z DAC+ VREF
The equation for the DAC output impedance stays
the same:
IDAC+ RX
ZDAC + = R X || R1 || ( R 2 + R3 ) (21) R2 ~0
I~
Vp
To solve Equations 20 and 21, which are simultaneous VDAC+
equations with more variables than equations, the designer R1 R3
must choose or identify values based on other design

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Texas Instruments Incorporated Amplifiers: Op Amps

With these constraints, algebra and simultaneous-equation

Figure 14. Negative side of analysis circuit
techniques can be applied to Equations 20 and 21 to solve
for 1/R1:
AVDD VREF
1 1 1 Z DAC–
= − (22)
R1  1  R 2 + R3 IDAC– Vn
1 + V  RY
ZDAC +  REF 
RG RF
 − 1  VOUT
 VDAC +(min)  VDAC –
R4
The known value for R1 can be substituted into Equation
21, which can then be rearranged to find 1/RX. The result
is exactly the same as in Part 1:
1 1 1 1
= − − (23)
R X ZDAC + R1 R 2 + R3
side to its minimum value, VDAC– = VDAC–(min), and sets
Analysis of negative side the DAC voltage on the positive side to its maximum
Figure 14 shows the analysis circuit for the negative side. value, VDAC+ = VDAC+(max). The value of 1/R4 can then be
The node equation at the VDAC– output is the same as in used to find 1/RY:
Part 1 except for the DAC current’s change in polarity:  R3 
ZDAC + × α  
VDAC − − VREF VDAC − VDAC − − Vn
+ + − I DAC − = 0 (24)  R 2 + R3 
RY R4 RG + R 3 1−
1 RG  1 1 
= − +  (28)
The equation for the DAC output impedance stays RY ZDAC − R
 4 R G
the same:
Note that α, the multiplication factor from Vp to Vn, in
VDAC − essence expresses the difference between the input pins.
ZDAC − = (25)
I DAC − In a voltage-feedback amplifier, α is set by the loop gain of
With substitution and rearrangement, the amplifier. In a current-feedback amplifier, α is the gain
of the input buffer between the inputs. All that aside, α is
R3
Vp = VDAC + × , typically close enough to 1 that it can simply be removed
R 2 + R3 from the calculation.
and Vn = αVp can be used to rewrite Equation 25 as Calculating output voltage
1 1  1 1 1  Superposition can be used to write equations for the sepa-
= × + +  . (26) rate terms referred to VOUT . These equations are the same
ZDAC −  R 3   R Y R 4 RG 
ZDAC + × α  as those in Part 1. The difference is that now the DAC only

 R 2 + R3  sources current, which is by convention positive current
1− flow, making the direction of the op amp’s output-voltage
RG
swing match that of the DAC. In other words, when the
Using the same substitutions and general design con- DAC is sourcing current on the positive side, the output of
straints used on the positive side to drive values for ZDAC– , the op amp tends to swing positive, and when the DAC is
VREF, and RG, simultaneous-equation techniques can be sourcing current on the negative side, the output of the
applied to Equations 24 and 26 to solve for 1/R4 (Equation op amp tends to swing negative. This means that in the
27 below). Note that the equations are solved for the con- following equations, IDAC+ and IDAC– are always positive
dition where the DAC current on the negative side is zero: or zero.
IDAC– = 0 mA. This sets the DAC voltage on the negative

 R3 
ZDAC + × α  
 R 2 + R3   VDAC +(max) × α 
R3  
1−  R + R  − VDAC − (min) 
RG  2 3  1 
+  − 1 
 
1 ZDAC −  V REF − VDAC − (min)   RG 
= (27)
R4 VDAC − (min)
+1
VREF − VDAC − (min)

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 Amplifiers: Op Amps Texas Instruments Incorporated

The output-referred DC bias from the positive side is

 RF   R1R3 
VOUT _ V = 1 +  ×  VREF × .
p( DC )
 R G + R Y || R 4  R1 ( R 2 + R 3 ) + R X ( R1 + R 2 + R )
3 

The output-referred DAC signal from the positive side is

 RF   R X R1R3 
VOUT _ V = 1 +  × I DAC + × .
p( DAC )
 R G + R Y || R 4  R R
X 1 + ( R1 + R X ) ( R 2 + R )
3 

The output-referred DC bias from the negative side is

 R4 RF 
VOUT _V = −  VREF × × .
n ( DC )
 R Y + R 4 R G + R Y || R 4

The output-referred DAC signal from the negative side is

 R Y R4 RF 
VOUT _V = −  I DAC − × .
n ( DAC )
 R R
Y 4 + R R
G 4 + R R
Y G

Adding these four equations provides an expression for VOUT:

VOUT = VOUT _V + VOUT _V + VOUT _V + VOUT _V (29)
p( DC ) p( DAC ) n ( DC ) n ( DAC )

If it is assumed that IDAC = IDAC+ – IDAC–, Z = ZDAC+ = require VREF to be a negative voltage. The DAC full-scale
ZDAC–, and RF/RG = R3/R2, the DC component of the DAC output is set to 20 mA. To get a 5-VPP, DC-coupled single-
outputs will cancel and the AC signal’s gain equation from ended output signal, the circuit shown in Figure 12 can be
the DAC output current to the voltage output of the op used. Since a ±5-V power supply is being used for the op
amp can be simplified and written as amp, it is convenient to make VREF = –5 V. Given that
VOUT R IDAC± = 20 mA and VDAC± = 2.25 VPP, the target impedance,
= 2Z × F . (30) ZDAC±, can be calculated to equal 112.5 Ω.
I DAC RG
With the starting design constraints given earlier, the
Texas Instruments THS3095 current-feedback op amp is
Design example and simulation selected as the amplifier, where R3 = RF = 750 Ω. The gain
For an example of how to proceed with the design, assume from VDAC± to the output is given by the resistor ratios
that the PMOS DAC noted earlier, with a compliance volt- RF/RG = R3/R2, so RG can be calculated as
age ranging from –1.0 V to +1.25 V, is being used. Also
VDAC ± 2 ( 2.25 V )
assume that the full compliance voltage range will be used RG = R 2 = R F × = 750 Ω × = 675 Ω .
to maximize the DAC output voltage, which in turn will VOUT 5V
minimize the gain required from the op amp and will The nearest standard 1% value, 681 Ω, should be used.

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High-Performance Analog Products www.ti.com/aaj 4Q 2009 Analog Applications Journal

Texas Instruments Incorporated Amplifiers: Op Amps

Equations 22, 23, 27, and 28 can be used to find, respectively, R1, RX, R4, and RY:

1 1
R1 = = = 155.95 Ω
1 1 1 1
− −
 1  R 2 + R3  1  681 Ω + 750 Ω
ZDAC + 1 +  112.50 Ω 1 + 
VREF  −5 V

 − 1  − 1
 VDAC +(min)   −1 V 

1 1
RX = = = 562.5 Ω
1 1 1 1 1 1
− − − −
ZDAC + R1 R 2 + R3 112.5 Ω 155.95 Ω 681 Ω + 750 Ω

VDAC − (min)
+1
VREF − VDAC − (min)
R4 =
 R3 
ZDAC + × α  
 R 2 + R3    R3  
1−  VDAC +(max) × α  R + R  − VDAC − (min) 
RG  2 3  1 
+ − 1 
ZDAC −  V − V  R 
 REF DAC − (min)  G 

−1 V
+1
−5 V + 1 V
= = 206.84 Ω
112.5 Ω × 1 × 750 Ω
681 Ω + 750 Ω  1.25 V × 1 × 750 Ω
1−  + 1 V 
681 Ω + 681 Ω + 750 Ω  1 
− 1  
112.5 Ω  −5 V + 1 V   681 Ω 

1 1
RY = = = 550.58 Ω
 R3  750 Ω
ZDAC + × α  112.5 Ω × 1 ×
 681 Ω + 750 Ω
 R 2 + R3  1−
1− 681 Ω  1 1 
RG  1 1  − + 
− +  112.5 Ω  206.84 Ω 681 Ω 
ZDAC − R
 4 R G 

The nearest standard 1% values should be used: SPICE simulation is a great way to validate the design.
R1 = 154 Ω, RX = 562 Ω, R4 = 205 Ω, and RY = 549 Ω. To see a TINA-TI™ simulation of the circuit in this exam-
These equations are easily solved when set up in a ple, go to http://www.ti.com/lit/zip/slyt360 and click Open
spreadsheet. To see an example Excel® worksheet, go to to view the WinZip directory online (or click Save to
http://www.ti.com/lit/zip/slyt360 and click Open to view download the WinZip file for offline use). If you have the
the WinZip® directory online (or click Save to download TINA-TI software installed, you can open the file DAC_
the WinZip file for offline use). Then open the file DAC_ Source_to_Op_Amp_No_Filter.TSC to view the example.
Source_to_Op_Amp_Wksht.xls and select the “DAC To download and install the free TINA-TI software, visit
Source to Op Amp, No Filter” worksheet tab. www.ti.com/tina-ti and click the Download button.

27

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 Amplifiers: Op Amps Texas Instruments Incorporated

Figure 15. Simulation of current-sourcing DAC interfaced to op amp

DAC Current Source Ideal Model

IS1 10m
VCCS1 1
+ VDAC-
IDAC-
- Rg 681 Rf 750
A +

VCVS1 10m
Ry 549 R4 205
Ideal Op Amp
+ +
+

AVDD 3.3 + Vout

VG1 Vin+ VCVS3 1G VOUT
- -
+ +

+
VREF -5 - -
IS2 10m RL 100
VCCS2 1
Vin-
+ Rx 562 R1 154
IDAC+
- R2 681 R3 750
A +
VDAC+

0
IDAC+
The simulation circuit and waveforms in Figure 15 show (mA)
that the circuit simulates as expected. IDAC+ and IDAC– are –20
0
the DAC currents, VDAC+ and VDAC– are the voltages devel- IDAC–
oped at the DAC outputs, and VOUT is the output of the (mA)
amplifier. The current-sourcing DAC and op amp are ideal –20
1.24
elements constructed with SPICE macros and are intended VDAC+
to show that the equations derived earlier for R1, RX, R4, (V)
and RY are valid for ideal elements. Actual performance –0.992
1.24
will vary depending on selected devices. VDAC–
(V)
DAC image-filter considerations –0.998
Part 1 discussed the need for filtering to reduce the ampli- 2.46
tude of the DAC sampling images and recommended filter- VOUT
(V)
ing directly at the DAC output before the op amp to achieve –2.46
the best performance. The situation is the same here. As 0 15 30
mentioned in Part 1, it is usually much easier to find stan- Time (µs)
dard component values to implement the filter when the
input and output impedances to the filter are balanced.

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Texas Instruments Incorporated Amplifiers: Op Amps

Figure 16. Inserting DAC image filter

AVDD
VREF 2ZDAC+ VREF
IDAC+
R´X R´´X R2
Filter
R´1 R´´1 VS+
R3 Vp
AVDD +
Op Amp VOUT
VREF VREF Vn
–
I DAC –
RÝ R´´Y VS –
Filter
Current- R´4 R´4́ RG RF
Sourcing
DAC 2ZDAC–

Figure 16 shows the proposed circuit implementation 1 1 1

where R1, RX, R4, and RY have been replaced with prime = − (32)
R1′′  1  R 2 + R3
and double-prime components on either side of the filter, 2ZDAC + 1 + 
so that  VREF 
 − 1 
R1 = R′1 || R″1,  VDAC +(min) 
RX = R′X || R″X,
R4 = R′4 || R″4, and
RY = R′Y || R″Y. 1 1 1
= − (33)
R′X 2ZDAC + R1′
At the same time, the impedance seen on each terminal of
the filter is 2 × ZDAC±. By use of algebra, the following
equations can be derived: 1 1 1 1
= − − (34)
R′′X 2ZDAC + R1′′ R 2 + R3
1 1
= (31)
R1′  1 
2ZDAC + 1 + 
VREF   R3  
 − 1
 VDAC +(min)   ZDAC + × α  R + R  
  1 −  2 3

 RG 
 2 Z 
1  DAC − 
= (35)
R′4 VDAC − (min)
+1
VREF − VDAC −(min)

 R3 
ZDAC + × α  
 R 2 + R3    R3  
1−  VDAC +(max) × α  R + R  − VDAC − (min) 
RG  2 3   1 
+  − 1   
1 2 ZDAC −  VREF − VDAC − (min)   RG 
= (36)
R4′′ VDAC − (min)
+1
VREF − VDAC − (min)

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Analog Applications Journal 4Q 2009 www.ti.com/aaj High-Performance Analog Products

 Amplifiers: Op Amps Texas Instruments Incorporated

outputs from a current-sourcing DAC to a single-ended

 R3 
ZDAC + × α   voltage. Equations were derived and a methodology pre-
 R 2 + R3  sented for proper selection of component values to set
1−
1 RG 1 the DAC’s output-voltage compliance while maintaining
= − (37) balanced input signals to the op amp for best overall per-
R Y′ 2 ZDAC − R4′
formance. Filter-design considerations were also included
to explain proper insertion when filtering before the
 R3  amplifier is desired.
ZDAC + × α  
 R 2 + R3  Reference
1−
1 RG  1 1  For more information related to this article, you can down­
= − +  (38) load an Acrobat® Reader® file at www-s.ti.com/sc/techlit/
R Y′′ 2 ZDAC−  R4′′ RG 
litnumber and replace “litnumber” with the TI Lit. # for
the materials listed below.
These equations are easily solved when set up in a
Document Title TI Lit. #
spreadsheet. To see an example Excel worksheet, go to
http://www.ti.com/lit/zip/slyt360 and click Open to view 1. Jim Karki, “Interfacing Op Amps to High-
the WinZip directory online (or click Save to download the Speed DACs, Part 1: Current-Sinking DACs,”
WinZip file for offline use). Then open the file DAC_ Analog Applications Journal (3Q 2009) . . . . . slyt342
Source_to_Op_Amp_Wksht.xls and select the “DAC Related Web sites
Source to Op Amp, Filtered” worksheet tab.
amplifier.ti.com
The performance is similar to that shown in the SPICE
www.ti.com/sc/device/partnumber
simulation for Part 1 (Reference 1). Please refer to that
Replace partnumber with DAC902, DAC2902, DAC5662,
simulation to see the effects of balancing and matching
DAC5674, or THS3095
the filter impedance versus using a filter with unmatched
impedance. TINA-TI and spreadsheet support files for examples:
www.ti.com/lit/zip/slyt360
Conclusion To download TINA-TI software:
This article has shown a circuit implementation using a www.ti.com/tina-ti
single-stage op amp to convert complementary-current

30

High-Performance Analog Products www.ti.com/aaj 4Q 2009 Analog Applications Journal

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