D10 Application Training

D10 Training Outline

Day1:
- Plateform Overview
- Timing And STIL
- Passive Load
- Instrument Pin Introduction
- Program Overview(.job, .res, .sig, user_main, user_load,
API etc)

Day2:
- Lab: ITE Environment
- Lab: Run the Program
- Lab: Run the Tool(shmoo, margin, pattern tool etc)
- Frequency Measurement
- To Use the DIBU
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 D10 Training Outline

Day3:
- Lab: Write your own test program (74193)
- Binning
- OIC

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D-10 Technical Overview
 Use of Existing Technology

Use of industry standards
- STIL (Standard Tester Interface Language) Syntax
- Star Fabric cPCI bridge to backplane
- cPCI data bus interface
- Third-party cPCI and PXI instruments
- Third-party software tools

Use of existing Credence technology
- Omni ASIC for the DPIN96
- Octet analog instruments for DMSI
- Program Developer for program generation
- Test Developer for pattern generation
- Debug tools adapted from multiple platforms
- VI technology from SZ
- RF and Power Management technology from ASL

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 Architected for Performance

Designed for multi-site

- Sites management implemented in hardware for maximum
throughput and minimum overhead
- Multi-site analog and DC instruments
- D-10 software designed for multi-site

Designed for Maximum throughput
- 250 Mbyte/s Star Fabric bridge for fast data transfers and
pattern loads
- FPGA based firmware algorithms implemented to accelerate
throughput

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 Sapphire D-10

61cm DPIN96

58.5cm 25.5cm

48V Power 10 slot cPCI

Supply backplane

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 D-10 Digital / MS Instruments
Digital Pins Device Power VI Sources Quad M/S Instruments

96 pins, 200Mbps
16 supplies
16 pins, 4 quadrant
Audio/Video AWG

16M parallel vector
0 to +6V, 2A
20V, 300ma
Audio/Video Digitizer
memory,

Gangable to 16A
60V, 100ma
reconfigurable scan

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DPIN96 Digital Pincard
1 0 H L
Feature Diamond DPIN96
Channels per card 96
Max Drv or Cmp 200Mbps
Full Format I/O 200 Mbps
EPA ±500ps
Edge Resolution 19.5ps
Rise Time 1.2ns @ 3V
Drv Min Pulse 4ns @ 3V
Drv / Cmp Range -1V to 6V
Drv Super Voltage 12V
Per Pin PMU -2V to 12V, ± 25mA
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DPIN96 Digital / Omni asic
1 0 H L

Feature Diamond DPIN96

Instruction Rate 100 MHz
Edges per pin 4
Data bits per pin 4
Time Sets: 256 period (global)
t1 t2 t3 t4 256 edge per pin (global)
f1 f2 f3 f4 256 format per pin (global)
Memory Depth 16 Meg
Scan Yes/Reconfigurable
Fail Capture 64 / 16 Meg

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DPIN96 Timing
 Vector Data Flow
0
Channel 0 Channel 47 Fset Tset Seq
channel 1 data … channel 46 data
Data (x4) Data (x4) Addr (x8) Addr (x8) Control
16M

8 8
4 (data direction configurable)
Fmt Mem Time Set Mem
0 0
F F F F T T T T
m m m m 1 2 3 4
T T T T
1 2 3 4
255 255

6 6 6 6 19 19 19 19
vih
Drive Data 0 F1 Format
DUT Lookup Table T1 Edge Generator
Hi-Z W G 63
a e 0
voh F2 Format
v n Lookup Table T2 Edge Generator
vil 63
e e
F r 0 F3 Format
o a Lookup Table T3 Edge Generator
r t 63
m o
0 F4 Format
r T4 Edge Generator
Lookup Table
vol 63

Pin Electronics Formatting Logic Timing Generators

(1) Omni path shown / (1) channel data path shown

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Timing Examples in STIL
 The STIL File
STIL 1.0;
Signals {
"mr" In;
"pl_" In; Signal Definitions
}
SignalGroups {

}
all = '"mr"+"pl”'; Signal Group Definitions
Timing "EasyTiming" {
WaveformTable "wftEasy" {
Period '100ns';
Waveforms {
“all" { 0 { '0.0ns' D;}} Waveform Tables (timing & formats)
“all" { 1 { '0.0ns' U;}}
}
}
}
PatternBurst "EasyPat" {
PatList {

}
"Easy";
Pattern Bursts (list of patterns)
}
PatternExec “EasyExec” {
Timing "EasyTiming";
PatternBurst "EasyPat"; Pattern Execs (bursts & timing)
}
Pattern Easy {
EasyStart:
W "wftEasy";
V { all = 10 11 0000 xxxx xx ; }
V { all = 10 11 0000 xxxx xx ; } Patterns
EasyStop:
V { all = 01 01 0000 LLLL xx ; }
Stop;
}

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 Signals and Signal List Definitions
Signals {
"mr" In;
Vaild types are In, Out, InOut,
Supply and Pseudo
"pl_" In;

Scan pins also declared here
}
SignalGroups {
Expressions may contain signal
names or signal group names
all = ‘”mr”+”pl”';

“Quotes” around names are
} optional

See the Programmer’s Reference Manual or the STIL

IEEE spec for more information on STIL file syntax

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 Waveform Table Examples
Timing "EasyTiming" {
WaveformTable "wftEasy" {
Period '100ns'; Tester period
Waveforms {
“dnrz_pins" { 0 { ‘5.0ns' D;}}
“dnrz_pins" { 1 { ‘5.0ns' U;}}

“r1_pins" { 0 { ‘5.0ns' D; 55.0ns U;}}

“r1_pins" { 1 { ‘5.0ns' U;}}

“rz_pins" { 0 { ‘5.0ns' D;}}

“rz_pins" { 1 { ‘5.0ns' U; 55.0ns D;}}
}
}
Characters that will
} appear in the patternDescription of waveform for
each pattern character
Signals or Signal Lists
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 Waveforms for Timing Examples
Cycle= 100ns Cycle= 100ns
Period ‘100ns’;

0 { ‘5.0ns' D; 55.0ns U;}

R1 0 1 1 { ‘5.0ns' U;}

0 { ‘5.0ns' D;}
DNRZ
1 { ‘5.0ns' U;}

0 { ‘5.0ns' D;}
RZ 1 0
1 { ‘5.0ns' U; 55.0ns D;}

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 Four Edges Per Cycle

The D-10 STIL compiler imposes some rules on the edge formats

If not specified by defining ‘Z’ for a given signal, then the inhibit edge
will default to 0ns

Pattern states are:
Z= inhibit driver X= mask
D= drive down U= drive up
T,t= compare for tristate V,v= compare for valid
H,h= compare for high L,l= compare for low

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 Waveform Table Examples
Timing "EasyTiming" {
WaveformTable "wftEasy" {
Period '100ns';
Waveforms {
“dnrz_pins" { 0 { ‘5.0ns' D;}}
Edge1
“dnrz_pins" { 1 { ‘5.0ns' U;}}
Edge1 Edge2
“r1_pins" { 0 { ‘5.0ns' D; 55.0ns U;}}
“r1_pins" { 1 { ‘5.0ns' U;}} Edge1

“outputs" { H { ‘5.0ns' H;}}

Edge3
Edge0 “outputs" { L { ‘5.0ns' L;}}
“outputs" { T { ‘5.0ns' T;}} Edge2
}
}
}

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 The STIL File
PatternBurst "EasyPat" {
PatList {
"Easy"; Pattern Bursts (list of patterns)
}
}
PatternExec “EasyExec” {
Timing "EasyTiming";
Pattern Execs (bursts & timing)
PatternBurst "EasyPat";
}
Pattern Easy {
EasyStart:
W "wftEasy";
V { all = 10; }
V { all = 10 ; }
Patterns
EasyStop:
V { all = 01 ; }
Stop;
}

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 DPS16 Device Power Supply

16 source / measure channels

Vforce:
- 0 – 6 V positive only
- 0.1% accuracy
- 13 bit resolution
- 2 amps per channel
- 8 channels ganged to 16 amps

Iranges:
- 2A / 200mA / 2mA / 200uA
- 0.2% accuracy
- 16 bit resolution

Current clamps:
- 2% accuracy
- 2A range

Programmable / triggered 4k location cmd stack

64k location sample memory w/ on board averaging

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 VIS16 – 4 Quadrant VI Source

Sixteen VI source / measure channels

Four quadrant operation in two configurations:
- ±20V @ ±300mA
- ±60V @ ±100mA

20V / 60V configuration programmable per channel

Single ended voltage ranges:
- ±2V / ±6V / ±20V / ±60V

Differential voltage meas ranges (between 2 channels):
- ±20mV / ±200mV / ±2V / ±10V

Current ranges:
- ±300nA / ±3uA / ±300uA / ±30mA / ±300mA

±.03% FSR accuracy / ±.01% FSR repeatability

Programmable compensation for speed and stability

Programmable low pass filter for measured functions

Analog modulation up to 20kHz for PSRR tests

Internal and external triggers for measurement sampling
into 1024 location capture memory

50uF max capacitive load

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 D-10 AWG

Multi-Site, Multi-Band AWG

Memory
• Channels can be used
single-ended or differentially
Video Path • 4 channels share the same
Waveform waveform memory and the
Engine same clocking
Audio Path • Offset voltage is
independently adjustable
Clock
•A high-frequency video path
and a high-resolution audio
path are available for each
AWG
channel

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 D-10 AWG

Multi-Site AWG
Memory • Sampling rate: 300Msps
• Audio w/1KHz BPF:
THD 120dB
Video Path
SNR 105dB
Waveform • Video:
Engine
SNR 70dB
Audio Path SFDR@20MHz 70dB

Clock Instrument Clock

• Jitter < 3ps rms

AWG

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 Sapphire D-10 AWG
Feature Sapphire D-10 AWG
Number of outputs 8 SE or 4 differential
Output impedance 50 Ohms
Output range (open circuit) 8V p-p with ±4V common offset
and ±400mV independent offset
Hardware resolution 20 bits
Maximum sample rate 300 Msps
Waveform memory 1 Megaword
Bandwidth (3dB typical) LF path: 2MHz, HF path: >100MHz

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 Sapphire D-10 AWG

Feature Sapphire D-10 AWG

Jitter (typical) 3 ps rms
HF path filters 2 MHz, 6.3 MHz, 20 MHz, 63 MHz (LP, 5
pole Bessel)
LF path filters 2 kHz, 20 kHz, 200 kHz (LP, 6 pole Bessel)
1 kHz Bandpass (4th-order Butterworth)
Noise density 8 nV/Hz1/2 (HF path, 1V p-p into 50 Ohms)
SFDR (including 85dB at 1MHz
harmonics) 70dB at 20MHz

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 D-10 Digitizer

Video Capture Multi-Site, Multi-band DIG

Audio Capture
Capture
Video Capture
• 4 differential input channels
Memory
Audio Capture share the same clocking and
Video Capture triggering
Audio Capture
•A high-frequency video path
Video Capture
Audio Capture and a high-resolution audio
path are available for each
Clock
channel

DIG

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 D-10 Digitizer

•Multi-Site DIG
Video Capture • Sampling rate: 100Msps
Audio Capture
Capture
• Audio w/1KHz notch:
Video Capture
Memory THD 120dB
Audio Capture
SNR 100dB
Video Capture
Audio Capture
• Video
Video Capture
SNR 68dB
Audio Capture SFDR@20MHz 70dB
Clock
Instrument Clock
• Jitter < 3ps rms
AVD

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 Sapphire D-10 Digitizer
Feature Sapphire D-10 DIG
Number of channels 4 differential
Input impedance HF: 50 or 500 Ohms (100 or 1k
Ohms differential) to Vterm,
programmable from –2V to +6V
LF: 10 Mohm or 600 Ohm
Input range HF: 53mV to 4V (diff p-p, 2.5 dB
steps)
LF: 106 mV to 8 V (diff p-p, 2.5dB
steps)
Maximum sample rate 100 Msps
Waveform memory 0.5 Megaword

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 Sapphire D-10 Digitizer
Feature Sapphire D-10 DIG
ADC resolution HF: 14 bits, LF: 16 bits
Bandwidth (3 dB typical) HF: 230 MHz, LF: 4 MHz

Jitter (typical) 3 ps rms

Analog filters HF: 20 MHz, 63 MHz (low pass, 5 pole Bessel)
± (low pass, 4 pole Bessel)
LF: 63 kHz, 250 kHz
1 kHz (notch with 30 dB gain)
Halfband decimation 2x, 4x, 8x, 16x, 32x
filters
Noise density 4 nV/Hz½ (53 mV range)
22 nV/Hz½ (4.0 V range)
SFDR (including 70 dB at 20 MHz
harmonics) (SFDR is nearly flat below 20± MHz)

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 DIB Utility Board

Always goes in slot 9 (last slot)

Is required

Fixed supplies

Relay controls

Communication busses

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 D-10 Software

Simple

Intuitive

Open-architecture

Fast response time

Fast runtime

Based on
- Linux operating system
- C++ test program language
- STIL pattern format

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 D-10 Software

D-10 is committed to sharing
interfaces, tools and formats with
other Credence product lines as
much as possible
- STIL pattern format
- Analog Wave Tool
- Program Developer
- Test Developer
- Shmoo and Margin tool
- Handler/prober interface
- Galaxy data analysis
- Datalogging formats
- Test templates
- Many more……

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 Integrated Test Environment (ITE)

Project overview
- Program files
- Pattern files
- Tester configuration details

Operator interface
- Test setup
- Run control
- Datalogging

Interactive debugging tools
- Shmoo and Margin tool
- Pattern tool
- Analog Wave Tool (AWT)
- Pin and timing status displays
- Program Developer tool
- Interactive debug commands

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 Integrated Test Environment (ITE)
Navigation Drag and
pane drop
entries
from the
navigation
pane into
the display
pane to
view,
modify or
launch the
respective
Display and item
Setup Pane

Output and
Command Pane

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 STIL in ITE

Pattern, signal, pinlist and timing information

is automatically extracted from the STIL file

ITE provides a graphical display and edit
interface for the STIL information
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 Control Panels

Datalogging Pausing

Simple control panels allow the user to control the program

and set parameters such as pausing and datalogging flags

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 Debugging Tools

Shmoo & Margin AWT

Dragging and dropping tools into the display pane will

cause them to launch with setups for the current breakpoint

The display pane can be undocked

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 Credence Program Developer

Available on D-10,
Sapphire and Octet

Powerful program
development and debug
environment based on the
SlickEdit IDE

Browser is used to
navigate directories and
organize test templates
supplied by Credence or
written by users

Many standard IDE

features such as

Source code
debugger

Language-sensitive
editor

Context-sensitive help
Program Developer is launched by ITE for

Much, much more… test program development and debug

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Source Files and Job Creation

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Passive Load
 DPIN96

PlanetATE driver/comparator/PMU
dual channel devices

Omni ASICS for timing and APG

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 DPIN96 Loads

The DPIN96 has programmable loads per pin

Loads consist of termination voltage connected through a
resistive load

The value of the resistive load is selected from a list of 8
possible values

The termination voltage is programmable on a per-pin basis
across the range of –1.5V to 12V

Using the Ohm’s Law, the proper values can be chosen to
achieve the desired load current

Both Ioh and Iol can be tested by running a 2-pass functional
test with the loads set to the respective load currents for each
pass

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 Static Load Circuit

PMU Force Super Connection to

Voltage Voltage DUT Output

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Force and Measure Current Ranges

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