8/7/6/5/4/3/2/1 Multi-Phase

Buck Controller with

PWM_VID and I2C Interface

NCP81610
Description
The NCP81610 is a multiphase synchronous controller optimized www.onsemi.com
for new generation computing and graphics processors. The device is
capable of driving up to 8 phases and incorporates differential voltage
and phase current sensing, adaptive voltage positioning and
PWM_VID interface to provide and accurately regulated power for
computer or graphic controllers. The integrated power saving 1 40
interface (PSI) allows for the processors to set the controller in one of QFN40 5x5, 0.4P
three modes, i.e. all phases on, dynamic phases shedding or fixed low CASE 485CR
phase count mode, to obtain high efficiency in light−load conditions.
The dual edge PWM multiphase architecture ensures fast transient MARKING DIAGRAM
response and good dynamic current balance.
1
Features
• Compliant with NVIDIA OVR4i+ Specifications NCP81610
AWLYYWW
• Supports up to 8 Phases
• 2.8 V to 20 V Supply Voltage Range:
• 250 kHz to 1.2 MHz Switching Frequency (8 Phase) NCP81610 = Device Code
• Power Good Output A = Assembly Site
WL = Wafer Lot Number
• Under Voltage Protection (UVP) YY = Year of Production, Last Two Numbers
• Over Voltage Protection (OVP) WW = Work Week Number
• Per Phase Over Current Limiting (OCL)
• System Over Current Protection (OCP) PIN CONNECTIONS
• Startup into Pre−Charged Loads while Avoiding False OVP
• Configurable Load Line
• High Performance Operational Error Amplifier
• True Differential Current Balancing Sense Amplifiers for Each Phase
• Phase−to−Phase Dynamic Current Balancing
• Current Mode Dual Edge Modulation for Fast Initial Response to
Transient Loading
• Power Saving Interface (PSI)
• Automatic Phase Shedding with User Settable Thresholds
• PWM_VID and I2C Control Interface
• Compact 40 Pin QFN Package (5 x 5 mm Body, 0.4 mm Pitch)
• These Devices are Pb−Free and are RoHS Compliant

Typical Applications
• GPU and CPU Power ORDERING INFORMATION
• Graphic Cards Device Package Shipping†
• Desktop and Notebook Applications NCP81610MNTXG QFN40 5000 / Tape
(Pb−Free) & Reel
• Docking Stations
• Power Banks †For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

© Semiconductor Components Industries, LLC, 2016 1 Publication Order Number:

July, 2020 − Rev. 5 NCP81610/D
 J2 TP45 TP46 TP47 TP48 TP49 TP50 TP51
VCC_DUT VSN_sense
2 1

2
R128

2
4 3 1 2
6 5 ILIM
R38 J4
8 7 EN SDA
10 9

1
2
12 11 SCL C5
14 13
SDA 16 15 J3 C17
PSI
SCL 18 17 EN
R130

1
20 19 1 2
R129
1 2

J1

5
PGOOD
1
4 2
TP1 C2 R37 VSP_sense
1 2 1 2 TP52

3
TP53 TP54

2
TP36

2
TP44

TP37

R25
R16 REFIN

1 R28
R21

1
C18

40
39
38
37
36
35
34
33
32
31
TP42 C15 R43 R49
2
1 2 1 U1 2 1 2 1 2 12 1
TP38 R9

EN

PSI
1 2 TP43 C3

SCL
VSP

SDA
VSN

VCC
VIN 1 2
TP39

PGOOD
C16 TP55 TP57 TP58 TP59
R48 TP56

PWM_VID
1 30

VID_BUFF
1 C4 2 REFIN COMP 2 1 2 1
TP41
C1 2 29
TP40 VREF VREF FB
3 28

.
VRAMP DIFF
4 27
PWM8 PWM8/SS FSW
5 26
PWM7 PWM7/I2C NCP81610 TMON
6 25
PWM6 PWM6/LPC1 IOUT
7 24
1

ILIM
1

PWM5 PWM5/LPC2 ILIM

1

8 23
1
C21

PWM4 PWM4/PHTH1 CSCOMP

R124
R125

9 22
2

2
2

PWM3 PWM3/PHTH2 CSSUM

R126
2

10 21
R127
2

2
PWM2/PHTH3 CSREF
1

PWM2
1

PWM1
R55
R56
R57

41

PWM1/PHTH4
CSP8
CSP7
CSP6
CSP5
CSP4
CSP3
CSP2
CSP1
C13

DRON
2

PAD

2
2

2
2

2
2

2
2

11
12
13
14
15
16
17
18
19
20
R14 R18 R22 TP62
R2 R4 R7 R10 R13
R39 1
NCP81610

1
R40 1

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1

1
1
2

1
R51 1

R41 1
C19

DRON TP60
1

R42 1
2
2

2
R44 1
2
C185

R45 1
2

2
1

2 R150 1
2
2 R46 1
R47
2

Ext_bias
1

1
1

1
1
1

1
1

Figure 1. Typical Controller Application Circuit

R148

R145
R147

R143
R144
R149

R142
R146
2

2
2

2
2
2

2
2

TP61
CSN2

CSN7
CSN6
CSN5
CSN3
CSN1

CSN8
CSN4

2 1
R30
2 1
R29
TMON2

TMON7
TMON6
TMON5
TMON3
TMON1

TMON4

2 1
TMON8

2R31 1
R33
2 1
R34
2 1
R35
2 1
2 R36 1
R32
ISNS3

ISNS7
ISNS6
ISNS5

ISNS8
ISNS4
ISNS2
ISNS1
 NCP81610

PIN DESCRIPTION
Pin No. Pin Name Pin Type Description
1 REFIN I Reference voltage input for output voltage regulation.
2 VREF O 2.0 V output reference voltage. A 10 nF ceramic capacitor is required to connect this pin to ground.
3 VRMP I Feed−forward input of VIN for the ramp slope compensation.
4 PWM8/SS I/O PWM 8 output / Soft Start setting. During startup it is used to program the soft start time with a
resistor to ground.

5 PWM7/I2C I/O PWM 7 output / I2C address. During startup it is used to program I2C address with a resistor to
ground.

6 PWM6/LPC1 I/O PWM 6 output / Low phase count 1. During startup it is used to program the warm boot−up
power zone (PSI set low) with a resistor to ground.

7 PWM5/LPC2 I/O PWM 5 output / Low phase count 2. During startup it is used to program the cold boot−up power
zone (PSI set low) with a resistor to ground.

8 PWM4/PHTH1 I/O PWM 4 output / Phase Shedding Threshold 1. During startup it is used to program the phase
shedding threshold 1 (PSI set to mid state) with a resistor to ground.

9 PWM3/PHTH2 I/O PWM 3 output / Phase Shedding Threshold 2. During startup it is used to program the phase
shedding threshold 2 (PSI set to mid state) with a resistor to ground.

10 PWM2/PHTH3 I/O PWM 2 output / Phase Shedding Threshold 3. During startup it is used to program the phase
shedding threshold 3 (PSI set to mid state) with a resistor to ground.

11 PWM1/PHTH4 I/O PWM 1 output / Phase Shedding Threshold 4. During startup it is used to program the phase
shedding threshold 4 (PSI set to mid state) with a resistor to ground.

12 DRON I/O Bidirectional gate driver enable for external drivers.

13 CSP8 I Non−inverting input to current balance sense amplifier for phase 8. Pull−up to VCC with a 2 k
resistor to disable the PWM8 output.
14 CSP7 I Non−inverting input to current balance sense amplifier for phase 7. Pull−up to VCC with a 2 k
resistor to disable the PWM7 output.
15 CSP6 I Non−inverting input to current balance sense amplifier for phase 6. Pull−up to VCC with a 2 k
resistor to disable the PWM6 output.
16 CSP5 I Non−inverting input to current balance sense amplifier for phase 5. Pull−up to VCC with a 2 k
resistor to disable the PWM5 output.
17 CSP4 I Non−inverting input to current balance sense amplifier for phase 4. Pull−up to VCC with a 2 k
resistor to disable the PWM4 output.
18 CSP3 I Non−inverting input to current balance sense amplifier for phase 3. Pull−up to VCC with a 2 k
resistor to disable the PWM3 output.
19 CSP2 I Non−inverting input to current balance sense amplifier for phase 2. Pull−up to VCC with a 2 k
resistor to disable the PWM2 output.
20 CSP1 I Non−inverting input to current balance sense amplifier for phase 1. Pull−up to VCC with a 2 k
resistor to disable the PWM1 output.
21 CSREF I Total output current sense amplifier reference voltage input.
22 CSSUM I Inverting input of total current sense amplifier.
23 CSCOMP O Output of total current sense amplifier.
24 ILIM I/O Over current limit (OCL) threshold setting input. The threshold is set by a shunt resistor to the
ground.

25 IOUT O Total output current. A resistor to GND is required to provide a voltage drop of 2V at the
maximum output current.

26 TMON I DRMOS temperature monitoring.

27 FSW I Resistor to ground from this pin sets the operating frequency of the regulator.
28 DIFF O Output of the regulators differential remote sense amplifier.
29 FB I Error amplifier inverting (feedback) input.
30 COMP O Output of the error amplifier and the inverting input of the PWM comparator.

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 NCP81610

PIN DESCRIPTION (continued)

Pin No. Pin Name Pin Type Description
31 VSP I Differential Output Voltage Sense Positive terminal.
32 VSN I Differential Output Voltage Sense Negative terminal.
33 VCC I Power for the internal control circuits. A 1 F decoupling capacitor is requires from this pin to
ground.
34 SDA I/O Serial Data bi−directional pin, requires pull−up resistor to VCC.
35 SCL I Serial Bus clock pin, requires pull−up resistor to VCC.
36 EN I Logic input. Logic high enables regulator output logic low disables regulator output.
37 PSI I Power Saving Interface control pin. This pin can be set low, high or left floating.
38 PGOOD O Open Drain power good indicator.
39 PWM_VID I PWM_VID buffer input.
40 VID_BUFF O PWM_VID pulse output from internal buffer.
41 AGND GND Analog ground and thermal pad, connected to system ground.

MAXIMUM RATINGS
Pin Symbol Rating Min Typ Max Unit
VSN Pin Voltage Range (Note 1) GND−0.3 − GND+0.3 V
VCC −0.3 − 6.5 V
VRMP −0.3 − 25 V
PWM_VID −0.3 (−2, <50 ns) − VCC+0.3 V
All other pins −0.3 − VCC+0.3 V
COMP Pin Current range −2 − 2 mA
CSCOMP
DIFF
PGOOD
VSN −1 − 1 mA
MSL Moisture Sensitivity Level − 1 − −
TSLD Lead Temperature Soldering − 260 − °C
Reflow (SMD Styles Only), Pb−Free Versions (Note 2)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. All signals referenced to GND unless noted otherwise
2. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

THERMAL CHARACTERISTICS
Symbol Rating Min Typ Max Unit
RJA Thermal Characteristics, QFN40, 5 x 5 mm) − 68 − °C/W
Thermal Resistance, Junction−to−Air (Note1)
TJ Operating Junction Temperature Range (Note 2) −40 − 125 °C
TA Operating Ambient Temperature Range −10 − 100 °C
TSTG Maximum Storage Temperature Range −55 − 150 °C

1 JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM )

2 JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM )

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 NCP81610

ELECTRICAL CHARACTERISTICS (−10°C < TA < 100°C; 4.6 V < VCC < 5.4 V; CVCC = 0.1 F unless otherwise noted)
Symbol Parameter Test Conditions Min Typ Max Unit
VCC SUPPLY
VCC Supply voltage range 4.6 − 5.4 V
ICC VCC Quiescent current Enable low, 2nd time − − 100 A
8 phase operation − 40 − mA
1 phase − DCM operation − 10 − mA
UVLORise UVLO Threshold VCC Rising − − 4.5 V
UVLOFall VCC Falling 4 − − V
UVLOHyst VCC UVLO Hysteresis − 200 − mV
SWITCHING FREQUENCY
FSW Switching Frequency Range 8 phase configuration 250 − 1200 kHz
FSW Switching Frequency Accuracy FSW = 810 kHz −4 − +4 %
ENABLE INPUT
IL Input Leakage EN = 0 V or VCC −1.0 − 1.0 A
VIH Upper Threshold 1.2 − − V
VIL Lower Threshold − − 0.6 V
DRON
VOH Output High Voltage Sourcing 500 A 3.0 − − V
VOL Output Low Voltage Sinking 500 μA − − 0.1 V
tR, tF Rise time (Note 3) Cl (PCB) = 20 pF, Vo = 10% to 90% − 160 − ns
Fall time (Note 3) Cl (PCB) = 20 pF, Vo = 10% to 90% − 3 − ns
RPULL−UP Internal Pull−up Resistance (Note 3) − 2.0 − k
RPULL_DOWN Internal Pull Down Resistance (Note 3) Vcc = 0 V − 12 − k
PGOOD
VOL Output low voltage IPGOOD = 10 mA (sink) − − 0.4 V
IL Leakage Current PGOOD = 5 V − − 0.2 A
T_init Output voltage initialization time From EN to ramp starts, 2nd ENABLE − − 0.5 ms
T_total Total Soft Startup Period T_Ramp ≤ 0101, RT_Ramp ≤ 41.2 k; − − 2.0 ms
From EN to PGOOD
VRMP
VRMP Supply Range 2.8 − 20 V
VRMPrise UVLO VRMP rising − − 2.8 V
VRMPfall VRMP falling 2.5 − − V
VRMPhyst VRMP UVLO Hysteresis − 150 − mV
PROTECTION FEATURES: OVP, UVP, TMON, ILIM, CLIM, TSD
UVP Under Voltage Protection (UVP) Threshold Relative to REFIN Voltage − − −400 mV
TUVP Under Voltage Protection (UVP) Delay − 5 − s
(Note 3)

OVP Over Voltage Protection (OVP) Threshold Relative to REFIN Voltage 500 − − mV
TOVP Over Voltage Protection (OVP) Delay − 5 − s
(Note 3)

TMON External Temperature Monitoring (TMON) 0.6 − 1.9 V

Linear Range

TMONLT TMON Latch Threshold Default 1.9 2.0 2.1 V

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 NCP81610

ELECTRICAL CHARACTERISTICS (−10°C < TA < 100°C; 4.6 V < VCC < 5.4 V; CVCC = 0.1 F unless otherwise noted) (continued)
Symbol Parameter Test Conditions Min Typ Max Unit
PROTECTION FEATURES: OVP, UVP, TMON, ILIM, CLIM, TSD
TMONLN TMON Linear Range 0 − 2.0 V
TMON_ADC TMON Input to ADC Accuracy − 5 − %
TSD Chip Thermal Shutdown Temperature Temperature Rising 145 155 − C
(Note 3)

TSD_HYS Chip Thermal Shutdown Hysteresis − 15 − C

(Note 3)

CLIMFALL CLIM Overall Current Limit Entering CSCOMP Falling − 225 − mV

ILIM ILIM Sourcing Current 9 10 11 A
VILIM ILIM range 0 − 2 V
RILIM RILIM range 0 − 200 k
PWM OUTPUTS
VOH Output High Voltage Sourcing 500 A VCC−0.2 − − V
VMID Output Mid Voltage 1.4 1.5 1.6 V
VOL Output Low Voltage Sinking 500 A − − 0.6 V
tR, tF Rise and Fall Time (Note 3) CL(PCB) = 50 pF, Vo = 10% to 90% of − 10 − ns
VCC
IL Tri−State Output Leakage Gx = 2.0 V, x = 1 − 8, EN = Low −1.0 − 1.0 A
Ton Minimum On Time (Note 3) FSW=600 kHz − 12 − ns
VCOMP0% 0% Duty Cycle Comp voltage when PWM = Low − 1.3 − V
VCOMP100% 100% Duty Cycle Comp voltage when PWM = High − 2.5 − V
∅ PWM Phase Angle Error Between Adjacent phases − ±15 − °
PHASE DETECTION
VPHDET Phase Detection Threshold Voltage CSP2 to CSP8 − − VCC−0.1 V
TPHDET Phase Detect Timer (Note 3) CSP2 to CSP8 − 1.1 − ms
ERROR AMPIFIER
IBIAS Input Bias Current −400 − 400 nA
GOL Open Loop DC Gain (Note 3) CL = 20 pF to GND, RL = 10 k to GND − 80 − dB
GBW Open Loop Unity Gain Bandwidth (Note CL = 20 pF to GND, RL = 10 k to GND − 20 − MHz
3)

SR Slew Rate (Note 3) Vin = 100 mV, G = −10 V/V, − 5 − V/s

Vout = 0.75 V – 1.52 V,
CL = 20 pF to GND, RL = 10 k to GND
VOUT Maximum Output Voltage ISOURCE = 2mA 3.5 − − V
VOUT Minimum Output Voltage ISINK = 2mA − − 1 V
DIFFERENTIAL SUMMING AMPLIFIER
IBIAS Input bias current −400 − 400 nA
VIN VSP input voltage 0 − 2 V
VIN VSN input voltage −0.3 − 0.3 V
BW −3 dB Bandwidth (Note 3) CL = 20 pF to GND, RL = 10 k to GND − 12 − MHz
G Closed loop DC gain (VSP−VSN to DIFF) VSP to VSN = 0.5 to 1.3 V − 1 − V/V
VOUT Maximum output voltage ISOURCE = 2 mA 3 − − V
VOUT Minimum output voltage ISINK = 2 mA − − 0.8 V

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 NCP81610

ELECTRICAL CHARACTERISTICS (−10°C < TA < 100°C; 4.6 V < VCC < 5.4 V; CVCC = 0.1 F unless otherwise noted) (continued)
Symbol Parameter Test Conditions Min Typ Max Unit
CURRENT SUMMING AMPLIFIER
VOS Offset Voltage −500 − 500 V
IL Input Bias Current CSSUM = CSREF = 1 V −7.5 − 7.5 A
G Open Loop Gain (Note 3) − 80 − dB
GBW Current sense Unity Gain Bandwidth CL = 20 pF to GND, RL = 10 k to GND − 10 − MHz
(Note 3)

VOUT Maximum CSCOMP Output Voltage ISOURCE = 2 mA 3.5 − − V

VOUT Minimum CSCOMP Output Voltage ISINK = 1 mA − − 0.3 V
PHASE CURRENT AMPLIFIER
IBIAS Input Bias Current CSPX − CSPX + 1 = 1.2 V −50 − 50 nA
VCM Common Mode Input Voltage Range CSPx = CSREF 0 − 2 V
(Note 3)

VDIFF Differential Mode Input Voltage Range CSREF = 1.2 V −250 − 250 mV
Closed loop Input Offset Voltage Matching CSPx = 2 V, Measured from the average −1.5 − 1.5 mV
G Current Sense Amplifier Gain −250 mV < CSPx − CSREF < 250 mV 5.5 6.0 6.5 V/V
BW −3dB Bandwidth (Note 3) − 8 − MHz
VZCD Single Phase ZCD comparator threshold PSI = 0, Single Phase, By Default − 0 − mV
CSP1 − CSREF

TZCD ZCD Comparator Delay (Note 3) − 150 − ns

VZCD_UNIT ZCD User Trim Resolution (Note 3) − 1.2 − mV
IOUT
VOS Input Reference Offset Voltage CSCOMP to CSREF −10 − 10 mV
IOUT Output Current Max 10 A on Rcur − 100 − A
GIOUT IOUT Current Gain Iout / IRcur − 10 − A/A
VIOUT_RG IOUT Linear Range 0 − 3 V
VIOUT_ADC IOUT Input to ADC Accuracy 0 < VIOUT < 2 V − 5 − %
VOLTAGE REFERENCE
VREF VREF Reference Voltage IREF = 1 mA 1.98 2 2.02 V
VREF VREF Reference accuracy Over Temp − 1 1.5 %
PWM_VID BUFFER
VIH Upper threshold 1.4 − − V
VIL Lower threshold − − 0.5 V
FPWM_VID PWM_VID switching frequency 400 − 5000 kHz
tR Output Rise Time (Note 3) − 3 − ns
tF Output Fall Time (Note 3) − 3 − ns
t Rising and falling edge delay (Note 3) t = tR − tF − 0.5 − ns
tPD Propagation Delay (Note 3) tPD = tPDHL = tPDLH − 8 − ns
tPD Propagation Delay Error (Note 3) tPD = tPDHL − tPDLH − 0.5 − ns
VOCL_min
VOCL_min VOCL_min voltage range 0.2 − 1.3 V
VOCL_min_var VOCL_min accuracy VOCL_min = 1 V − 2 − %
PSI
VIH PSI high Threshold 1.45 − − V

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 NCP81610

ELECTRICAL CHARACTERISTICS (−10°C < TA < 100°C; 4.6 V < VCC < 5.4 V; CVCC = 0.1 F unless otherwise noted) (continued)
Symbol Parameter Test Conditions Min Typ Max Unit
PSI
VMID PSI mid threshold Auto Phase Shedding Enabled 0.8 − 1 V
VIL PSI low threshold − − 0.575 V
IL PSI input leakage current VPSI = 0 V o VCC −1 − 1 A
VMON
VMONLN VMON Linear Range 0 − 2.0 V
VMON_ADC VMON Input to ADC Accuracy − 5 − %
REFIN
RDISCH REFIN Discharge Switch ON− Resistance IREEFIN (SINK) = 2 mA − 10 − 
(Note 3)

VORP/VREFIN Ratio of Output voltage ripple transferred FPWM_VID = 400 kHz, FSW ≤ 600 kHz − 10 − %
from REFIN / REFIN Voltage ripple
VORP/VREFIN (Note 3) FPWM_VID = 1000 kHz, FSW ≤ 600 kHz − 30 −

I2C (Note 3)
VIH Logic High Input Voltage 1.4 − 5 V
VIL Logic Low Input Voltage 0 − 0.5 V
Hysteresis − 80 − mV
VOL Output Low Voltage ISDA = −6 mA − − 0.4 V
IL Input Current −1 − 1 A
CSDA, CSCL Input Capacitance − 5 − pF
fSCL Clock Frequency see Figure 2 − − 400 kHz
tLOW SCL Low period 1.3 − − s
tHIGH SCL High period 0.6 − − s
tR SCL/SDA rise time − − 300 ns
tF SCL/SDA fall time − − 300 ns
tSU;STA Start condition setup time 600 − − ns
tHD;STA Start condition hold time (Note 4) 600 − − ns
tSU;DAT Data setup time (Note 5) 100 − − ns
tHD;DAT Data hold time (Note 5) 300 − − ns
tSU;STO Stop condition setup time (Note 6) 600 − − ns
tBUF Bus free time between stop and start 1.3 − − s
3. Guaranteed by design, not production tested.
4. Time from 10% of SDA to 90% of SCL
5. Time from 10% or 90%of SDA to 10% of SCL
6. Time from 90% of SCL to 10% of SDA

Figure 2. I2C Timing Diagram

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 NCP81610

Applications Information REFIN pin average voltage will change the PWM outputs
The NCP81610 is a multi−phase buck converter duty cycle until the two voltages are identical. The load
controller optimized for the next generation computing and current is current is continuously monitored on each phase
graphic processor applications. It contains eight PWM and the PWM outputs are adjusted to ensure adjusted to
channels which can be individually configured to operate ensure even distribution of the load current across all phases.
from one to eight phases. Per phase current is monitored cycle by cycle with current
The output voltage is set by applying a PWM signal to the limiting.
PWM_VID input of the device. The controller converts the The device incorporates different fault protections
PWM_VID signal (400 kHz ~ 5 MHz) with variable high including per phase overcurrent limiting (OCL), on chip
and low levels into a 2 V PWM signal which is then being over temperature (TSD), external power stage over
filtered and averaged, and applied to the REFIN pin for temperature monitoring (TMON), output under voltage
internal regulation reference. (UVP) and output overvoltage (OVP) protections.
The remote output voltage and ground are differentially The communication between the NCP81610 and the user
sensed and the REFIN value is subtracted from sensed is handled with two interfaces, PWM_VID to set the output
voltage. The result is biased ,combined with loadline input voltage and I2C to configure or monitor the status of the
and applied to the error amplifier. If the loadline is disabled, controller. The operation of the internal blocks of the device
any difference between the sensed output voltage and the is described in more details in the following sections.

VID_BUFF VREF VCC EN

REF UVLO & EN

PWM_VID 1.3 V
EN
TMON TMON TMONLT
Comparator +  VSP
DIFFOUT
EN −  VSN
PGOOD VSP DROP
PGOOD LLEN
Comparator VSN

REFIN Soft Start LLTH

FB − CSCOMP

+
OVP / UVP VSP CSREF
1.3 V VSN
CSSUM
COMP
OVP / UVP
ILIM
Total Output Current
Mux PSI Measurement, OCL
IOUT
OCL_TH
VSP − VSN
IOUT
PWM1  8

TMON
FSW
ADC

IPH1
CSP1
IPH2 CSP2
Current Balance
IPH3 CSP3
IPH4 Amplifiers
Data CSP4
IPH5 and
Registers CSP5
IPH6 per Phase OCP CSP6
IPH7 Comparators CSP7
SDA Control IPH8 CSP8
SCL Interface
OCL_CTL
Ramp1
Ramp2 PWM1/PHTH4
FSW Ramp3 PWM2/PHTH3
PWM3/PHTH2
Ramp Ramp4 PWM Power State
VRMP Ramp5 PWM4/PHTH1
Generators Generators Stage PWM5/LPC2
Ramp6
PSI PWM6/LPC1
Ramp7
Ramp8 PWM7/I
PWM8/SS
TMONLT
OVP / UVP

DRON
OCP
EN

GND

Figure 3. NCP81610 Functional Block Diagram

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 NCP81610

Soft Start only de−asserts (pull low) when the controller shuts down
Soft start is defined as the transition from Enable assertion due to a fault condition (UVLO, OVP or UVP event).
high to the assertion of Power good as shown in Figures 4, 5. The output voltage ramp−up time is user settable by
The output is set to the desired voltage in two steps: T_init connecting a resistor between pin PWM8/SS and GND. The
is a fixed initialization step of less than 1 ms followed by a controller will measure the resistance value at power−up by
ramp−up step T_ramp where the output voltage is ramped to sourcing a 10 A current through this resistor and set the
the final value set by the PWM_VID interface and REFIN. ramp time (T_ramp) as shown in Table 11. To prevent false
During the soft start phase, PGOOD pin is initially set low over current claim, CSREF signal of the current summing
and will be set high when the output voltage is within amplifier needs to be ready before the soft start is complete.
regulation and the soft start is complete. The PGOOD signal

4.2 V
VCC

EN = 0 V

VSP − VSN = 0 V

PGOOD = Low

ICC <250 A Standby current <250 A

1  2 ms

Internal States Read Config / Cal / ADC STAND BY

Figure 4. VCC across UVLO with EN = 0

VCC = 5 V

EN

 REFIN

VOUT

T_init <1 ms T_ramp

T_total
PGOOD

Internal Read Regs Soft Start SS Done

State

ICC
<250 A

Figure 5. Soft Start by Toggling EN

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 NCP81610

PWM_VID Interface where,

PWM−VID is a single wire dynamic voltage control VDIFOUT is the output voltage of the differential
interface where the regulated voltage is set by the duty cycle amplifier
of the PWM signal applied to the controller.
VVSP−VVSN is the regulated output voltage sensed at
The device controller converts the variable amplitude
the load
PWM signal into a constant 2 V amplitude PWM signal
while preserving the duty cycle information of the input VREFIN is the voltage at the output pin set by the
signal. In addition, if the PWM_VID input is left floating, PWM_VID interface
the VID_BUFF output is tri−stated (floating). VDROOP−VCSREF is the expected drop in the
The constant amplitude PWM signal is then connected to regulated voltage as a function of the load
the REFIN pin through a scaling and filtering network (see current (load−line)
Figure 6). This network allows the user to set the minimum 1.3 V is an internal reference voltage used to bias the
and maximum REFIN voltages corresponding to 0% and amplifier inputs to allow both positive and
100% duty cycle values. negative output voltage for VDIFOUT
VCC Error Amplifier
0.1 F A high performance wide bandwidth error amplifier is
Internal provided for fast response to transient load events. Its
precision VREF
reference inverting input is biased internally with the same 1.3 V
Vref = 2 V
reference voltage as the one used by the differential sense
10 nF
R1
amplifier to ensure that both positive and negative error
PWM_VID VID_BUFF
voltages are correctly handled.
R3
An external compensation circuit should be used (usually
GND type III) to ensure that the control loop is stable and has
R2 C1 adequate response.
Ramp Feed−Forward Circuit
The ramp generator circuit provides the ramp used to
REFIN
generate the PWM signals using internal comparators (see
Controller
Figure 7) The ramp generator provides voltage
Figure 6. PWM VID Interface feed−forward control by varying the ramp magnitude with
respect to the VRMP pin voltage.
The minimum (0% duty cycle), maximum (100% duty The VRMP pin also has a UVLO function. The VRMP
cycle) and boot (PWM_VID input floating) voltages can be UVLO rising threshold is 2.8 V, only active after the EN is
calculated with the following formula: toggled high. The VRMP pin is a high impedance input
when the controller is disabled.
1
V MAX + V REF @
R1 @ R3 (eq. 1)
1) R 2 @ (R 1 ) R 3)
Vin

Vramp_pp
1 Comp−IL
V MIN + V REF @
R 1 @ (R 2 ) R 3) (eq. 2)
1) R2 @ R3
Duty

1 Figure 7. Ramp Feed−Forward Circuit

V BOOT + V REF @
R1 (eq. 3)
1) R2
PWM Output Configuration
Remote Voltage Sense By default the controller operates in 8 phase mode,
A high performance true differential amplifier allows the however the phases can be disabled by connecting the
controller to measure the output voltage directly at the load corresponding CSP pins to VCC. At power−up the
using the VSP (VOUT) and VSN (GND) pins. This keeps NCP81610 measures the voltage present at each CSP pin
the ground potential differences between the local controller and compares it with the phase detection threshold. If the
ground and the load ground reference point from affecting voltage exceeds the threshold, the phase is disabled. The
regulation of the load. The output voltage of the differential phase configurations that can be achieved by the device are
amplifier is set by the following equation: listed in Table 2. The active phase (PWMX) information is
V DIFOUT + (V VSP * V VSN) ) (1.3 V * V REFIN) ) (V DROOP * V CSREF) also available to the user in the phase status register.
(eq. 4)

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PSI, LPCX , PHTHX UVLO, EN is set high) while the LPC1 configuration sets
The NCP81610 incorporates a power saving interface the power zone in the consecutive soft startup by toggling
(PSI) to maximize the efficiency of the regulator under EN only (soft boot−up).
various loading conditions. The device supports up to five NCP81610 has the internal zero current detection
distinct operation modes, called power zones using the PSI, function (ZCD) enabled by default; if PSI = Low and the
LPCX and PHTHX pins (see Table 3). At power−up the system is configured to single phase mode (Power Zone = 4),
controller reads the PSI pin logic state and sources a 10 A the single phase switching circuit operates in diode
current through the resistors connected to the LPCX and emulation mode. The NCP81610 controller will sense the
PHTHX pins, measures the voltage at these pins and current information from CSP1−CSREF differential voltage
configures the device accordingly. in the internal ZCD mode with PWM1 toggling between
The configuration can be changed by the user by writing High, Mid and Low voltage levels accordingly. The
to the LPCX and PHTHX configuration registers. controller ZCD threshold can be adjusted by I2C command
After EN is set high, the NCP81610 ignores any change to accommodate different power stages and the propagation
in the PSI pin logic state until the output voltage reaches the delay.
nominal regulated voltage. The ZCD function within the NCP81610 can be disabled
When PSI = High, the controller operates with all active through the I2C command. While internal ZCD function is
phases enabled regardless of the load current. If PSI = Mid, disabled, PWM1 can be configured to either toggle between
the NCP81610 operates in dynamic phase shedding mode High and Low or High and Mid−level depending on type of
where the voltage present at the IOUT pin (the total load the power stage devices; In this case the power stage current
current) is measured every 10 s and compared to the sensing circuit will be used for zero current detection
PHTHX thresholds to determine the appropriate power function if necessary.
zone. NCP81610 I 2C Address
The resistors connected between the PHTHX and GND On power up, a 10 A current is sourced from PWM7/I2C
should be picked to ensure that with a 10 A source current pin to the shunt resistor to configure the I2C slave address
the voltage reading will match the voltage drop at the IOUT of the NCP81610. There are four I2C addresses available for
pin at the desired load current. Please note that the maximum this chip associated with different shunt resistor values.
allowable voltage at the IOUT pin at the maximum load
current is 2 V. Any PHTHX threshold can be disabled if the
voltage drop across the PHTHX resistor is ≥2 V for a 10 A Table 1. I2C ADDRESS SETTING
current, the pin is left floating or 0xFF is written to the Resistance (kW) I2C Address
appropriate PHTHX configuration register. The automatic 10 0x20
phase shedding mode is only enabled after the output voltage
41.2 0x30
reaches the nominal regulated voltage.
When PSI = low, the controller is set to a fixed power zone 100 0x40
regardless of the load current, programmable through user 249 0x50
register 0x34 and 0x36. The LPC2 setting controls the power
zone used during cold boot−up (After power on VCC

Table 2. PWM OUTPUT CONFIGURATION

CSP Pin Configuration ( = Normal Connection, X = Tied to VCC) Enabled PWM
Phase Outputs
Configuration Configuration CSP1 CSP2 CSP3 CSP4 CSP5 CSP6 CSP7 CSP8 (PWMX Pins)
1 8 phase         1, 2, 3, 4, 5, 6, 7, 8
2 7 phase        X 1, 2, 3, 4, 5, 6, 7
3 6 phase       X X 1, 2, 3, 4, 5, 6
4 5 phase      X X X 1, 2, 3, 4, 5
5 4 phase     X X X X 1, 2, 3, 4
6 3 phase    X X X X X 1, 2, 3
7 2 phase   X X X X X X 1, 2
8 1 phase  X X X X X X X 1

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Table 3. PSI, LPCX, PHTHX CONFIGURATION

Power Zone
PSI LPC1, LPC2
Logic Resistor IOUT vs. PHTHX 8 7 6 5 4 3 2 1
State (kW) Comparison Phase Phase Phase Phase Phase Phase Phase Phase
High Disabled Function Disabled 0 0 0 0 0 0 0 0
Low 10 0 0 0 0 0 0 0 0
23.2 1 1 0 0 0 0 0 0
37.4 2 2 2 0 2 0 0 0
54.9 3 3 3 3 3 3 3 0
78.7 4 4 4 4 4 4 4 4
Mid Function IOUT > PHTH4 0 0 0 0 0 0 0 0
Disabled
PTHT4 > IOUT > PHTH3 1 1 0 0 0 0 0 0
PHTH3 > IOUT > PHTH2 2 2 2 0 2 0 0 0
PHTH2 > IOUT > PHTH1 3 3 3 3 3 3 3 0
IOUT < PHTH1 4* 4 4 4 4 4 4 4

NOTES: Power zone 4 is usually DCM, while zones 0 to 3 are CCM.

Table 4. PSI, LPCX, PHTHX CONFIGURATION

PWM Output Status (  = Enabled, X = Disabled)
PWM Output
Power Zone Configuration PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8
0 8 phase        
1  X  X  X  X
2  X X X  X X X
3  X X X X X X X
4  X X X X X X X
0 7 phase        X
1  X    X  X
2  X X  X X  X
3  X X X X X X X
4  X X X X X X X
0 6 phase       X X
2  X  X  X X X
3  X X X X X X X
4  X X X X X X X
0 5 phase      X X X
3  X X X X X X X
4  X X X X X X X
0 4 phase     X X X X
2  X  X X X X X
3  X X X X X X X
4  X X X X X X X

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Table 4. PSI, LPCX, PHTHX CONFIGURATION

PWM Output Status (  = Enabled, X = Disabled)
PWM Output
Power Zone Configuration PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8
0 3 phase    X X X X X
3  X X X X X X X
4  X X X X X X X
0 2 phase   X X X X X X
3  X X X X X X X
4  X X X X X X X
0 1 phase  X X X X X X X
4  X X X X X X X

Power Zone Transition / Phase Shedding zone and allow the transition. When the controller is set to
The power zones supported by the NCP81610 are set by automatic phase shedding, the power zone will be
the resistors connected to the LPCX pins (PSI = Low) or automatically disabled.
PHTHX pins (PSI = Mid). VID Down Operation in Single Phase Mode
When PSI is set to the Mid−state, the NCP81610 employs When VID Down change bit (0x31) is enabled and there
a phase shedding scheme where the power zone is is a fast VID down transition (REFIN down) detected in
automatically adjusted for optimal efficiency by single phase operation power zone (Zone 3 or Zone 4), the
continuously measuring the total output current (voltage at controller will force all phases to turn on for 2 ms to protect
the IOUT pin) and compare it with the PHTHX thresholds. the external power stage against damage from large
When the comparison result indicates that a lower power discharging current and achieve fast and smooth VID down
zone number is required (an increase in the IOUT value), the transition in the meantime.
controller jumps to the required power zone immediately.
A decrease in IOUT that indicates that the controller needs Switching Frequency
to switch into a higher power zone number, the transition A programmable precision oscillator is provided for the
will be executed with a delay of 200 s set by the phase shed switching frequency. The clock oscillator serves as the
delay configuration register. The value of the delay can be master clock to the ramp generator circuit. This oscillator is
adjusted by the user in steps of 10 s if required. programmed by a resistor to ground on the FSW pin. The
To avoid excessive ripple on the output voltage, all power FSW pin provides approximately 2 V out and the source
zone changes are gradual and include all intermediate power current is mirrored into the internal ramp oscillator. The
zones between the current zone and the target zone set by the oscillator frequency is approximately proportional to the
comparison of the output current with the PHTHX current flowing in the resistor. Table 14 lists the switching
thresholds, each transition introducing a programmable frequencies that can be set using discrete resistor values for
200s delay. each phase configuration. Also, the switching frequency
To avoid false changes from one power zone to another information is available in the FSW configuration register
caused by noise or short IOUT transients, the comparison and it can be changed by the user by writing to the FSW
between IOUT and PHTHX threshold uses hysteresis. The configuration register.
switch to a lower power zone is executed if IOUT exceeds Total Current Summing: IMON Sensing Method
the PHTHX threshold values while a transition to a higher The controller sums the phase currents from each current
power zone number is only executed if IOUT is below sense power stage device into a single total current signal
PHTHX−Hysteresis value. The hysteresis value is set to (Figure 8). This signal is then used to generate the output
0x44h and can be changed by the user by writing to the phase voltage droop, total current limit, and the current monitoring
shedding configuration register. If a power zone/PHTHX output. The total current signal is the difference between
threshold is disabled, the controller will skip it during the CSCOMP and CSREF with CSREF connected to an
power zone transition process. external voltage bias as required by the power stage current
When PSI = Low and the user requires to change the sense output.
power zone, the transition to the new power zone is identical The DC gain equation for the current sensing is given by
to the transition process used when PSI is set to the the following equation:
Mid−state. The only exception is when the target power zone CSREF * CSCOMP + Iout @ Aips @ Rcssum
is disabled in automatic phase shedding mode. In this case, (eq. 5)
the controller will automatically enable the target power Where Aips is the current sense gain of the power stage.

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Programming Load Line Iout_max @ Aips @ Rcssum + CSSUM * CSCOMP + CSREF * CSCOMP
The signals CSCOMP and CSREF are differentially (eq. 7)
summed with the output voltage feedback to add precision As an example, if CSREF bias voltage is 1.3 V and the
voltage droop to the output voltage if the load line is enabled. minimum summing amplifier output voltage is set to 0.3 V,
V DROOP + LLTH @ (CSREF * CSCOMP)
(eq. 6)
the Aips x Rcssum has to be chosen to ensure Iout x Aips x
Rcssum = CSREF − CSCOM always less than 1 V in all the
The load line Coefficient LLTH can be configured by I2C normal operating conditions. Since the internal resistor Rcur
register 0x39 to 0% (default), 25%, 50%, 100%. is 100 k, that means a less than 10 A pulling through Rcur
Programming IOUT in the normal operating conditions. For a 2 V maximum
The IOUT pin sources a current in proportion to the total output voltage of IOUT pin, the shunt resistor Riout can be
output current summed up through the current summing calculated by the following equation:
amplifier. The voltage on the IOUT pin is monitored by the 2V
internal A/D converter and should be scaled with an external Riout + + 20 k
10 A @ 10
(eq. 8)
resistor to ground such that a load equal to system max
current generates a 2 V signal on IOUT. A pull−up resistor
to VCC can be used to offset the IOUT signal if needed.

Figure 8. Total Current Summing Amplifier, DRMOS IMON Sensing

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Figure 9. Total Current Summing Amplifier, DCR Sensing Example

Figure 10. Total Current Summing Amplifier, Pseudo DCR Sensing Example

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Total Current Summing: DCR or Pseudo DCR Methods 0x46 and 0x47 determines whether the external resistor
Two current summing methods in Figure 9, 10 are similar, value or internal register value is selected.
they both convert the current signals drop across inductor
DCR or DRMOS IMON current signal across a low value Protections
resistor to low impedance voltage signals and then sums TMON Monitoring
them up with the current summing amplifier. External power stages can send signals with its own
For DCR method, temperature information or other fault information through
CSREF * CSCOMP + Iout @ DCRL @ RcssumńRph TMON pin. The TMON signal proportional to the
(eq. 9)
corresponding power stage temperature usually ranges from
Where Rcssum = Rcs2 + Rcs1 // NTC, and the pole 0 V to 2 V. When the power stage device is over heated or
frequency of CSCOMP filter needs to be selected to be equal under other fault conditions, the signal will be pulled high to
to the zero frequency from the inductor DCRL, or across TMON trigger threshold (0x4A, 2.0 V by default),
Rcssum * C1 = L / DCRL to recover the inductor DCR drop NCP81610 will be able to detect this fault and force the
current signal. system into two different subsequent states based on the
For Pseudo DCR method, TMON configuration register setting: latch up(by default),
CSREF * CSCOMP + Iout @ Aips @ Rsns @ RcssumńRph or timer based hiccup mode. The TMON fault can also be
(eq. 10) masked through register 0x22. Once masked, the controller
Where Aips is the current sense gain of the power stage, will ignore TMON warning from the power stages.
and Aips * Rsns = DCRps is the equivalent DCR. Overcurrent Limiting (OCL) and
The selection of IOUT resistor, and DROOP Undervoltage Protection (UVP)
configuration are similar to the IMON sensing method in The device incorporates a per phase overcurrent limiting
previous sections. (OCL) mechanism to limit per phase current and the energy
Programming the Current Limit ILIM transferred from input to the output to protect against
By default, per phase current limit threshold is damage due to an over current event. The current limit
programmed through an external shunt resistor of the ILIM threshold can be programmed with a shunt resistor on ILIM
pin on the fly. pin, as shown in the Programming the Current Limit ILIM
section.
perphase_CLIM @ DCRps @ 6
RILIM + By default, OCL will always be functional, a large
10 A (eq. 11)
overcurrent event will pull the output below the Under
Where DCRps is the equivalent DCR of the power stage, Voltage Protection threshold (UVP) or 400 mV below
it can be inductor current sensing (DCRL) or DRMOS REFIN to enforce a system latch up. Once latched up, the
IMON sensing (Aips * Rpu) or DRMOS pseudo DCR system will remain disabled until the EN pin is toggled.
sensing (Aips* Rsns). VOCL_min is a threshold level to allow the OCL function
to be temporarily disabled when the output voltage is below
the threshold; by default VOCL_min function is disabled. If
the VOCL_min function is enabled during a current limiting
event, the output will droop to the VOCL_min threshold if
UVP is disabled or VOCL_min is set to above UVP
threshold, OCL function will be disabled for a 2ms period to
allow the system to go back to output voltage regulation. It
is recommended that the system designer be aware of this
over load condition to avoid per phase current exceeding the
inductor saturation current.
VOCL_min threshold can be configured through the I2C
interface with a range of 0.2 V to 1.3 V and a 35 mV step
resolution.
Figure 11. External / Internal ILIM Setting
Latched Mode Over−Current Protection (OCP)
During power on, a 10 A current is sourced from ILIM To prevent catastrophic system failure, NCP81610 is able
pin to generate ILIM voltage, it is sampled and stored into to detect the total output current exceeding the overall
register 0x2D on the fly. As an option, the ILIM threshold current limit and force the chip to latch up. When current
can also be configured through an internal register 0x2E. summing amplifier has its output CSCOMP voltage droop
The external ILIM voltage ranges from 0 V to 2 V. Internal to less than 225 mV (CLIM), the system is considered as
ILIM value controlled by a 5 bit register (0x2E) has a range total current OCP and enter latched mode protection
from 0.2 V to 1.75 V. One ILIM configuration bit in register

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immediately with all the PWMs going to the mid−state, disabled. The output will remain disabled until the EN pin
toggling EN is required to restart the system. is toggled.
Under Voltage Lock−Out (VCC UVLO) VRMP (Line Input) Protection
VCC is constantly monitored for the under voltage A line input voltage monitor is incorporated into the
lockout(UVLO). During power up the VCC pin are controller. During normal operation, if the line voltage is
monitored Only after VCC exceeds its UVLO threshold will below the VRMP under voltage threshold (2.5 V), the
the full circuit be activated and ready for the soft start ramp. system will be latched up. The output will remain disabled
Over Voltage Protection until the EN pin is toggled.
An output voltage monitor is incorporated into the Over Temperature Shutdown (TSD)
controller. During normal operation, if the output voltage is NCP81610 constantly monitors its own junction
500 mV over the REFIN value, the PGOOD pin will be temperature during operation. If its temperature is over
pulled low, the DRON will assert low and the PWM outputs 150°C, an over−temperature fault will be reported. The
are set low. The OVP limit will be clamped at 2 V if OVP is system will either latch up, or enter into a timer based hiccup
mode based on internal register (0x4B) settings.

Table 5. REGISTER MAP

Address R/W Default Value Description Notes:
0x20 R/W 0xFF IOUT_OC_WARN_LIMIT
0x21 R 0x00 STATUS BYTE
0x22 R/W 0x00 FAULT MASK
0x23 R 0x00 STATUS Fault
0x24 R 0x00 STATUS Warning
0x26 R 0x00 READ_IOUT
0x27 R 0x1A MFR_ID
0x28 R 0x10 MFR_MODEL
0x29 R MFR_REVISION
0x2A R/W 0x00 Lock/Reset
0x2B R 0x00 Soft Start status
0x2C N/A 0x00 Soft Start configuration
0x2D R OCL status
0x2E R/W 0x00 OCL configuration
0x2F R Switching frequency status
0x30 R/W 0x00 Switching frequency configuration
0x31 R/W 0x01 VID_DOWN enable
0x32 R PSI status
0x33 R Phase Status
0x34 R/W 0x1F LPC_Zone_enable
0x35 R LPC status
0x36 R/W 0x03 LPC configuration
0x38 R LL status
0x39 R/W 0x03 LL configuration Default: Load disabled
0x3A RW 0x00 PHTH1 configuration
0x3B R PHTH1 status
0x3C R/W 0x00 PHTH2 configuration
0x3D R PHTH2 status

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Table 5. REGISTER MAP (continued)

Address R/W Default Value Description Notes:
0x3E R/W 0x00 PHTH3 configuration
0x3F R PHTH3 status
0x40 R/W 0x00 PHTH4 configuration
0x41 R PHTH4 status
0x44 R/W 0x08 Phase shedding hysteresis
0x45 R/W 0x14 Phase shedding delay
0x46 R/W 0x00 Second function configuration register latch A
0x47 R/W 0x00 Second function configuration register latch B
0x48 R READ_VOUT
0x49 R READ_TMON
0x4A R/W 0x00 TMON_RESPONSE CONFIG
0x4B R/W 0x00 TSD_enable
TSD_fault response
0x4C R/W 0x00 ZCD_CONFIG
0x4D R/W 0x00 ZCD_USER_TRIM
0x4E R/W 0x00 VOCL_min: Threshold to disable OCL
VOCL_min enable
0x4F R/W 0x00 OVP CONFIGURATION
0x50 R/W 0x00 UVP CONFIGURATION
0x51 R/W 0xFF TMON WARNING CONFIGURATION
0x52 R/W 0x00 CLEAR REG
0x53 R/W 0x00 CONFIGURATION AUX

IOUT_OC_WARN_LIMIT Register (0x20)

8 bit register sets the threshold for IOUT voltage output and usually it is to monitor the total current. Once the READ_IOUT
register value exceeds this limit, the IOUT_OC bit will be set in the STATUS BYTE register (0x21) and an ALERT is generated.
Its default value is 0xFF.

STATUS BYTE Register (0x21)

Table 6. STATUS BYTE REGISTER SETTINGS

Bits Name Description
7 TMON This bit gets set whenever TMON is over its set threshold.
6 TSD This bit gets set whenever NCP81610 exceeds its thermal shutdown temperature.
5 VOUT_OV This bit gets set whenever the NCP81610 goes into OVP mode
4 IOUT_OC This bit gets set if READ_IOUT value is over the IOUT_OC_WARN_LIMIT register value
0:3 Reserved N/A

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Fault Mask Register (0x22)

Table 7. FAULT MASK REGISTER SETTINGS (DEFAULT 0X00)

Bits Name Description
7 Reserved
6 VRMP_UV Set to 1 means VRMP(VIN) under voltage will not trigger a latchup event but the fault will be reported in the
fault status register

5 TMON Set to 1 means TMON fault will not trigger a latchup or hiccup event but the fault will be reported in the fault
status register

4 TSD Set to 1 means TSD fault will not trigger a latchup or hiccup event but the fault will be reported in the fault
status register

3 CLIM Set to 1 means CLIM_fault will not trigger a latchup or hiccup event but the fault will be reported in the fault
status register

2 per phase ILIM Set to 1 means OCL per phase per phase current limiting function is disabled.
1 OVP Set to 1 means OVP will not trigger a latchup event but the fault will be reported in the fault status register
0 UVP Set to 1 means UVP will not trigger a latchup event but the fault will be reported in the fault status register

STATUS Fault Register (0x23)

Table 8. STATUS FAULT REGISTER SETTINGS

Bits Name Description
7 Reserved
6 VRMP_UV_fault VRMP (VIN) under voltage
5 TMON_fault TMON over threshold
4 TSD_fault NCP81610 over temperature
3 CLIM_fault CLIM fault
2 Per phase_ILIM_fault Per phase current limiting (of any phase)
1 OVP_fault Overvoltage fault
0 UVP_fault Undervoltage fault

STATUS Warning Register (0x24)

Table 9. STATUS WARNING REGISTER SETTINGS

Bits Name Description
7:1 Reserved N/A
0 IOUT Overcurrent Warning This bit sets if IOUT is over the warning value set by 0x20

READ_IOUT Register (0x26)

Read back output current. ADC conversion 0xff = 2 V on IOUT pin which should equate to max current.

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Lock/Reset Register (0x2A)

Table 10. LOCK/RESET REGISTER SETTINGS

Bits Name Description
7:2 Reserved N/A
1 Software reset Reserved
0 Lock Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become read−
only and cannot be modified until the NCP81610 is powered down and powered up again. This prevents
rogue programs such as viruses from modifying critical system limit settings (Lockable).

Soft Start Status and Configuration Register (0x2B, 0x2C)

These registers contain the values that set the slew rate of the output voltage during power−up. When power on, the controller
reads the value of the resistor connected to the PWM8/SS pin and sets the slew rate. The codes corresponding to each resistor
setting are shown in Table 11. The soft start timer can be configured through 0x2C with 4bit resolution. One bit in control
registers 0x46, 0x47 needs to be set to select internal soft start settings.

Table 11. SOFT START STATUS AND CONFIGURATION REGISTER SETTINGS

tRAMP Resistor (kW) Bits Name Value tRAMP (ms), REFIN = 1 V tRAMP (ms), REFIN = 0.8 V
− 7:4 Reserved N/A N/A N/A
10 3:0 T_Ramp 0000 0.15 0.12
14.7 0001 0.3 0.24
20 0010 0.45 0.36
26.1 0011 0.6 0.48
33.2 0100 0.75 0.6
41.2 0101 0.9 0.72
49.9 0110 1 0.8
60.4 0111 2 1.6
71.5 1000 3 2.4
84.5 1001 4 3.2
100 1010 5 4
118.3 1011 6 4.8
136.6 1100 7 5.6
157.7 1101 8 6.4
182.1 1110 9 7.2
249 1111 10 8

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OCL_ILIM Status Register and Configuration Register (0x2D, 0x2E)

These registers contain per phase current limit (OCL_ILIM) status and configuration information. By default, a 10 A
constant current will be sourced to the external ILIM resistor and read back the OCL_ILIM threshold level on the fly.
OCL_ILIM threshold can also be dynamically configured by 0x2E register with 5bit resolution. One bit in registers 0x46, 0x47
needs to be set to select internal OCL setting shown in Table 13. When one phase is in OCL mode, the corresponding register
bit will be set in 0x2D.

Table 12. OCL_ILIM STATUS REGISTER SETTINGS (0X2D)

Bits Name Description
7:0 Per phase OCL Bit 7: Phase 8 current limit triggered.
.
.
.
Bit 0: Phase 1 current limit triggered.

Table 13. OCL_ILIM CONFIGURATION REGISTER SETTINGS (0X2E)

Bits Name Description
7:5 Reserved N/A
4:0 Per phase OCL configuration Configure the threshold for per phase current limit.
0x00: 0.2 V
0x01: 0.25 V
…
0x1F: 1.75 V

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Switching Frequency Status and Configuration Registers (0x2F, 0x30)

These registers contain the values that set the switching frequency of the controller When power on, the controller reads the
value of the resistor connected to the FSW pin and sets the switching frequency according to Table 14.The codes corresponding
to each setting are also shown in Table 14.
The switching frequency configuration register allows the user to dynamically change the switching frequency through the
I2C interface provided that the FSW bits from the second function configuration registers A and B (0x46, 0x47) are set.

Table 14. SWITCHING FREQUENCY STATUS AND CONFIGURATION REGISTER SETTINGS

Value Switching Frequency (kHz)
FSW Pin
Resistor Status Configuration 8 7 6 5 4 3 2 1
Value (kW) Bits Register Register Phase Phase Phase Phase Phase Phase Phase Phase

7:5 Reserved Reserved N/A N/A N/A N/A N/A N/A N/A N/A
10 4:0 00000 00000 221 253 295 355 221 293 223 232
(default)
− 00001 244 276 330 399 244 329 243 252
14.7 00010 00010 266 309 355 425 266 358 264 272
− 00011 293 327 387 460 293 381 294 297
20 00100 00100 307 351 412 501 307 407 317 322
− 00101 333 384 441 542 333 450 335 340
26.1 00110 00110 351 409 480 561 351 480 352 361
− 00111 373 431 499 615 373 510 380 385
33.2 01000 01000 394 451 528 639 394 530 399 413
− 01001 421 481 559 676 421 562 420 435
41.2 01010 01010 449 495 593 725 449 600 436 456
− 01011 469 525 612 746 469 614 454 478
49.9 01100 01100 479 563 639 757 479 631 483 500
− 01101 509 570 681 799 509 663 508 509
60.4 01110 01110 518 588 697 831 518 688 526 518
− 01111 543 617 722 874 543 722 543 540
71.5 10000 10000 581 665 779 930 581 789 583 578
− 10001 649 718 881 1043 649 859 656 638
84.5 10010 10010 708 790 937 1129 708 930 698 698
− 10011 751 868 1010 1211 751 1010 771 758
100 10100 10100 799 918 1073 1278 799 1095 807 818
− 10101 866 1003 1136 1372 866 1147 860 878
118.3 10110 10110 919 1025 1220 1449 919 1233 899 938
− 10111 964 1111 1297 1533 964 1260 950 972
136.6 11000 11000 993 1140 1339 6716 993 1341 1003 1014
− 11001 1059 1198 1438 1687 1059 1372 1052 1067
157.7 11010 11010 1098 1262 1485 1734 1098 1450 1096 1106
− 11011 1141 1295 1533 1821 1141 1539 1154 1155
182.1 11100 11100 1200 1338 1587 7530 1200 1619 1205 1201
− 11101 1236 1405 1608 1954 1236 1618 1227 1245
249 11110 11110 1291 1459 1707 2012 1291 1674 1274 1280
− 11111 1312 1493 1724 2096 1312 1724 1316 1330

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 NCP81610

VID DOWN Enable Register (0x31)

One control bit to enable or disable VID DOWN phase operation change during DCM mode.

Table 15. STATUS BYTE REGISTER SETTINGS

Bits Name Description
7:1 Reserved N/A
0 VID DOWN enable 0: VID DOWN change disabled
1 (default): VID DOWN change enabled

PSI Status Register (0x32)

The PSI status register provides the information regarding the current status of the PSI pin though the I2C interface as shown
in Table 16.

Table 16. PSI STATUS REGISTER SETTINGS

Bits Name Description
7:2 Reserved N/A
1:0 PSI input level 00 = PSI MID (Auto PSI)
01 = PSI LOW
10 = PSI HIGH

Phase Status Register (0x33)

The Phase Status register provides the information about the status of each of the eight available phases as shown in Table17.

Table 17. PHASE STATUS REGISTER SETTINGS

Bits Name Description
7 Phase 8 0 = Disabled
1 = Enabled
6 Phase 7 0 = Disabled
1 = Enabled
5 Phase 6 0 = Disabled
1 = Enabled
4 Phase 5 0 = Disabled
1 = Enabled
3 Phase 4 0 = Disabled
1 = Enabled
2 Phase 3 0 = Disabled
1 = Enabled
1 Phase 2 0 = Disabled
1 = Enabled
0 Phase 1 0 = Disabled
1 = Enabled

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 NCP81610

LPC_Zone_Enable Register (0x34)

The LPC_Zone_enable register allows the user to enable or disable power zones while the controller has the PSI set low using
the I2C interface as shown in Table 18.

Table 18. LPC_ZONE_ENABLE REGISTER SETTINGS

Bits Name Description
7:5 Reserved N/A
4 Zone 5 0 = Disabled
1(default) = Enabled
3 Zone 4 0 = Disabled
1(default) = Enabled
2 Zone 3 0 = Disabled
1(default) = Enabled
1 Zone 2 0 = Disabled
1(default) = Enabled
0 Zone 1 0 = Disabled
1(default) = Enabled

LPC Status and Configuration Registers (0x35, 0x36)

These registers contain the values that set the operating power zone when the PSI pin is set low. When power on, the controller
reads the value of the resistor connected to the PWM6/LPC1 and PWM5/LPC2 pins and sets the power zone according to
Table 3. The codes corresponding to each setting are shown in Table 19.
The LPC configuration register allows the user to dynamically change the power zone (PSI = low) through the I2C interface
provided that the LPC bits from the second function configuration registers A and B (0x46, 0x47) are set. The achievable power
zone settings are listed in Table 19.

Table 19. LPC STATUS AND CONFIGURATION REGISTER SETTINGS

Bits Name Value Level
7:6 Reserved N/A N/A
5:3 LPC1 configuration 000 (default) 0
001 1
010 2
011 3
100 4
101 = Reserved N/A
111 = Reserved N/A
2:0 LPC2 configuration 000 (default) 0
001 1
010 2
011 3
100* 3
101 = Reserved N/A
110 = Reserved N/A
111 = Reserved N/A

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 NCP81610

Load Line Configuration Registers (0x39)

This register contains the value that set the fraction of the externally configured load line (LL) to be used during the normal
operation of the device. The codes corresponding to each setting are shown in Table 20. The LL configuration register allows
the user to dynamically change the load line settings through the I2C. By default, the load line is disabled.

Table 20. LL STATUS AND CONFIGURATION REGISTERS SETTINGS

Bits Description
7:2 Reserved
1:0 00 = 100% of externally set load line
01 = 50% of externally set load line
10 = 25% of externally set load line
11 (default) = 0% of externally set load line

PHTH1 to PHTH4 Configuration Registers (0x3A, 0x3C, 0x3E, 0x40)

These 8 bit registers contain the values that control the phase shedding thresholds and are active when the PHTHX bits from
the second function configuration registers A and B (0x46 and 0x47) are set. These thresholds allow the user to dynamically
change the thresholds through the I2C interface. The values written to these registers should match the value of the
READ_IOUT register (0x26) at the desired load current. If 0xFF is written to a register, the phase shedding threshold
corresponding to that register is disabled.
PHTH1 to PHTH4 Status Registers (0x3B, 0x3D, 0x3F, 0x41)
These 8 bit registers contain the phase shedding threshold values set by the resistors connected to the PHTHX pins. The values
of the thresholds are updated during the power on period. The resistor values should be chosen to ensure that the voltage drop
across them developed by the 10 A current sourced by the NCP81610 during power−up (EN set high) matches the value of
the READ_IOUT register (0x26) at the desired load current. Setting the resistors to generate a voltage above 2 V will disable
the PHTHX threshold for that pin.
Phase Shedding Hysteresis Register (0x44)
This register sets the hysteresis during a transition from a high count phase to a low count phase configuration. The hysteresis
is expressed in codes (LSBs) of the PHTHX threshold values.
Phase Shedding Delay Register (0x45)
This register sets the delay during a transition from a high count phase to a low count phase configuration. The power−up
default value is 200 s (14H) and it can be dynamically changed in steps of 30 μs (1 LSB) through the I2C interface.

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 NCP81610

Second Function Configuration Register Latch A and B Registers (0x46, 0x47)

These registers allow the user to select whether the second functions settings (FSW, Soft Start, OCL, LPC and PHTHX) are
controlled by the external resistors or the configuration registers (see Table 21). When power on and enabled (cold start), the
default control mode for the functions is the external resistor. Switching between the two modes can be done by simply writing
the appropriate byte (the same byte) to both registers (the order doesn’t matter).

Table 21. SECOND CONFIGURATION LATCH REGISTER A AND B

Bits Second Function Configuration Register Description
7:6 Reserved N/A
5 FSW 0 (default) = switching frequency set by external resistor
1 (default) = switching frequency set by register 0x30
4 Reserve Reserve
3 Soft Start Timer 0 (default) = soft start timer set by external resistor
1 (default) = soft start timer set by register 0x2C
2 OCL_ILIM 0 (default) = per phase current limit set by external resistor
1 = per phase current limit set by register 0x2E
1 LPC1,LPC2 0 (default) = low power zone set by external resistor
1 = low power zone set by register 0x36
0 PHTHX 0 (default) = set by external resistors connected between PHTHX pins and GND
1 = set by registers 0x3A, 0x3C, 0x3E and 0x40

VMON Register (0x48)

8 bit regsister to monitor VSP − VSN differential voltage value (Max FFH, 2 V).
TMON External Power Stage Thermal Monitoring Register (0x49)
8 bit register to monitor external power stage thermal temperature (Max FFH, 2 V).
TMON Fault Response Configuration Register (0x4A)

Table 22. TMON CONFIGURATION THRESHOLD

Bits Name Description

7:1 Reserved N/A

0 TMON fault response 0 (default): Latch response
1: Hiccup mode

TSD Fault Threshold / Response Configuration Register (0x4B)

Table 23. TSD CONFIGURATION THRESHOLD

Bits Name Description
7:2 Reserved N/A
1 TSD enable 0 (default): TSD disabled
1: TSD enabled
0 TSD fault response 0 (default): Latch response
1: Hiccup mode

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 NCP81610

ZCD Configuration Register (0x4C)

Table 24. ZCD CONFIGURATION REGISTER

Bits Name Description
7:3 Reserved N/A
2 ZCD PWM level configuration 0 (default): PWM = H/L
1: PWM = H/M, PWM can go to Mid state

1 ZCD reset Default 0: reset ZCD threshold

0 ZCD disable 0 (default): ZCD enabled
1: ZCD disabled

ZCD User Trim Register (0x4D)

Allow user to set their own ZCD threshold values.

Table 25. ZCD USER TRIM REGISTER

Bits Name Description
7:6 Reserved N/A
5:0 Trim ZCD threshold 0x111111: +18.6 mV
0x100000: +0.6 mV
0x000000 (Default): 0 mV
0x000001: −0.6 mV
0x011111: −18.6 mV

VOCL_Min Configuration Register (0x4E)

VOUT per phase OCL disable threshold values relative to DIFFOUT. VOCL_min function can be disabled by bit 0.

Table 26. VOCL_MIN CONFIGURATION REGISTER

Bits Name Description

5:1 VOCL_min threshold 5 bit, with 35 mV resolution

00000 (default): 0.215 V
00001: 0.250 V
…
11111: 1.3 V
0 VOCL_min enable 0 (default): VOCL_min disabled
1: VOCL_min enable

OVP Configuration Register (0x4F)

OVP can be changed by this register with 50 mV resolution.

Table 27. OVP_CONFIGURATION REGISTER

Bits Name Description
7:3 Reserved
2:0 OVPth 000 (default): typ: 600 mV, min: 500 mV
001: +50 mV
010: +100 mV
011: +150 mV
100: OVP Clamped to 2.0 V
101: −50 mV
110: −100 mV
111: −150 mV

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 NCP81610

UVP Configuration Register (0x50)

UVP configuration can be changed by this register with 50 mV resolution.

Table 28. UVP_THRESHOLD REGISTER

Bits Name Description
7:3 Reserved
2:0 UVPth 000 (default): max: −400 mV; typ: −500 mV
001: −50 mV
010: −100 mV
011: −150 mV
100: UVP disabled
101: +50 mV
110: +100 mV
111: +150 mV

TMON Warning Threshold Register (0x51)

TMON warning threshold is usually less than TMON fault threshold.

Table 29. TMON WARNING THRESHOLD REGISTER

Bits Name Description

7:0 TMON WARNING threshold Default 0xFF or 2.0 V,

0x00: 0 V
0x01: 0.008 V
…
0x0F: 2.040 V

Clear_Reg Register (0x52)

Clear_reg register is used to reset the OCP_ILIM status register by transition from “0” to “1”.

Table 30. CLEAR_REG REGISTER

Bits Name Description
7:1 Reserved N/A
0 Clear_Reg Bit 0 Transition from 0 to 1 cause the reset of OCP_ILIM status register (0x2D). Please notice
that this register remain writable even the lock bit has been set.

Auxiliary Configuration Register (0x53)

Table 31. AUXILIARY CONFIGURATION REGISTER

Bits Name Description
7:4 Reserved N/A
3 SONIC_TMR_EN 0 (default): Ultrasonic timer disabled
1: Ultrasonic timer enabled

2 I2C_or_fuse_sel 0 (default): select fuse settings

1: select I2C settings

1 CLIM_sel 0 (default): CSCOMP <0.225 V trigger CLIM

1: CSREFE − CSCOMP >1.0 V trigger CLIM

0 TBD TBD

ON Semiconductor is licensed by the Philips Corporation to carry the I2C bus protocol.

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29
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

QFN40 5x5, 0.4P

CASE 485CR
ISSUE C
1 40 DATE 27 AUG 2013
SCALE 2:1
D A L2 NOTES:
1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994.

ÉÉÉ
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED

ÉÉÉ
PIN ONE TERMINAL AND IS MEASURED BETWEEN
LOCATION L2 0.15 AND 0.30mm FROM THE TERMINAL TIP.

ÉÉÉ
4. COPLANARITY APPLIES TO THE EXPOSED
DETAIL A PAD AS WELL AS THE TERMINALS.
E MILLIMETERS
L L DIM MIN MAX
A 0.80 1.00
0.15 C A1 −−− 0.05
A3 0.20 REF
L1 b 0.15 0.25
0.15 C TOP VIEW D 5.00 BSC
DETAIL A D2 3.40 3.60
ALTERNATE TERMINAL E 5.00 BSC
DETAIL B (A3) CONSTRUCTIONS E2 3.40 3.60

ÉÉ
0.10 C e 0.40 BSC
L 0.30 0.50
A L1 −−− 0.15

ÉÉ
EXPOSED Cu MOLD CMPD
L2 0.12 REF
0.08 C A1
SEATING
NOTE 4 SIDE VIEW C PLANE GENERIC
MARKING DIAGRAM*
DETAIL B
0.10 M C A B ALTERNATE
1
CONSTRUCTION
DETAIL A D2 XXXXXXXX
11
XXXXXXXX
21 0.10 M C A B AWLYYWWG
G
E2
XXXXX = Specific Device Code
1
A = Assembly Location
40
40X b WL = Wafer Lot
40X L e YY = Year
0.10 M C A B
e/2 WW = Work Week
0.05 M C NOTE 3
G = Pb−Free Package
BOTTOM VIEW
(Note: Microdot may be in either location)
RECOMMENDED
SOLDERING FOOTPRINT *This information is generic. Please refer
to device data sheet for actual part
5.30 marking.
40X Pb−Free indicator, “G” or microdot “ G”,
3.64 0.63 may or may not be present.

3.64 5.30

PKG 40X
OUTLINE 0.40 0.25
PITCH
DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON83971E Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: QFN40, 5x5, 0.4P PAGE 1 OF 1

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