SYSTEM VERILOG

SHORT NOTES

Bala Murali Krishna Baisani

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Int - 2 state 32 bit signed.
Integer - 4 state 32 bit signed.
Bit - 2 state unsigned.
Byte - 2 state 8 bit signed.
Logic - 4 state unsigned.
Reg - 4 state unsigned.

Type def
Enum - A set of integral named constants is called an enumerated type. It defines a set of named values having
an anonymous int type.

Arrays:

Packed arrays:
Ex:
reg [5:0] array; // [5:0] is packed dimension or vector width.
bit [2:0][3:0] array;

Unpacked arrays:
Ex:
reg arr [3:0]; // [3:0] is unpacked dimension.
int array [2:0][3:0];

Associative array:
Ex:
data_type array_name [ index_type ];
bit[7:0] assoc_array [int];

Advantages of associative array over dynamic array:

1) In a dynamic array, we need to allocate memory before using it. But in an associative array, memory can be
allocated when it is used.
2) A dynamic array is specific for a particular data type. When it comes to an associative array, elements of an array
can be of any type. We can store the concatenation of various data types or class structures as well.

Queue:
There were 2 types of queues.
1) Bounded queue - Queue having a specific size or a limited number of entries.
2) Un bounded queue - Queue having non-specific queue size or unlimited entries.

Ex:
bit q_1[$]; // Unbounded queue of bit
byte q_2[$]; // Unbounded queue of byte
int q_3 [$:9]; // Bounded queue with qsize = 10

int q_4[$] = {5,6,7};

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if – else if :

if there is no else statement in if – elseif loop it will give run time error/warning.
So we can use unique0 if to overcome this problem.

Unique0 if: System Verilog allows us to use a ‘unique’ keyword before ‘if’ statement. Following
error/warnings are expected:
1) None of ‘if’ conditions are true or there is no ‘else’ statement.
2) More than one ‘if’ or ‘else if’ conditions are true.

While loop:
Syntax:
while(<condition>) begin
...
end

do while loop:
Syntax:
do begin
...
end
while(<condition>);

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forever and always loops :
forever loop can used in procedural block and in class as well, but always cannot be used in procedural block and in
class.

Correct way of using always block It will throw error as always block is in initial – begin block
Same way it will throw error if we use in class as well

for loop:
Syntax:
for (<initialization>; <condition>; <update>) begin
...
end

forever loop:
Syntax:
foreach (variable[iterator]) begin
...
end

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repeat loop:
Syntax:
repeat(<number>) begin // <number> can be variable or fixed value
...
end

Static and Automatic function:

1. By default, functions declared are static except they are declared inside a class scope. If the function is
declared within class scope, they behave as an automatic function by default unless they are specifically
mentioned as static functions. We will discuss more on this concept in class (OOP) concepts.
2. All variables declared in a static function are static variables unless they are specifically mentioned as an
automatic variable.
3. All variables declared in an automatic function are automatic variables unless they are specifically mentioned
as a static variable.

Class :

Static properties in class :

In the below example, we will have two variables “static int s_id” (static variable) and “int id” (non-static variable).
There are 5 instances of a class that has been created and both variables are incremented by 1 in the constructor method of a
class. The intention is to have a unique id for each class instance.

Inheritence :
An Inheritance is the concept of OOP which allows users to create an extended class from the existing class.
The “extends” keyword is used to inherit the child class from its base class.
1. Child class has access to class properties and class methods of its base class. Thus, inheritance grants re-
usability.
2. Along with existing class properties and methods, a derived class can also add new properties and methods
based on the requirement.
3. A child class can modify its base class properties and methods without disturbing the base class.
4. Multilevel inheritance is also possible in SystemVerilog. A derived class can also further extended, this is
multilevel inheritance.

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Virtual function and task : ()
When a child class handle is assigned to its base class. On calling a method using a base class handle, the base class
method will be executed. On declaring a method as a virtual method, a base class handle can call the method of its child class.
With virtual without virtual

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Abstract class :
An abstract class is a special type of base class that is not intended to be instantiated and a set of derived classes can be
created.
1. An abstract class is an incomplete class that may contain method implementation or may contain only the
prototype of methods without actual implementation (known as pure virtual methods). It can not be
instantiated and it can only be derived.
2. The virtual keyword is used in front of the class to differentiate it from the normal class.
3. An abstract class is also known as a virtual class.
4. Method type, number of arguments, and return type (if required) should be the same for the virtual methods
in their derived classes.
5. It is not mandatory to add methods in the abstract class.

Polymorphism:
A base class handle can invoke methods of its child class which has the same name. Hence, an object can take many
forms.
1. As we know, the derived class object can override methods of its base class. Similarly, the base class
object can also override the method of one of the child classes. It means a base class method has
different forms based on derived class implementation.
2. To use many forms of the method, the virtual keyword must be used in the method definition.

In the below example, child_A, child_B, and child_C are derived from the parent class. All child class handles are
assigned to the parent class handle. Using the polymorphism concept, the parent class handle can invoke child class
methods as shown in example.

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Scope resolution operator :
The scope resolution operator provides:
1. Access to static members (methods and class properties), enumerations, type declaration from
outside the class hierarchy.
2. The derived classes can access public or protected class members of their base class.
3. Access to type declarations and enumeration named constants declared inside the class from outside
the class hierarchy or from within derived classes.

Local access qualifier:

If a class member is declared as a local, they will be available to that class alone. The child classes will not
have access to a local class member of their parent class.

Protected access qualifier:

As discussed earlier, local access qualifiers cannot be accessed outside of the class scope. But sometimes it is
required to provide class member access to derived classes. This access is provided by a protected access qualifier.
A protected class member cannot be accessed outside class scope except access by their child classes.

Constants :
1. Global constants
2. Instance constants

1. Global constants :
During variable declaration, an initial value is assigned, such class properties known as global constants.
The value of a variable cannot be changed after the declaration of the variable.

2. Instance constants :
During variable declaration, an initial value is not assigned, such class properties are known as instance
constants. An instance constant allows a user to assign value in run time only once in the class constructor.

Typedef class in sv :
In certain cases, the class handle of another class is required even if it is not declared yet. In such cases,
SystemVerilog provides a forward declaration of the class using the typedef keyword.
typedef Class in SV - VLSI Verify

will give error won’t give error

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Randomization :

rand keyword : On randomizing an object, the rand keyword provides uniformly distributed random values.

randc keyword : On randomizing an object, the randc keyword provides random value without repeating the same
value unless a complete range is covered.

Inside keyword :
The inside keyword is helpful when randomized values have to be in the provided range.

If else in constraint:

EX 1 :-

EX 2 :-

Conditional operator in constraint :

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Implication operator in constraint :

EX 1 :-

dist key word in constraint :

There are two ways to provide weightage for values.
1. Using :/ operator
2. Using := operator

:/ operator :
1. If single value weightage will be assigned to particular.
2. If range of value weightage will be divided equally divided and assigned to all .

:= operator :
1. If single value weightage will be assigned to particular.
2. If range of value, same weightage will be assigned to all .

Inheritance in constraint :
Constraint in the parent class can be overridden in the child class, to do the same child class should have same
nomenclature

Function in constraint :

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 Sometime constraint value has to be decided using some mathematical equations, instead of writing whole
equation in constraint we can use functi

Disable randomization :
Randomization can be disabled using rand_mode(0) .

To disable randomization

To enable randomization

To disable randomization of value 2

Disabling constraint :
Like disabling randomization, we can disable particular constraint by using
<constraint_name>.conastraint_mode(0)
EX :

Static Constraint :

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 Static constraints - VLSI Verify

Unique constraint :
A unique constraint is useful to generate unique values for variables and elements in an array.

randcase :
Randcase is a case statement that randomly selects one of its branch statements based on the probability of each
statement.

Interprocess communication in sv :
There are 3 mechanisms in sv for interprocess comm.
1) Events
2) Semaphores
3) Mailbox

Events :
-> -- Used to trigger instantaneously and unblocks waiting process.
->> -- Same as -> but it was non-blocking.
@ -- This operator blocks process till event is triggered, will unblock the process even if triggering
happens previously as well
wait -- This construct is like @ but it will unlock process if trigger happen at same time of execution of wait
statement

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wait_order in sv :
wait_order construct helpful when events to be executed in order if not it will trigger run time error or display
message.

Merging event in sv :
An event can be assigned to other event so that if one event trigger other event can also be un blocked, for this we
need to assigned one event to other.

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Semaphores in sv :
Tis provide controlled access to the shared resources.

new() -- to create semaphore

get() -- To obtain semaphore
put() -- To return the number of keys
try_get () -- same as get bus non-blocking

Ex :

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Mailbox in sv :
Mailbox is a way of comm. Between the different process, one can put data into mailbox and other can retrieve
data, it behaves as FIFO.
Types of mailboxes :
1) Generic mailbox
2) Parameterized mailbox
Depends on size
1) Bounded mailbox -- If size is defined then its bounded mailbox, once mailbox is full, we can’t put more data in
2) Unbounded mailbox -- if size is not defined then its unbounded mailbox,

Generic mailbox :
Any type of data can be put and get in generic mailbox.

Syntax :
mailbox <mailbox_name>

Parameterized mailbox :
Particular data type can be put and get which it was parameterized with in parameterized mailbox.

Syntax :
mailbox #(<type>) <mailbox_name>

Mailbox methods :

Method name Description

function new(int bound = 0) Returns mailbox handle. An argument represents bounded mailbox size otherwise,
it is an unbounded mailbox
task put(<data>) Blocking method that stores data in the mailbox.
function int try_put(<data>) The non-blocking method that stores data if it is not full and returns 1 else 0.
task get(ref <data>) Blocking method to retrieve data from the mailbox
function int try_get(ref <data>) The non-blocking method returns data if a mailbox is non-empty, else returns 0.
task peek(ref <data>) Copies data from the mailbox without removing it from a mailbox
function int try_peek(ref <data>) Tries to copy data from the mailbox without removing it from a mailbox
function int num() Returns number of entries in the mailbox

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SV interface :
System Verilog provides an interface construct that simply contains a bundle of sets of signals. This encapsulates
signals and communicates with design, testbench components.

Basic interface :

Parameterized interface :

Q) Why is the logic data type used for signal other than bit data type ?

A) A bit data type is a 2-state data type that can have either 0 or 1 value. For incorrect RTL behavior like X or Z
testbench would have sampled as 0. So, it needs a 4-state data type that can capture all 4 states 0, 1, X, or Z.

Modport in SV :
Within an interface to declare port directions for signals modport is used. The modport also put some restrictions
on interface access. Modport put access restriction by specifying port directions that avoid driving of the same signal by
design and testbench.
Syntax :

modport <name> ( input <port_list>, output <port_list>);

Example :
modport TB (output a,b, en, input out, ack);
modport RTL (input clk, reset, a,b, en, output out, ack);

Clocking block in SV :
To specify synchronization scheme and timing requirements for an interface, a clocking block is used.
Syntax :
clocking <clocking_name> (<clocking event>);
Default input <delay> output <delay>;
<signals>
endclocking

Advantages of clocking block :

1. It provides a group of signals that are synchronous with a particular clock in DUT and testbench
2. Provides a facility to specify timing requirements between clock and signals.

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Clocking Skew :
The input or output clocking block signals can be sampled before or after some time unit delay known as clocking
skew. It is declared as
Example :
default input #2 output #3;

For the above example : input clock skew is #2

Output clock skew is #3

Which means input signal is sampled #2-time units before clocking event and output is sampled #3-time units after
clocking event.
By default, input and output skew are 0-time units, if time units are not specified by default skews will be considered
based ion the time scale in current scope.

Virtual interface :
Interface and DUT will be static in nature. Hence, they can’t be used dynamically. In test bench randomized class objects
are used and connected to design dynamically, to bridge the gap between these two objects we are using virtual
interface, virtual interface is used as a pointer or handle for an actual interface.

System Verilog regions :

Program block :
All elements in program block are scheduled to excecute in reactive region, this helps to avoid race around condition
between testbench and design.

How will program block avoid race around condition ?

As per system Verilog scheduling semantics events will follow active region -> non-blocking region -> reactive region
The non-blocking assignments are evaluated in active region and will get updated in NBA region, when design module
assign some value to variable in initial block, tb modules tries to access variable and perform action in active region, so
there will chances of race around condition as the chances of action completion in design will there in NBA region.

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Race around condition example :
Design code :

module dut_example (output bit [3:0] out);

initial begin
out <= 2;
end
endmodule

In the active region of a time slot, the RHS value of non-blocking assignment out (<= 2;) is evaluated, LHS value is not yet
updated. At the same time, testbench tries to access the variable that has an older value (default value in this case).
Thus, the testbench operation will be affected.
Tb code :

module tb_mod_top;
wire [3:0] out;

dut_example DUT(out);
initial begin
if(out == 2)
$display("Design assigned out is 2");
else
$display("Design assigned out = %0d", out);
end
endmodule

Output :
Design assigned out = 0

Race around condition solving using program block :

Tb code :
program tb_pro(input [3:0] out);
initial begin
if(out == 2)
$display("Design assigned out is 2");
else
$display("Design assigned out = %0d", out);
end
endprogram

module tb_mod_top;
wire [3:0] out;

dut_example DUT(out);
tb_pro tb(out);
endmodule

Output :
Design assigned out is 2

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System Verilog casting :
Casting is the process of converting from one data type to other for compatibility.
In System Verilog, a data type is essential to mention while declaring a variable and it can hold values of the same data
type.
For example, the int data type cannot hold real data type values. If we try doing so, it will lead to a compilation error.
Casting helps to resolve this problem.
Casting is of two types :
1) Static casting
2) Dynamic casting

Static casting :
Static casting will be only applicable to fixed type of data.

Syntax :
<data_type>'(value or variable or expression)
Example :
module casting_example;
string name;
int num[3];
real r_num;
initial begin
name = "A";
r_num = 2.8;

num[0] = int'(name); //Takes ascii value for string

num[1] = int'(r_num);

r_num = 2.125 + real'({4'h1, 4'hA}); // 'h1A = 'd26

num[2] = int'((num[0] == 65)?r_num: 4.7);

$display("casting from string to int: num[0] = %0d", num[0]);

$display("casting from real to int: num[1] = %0d", num[1]);
$display("casting from int to real: r_num = %0f", r_num);
$display("casting an expression from real to int: num[2] = %0d", num[2]);
end
endmodule

Output :
casting from string to int: num[0] = 65
casting from real to int: num[1] = 3
casting from int to real: r_num = 28.125000
casting an expression from real to int: num[2] = 28

Dynamic casting:
Dynamic casting is used to cast the assigned values to the variables that might not be ordinarily valid. $cast can be
either function or task.
If $cast is a task and if it fails, it will give runtime error, ir $cast used as a function returns 1 for legal casting and returns
0 for illegal casting and destination will remain same.

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Syntax :
function int $cast(destination, source);
task $cast(destination, source);

In both case $cast will assign source value to destination variable, if dynamic casting fails destination will remain
unchanged in both.
$cast as a task :

module dynamic_cast_example;
typedef enum {DIODE=10, BJT=100, MOSFET=250, FINFET=300}
devices;
initial begin
devices dev;

$cast(dev, 250 + 50);

$display("A: Device used = %s",dev.name());

$cast(dev, 250 + 20);

$display("B: Device used = %s",dev.name());
end
endmodule
Output
A: Device used = FINFET
$cast(dev, 250 + 20);
|
*E,INVCST (./testbench.sv,9|8): Invalid cast: the source expression can not be cast to the type of the destination
variable.

$cast as a function :
The first $cast is a valid assignment, and the second $cast has an invalid assignment. Notice that, simulation is not
terminated with run time error.

module dynamic_cast_example;
typedef enum {DIODE=10, BJT=100, MOSFET=250, FINFET=300} devices;
initial begin
devices dev;

if($cast(dev, 250 + 50))

$display("A: Device used = %s",dev.name());
else
$display("A: Dynamic casting failed");

if($cast(dev, 250 + 20))

$display("B: Device used = %s",dev.name());
else
$display("B: Dynamic casting failed");
end
endmodule

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Output :

A: Device used = FINFET

B: Dynamic casting failed

Package :
System Verilog package provides a systemic mechanism for sharing parameters, functions, data, types, property to
other interfaces, programs, or modules that can be declared within a package.

 The package can be made accessible within the interface, programs, modules, and other packages using an import
keyword followed by scope resolution operator :: and what has to import. An import mechanism provides
controlled access based on what is imported

Example :
package pkg;
class transaction;
int data = 5;

function void display();

$display("data = %0d", data);
endfunction
endclass

function pkg_funct();
$display("Inside pkg_funct");
endfunction
endpackage

Here as whole package in imported we can use all functions and variables can be used
import pkg::*;
module package_example;
initial begin
transaction tr = new();
tr.display();
pkg_funct();
end
endmodule

Here as only class transaction is imported, we can’t use pkg_funct() function

import pkg::transaction;
module package_example;
initial begin
transaction tr = new();
tr.display();
//pkg_funct(); // Not accessible
end
endmodule

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Compiler directives :
The compiler directives tell the compiler how it should process its input, some of compiler directives were :
1) `define
2) `include

`define macro :
The System Verilog macro is a compiler directive that substitutes itself in the code with a defined context.
1) Macro uses global space. It can be defined outside or inside of a module, class, program, etc with proper
compilation order.
2) Multi-line macro context is also possible using \. But make sure after \, everything should be empty. Even a
single space is also not accepted.
3) “ is used to delimit lexical tokens without adding any white space for macro argument.
4) `” overrides the lexical meaning of “. The macro argument allows string literals to be constructed using `”.
5) `\ is used to include an escape sequence. For example: `\t will include \t. `\`” will include “

Example :

`define display_string(name, str) \

`"Hello `\t `\`"name`\`", This is System``str Tutorial.`"

// `" --> overrides the lexical meaning of ".

// `\t --> \t
// `\`" --> "
// `` --> delimits lexical tokens without adding any white space

module define_example;
initial begin
$display("%s",`display_string(Alex, Verilog));
$display("%s",`display_string(Robin, C));
end
endmodule

Output :
Hello "Alex", This is SystemVerilog Tutorial.
Hello "Robin", This is SystemC Tutorial.

`include define :
If the file name A is included in the file B we can use that files A’s
functions and variables in file B as well.

output :

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