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stm32h755bi stm32h745bi
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STM32H755xI Pin descriptions

Table 8. STM32H755xI pin/ball definition

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208 (function Alternate functions

functions
after reset)

TRACECLK, SAI1_CK1,
SPI4_SCK,
SAI1_MCLK_A,
FT_ SAI4_MCLK_A,
1 C3 1 1 C3 PE2 I/O - -
h QUADSPI_BK1_IO2,
SAI4_CK1,
ETH_MII_TXD3,
FMC_A23, EVENTOUT
TRACED0, TIM15_BKIN,
FT_ SAI1_SD_B,
2 B2 2 2 D3 PE3 I/O - -
h SAI4_SD_B, FMC_A19,
EVENTOUT
TRACED1, SAI1_D2,
DFSDM1_DATIN3,
TIM15_CH1N,
FT_
3 B1 3 3 D2 PE4 I/O - SPI4_NSS, SAI1_FS_A, -
h
SAI4_FS_A, SAI4_D2,
FMC_A20, DCMI_D4,
LCD_B0, EVENTOUT
TRACED2, SAI1_CK2,
DFSDM1_CKIN3,
TIM15_CH1,
SPI4_MISO,
FT_
4 D3 4 4 D1 PE5 I/O - SAI1_SCK_A, -
h
SAI4_SCK_A,
SAI4_CK2, FMC_A21,
DCMI_D6, LCD_G0,
EVENTOUT
TRACED3, TIM1_BKIN2,
SAI1_D1, TIM15_CH2,
SPI4_MOSI, SAI1_SD_A,
FT_ SAI4_SD_A, SAI4_D1,
5 E3 5 5 E5 PE6 I/O - -
h SAI2_MCLK_B,
TIM1_BKIN2_COMP12,
FMC_A22, DCMI_D7,
LCD_G1, EVENTOUT
6 A1 6 6 A1 VSS S - - - -
7 D5 7 7 - VDD S - - - -
8 E2 8 8 B1 VBAT S - - - -
- A15 - - B2 VSS S - - - -

DS12919 Rev 2 61/256

103
Pin descriptions STM32H755xI

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

RTC_TAMP2/
- - - 9 E4 PI8 I/O FT - EVENTOUT
WKUP3
RTC_TAMP1/
9 C1 9 10 E3 PC13 I/O FT - EVENTOUT
RTC_TS/WKUP4
- C2 - - - VSS S - - - -
PC14-
OSC32_IN
10 D2 10 11 C2 I/O FT - EVENTOUT OSC32_IN
(OSC32_IN)
(1)

PC15-
OSC32_OUT
11 D1 11 12 C1 I/O FT - EVENTOUT OSC32_OUT
(OSC32_
OUT)(1)
UART4_RX,
FT_ FDCAN1_RX, FMC_D30,
- - - 13 E2 PI9 I/O - -
h LCD_VSYNC,
EVENTOUT
ETH_MII_RX_ER,
FT_
- - - 14 F3 PI10 I/O - FMC_D31, LCD_HSYNC, -
h
EVENTOUT
LCD_G6,
- - - 15 F4 PI11 I/O FT - OTG_HS_ULPI_DIR, WKUP5
EVENTOUT
12 D10 12 16 A17 VSS S - - - -
13 D11 13 17 E6 VDD S - - - -
14 F2 14 18 F2 VSSSMPS S - - - -
15 F1 15 19 E1 VLXSMPS S - - - -
16 G1 16 20 F1 VDDSMPS S - - - -
17 G2 17 21 G2 VFBSMPS S - - - -
I2C2_SDA, FMC_A0,
- F4 18 22 G4 PF0 I/O FT_f - -
EVENTOUT
I2C2_SCL, FMC_A1,
- F3 19 23 G3 PF1 I/O FT_f - -
EVENTOUT
I2C2_SMBA, FMC_A2,
- G3 20 24 G1 PF2 I/O FT - -
EVENTOUT

62/256 DS12919 Rev 2

STM32H755xI Pin descriptions

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

LCD_HSYNC,
- - - - H1 PI12 I/O FT - -
EVENTOUT
LCD_VSYNC,
- - - - H2 PI13 I/O FT - -
EVENTOUT
FT_
- - - - H3 PI14 I/O - LCD_CLK, EVENTOUT -
h
FT_
- H4 21 25 H4 PF3 I/O - FMC_A3, EVENTOUT ADC3_INP5
ha
FT_ ADC3_INN5,
- H2 22 26 J5 PF4 I/O - FMC_A4, EVENTOUT
ha ADC3_INP9
FT_
- H3 23 27 J4 PF5 I/O - FMC_A5, EVENTOUT ADC3_INP4
ha
18 E1 24 28 C10 VSS S - - - -
19 E4 25 29 E9 VDD S - - - -
TIM16_CH1, SPI5_NSS,
SAI1_SD_B, UART7_RX,
FT_ ADC3_INN4,
20 H1 26 30 K2 PF6 I/O - SAI4_SD_B,
ha ADC3_INP8
QUADSPI_BK1_IO3,
EVENTOUT
TIM17_CH1, SPI5_SCK,
SAI1_MCLK_B,
FT_ UART7_TX,
21 J3 27 31 K3 PF7 I/O - ADC3_INP3
ha SAI4_MCLK_B,
QUADSPI_BK1_IO2,
EVENTOUT
TIM16_CH1N,
SPI5_MISO,
SAI1_SCK_B,
FT_ UART7_RTS/UART7_DE ADC3_INN3,
22 J2 28 32 K4 PF8 I/O -
ha , SAI4_SCK_B, ADC3_INP7
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
TIM17_CH1N,
SPI5_MOSI, SAI1_FS_B,
FT_ UART7_CTS,
23 J4 29 33 L4 PF9 I/O - ADC3_INP2
ha SAI4_FS_B, TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT

DS12919 Rev 2 63/256

103
Pin descriptions STM32H755xI

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

TIM16_BKIN, SAI1_D3,
FT_ QUADSPI_CLK, ADC3_INN2,
24 K3 30 34 L3 PF10 I/O -
ha SAI4_D3, DCMI_D11, ADC3_INP6
LCD_DE, EVENTOUT
PH0-
25 J1 31 35 J2 OSC_IN I/O FT - EVENTOUT OSC_IN
(PH0)
PH1-
26 K1 32 36 J1 OSC_OUT I/O FT - EVENTOUT OSC_OUT
(PH1)
27 L1 33 37 K1 NRST I/O RST - - -
DFSDM1_CKIN0,
DFSDM1_DATIN4,
FT_ SAI2_FS_B,
28 L2 34 38 L2 PC0 I/O - ADC123_INP10
a OTG_HS_ULPI_STP,
FMC_SDNWE, LCD_R5,
EVENTOUT
TRACED0, SAI1_D1,
DFSDM1_DATIN0,
DFSDM1_CKIN4,
SPI2_MOSI/I2S2_SDO, ADC123_INN10,
FT_ SAI1_SD_A, ADC123_INP11,
29 L3 35 39 M2 PC1 I/O -
ha SAI4_SD_A, RTC_TAMP3/
SDMMC2_CK, SAI4_D1, WKUP6
ETH_MDC,
MDIOS_MDC,
EVENTOUT
FT_ C1DSLEEP, ADC123_INN11,
- M1 - - M3(2) PC2 I/O -
a DFSDM1_CKIN1, ADC123_INP12
SPI2_MISO/I2S2_SDI,
DFSDM1_CKOUT,
TT_ OTG_HS_ULPI_DIR, ADC3_INN1,
30(3) N1(3) 36(3) 40(3) R1(2) PC2_C ANA - ETH_MII_TXD2,
a ADC3_INP0
FMC_SDNE0,
EVENTOUT
FT_ C1SLEEP, ADC12_INN12,
- M2 - - M4(2) PC3 I/O -
a DFSDM1_DATIN1, ADC12_INP13
SPI2_MOSI/I2S2_SDO,
OTG_HS_ULPI_NXT,
TT_ ETH_MII_TX_CLK,
31(3) N2(3) 37(3) 41(3) R2(2) PC3_C ANA - ADC3_INP1
a FMC_SDCKE0,
EVENTOUT

64/256 DS12919 Rev 2

STM32H755xI Pin descriptions

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

32 E12 - - E11 VDD S - - - -

33 F6 - - C13 VSS S - - - -
34 N3 38 42 P1 VSSA S - - - -
- L4 - - N1 VREF- S - - - -
35 M3 39 43 M1 VREF+ S - - - -
36 M4 40 44 L1 VDDA S - - - -
FT_ TIM2_CH1/TIM2_ETR, ADC1_INP16,
37 P1 41 45 N5(2) PA0 I/O -
a TIM5_CH1, TIM8_ETR, WKUP1
TIM15_BKIN,
USART2_CTS/USART2_
NSS, UART4_TX,
TT_ SDMMC2_CMD, ADC12_INN1,
- R3 - - T1(2) PA0_C ANA -
a SAI2_SD_B, ADC12_INP0
ETH_MII_CRS,
EVENTOUT
FT_ TIM2_CH2, TIM5_CH2, ADC1_INN16,
38 P2 42 46 N4(2) PA1 I/O -
ha LPTIM3_OUT, ADC1_INP17
TIM15_CH1N,
USART2_RTS/USART2_
DE, UART4_RX,
TT_ QUADSPI_BK1_IO3,
- P3 - - T2(2) PA1_C ANA - SAI2_MCLK_B, ADC12_INP1
a
ETH_MII_RX_CLK/ETH_
RMII_REF_CLK,
LCD_R2, EVENTOUT
TIM2_CH3, TIM5_CH3,
LPTIM4_OUT,
TIM15_CH1,
FT_ USART2_TX, ADC12_INP14,
39 R2 43 47 N3 PA2 I/O -
a SAI2_SCK_B, WKUP2
ETH_MDIO,
MDIOS_MDIO, LCD_R1,
EVENTOUT
LPTIM1_IN2,
QUADSPI_BK2_IO0,
FT_ SAI2_SCK_B,
- N4 - 48 N2 PH2 I/O - ADC3_INP13
ha ETH_MII_CRS,
FMC_SDCKE0, LCD_R0,
EVENTOUT
- G4 44 49 F5 VDD S - - - -

DS12919 Rev 2 65/256

103
Pin descriptions STM32H755xI

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

- F7 45 50 C16 VSS S - - - -
QUADSPI_BK2_IO1,
SAI2_MCLK_B,
FT_ ADC3_INN13,
- R4 - 51 P2 PH3 I/O - ETH_MII_COL,
ha ADC3_INP14
FMC_SDNE0, LCD_R1,
EVENTOUT
I2C2_SCL, LCD_G5,
FT_f ADC3_INN14,
- P4 - 52 P3 PH4 I/O - OTG_HS_ULPI_NXT,
a ADC3_INP15
LCD_G4, EVENTOUT
I2C2_SDA, SPI5_NSS,
FT_f ADC3_INN15,
- R5 - 53 P4 PH5 I/O - FMC_SDNWE,
a ADC3_INP16
EVENTOUT
TIM2_CH4, TIM5_CH4,
LPTIM5_OUT,
TIM15_CH2,
FT_
40 N5 46 54 U2 PA3 I/O - USART2_RX, LCD_B2, ADC12_INP15
ha
OTG_HS_ULPI_D0,
ETH_MII_COL, LCD_B5,
EVENTOUT
41 F8 47 55 - VSS S - - - -
42 H12 48 56 G5 VDD S - - - -
D1PWREN, TIM5_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK,
TT_ ADC12_INP18,
43 P5 49 57 U3 PA4 I/O - SPI6_NSS,
a DAC1_OUT1
OTG_HS_SOF,
DCMI_HSYNC,
LCD_VSYNC,
EVENTOUT
D2PWREN,
TIM2_CH1/TIM2_ETR,
TIM8_CH1N, ADC12_INN18,
TT_
44 P6 50 58 T3 PA5 I/O - SPI1_SCK/I2S1_CK, ADC12_INP19,
ha
SPI6_SCK, DAC1_OUT2
OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT

66/256 DS12919 Rev 2

STM32H755xI Pin descriptions

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO/I2S1_SDI,
SPI6_MISO,
FT_ TIM13_CH1,
45 R7 51 59 R3 PA6 I/O - ADC12_INP3
a TIM8_BKIN_COMP12,
MDIOS_MDC,
TIM1_BKIN_COMP12,
DCMI_PIXCLK, LCD_G2,
EVENTOUT
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SDO,
SPI6_MOSI, ADC12_INN3,
TT_
46 N6 52 60 R5 PA7 I/O - TIM14_CH1, ADC12_INP7,
a
ETH_MII_RX_DV/ETH_R OPAMP1_VINM
MII_CRS_DV,
FMC_SDNWE,
EVENTOUT
C2DSLEEP,
DFSDM1_CKIN2,
I2S1_MCK,
ADC12_INP4,
TT_ SPDIFRX1_IN3,
47 R6 53 61 T4 PC4 I/O - OPAMP1_VOUT,
a ETH_MII_RXD0/ETH_R
COMP1_INM
MII_RXD0,
FMC_SDNE0,
EVENTOUT
C2SLEEP, SAI1_D3,
DFSDM1_DATIN2,
SPDIFRX1_IN4,
SAI4_D3, ADC12_INN4,
TT_
48 M7 54 62 U4 PC5 I/O - ETH_MII_RXD1/ETH_R ADC12_INP8,
a
MII_RXD1, OPAMP1_VINM
FMC_SDCKE0,
COMP1_OUT,
EVENTOUT
- K4 - - G13 VDD S - - - -
- F9 - - R4 VSS S - - - -

DS12919 Rev 2 67/256

103
Pin descriptions STM32H755xI

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

TIM1_CH2N, TIM3_CH3,
TIM8_CH2N,
ADC12_INN5,
DFSDM1_CKOUT,
FT_ ADC12_INP9,
49 R8 55 63 U5 PB0 I/O - UART4_CTS, LCD_R3,
a OPAMP1_VINP,
OTG_HS_ULPI_D1,
COMP1_INP
ETH_MII_RXD2,
LCD_G1, EVENTOUT
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N,
DFSDM1_DATIN1,
TT_ ADC12_INP5,
50 M8 56 64 T5 PB1 I/O - LCD_R6,
a COMP1_INM
OTG_HS_ULPI_D2,
ETH_MII_RXD3,
LCD_G0, EVENTOUT
RTC_OUT, SAI1_D1,
DFSDM1_CKIN1,
SAI1_SD_A,
FT_
51 P7 57 65 R6 PB2 I/O - SPI3_MOSI/I2S3_SDO, COMP1_INP
ha
SAI4_SD_A,
QUADSPI_CLK,
SAI4_D1, EVENTOUT
LCD_G2, LCD_R0,
- - - 66 P5 PI15 I/O FT - -
EVENTOUT
LCD_R7, LCD_R1,
- - - - N6 PJ0 I/O FT - -
EVENTOUT
- - - - P6 PJ1 I/O FT - LCD_R2, EVENTOUT -
- - - - T6 PJ2 I/O FT - LCD_R3, EVENTOUT -
- - - - U6 PJ3 I/O FT - LCD_R4, EVENTOUT -
- - - - U7 PJ4 I/O FT - LCD_R5, EVENTOUT -
SPI5_MOSI, SAI2_SD_B,
FT_
52 N7 58 67 T7 PF11 I/O - FMC_SDNRAS, ADC1_INP2
a
DCMI_D12, EVENTOUT
FT_ ADC1_INN2,
- P11 59 68 R7 PF12 I/O - FMC_A6, EVENTOUT
ha ADC1_INP6
- F10 - - J3 VSS S - - - -
- L12 - - H5 VDD S - - - -
DFSDM1_DATIN6,
FT_
- N11 60 69 P7 PF13 I/O - I2C4_SMBA, FMC_A7, ADC2_INP2
ha
EVENTOUT

68/256 DS12919 Rev 2

STM32H755xI Pin descriptions

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

DFSDM1_CKIN6,
FT_f ADC2_INN2,
53 R10 61 70 P8 PF14 I/O - I2C4_SCL, FMC_A8,
ha ADC2_INP6
EVENTOUT
FT_f I2C4_SDA, FMC_A9,
54 N10 62 71 R9 PF15 I/O - -
h EVENTOUT
FT_
- P8 63 72 T8 PG0 I/O - FMC_A10, EVENTOUT -
h
55 F12 64 73 J16 VSS S - - - -
56 M5 65 74 H13 VDD S - - - -
TT_
- N9 66 75 U8 PG1 I/O - FMC_A11, EVENTOUT OPAMP2_VINM
h
TIM1_ETR,
DFSDM1_DATIN2,
TT_ UART7_RX, OPAMP2_VOUT,
57 P9 67 76 U9 PE7 I/O -
ha QUADSPI_BK2_IO0, COMP2_INM
FMC_D4/FMC_DA4,
EVENTOUT
TIM1_CH1N,
DFSDM1_CKIN2,
UART7_TX,
TT_
58 N8 68 77 T9 PE8 I/O - QUADSPI_BK2_IO1, OPAMP2_VINM
ha
FMC_D5/FMC_DA5,
COMP2_OUT,
EVENTOUT
TIM1_CH1,
DFSDM1_CKOUT,
TT_ UART7_RTS/UART7_DE OPAMP2_VINP,
59 R11 69 78 P9 PE9 I/O -
ha , QUADSPI_BK2_IO2, COMP2_INP
FMC_D6/FMC_DA6,
EVENTOUT
- G6 70 79 J17 VSS S - - - -
- M9 71 80 J13 VDD S - - - -
TIM1_CH2N,
DFSDM1_DATIN4,
FT_ UART7_CTS,
60 R9 72 81 N9 PE10 I/O - COMP2_INM
ha QUADSPI_BK2_IO3,
FMC_D7/FMC_DA7,
EVENTOUT

DS12919 Rev 2 69/256

103
Pin descriptions STM32H755xI

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

TIM1_CH2,
DFSDM1_CKIN4,
FT_
61 R12 73 82 P10 PE11 I/O - SPI4_NSS, SAI2_SD_B, COMP2_INP
ha
FMC_D8/FMC_DA8,
LCD_G3, EVENTOUT
TIM1_CH3N,
DFSDM1_DATIN5,
SPI4_SCK,
FT_
62 P12 74 83 R10 PE12 I/O - SAI2_SCK_B, -
h
FMC_D9/FMC_DA9,
COMP1_OUT, LCD_B4,
EVENTOUT
TIM1_CH3,
DFSDM1_CKIN5,
FT_ SPI4_MISO, SAI2_FS_B,
63 P13 75 84 T10 PE13 I/O - -
h FMC_D10/FMC_DA10,
COMP2_OUT, LCD_DE,
EVENTOUT
- G7 - - T12 VSS S - - - -
- - - - K13 VDD S - - - -
TIM1_CH4, SPI4_MOSI,
FT_ SAI2_MCLK_B,
64 M12 76 85 U10 PE14 I/O - -
h FMC_D11/FMC_DA11,
LCD_CLK, EVENTOUT
TIM1_BKIN,
FMC_D12/FMC_DA12,
FT_
65 P14 77 86 R11 PE15 I/O - TIM1_BKIN_COMP12/C -
h
OMP_TIM1_BKIN,
LCD_R7, EVENTOUT
TIM2_CH3,
HRTIM_SCOUT,
LPTIM2_IN1, I2C2_SCL,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN7,
66 N12 78 87 P11 PB10 I/O FT_f - -
USART3_TX,
QUADSPI_BK1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER,
LCD_G4, EVENTOUT

70/256 DS12919 Rev 2

STM32H755xI Pin descriptions

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

TIM2_CH4,
HRTIM_SCIN,
LPTIM2_ETR,
I2C2_SDA,
DFSDM1_CKIN7,
67 P10 79 88 P12 PB11 I/O FT_f - -
USART3_RX,
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_R
MII_TX_EN, LCD_G5,
EVENTOUT
68 R13 80 89 U11 VCAP S - - - -
69 M10 81 90 - VSS S - - - -
70 R14 82 91 U12 VDDLDO S - - - -
71 - - - L13 VDD S - - - -
- - - - R12 PJ5 I/O FT - LCD_R6, EVENTOUT -
TIM12_CH1,
I2C2_SMBA, SPI5_SCK,
- P15 - 92 T11 PH6 I/O FT - ETH_MII_RXD2, -
FMC_SDNE1, DCMI_D8,
EVENTOUT
I2C3_SCL, SPI5_MISO,
FT_f ETH_MII_RXD3,
- M11 - 93 U13 PH7 I/O - -
a FMC_SDCKE1,
DCMI_D9, EVENTOUT
TIM5_ETR, I2C3_SDA,
FT_f FMC_D16,
- N13 - 94 T13 PH8 I/O - -
ha DCMI_HSYNC, LCD_R2,
EVENTOUT
- G9 - - - VSS S - - - -
- - - - M13 VDD S - - - -
TIM12_CH2,
FT_ I2C3_SMBA, FMC_D17,
- M14 - 95 R13 PH9 I/O - -
h DCMI_D0, LCD_R3,
EVENTOUT
TIM5_CH1, I2C4_SMBA,
FT_
- N14 - 96 P13 PH10 I/O - FMC_D18, DCMI_D1, -
h
LCD_R4, EVENTOUT

DS12919 Rev 2 71/256

103
Pin descriptions STM32H755xI

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

TIM5_CH2, I2C4_SCL,
FT_f
- M13 - 97 P14 PH11 I/O - FMC_D19, DCMI_D2, -
h
LCD_R5, EVENTOUT
TIM5_CH3, I2C4_SDA,
FT_f
- N15 - 98 R14 PH12 I/O - FMC_D20, DCMI_D3, -
h
LCD_R6, EVENTOUT
- G10 83 99 N16 VSS S - - - -
- - 84 100 - VDD S - - - -
TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
DFSDM1_DATIN1,
USART3_CK,
FT_
72 M15 85 101 T14 PB12(4) I/O - FDCAN2_RX, -
u
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_R
MII_TXD0, OTG_HS_ID,
TIM1_BKIN_COMP12,
UART5_RX, EVENTOUT
TIM1_CH1N,
LPTIM2_OUT,
SPI2_SCK/I2S2_CK,
DFSDM1_CKIN1,
FT_ USART3_CTS/USART3_
73 L15 86 102 U14 PB13(4) I/O - OTG_HS_VBUS
u NSS, FDCAN2_TX,
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_R
MII_TXD1, UART5_TX,
EVENTOUT
TIM1_CH2N,
TIM12_CH1,
TIM8_CH2N,
USART1_TX,
SPI2_MISO/I2S2_SDI,
FT_ DFSDM1_DATIN2,
74 K15 87 103 U15 PB14 I/O - -
u USART3_RTS/USART3_
DE,
UART4_RTS/UART4_DE
, SDMMC2_D0,
OTG_HS_DM,
EVENTOUT

72/256 DS12919 Rev 2

STM32H755xI Pin descriptions

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

RTC_REFIN,
TIM1_CH3N,
TIM12_CH2,
TIM8_CH3N,
USART1_RX,
FT_
75 K14 88 104 T15 PB15 I/O - SPI2_MOSI/I2S2_SDO, -
u
DFSDM1_CKIN2,
UART4_CTS,
SDMMC2_D1,
OTG_HS_DP,
EVENTOUT
DFSDM1_CKIN3,
SAI3_SCK_B,
FT_ USART3_TX,
76 L14 89 105 U16 PD8 I/O - -
h SPDIFRX1_IN2,
FMC_D13/FMC_DA13,
EVENTOUT
DFSDM1_DATIN3,
SAI3_SD_B,
FT_
77 K13 90 106 T17 PD9 I/O - USART3_RX, -
h
FMC_D14/FMC_DA14,
EVENTOUT
DFSDM1_CKOUT,
SAI3_FS_B,
FT_
78 L13 91 107 T16 PD10 I/O - USART3_CK, -
h
FMC_D15/FMC_DA15,
LCD_B3, EVENTOUT
79 - 92 108 N12 VDD S - - - -
80 H6 93 109 U17 VSS S - - - -
LPTIM2_IN2,
I2C4_SMBA,
USART3_CTS/USART3_
FT_
81 J13 94 110 R15 PD11 I/O - NSS, -
h
QUADSPI_BK1_IO0,
SAI2_SD_A, FMC_A16,
EVENTOUT
LPTIM1_IN1, TIM4_CH1,
LPTIM2_IN1, I2C4_SCL,
FT_f USART3_RTS/USART3_
82 J15 95 111 R16 PD12 I/O - -
h DE, QUADSPI_BK1_IO1,
SAI2_FS_A, FMC_A17,
EVENTOUT

DS12919 Rev 2 73/256

103
Pin descriptions STM32H755xI

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

LPTIM1_OUT,
TIM4_CH2, I2C4_SDA,
FT_f
83 H15 96 112 R17 PD13 I/O - QUADSPI_BK1_IO3, -
h
SAI2_SCK_A, FMC_A18,
EVENTOUT
- R1 - 113 - VSS S - - - -
- - - 114 N11 VDD S - - - -
TIM4_CH3,
SAI3_MCLK_B,
FT_
84 H14 97 115 P16 PD14 I/O - UART8_CTS, -
h
FMC_D0/FMC_DA0,
EVENTOUT
TIM4_CH4,
SAI3_MCLK_A,
FT_
85 J12 98 116 P15 PD15 I/O - UART8_RTS/UART8_DE -
h
, FMC_D1/FMC_DA1,
EVENTOUT
TIM8_CH2, LCD_R7,
- - - 117 N15 PJ6 I/O FT - -
EVENTOUT
TRGIN, TIM8_CH2N,
- - - 118 N14 PJ7 I/O FT - -
LCD_G0, EVENTOUT
- - 99 119 N10 VDD S - - - -
- D6 100 120 R8 VSS S - - - -
TIM1_CH3N, TIM8_CH1,
- - 101 121 N13 PJ8 I/O FT - UART8_TX, LCD_G1, -
EVENTOUT
TIM1_CH3, TIM8_CH1N,
- - 102 122 M14 PJ9 I/O FT - UART8_RX, LCD_G2, -
EVENTOUT
TIM1_CH2N, TIM8_CH2,
- - 103 123 L14 PJ10 I/O FT - SPI5_MOSI, LCD_G3, -
EVENTOUT
TIM1_CH2, TIM8_CH2N,
- - 104 124 K14 PJ11 I/O FT - SPI5_MISO, LCD_G4, -
EVENTOUT
- - 105 125 N8 VDD S - - - -
- - - - P17 VDD S - - - -

74/256 DS12919 Rev 2

STM32H755xI Pin descriptions

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

- R15 106 126 U1 VSS S - - - -

- - - - N17 NC - - - - -
- - - - M16 NC - - - - -
- - - - M17 NC - - - - -
- - - - K15 VSS S - - - -
- - - - L16 NC - - - - -
- - - - L17 NC - - - - -
- - - - K16 NC - - - - -
- - - - K17 NC - - - - -
- - - - L15 VSS S - - - -
TIM1_CH1N, TIM8_CH3,
- - 107 127 J14 PK0 I/O FT - SPI5_SCK, LCD_G5, -
EVENTOUT
TIM1_CH1, TIM8_CH3N,
- - 108 128 J15 PK1 I/O FT - SPI5_NSS, LCD_G6, -
EVENTOUT
TIM1_BKIN, TIM8_BKIN,
TIM8_BKIN_COMP12,
- - 109 129 H17 PK2 I/O FT - -
TIM1_BKIN_COMP12,
LCD_G7, EVENTOUT
TIM8_BKIN,
FT_
- G15 110 130 H16 PG2 I/O - TIM8_BKIN_COMP12, -
h
FMC_A12, EVENTOUT
TIM8_BKIN2,
FT_
- H13 111 131 H15 PG3 I/O - TIM8_BKIN2_COMP12, -
h
FMC_A13, EVENTOUT
- H10 112 132 - VSS S - - - -
- - 113 133 N7 VDD S - - - -
TIM1_BKIN2,
FT_ TIM1_BKIN2_COMP12,
- G14 114 134 H14 PG4 I/O - -
h FMC_A14/FMC_BA0,
EVENTOUT
TIM1_ETR,
FT_
- F15 115 135 G14 PG5 I/O - FMC_A15/FMC_BA1, -
h
EVENTOUT

DS12919 Rev 2 75/256

103
Pin descriptions STM32H755xI

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

TIM17_BKIN,
HRTIM_CHE1,
FT_
86 F14 116 136 G15 PG6 I/O - QUADSPI_BK1_NCS, -
h
FMC_NE3, DCMI_D12,
LCD_R7, EVENTOUT
HRTIM_CHE2,
SAI1_MCLK_A,
FT_
87 G13 117 137 F16 PG7 I/O - USART6_CK, FMC_INT, -
h
DCMI_D13, LCD_CLK,
EVENTOUT
TIM8_ETR, SPI6_NSS,
USART6_RTS/USART6_
FT_ DE, SPDIFRX1_IN3,
88 G12 118 138 F15 PG8 I/O - -
h ETH_PPS_OUT,
FMC_SDCLK, LCD_G7,
EVENTOUT
89 J6 119 139 G16 VSS S - - - -
VDD50USB
90 E15 120 140 G17 (5) S - - - -

91 F13 121 141 F17 VDD33USB S - - - -

92 - - - M5 VDD S - - - -
HRTIM_CHA1,
TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3,
I2S2_MCK, USART6_TX,
FT_ SDMMC1_D0DIR,
93 E14 122 142 F14 PC6 I/O - SWPMI_IO
h FMC_NWAIT,
SDMMC2_D6,
SDMMC1_D6, DCMI_D0,
LCD_HSYNC,
EVENTOUT

76/256 DS12919 Rev 2

STM32H755xI Pin descriptions

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

TRGIO, HRTIM_CHA2,
TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3,
I2S3_MCK,
USART6_RX,
FT_
94 D15 123 143 F13 PC7 I/O - SDMMC1_D123DIR, -
h
FMC_NE1,
SDMMC2_D7,
SWPMI_TX,
SDMMC1_D7, DCMI_D1,
LCD_G6, EVENTOUT
TRACED1,
HRTIM_CHB1,
TIM3_CH3, TIM8_CH3,
USART6_CK,
FT_
95 D14 124 144 E13 PC8 I/O - UART5_RTS/UART5_DE -
h
, FMC_NE2/FMC_NCE,
SWPMI_RX,
SDMMC1_D0, DCMI_D2,
EVENTOUT
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN, UART5_CTS,
FT_f QUADSPI_BK1_IO0,
96 E13 125 145 E14 PC9 I/O - -
h LCD_G3,
SWPMI_SUSPEND,
SDMMC1_D1, DCMI_D3,
LCD_B2, EVENTOUT
- J7 - - - VSS S - - - -
- - 126 - L5 VDD S - - - -
MCO1, TIM1_CH1,
HRTIM_CHB2,
TIM8_BKIN2, I2C3_SCL,
USART1_CK,
FT_f
97 B14 127 146 E15 PA8 I/O - OTG_FS_SOF, -
ha
UART7_RX,
TIM8_BKIN2_COMP12,
LCD_B3, LCD_R6,
EVENTOUT

DS12919 Rev 2 77/256

103
Pin descriptions STM32H755xI

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

TIM1_CH2,
HRTIM_CHC1,
LPUART1_TX,
FT_
98 D13 128 147 D15 PA9 I/O - I2C3_SMBA, OTG_FS_VBUS
u
SPI2_SCK/I2S2_CK,
USART1_TX, DCMI_D0,
LCD_R5, EVENTOUT
TIM1_CH3,
HRTIM_CHC2,
LPUART1_RX,
FT_ USART1_RX,
99 C14 129 148 D14 PA10 I/O - -
u OTG_FS_ID,
MDIOS_MDIO, LCD_B4,
DCMI_D1, LCD_B1,
EVENTOUT
TIM1_CH4,
HRTIM_CHD1,
LPUART1_CTS,
SPI2_NSS/I2S2_WS,
FT_
100 C15 130 149 E17 PA11 I/O - UART4_RX, -
u
USART1_CTS/USART1_
NSS, FDCAN1_RX,
OTG_FS_DM, LCD_R4,
EVENTOUT
TIM1_ETR,
HRTIM_CHD2,
LPUART1_RTS/LPUART
1_DE,
SPI2_SCK/I2S2_CK,
FT_
101 B15 131 150 E16 PA12 I/O - UART4_TX, -
u
USART1_RTS/USART1_
DE, SAI2_FS_B,
FDCAN1_TX,
OTG_FS_DP, LCD_R5,
EVENTOUT
PA13(JTMS/ JTMS-SWDIO,
102 B13 132 151 C15 I/O FT - -
SWDIO) EVENTOUT
103 A14 133 152 D17 VCAP S - - - -
104 M6 134 153 - VSS S - - - -
105 A13 135 154 C17 VDDLDO - - - - -
106 - 136 155 K5 VDD S - - - -

78/256 DS12919 Rev 2

STM32H755xI Pin descriptions

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

TIM8_CH1N,
FT_ UART4_TX,
- C13 - 156 D16 PH13 I/O - -
h FDCAN1_TX, FMC_D21,
LCD_G2, EVENTOUT
TIM8_CH2N,
UART4_RX,
FT_
- B12 - 157 B17 PH14 I/O - FDCAN1_RX, FMC_D22, -
h
DCMI_D4, LCD_G3,
EVENTOUT
TIM8_CH3N, FMC_D23,
FT_
- D12 - 158 B16 PH15 I/O - DCMI_D11, LCD_G4, -
h
EVENTOUT
TIM5_CH4,
FT_ SPI2_NSS/I2S2_WS,
- - - 159 A16 PI0 I/O - -
h FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
- J9 - 160 - VSS S - - - -
- - - 161 - VDD S - - - -
TIM8_BKIN2,
SPI2_SCK/I2S2_CK,
FT_
- - - 162 A15 PI1 I/O - TIM8_BKIN2_COMP12, -
h
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT
TIM8_CH4,
FT_ SPI2_MISO/I2S2_SDI,
- - - 163 B15 PI2 I/O - -
h FMC_D26, DCMI_D9,
LCD_G7, EVENTOUT
TIM8_ETR,
FT_ SPI2_MOSI/I2S2_SDO,
- - - 164 C14 PI3 I/O - -
h FMC_D27, DCMI_D10,
EVENTOUT
- J10 137 - - VSS S - - - -
- - - - - VDD S - - - -
PA14(JTCK/ JTCK-SWCLK,
107 A12 138 165 B14 I/O FT - -
SWCLK) EVENTOUT

DS12919 Rev 2 79/256

103
Pin descriptions STM32H755xI

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

JTDI,
TIM2_CH1/TIM2_ETR,
HRTIM_FLT1, CEC,
SPI1_NSS/I2S1_WS,
108 A11 139 166 A14 PA15(JTDI) I/O FT - SPI3_NSS/I2S3_WS, -
SPI6_NSS,
UART4_RTS/UART4_DE
, UART7_TX,
EVENTOUT
HRTIM_EEV1,
DFSDM1_CKIN5,
SPI3_SCK/I2S3_CK,
FT_ USART3_TX,
109 C12 140 167 A13 PC10 I/O - -
ha UART4_TX,
QUADSPI_BK1_IO1,
SDMMC1_D2, DCMI_D8,
LCD_R2, EVENTOUT
HRTIM_FLT2,
DFSDM1_DATIN5,
SPI3_MISO/I2S3_SDI,
FT_ USART3_RX,
110 C11 141 168 B13 PC11 I/O - -
h UART4_RX,
QUADSPI_BK2_NCS,
SDMMC1_D3, DCMI_D4,
EVENTOUT
TRACED3,
HRTIM_EEV2,
SPI3_MOSI/I2S3_SDO,
FT_
111 B11 142 169 C12 PC12 I/O - USART3_CK, -
h
UART5_TX,
SDMMC1_CK,
DCMI_D9, EVENTOUT
- J14 - - - VSS S - - - -
- - - - - VDD S - - - -
DFSDM1_CKIN6,
SAI3_SCK_A,
FT_ UART4_RX,
112 C10 143 170 D13 PD0 I/O - -
h FDCAN1_RX,
FMC_D2/FMC_DA2,
EVENTOUT

80/256 DS12919 Rev 2

STM32H755xI Pin descriptions

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

DFSDM1_DATIN6,
SAI3_SD_A, UART4_TX,
FT_
113 A10 144 171 E12 PD1 I/O - FDCAN1_TX, -
h
FMC_D3/FMC_DA3,
EVENTOUT
TRACED2, TIM3_ETR,
FT_ UART5_RX,
114 B10 145 172 D12 PD2 I/O - -
h SDMMC1_CMD,
DCMI_D11, EVENTOUT
DFSDM1_CKOUT,
SPI2_SCK/I2S2_CK,
FT_ USART2_CTS/USART2_
115 A9 146 173 B12 PD3 I/O - -
h NSS, FMC_CLK,
DCMI_D5, LCD_G7,
EVENTOUT
HRTIM_FLT3,
SAI3_FS_A,
FT_
116 C9 147 174 A12 PD4 I/O - USART2_RTS/ -
h
USART2_DE,
FMC_NOE, EVENTOUT
HRTIM_EEV3,
FT_
117 B9 148 175 A11 PD5 I/O - USART2_TX, -
h
FMC_NWE, EVENTOUT
118 K2 - - - VSS S - - - -
119 - - - - VDD S - - - -
SAI1_D1,
DFSDM1_CKIN4,
DFSDM1_DATIN1,
SPI3_MOSI/I2S3_SDO,
SAI1_SD_A,
FT_
120 D9 149 176 B11 PD6 I/O - USART2_RX, -
h
SAI4_SD_A, SAI4_D1,
SDMMC2_CK,
FMC_NWAIT,
DCMI_D10, LCD_B2,
EVENTOUT

DS12919 Rev 2 81/256

103
Pin descriptions STM32H755xI

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

DFSDM1_DATIN4,
SPI1_MOSI/I2S1_SDO,
DFSDM1_CKIN1,
FT_
121 B8 150 177 C11 PD7 I/O - USART2_CK, -
h
SPDIFRX1_IN1,
SDMMC2_CMD,
FMC_NE1, EVENTOUT
TRGOUT, LCD_G3,
- - - - D11 PJ12 I/O FT - -
LCD_B0, EVENTOUT
LCD_B4, LCD_B1,
- - - - E10 PJ13 I/O FT - -
EVENTOUT
- - - - D10 PJ14 I/O FT - LCD_B2, EVENTOUT -
- - - - B10 PJ15 I/O FT - LCD_B3, EVENTOUT -
- K6 151 178 - VSS S - - - -
- - 152 179 - VDD S - - - -
SPI1_MISO/I2S1_SDI,
USART6_RX,
SPDIFRX1_IN4,
FT_ QUADSPI_BK2_IO2,
122 A8 153 180 A10 PG9 I/O - -
h SAI2_FS_B,
FMC_NE2/FMC_NCE,
DCMI_VSYNC,
EVENTOUT
HRTIM_FLT5,
SPI1_NSS/I2S1_WS,
FT_
123 C8 154 181 A9 PG10 I/O - LCD_G3, SAI2_SD_B, -
h
FMC_NE3, DCMI_D2,
LCD_B2, EVENTOUT
LPTIM1_IN2,
HRTIM_EEV4,
SPI1_SCK/I2S1_CK,
FT_ SPDIFRX1_IN1,
124 A7 155 182 B9 PG11 I/O - -
h SDMMC2_D2,
ETH_MII_TX_EN/ETH_R
MII_TX_EN, DCMI_D3,
LCD_B3, EVENTOUT

82/256 DS12919 Rev 2

STM32H755xI Pin descriptions

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

LPTIM1_IN1,
HRTIM_EEV5,
SPI6_MISO,
USART6_RTS/USART6_
FT_
125 D8 156 183 C9 PG12 I/O - DE, SPDIFRX1_IN2, -
h
LCD_B4,
ETH_MII_TXD1/ETH_R
MII_TXD1, FMC_NE4,
LCD_B1, EVENTOUT
TRACED0,
LPTIM1_OUT,
HRTIM_EEV10,
SPI6_SCK,
FT_
126 B7 157 184 D9 PG13 I/O - USART6_CTS/USART6_ -
h
NSS,
ETH_MII_TXD0/ETH_R
MII_TXD0, FMC_A24,
LCD_R0, EVENTOUT
TRACED1,
LPTIM1_ETR,
SPI6_MOSI,
FT_ USART6_TX,
127 C7 158 185 D8 PG14 I/O - -
h QUADSPI_BK2_IO3,
ETH_MII_TXD1/ETH_R
MII_TXD1, FMC_A25,
LCD_B0, EVENTOUT
- K7 159 186 - VSS S - - - -
- - 160 187 - VDD S - - - -
- - - - C8 PK3 I/O FT - LCD_B4, EVENTOUT -
- - - - B8 PK4 I/O FT - LCD_B5, EVENTOUT -
- - - - A8 PK5 I/O FT - LCD_B6, EVENTOUT -
- - - - C7 PK6 I/O FT - LCD_B7, EVENTOUT -
- - - - D7 PK7 I/O FT - LCD_DE, EVENTOUT -
128 K8 - - - VSS S - - - -
129 - - - - VDD S - - - -
USART6_CTS/USART6_
FT_
- D7 161 188 D6 PG15 I/O - NSS, FMC_SDNCAS, -
h
DCMI_D13, EVENTOUT

DS12919 Rev 2 83/256

103
Pin descriptions STM32H755xI

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

JTDO/TRACESWO,
TIM2_CH2,
HRTIM_FLT4,
SPI1_SCK/I2S1_CK,
PB3(JTDO/T
130 A6 162 189 C6 I/O FT - SPI3_SCK/I2S3_CK, -
RACESWO)
SPI6_SCK,
SDMMC2_D2,
CRS_SYNC,
UART7_RX, EVENTOUT
NJTRST, TIM16_BKIN,
TIM3_CH1,
HRTIM_EEV6,
SPI1_MISO/I2S1_SDI,
PB4(NJTRS
131 B6 163 190 B7 I/O FT - SPI3_MISO/I2S3_SDI, -
T)
SPI2_NSS/I2S2_WS,
SPI6_MISO,
SDMMC2_D3,
UART7_TX, EVENTOUT
TIM17_BKIN, TIM3_CH2,
HRTIM_EEV7,
I2C1_SMBA,
SPI1_MOSI/I2S1_SDO,
I2C4_SMBA,
SPI3_MOSI/I2S3_SDO,
132 C6 164 191 A5 PB5 I/O FT - SPI6_MOSI, -
FDCAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1,
DCMI_D10, UART5_RX,
EVENTOUT
- K9 - - - VSS S - - - -
- - - - - VDD S - - - -

84/256 DS12919 Rev 2

STM32H755xI Pin descriptions

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

TIM16_CH1N,
TIM4_CH1,
HRTIM_EEV8,
I2C1_SCL, CEC,
I2C4_SCL, USART1_TX,
133 A5 165 192 B5 PB6 I/O FT_f - LPUART1_TX, -
FDCAN2_TX,
QUADSPI_BK1_NCS,
DFSDM1_DATIN5,
FMC_SDNE1, DCMI_D5,
UART5_TX, EVENTOUT
TIM17_CH1N,
TIM4_CH2,
HRTIM_EEV9,
I2C1_SDA, I2C4_SDA,
FT_f
134 B5 166 193 C5 PB7 I/O - USART1_RX, PVD_IN
a
LPUART1_RX,
DFSDM1_CKIN5,
FMC_NL, DCMI_VSYNC,
EVENTOUT
135 C5 167 194 E8 BOOT0 I B - - VPP
TIM16_CH1, TIM4_CH3,
DFSDM1_CKIN7,
I2C1_SCL, I2C4_SCL,
SDMMC1_CKIN,
FT_f UART4_RX,
136 A2 168 195 D5 PB8 I/O - -
h FDCAN1_RX,
SDMMC2_D4,
ETH_MII_TXD3,
SDMMC1_D4, DCMI_D6,
LCD_B6, EVENTOUT
TIM17_CH1, TIM4_CH4,
DFSDM1_DATIN7,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
I2C4_SDA,
FT_f SDMMC1_CDIR,
137 B3 169 196 D4 PB9 I/O - -
h UART4_TX,
FDCAN1_TX,
SDMMC2_D5,
I2C4_SMBA,
SDMMC1_D5, DCMI_D7,
LCD_B7, EVENTOUT

DS12919 Rev 2 85/256

103
Pin descriptions STM32H755xI

Table 8. STM32H755xI pin/ball definition (continued)

Pin/ball name

I/O structure
UFBGA176+25

TFBGA240+25

Pin type
Pin name

Notes
Additional
LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after reset)

LPTIM1_ETR,
TIM4_ETR,
HRTIM_SCIN,
FT_ LPTIM2_ETR,
138 B4 170 197 C4 PE0 I/O - -
h UART8_RX,
SAI2_MCLK_A,
FMC_NBL0, DCMI_D2,
EVENTOUT
LPTIM1_IN2,
FT_ HRTIM_SCOUT,
139 C4 171 198 B4 PE1 I/O - -
h UART8_TX, FMC_NBL1,
DCMI_D3, EVENTOUT
140 A4 172 199 A7 VCAP S - - - -
141 K10 173 200 B6 VSS S - - - -
142 D4 174 201 E7 PDR_ON I FT - - -
143 A3 175 202 A6 VDDLDO S - - - -
- - - - - VDD S - - - -
TIM8_BKIN,
SAI2_MCLK_A,
FT_
- - - 203 A4 PI4 I/O - TIM8_BKIN_COMP12, -
h
FMC_NBL2, DCMI_D5,
LCD_B4, EVENTOUT
TIM8_CH1,
SAI2_SCK_A,
FT_
- - - 204 A3 PI5 I/O - FMC_NBL3, -
h
DCMI_VSYNC, LCD_B5,
EVENTOUT
TIM8_CH2, SAI2_SD_A,
FT_
- - - 205 A2 PI6 I/O - FMC_D28, DCMI_D6, -
h
LCD_B6, EVENTOUT
TIM8_CH3, SAI2_FS_A,
FT_
- - - 206 B3 PI7 I/O - FMC_D29, DCMI_D7, -
h
LCD_B7, EVENTOUT
- K12 - 207 - VSS S - - - -
144 - 176 208 - VDD S - - - -
- - - - M15 VSS S - - - -
1. When this pin/ball was previously configured as an oscillator, the oscillator function is kept during and after a reset. This is
valid for all resets except for power-on reset.

86/256 DS12919 Rev 2