# Tutorial 2

Tutorial 2:
1. What general categories of functions are specified by computer instructions?
The categories are processor memory, processor I/O, data processing, and
control.
2. List and briefly define the possible states that define an instruction execution.
- Instruction address calculation(iac): Determine the address of the next

instruction to be executed.
- Instruction fetch (if): Read instruction from its memory location into the
processor.
- Instruction operation decoding: Analyze instruction to determine type of
operation to be performed and operands to be used.
- Operand address calculation (oac): If the operation involves reference to an
operand in memory or available via I/O, then determine the address of the
operand.
- Operand fetch (of): Fetch the operand from memory or read it in from I/O.
- Data operation: Perform the operation indicated in the instruction.
- Operand store (os): Write the result into memory or out to I/O.
3. List and briefly define two approaches to dealing with multiple interrupts.
Disabling interrupts- processor has the ability to and will ignore the specific
interrupts. Those interrupts remain pending and will be checked after the
processor has enabled interrupts.
Interrupt service routine(ISR) - priorities assigned to the different types of

interrupts. Interrupt service routines with higher priorities can interrupt ones with
lower priority, in which case the ISR with the lower priority is put on the stack until
that ISR is completed.
4. What types of transfers must a computer’s interconnection structure (e.g., bus)

support?
- Memory to processor
- Processor to memory
- I/O to processor
- Processor to I/O
- I/O to or from memory
5. What is the benefit of using a multiple-bus architecture compared to a single-bus

architecture?
It is efficient, since if only one bus is for everything, only one device can then
communicate at a time, since if more than one device were to try and send data
on the single bus, transmission would be garbled.
6. The hypothetical machine below also has two I/O instructions:
0011=Load AC from I/O
0111=Store AC to I/O
In these cases, the 12-bit address identifies a particular I/O device. Show the program execution
(using the format of below) for the following program:
1. Load AC from device 5.
2. Add contents of memory location 940.
3. Store AC to device 6.
Assume that the next value retrieved from device 5 is 3 and that location 940 contains a value of 2.
7. The program execution shown in figure below is described in the text using six steps.
Expand this description to show the use of the MAR and MBR.
8. Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two

fields: the first byte contains the opcode and the remainder the immediate operand or an
operand address.
a. What is the maximum directly addressable memory capacity (in bytes)?
2(32-8) = 224 = 16,777,216 bytes = 16 MB

16,777,216 bytes (16 Mbytes)
b. Discuss the impact on the system speed if the microprocessor bus has
1. a 32-bit local address bus and a 16-bit local data bus, or
2. a 16-bit local address bus and a 16-bit local data bus.
b. With a 32-bit local address bus and a 16-bit local data bus, it would take 2 cycles to fetch the
32-bit instruction.
c. A 16-bit local address bus would slow down operation due to only being able to pass half the
instruction a cycle.
c. How many bits are needed for the program counter and the instruction register?
For the PC needs 24 bits (24-bit addresses), and for the IR needs 32 bits (32-bit addresses).
9. Consider a hypothetical microprocessor generating a 16-bit address (for example, assume that
the program counter and the address registers are 16 bits wide) and having a 16-bit data bus.
a. What is the maximum memory address space that the processor can access directly if it is
connected to a “16-bit memory”?
- The Maximum memory address space = 2^16 = 64 Kbytes.
b. What is the maximum memory address space that the processor can access directly if it is
connected to an “8-bit memory”?
The Maximum memory address space = 2^16 = 64 Kbytes.
Therefore, in (a) and (b), the microprocessor is to access 64K bytes, but the difference thing
between them is that the access of 8-bit memory will transfer a 8 bits and the access of 16-bit
memory may transfer 8 bits or 16 bits word.
c. What architectural features will allow this microprocessor to access a separate “I/O space”?
Separate I/O instructions are needed because during its execution will generate separate its
own signals I/O signals. That signals will be different from the memory signals which is
generated during the execution for memory instructions. Therefore, one more output pin will
be needed to carry I/O signals.
d. If an input and an output instruction can specify an 8-bit I/O port number, how many 8-bit I/O
ports can the microprocessor support? How many 16-bit I/O ports? Explain.
With an 8-bit I/O port number the microprocessor can support 2^8 = 256 8-bit input ports,
and 2^8 = 256 8-bit output ports.
With an 8-bit I/O port number the microprocessor can support 2^8 = 256 16-bit input ports,
and 2^8 = 256 16-bit output ports.
Thus, the size of the I/O port will not change the number of I/O ports since the number of I/O
ports depends on the number of bits which is used to represent the I/O port number (equals
to 8 bits in both cases).
10. Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-MHz input
clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four
input clock cycles. What is the maximum data transfer rate across the bus that this
microprocessor can sustain, in bytes/s? To increase its performance, would it be better to make
its external data bus 32 bits or to double the external clock frequency supplied to the
microprocessor? State any other assumptions you make, and explain. Hint: Determine the
number of bytes that can be transferred per bus cycle.
Since minimum bus cycle duration = 4 clock cycles and bus clock = 8 MHz
Then, maximum bus cycle rate = 8 M / 4 = 2 M/s
Data transferred per bus cycle = 16 bit = 2 bytes
Data transfer rate per second = bus cycle rate * data per bus cycle = 2 M * 2 = 4 Mbytes/sec.
To increase its performance:

- By doubling the frequency, it may mean adopting a new chip manufacturing technology
(assuming each instruction will have the same number of clock cycles);
- By doubling the external data bus, that means wider (may be newer) on-chip data bus
drivers/latches and modifications to the bus control logic.
Therefore, in the first situation the speed of the memory chips will need to double, not to slow
down the microprocessor. Regarding the second situation, the word length of the memory will
must double to be able to send/receive 32-bit quantities.
11. Consider a 32-bit microprocessor whose bus cycle is the same duration as that of a 16-bit
microprocessor. Assume that, on average, 20% of the operands and instructions are 32 bits long,
40% are 16 bits long, and 40% are only 8 bits long. Calculate the improvement achieved when
fetching instructions and operands with the 32-bit microprocessor.

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Tutorial 2:

1. What general categories of functions are specified by computer instructions?

- Instruction address calculation(iac): Determine the address of the next

Interrupt service routine(ISR) - priorities assigned to the different types of

4. What types of transfers must a computer’s interconnection structure (e.g., bus)

5. What is the benefit of using a multiple-bus architecture compared to a single-bus

8. Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two

2(32-8) = 224 = 16,777,216 bytes = 16 MB

To increase its performance:

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