Analysis of topologies of MOSFET Current Mirrors

Vinı́cius Betim Guimarães, Felipe Z. Righi, Lucas Compassi-Severo, Paulo C. C. de Aguirre and Alessandro Girardi
Computer Architecture and Microelectronics Group - GAMA
Federal University of Pampa - UNIPAMPA
Alegrete, Brazil
[email protected]

Abstract—Current mirrors are circuits widely used in mi- voltage where the output current reached 10 uA at a nominal
croelectronics, especially in analog IC design. They have as a supply voltage of 1.5 V.
principle the generation of a replica of the reference current at It is important to emphasise that in all cases the reference
the output node. This paper aims to conduct a comparative study
on different topologies of NMOS current mirrors, specifically current was fixed at 10 µA and the temperature of the
the Simple Current Mirror, the Cascode Current Mirror, and simulation was 27 ºC.
the Wilson Current Mirror. We analyze their electrical char- After, we changed the operating temperature to evaluate
acteristics concerning the channel width (W) of the transistors its effects on the three topologies. For this analysis, the
and operating temperature. The Cadence Virtuoso was used as temperature was set to 0 ºC and 70 ºC. The value of the output
a simulation tool, and the target process technology was 130 nm.
As a result, we found that by increasing the W of the transistors current was annotated when the voltage of the output node
the minimum output voltage decreases. Moreover, we noticed a reached the minimum value at a temperature of 27 ºC.
considered effect of temperature over the output current in the The minimum and maximum output voltages (Voutmin and
three topologies. Finally, it can be concluded that the current Voutmax ) are the minimum and maximum voltage values,
mirrors followed the expected patterns of the main literature respectively, that the output node must reach for the current
and converged in the direction of what represented the main
equations that command the MOSFETs transistors. mirror to function properly. These points are called the com-
Index Terms—Cascode current mirror, Simple current mirror, pliance voltages and define the compliance range, which is the
Wilson current mirror. range of the output voltage in which the current mirror will
operate properly. We define the compliance range as the output
I. I NTRODUCTION voltage range where the mirrored current is within Iref ±10%.
In analog IC design, the current mirror (CM) is an essential We also define the voltage V1 , which is the output voltage that
circuit and its structure is one of the most commonly used the current mirror produces when Iout = Iref . Fig. 1 shows
concepts. Current mirrors are simply an extension of the an example of how these points are determined. It illustrates
current sink/source and are widely used in analog circuits the variation of the output current of a current mirror as a
where current bias is affected by the supply voltage [1] [2]. function of the output voltage.
The CM uses the principle that if the gate-source potentials II. C URRENT MIRROR TOPOLOGIES
of two identical MOS transistors are equal, the drain currents
should be equal if no second-order effects are considered [3] This section describes the three topologies of current mirrors
[4]. studied in this work, including their main characteristics and
The application of current mirrors is wide-ranging and can electrical behavior.
be found in current amplification, biasing of active loads A. Simple Current Mirror
and level shifting [2] as well as in physiological stimulation
[5], current mode signal processing [6] [5] and biomedical The most basic topology of a current mirror is shown in
applications [7]. Fig.4. It represents the simplest way to copy the current with
Therefore, this paper analyzes three CM topologies: a MOS transistors. As mentioned earlier, the current mirror is
simple current mirror, a cascode current mirror, and a Wilson based on the principle that if identical MOS transistors have
current mirror. To analyze the effect of temperature on the the same gate-source voltage, their drain currents should also
current mirrors, we used three different sizes for the channel be the same [3]. That is, two identical MOS devices having
length (W ) of transistors for each topology: 900 nm, 1800 nm, equal gate-source voltages and operating in saturation will
and 2700 nm. carry equal currents [8]. This is possible because ideally the
We then performed an analysis of the behavior of the current principle that Id = f (VGS ) holds for the MOSFET in the
mirrors by changing the W values of the transistors from 900 saturation region.
nm to 9000 nm. This analysis examined the value of the output From this fact it can also be concluded that VGS = f − 1(Id ).
Thus, the current Iout in Fig. 4 can be written as a function
This work is supported by CNPq research agency. of Iref , since the VGS of both transistors are equal. Thus, if
 (a) Simple Current Mirror

Fig. 1: Determination of V1 , compliance voltage Voutmin and

the gate-source voltage of the reference transistor is replicated

GS2 − VT 2
Iref L W  V 2  1 + λV 
1 2 DS2
= · · (1)
Iout W1 L2 VGS1 − VT 1 1 + λVDS11
B. Cascode Current Mirror
Another way to copy a current is through the Cascode
current mirror, whose schematic is shown in Fig. 6. In practice,
the error caused by channel length modulation produces a sig-
nificant error of the copied current, especially when minimum
length transistors are used.
The Cascode current mirror reduces ratio errors due to
differences in output and input voltages. Its small-signal output Fig. 3: V out x Iout for different values of W for the Wilson
resistance is much greater than that of a simple current mirror. current mirror.
This can be seen from the equations representing the output
resistance of both current mirrors. Equation 2 models the
output resistance of the simple current mirror and equation C. Wilson current mirror
3 models the output resistance of the cascode current mirror,
Another topology of the current mirror that provides a more
showing that the output resistance of the cascode is larger than
constant output current is the Wilson current mirror, shown in
that of the simple current mirror [3] [9] [10].
Fig. 7. It provides a much more accurate input to output current
1 gain.
rout = (2)
gds The output resistance of the Wilson current mirror is in-
creased by using negative current feedback. If Iout increases,
rout = rds2 + rds4 + gm4 · rds2 · rds4 · (1 + η) (3) then the current through M2 also increases. The mirror effect
of M1 and M2 causes the current in M1 to increase.
 Vdd Vdd

Iout Iout
Iref Iref

Fig. 4: Simple current mirror.

Fig. 6: Cascode current mirror.

Vdd

Iout
Iref

(a) Rout X W (Simple current mirror).

Fig. 7: Wilson current mirror.

gies studied.
It is important to emphasise that the channel length (L) of
the MOSFET transistors was fixed at 130 nm in all cases.
In the first round of simulation, a temperature of 27 ºC and a
VDD of 1.5 V were used. A sweep of the output voltage from 0
to VDD was considered in the simulation. The voltage values
at the output were recorded when the current Iout reached
(b) Rout X W (Cascode current mirror).
exactly 10 µA, indicating the values of V1 . The simulations
were repeated for W 900 nm to 9000 nm
After that, we kept VDD at 1.5 V and changed the tem-
perature to 0 ºC and 70 ºC. In this situation, the value of the
current Iout was extracted at the same V1 as in the previous
cases. For this case, the simulations were repeated for W =
900 nm, 1800 nm and 2700 nm.
A. Load sensitivity
We analyze the effect of load variations on the value of the
copied current. Fig.2 shows the case where the transistor W
(c) Rout X W (Wilson Current Mirror values were changed from 900 nm to 9000 nm, which was
Fig. 5: Output resistance in function of W for the three applied to the studied current mirrors. For this situation, V1
topologies of current mirror. represents the voltage when the current Iout reaches 10 µA,
in addition to V1 min and V1 max represents the change of
Iout in ±10%.
If Iref is constant and we assume that there is some An important fact to point out regarding the Wilson current
resistance between the gate of M3 (drain of M1) and the mirror is that it is designed for Iout = Iref /2, i.e., the expected
ground, the gate voltage of M3 decreases as the current Iout Iout is 5 µA because Iref is 10 µA. Thus, for the Wilson
increases. This configuration increases the output resistance of current mirror case, the voltage V1 was recorded when the
the current mirror. current Iout reached the value of 5 µA.
It is possible to point out that the Simple Current Mirror
III. S IMULATION R ESULTS has the smaller V1 , but the smaller compliance range.
This section presents the electrical simulation results for the Choosing V1 with a value of 1V , one can observe in Fig.5
experiments performed with the three current mirror topolo- that the simple current mirror has a Rout that is more sensitive
to the changes of W than the cascode current mirror and the TABLE I: Simulated results for 3 values of temperature and
Wilson current mirror. The Cascode Current Mirror, on the VDD fixed in 1.5 V.
other hand, has a larger V1 and a larger compliance range, Temperature = 27 ºC
along with a larger output resistance. Iout rout
Simple W=900 n 10 uA 121.21 kΩ
Another point is that the value of V1 for the simple current Current W=1800 n 10 uA 99.70 kΩ
mirror and the Cascode Current Mirror decreases when the Mirror W=2700 n 10 uA 90.99 kΩ
value of W is increased. This happens because of the relation- Cascode W=900 n 10 uA 2111.16 kΩ
Current W=1800 n 10 uA 1377.01 kΩ
ship between the current Iref and Iout shown in equation 1. Mirror W=2700 n 10 uA 1681.11 kΩ
Increasing W decreases the value of VGS required to produce Wilson W=900 n 5 uA 617.28 kΩ
the same drain current, and the same happens with the output Current W=1800 n 5 uA 751.87 kΩ
Mirror W=2700 n 5 uA 847.45 kΩ
transistor saturation voltage. Temperature = 0 ºC
In addition, another compelling fact is highlighted and Iout rout
illustrated in Fig.7, where it is possible to note that with a Simple W=900 n 9.63 uA 121.50 kΩ
Current W=1800 n 9.60 uA 100.20 kΩ
smaller W, it takes less voltage (V1) to reach the desired Iout, Mirror W=2700 n 9.57 uA 90.66 kΩ
in this case of 5uA, compared to a W of 9000n. The larger Cascode W=900 n 8.75 uA 2272.72 kΩ
the size of the W, the higher the value of V1 to reach 5 µA. Current W=1800 n 8.99 uA 1886.79 kΩ
Mirror W=2700 n 9.08 uA 1754.38 kΩ
Wilson W=900 n 4.73 uA 662.25 kΩ
B. Iout sensitivity to temperature Current W=1800 n 4.42 uA 793.65 kΩ
Mirror W=2700 n 4.01 uA 1010.40 kΩ
Temperature = 70 ºC
Table I shows the case where the temperature at which Iout rout
the current mirrors were simulated is varied. The applied Simple W=900 n 10.55 uA 120.77 kΩ
temperature was 27 ºC, 0 ºC, and 70 ºC. In these situations, Current W=1800 n 10.60 uA 99.60 kΩ
we observed the value of Iout when the output voltage is equal Mirror W=2700 n 10.62 uA 91.57 kΩ
Cascode W=900 n 11.57 uA 2000 kΩ
to the value of V1 obtained in the previous experiment. Current W=1800 n 11.44 uA 1754.38 kΩ
When the temperature drops to 0 ºC, a decrease in output Mirror W=2700 n 11.39 uA 1639.34 kΩ
Wilson W=900n 7.09 uA 568.18 kΩ
current values is observed in all cases. On the other hand, when Current W=1800 n 6.52 uA 704.22 kΩ
the temperature increases to 70 ºC, one can see an increase Mirror W=2700 n 6.32 uA 793.65 kΩ
in the output current. This is because the current mirrors are
biased with low currents and the values of VGS are close to
VT . The increase in temperature reduces the threshold voltage
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