Exp. 10 Flip-Flop

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Course: ECE 203 Experiment No.

: 10

Group No.: 4 Section: ECE22S1

Members: Date Performed: 05/07/2024

CELESTE, Maria Geecel T. Date Submitted: 05/16/2024

CHICANO, Orlando Instructor: Engr. Cayetano Hiwatig

GERONILLA, Kevin Ryan Honor Pledge:


“I accept responsibility for my role in
GRAJO, Gabriel M. ensuring the integrity of the work
submitted by the group in which i
TELADA, Rapp Norris T. participated”

Objective(s):
● Keep the output logic state unchanged for finite intervals of time
● Define the synchronous and the asynchronous inputs of a flip-flop
● Understand the operation of the flip-flop of type D and T and know how to carry
out them starting from a JK flip-flop
● Knowing how to read and compile the state tables, the state diagrams and the
time diagrams of devices

Data and Results:

3.3 S-R Flip-Flop with NOR operators

INPUTS PRES OUTPUTS


ENT
STAT
E

S R Q0 Q Q

0 0 0 0 1

0 0 1 1 0

0 1 0 0 1
0 1 1 0 1

1 0 0 1 0

1 0 1 1 0

1 1 0 x x

1 1 1 x x

3.4 S-R Flip-Flop with NAND operators

INPUTS PRES OUTPUT


ENT
STAT
E

S R Q0 Q Q

0 0 0 x x

0 0 1 x x

0 1 0 1 0

0 1 1 1 0

1 0 0 0 1

1 0 1 0 1

1 1 0 0 1

1 1 1 1 0
S-R Flip-Flop with NAND operators
https://www.tinkercad.com/things/9vKKJC7qK3l-sr-ff-nand?
sharecode=IjhqEXN-
zjY0PdUvRldBxNWxbYCmt0G00BP3bvdOyR4&fbclid=IwAR147YXSRxPtTTw0Cj
ZbEPHDoH609cY8zHF2sH4ZT_R2508waglA35TrF9U

3.6 MASTER-SLAVE J-K Flip-Flop

INPUT OUTPUT

CL PR C J K Q Q
R E
(R) (S)

0 1 x x x 0 1

1 0 x x x 1 0

0 0 x x x 1↑ 1↑

1 1 0 0 Q0 Q0

1 1 0 1 0 1

1 1 1 0 1 0

1 1 1 1 Q0 Q0
(TO
GG
LE)
J=0; K=0

J=0; K=1
J=1; K=0

J=1; K=1
https://www.tinkercad.com/things/ezUKHThqnoR-36-master-slave-jk-flipflop

3.7 T Flip-Flop
INPUTS OUTPUTS
CLR PRE
C Q Q
(R) (S)
0 1 X 0 1
1 0 X 1 0
0 0 X 1↑ 1↑
1 1 Q0 Q0

T Flip-Flop
https://www.tinkercad.com/things/a3h1GDUOF9z-t-ff?
sharecode=ownKRZ93bKzKodcQGQnCtHRqb5IbD7_cb27sIg43jvs&fbclid=IwAR
17cMp442EEHF_P8D5rmNV3tbwqTH2QCoOl47yVM-KzwBKcCYvQVMueqJQ

3.8 D Flip-Flop

INPUT OUTPUT

CLR (R) PRE (S) C D Q Q


0 1 x x 0 1

1 0 x x 1 0

0 0 x x 1↑ 1↑

1 1 ↑ 0 0 1

1 1 ↑ 1 1 0

1 1 ↑ x Q0 Q0

D Flip-Flop
https://www.tinkercad.com/things/5FiVzE5Jsdd-exp-10-38-d-flip-flop

Interpretation:

S-R Flip-Flop (Set-Reset Flip-Flop)


The S-R flip-flop is a basic type of flip-flop that has two inputs, S (Set) and R (Reset),
and two outputs, Q and Q’. It stores a single bit of data. When S is high (1) and R is
low (0), the flip-flop sets Q to 1. When S is low (0) and R is high (1), the flip-flop resets
Q to 0. When both S and R are low, the flip-flop retains its previous state. When both
S and R are high, the state is Invalid.

Master-Slave JK Flip-Flop
The master-slave JK flip-flop is an edge-triggered flip-flop designed to eliminate the
undefined state problem of the S-R flip-flop. It has two inputs, J and K, and two
outputs, Q and Q’. When both J and K are low, the output remains the same (no
change). When J is high and K is low, the output is set (Q = 1). When J is low and K is
high, the output is reset (Q = 0). When both J and K are high, the output toggles (Q
changes to Q’. The master section captures the input state on the leading edge of the
clock pulse, while the slave section updates the output on the trailing edge, for stable
operation.

T Flip-Flop (Toggle Flip-Flop)


The T flip-flop is a single input flip-flop used for toggling purposes, effectively
changing state on each clock cycle if the input T is high. When T is low (0), the flip-
flop retains its current state (no change). When T is high (1), the flip-flop toggles its
state (if Q was 0, it becomes 1; if Q was 1, it becomes 0). This type of flip-flop is often
used for binary counters.

D Flip-Flop (Data or Delay Flip-Flop)


The D flip-flop is designed to store a single bit of data and has one input, D (Data),
and two outputs, Q and Q’. It is known for its simplicity and reliability in ensuring no
undefined states. On the leading edge of the clock pulse, the state of the D input is
sampled and transferred to the output Q. Q will take the value of D (if D is 1, Q
becomes 1; if D is 0, Q becomes 0).

Conclusion:

In this experiment, flip-flops are used primarily for data storage, binary counting, and
state machine implementation. For the S-R Flip-Flop, it has basic set and reset
functions with a potential undefined state. For Master-Slave JK Flip-Flop, it eliminates
undefined states and provides stable toggle functionality. While T Flip-Flop efficiently
toggles states, which is ideal for counters. And D Flip-Flop are reliable single-bit data
storage, for data transfer and storage applications. They form the building blocks of
memory elements in computers, enable frequency division, and facilitate
synchronization of signals. These flip-flops are also needed in shift registers for data
transfer, debouncing mechanical switches, and creating timers and delays.

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