Power Electronics

(EEE / INSTR F 342)

BITS Pilani Prof. Dheerendra Singh

Pilani Campus
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 BITS Pilani
Pilani Campus

EEE / INSTR F 342 ( Power Electronics)

Module -2 (DC – DC Converter )
Lecture - 5
Out Line :
 Recap
 CUK’ Converter
Ckt. Analysis /Design
Relationship of Ripple in
Current
Voltage

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 ሖ
𝑪𝑼𝑲 𝑪𝑶𝑵𝑽𝑬𝑹𝑻𝑬𝑹
(CCM operation)
This topic is covered from book:
(1) Robert W. Erickson, Dragan Maksimovic, Fundamental Power Electronics: 2nd edit. Springer
International, 2001

Chapter 2 Section 2.4

CUK Converter
The CUK, essentially a BOOST-BUCK converter, may not be considered as basic converter along with its variations: the
SEPIC and the zeta converters.

Features of a buck converter are

 Pulsed input current, requires input filter.
 Continuous output current results in lower output voltage ripple.
 Output voltage is always less than input voltage.

Features of a boost converter are

 Continuous input current, eliminates input filter.
 Pulsed output current increases output voltage ripple.
 Output voltage is always greater than input voltage.

Features of a buck - boost converter are

 Pulsed input current, requires input filter
 Pulsed output current increases output voltage ripple
 Output voltage can be either greater or smaller than input voltage.
What is different in CUK Converter in comparison to basic DC-DC converter?

It will be desirable to combine the advantages of these basic converters into one converter. CuK converter is one such
converter. It has the following advantages.

 Continuous input current

 Continuous output current
 Output voltage can be either greater or less than input voltage.
REALIZATION OF CUK CONVERTER USING BUCK-BOOST CONVERTER
CuK converter is actually the cascade combination of a boost and a buck converter
Analysis of CUK Converter for ON-time of transistor,

Without Small-ripple approximation,

𝒗𝑳𝟏 = 𝑽𝒈
𝒗𝑳𝟐 = −𝒗𝟏 − 𝒗𝟐
𝒊𝑪𝟏 = 𝒊𝟐
𝒗𝟐
𝒊𝑪𝟐 = 𝒊𝟐 −
Transistor is ON 𝑹
Diode is OFF With Small-ripple approximation,
𝒗𝑳𝟏 = 𝑽𝒈
𝒗𝑳𝟐 = −𝑽𝟏 − 𝑽𝟐
𝒊𝑪𝟏 = 𝑰𝟐
𝑽𝟐
𝒊𝑪𝟐 = 𝑰𝟐 −
𝑹
Analysis of CUK Converter for OFF-time of transistor,

Without Small-ripple approximation,

𝒗𝑳𝟏 = 𝑽𝒈 − 𝒗𝟏
𝒗𝑳𝟐 = −𝒗𝟐
𝒊𝑪𝟏 = 𝒊𝟏
𝒗𝟐
Transistor is OFF 𝒊𝑪𝟐 = 𝒊𝟐 −
𝑹
Diode is ON With Small-ripple approximation,
𝒗𝑳𝟏 = 𝑽𝒈 − 𝑽𝟏
𝒗𝑳𝟐 = −𝑽𝟐
𝒊𝑪𝟏 = 𝑰𝟏
𝑽𝟐
𝒊𝑪𝟐 = 𝑰𝟐 −
𝑹
Waveform of Inductor Voltages

𝒗𝑳𝟏 = 𝑽𝒈 𝒗𝑳𝟏 = 𝑽𝒈 − 𝑽𝟏

𝒗𝑳𝟐 = −𝑽𝟏 − 𝑽𝟐

𝒗𝑳𝟐 = −𝑽𝟐
Waveform of Inductor Voltages

𝒊𝑪𝟏 = 𝑰𝟐 𝒊𝑪𝟏 = 𝑰𝟏

𝑽𝟐 𝑽𝟐
𝒊𝑪𝟐 = 𝑰𝟐 − 𝒊𝑪𝟐 = 𝑰𝟐 −
𝑹 𝑹
Inductor Volt-sec Balance Principle
𝑽𝒈 𝑫𝑻𝒔 + 𝑽𝒈 − 𝑽𝟏 𝟏 − 𝑫 𝑻𝒔 = 𝟎
𝑽𝒈
𝑽𝟏 =
(𝟏 − 𝑫)

(−𝑽𝟏 −𝑽𝟐 )𝑫𝑻𝒔 + −𝑽𝟐 𝟏 − 𝑫 𝑻𝒔 = 𝟎

𝑫𝑽𝒈
𝑽𝟐 = −
(𝟏 − 𝑫)

Capacitor Amp-sec balance Principle

𝑽𝟐 𝑽𝟐
(𝑰𝟐 − )𝑫𝑻𝒔 + (𝑰𝟐 − ) 𝟏 − 𝑫 𝑻𝒔 = 𝟎
𝑹 𝑹
𝑽𝟐 𝑫𝑽𝒈
𝑰𝟐 = =−
𝑹 𝟏−𝑫 𝑹

𝑰𝟐 𝑫𝑻𝒔 + 𝑰𝟏 𝟏 − 𝑫 𝑻𝒔 = 𝟎
𝑫𝑰𝟐 𝑫 𝟐 𝑽
𝒈
𝑰𝟏 = − =
𝟏−𝑫 𝟏−𝑫 𝑹

Note: These are some of important mathematical relations

Conversion Ratio for Cuk Converter

𝑫𝑽𝒈
𝑽𝟐 = −
(𝟏 − 𝑫)
Inductor Current(s) and capacitor voltage
Inductor Current(s) and capacitor voltage
ON-Time of Transistor
𝒅𝒊𝟏 𝒗𝑳𝟏 𝑽𝒈
= =
𝒅𝒕 𝑳𝟏 𝑳𝟏

𝒅𝒊𝟐 𝒗𝑳𝟐 −𝑽𝟏 − 𝑽𝟐

= =
𝒅𝒕 𝑳𝟐 𝑳𝟐

𝒅𝒗𝟏 𝒊𝑪𝟏 𝑰𝟐
= =
𝒅𝒕 𝑪𝟏 𝑪𝟏

OFF-Time of Transistor
𝒅𝒊𝟏 𝒗𝑳𝟏 𝑽𝒈 − 𝑽𝟏
= =
𝒅𝒕 𝑳𝟏 𝑳𝟏

𝒅𝒊𝟐 𝒗𝑳𝟐 −𝑽𝟐

= =
𝒅𝒕 𝑳𝟐 𝑳𝟐

𝒅𝒗𝟏 𝒊𝑪𝟏 𝑰𝟏
= =
𝒅𝒕 𝑪𝟏 𝑪𝟏
Ripple component: Inductor Current(s) and capacitor voltage
𝑽𝒈 𝑫𝑻𝒔
∆𝒊𝟏 =
𝟐𝑳𝟏
𝑽𝟏 + 𝑽𝟐
∆𝒊𝟐 = 𝑫𝑻𝒔
𝟐𝑳𝟐
−𝑰𝟐 𝑫𝑻𝒔 𝑫𝑽𝒈
𝑰𝟐 = −
∆𝒗𝟏 = 𝟏−𝑫 𝑹
𝟐𝑪𝟏
Eliminate V1 and V2,
𝑽𝒈 𝑫𝑻𝒔
∆𝒊𝟏 =
𝟐𝑳𝟏
𝑽𝒈 𝑫𝑻𝒔
∆𝒊𝟐 =
𝟐𝑳𝟐
𝑽𝒈 𝑫𝟐 𝑻𝒔
∆𝒗𝟏 =
𝟐 𝟏 − 𝑫 𝑹𝑪𝟏
CUK CONVERTER

𝑫𝑽𝒈
𝑶𝒖𝒕𝒑𝒖𝒕 𝒗𝒐𝒍𝒕𝒂𝒈𝒆, 𝑽𝟐 = −
𝟏−𝑫
𝑽𝟐 𝑫
M(D)= =−
𝑽𝒈 (𝟏−𝑫)

SEPIC CONVERTER

𝑫𝑽𝒈
𝑶𝒖𝒕𝒑𝒖𝒕 𝒗𝒐𝒍𝒕𝒂𝒈𝒆, 𝑽𝟐 =
𝟏−𝑫
𝑽𝟐 𝑫
M(D)= =
𝑽𝒈 (𝟏−𝑫)
Transistor ON, Diode OFF Transistor OFF, Diode ON
 BITS Pilani
Pilani Campus

EEE / INSTR F 342 ( Power Electronics)

Module -2 (DC – DC Converter )
Lecture - 6
Out Line :
 Recap
 Non-ideal Boost Converter
Ckt. Analysis After inclusion of non
ideal component (Inductor Copper Loss)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Boost Converter Analysis: Inclusion of Inductor copper loss
How inclusion of non-ideal components (here inductance with ESR) in converter
affect its performance?

Note: Analysis of any converter (for non-ideal or ideal case)

can be done using,
(1)Inductor Volt-second (flux-linkage) balance
(2)Capacitor Amp-second (Charge) balance
(3)Small Ripple Approximation
On-time and OFF-time Equivalent Circuits

MOSFET MOSFET
ON, OFF,
DIODE DIODE
OFF ON
ON-Time of controlled switch (Ton=DTs) Analysis
OFF-Time of controlled switch (Toff=(1-D)Ts) Analysis
USE PRINCIPLES (IVSB and CASB)
Principle#1 Inductor volt-second (flux-linkage) balance
𝑻𝒔
න 𝒗𝑳 𝒅𝒕 = 0
𝟎
(𝑽𝒈 − 𝑰𝑹𝑳 ) ∗ 𝑫𝑻𝒔 + (𝑽𝒈 − 𝑰𝑹𝑳 − 𝑽) ∗ (𝟏 − 𝑫)𝑻𝒔 =0

𝑽𝒈 − 𝑰𝑹𝑳 − 𝑽 = 𝟎
Principle#1 Capacitor Amp-second (Charge) balance
𝑻𝒔
න 𝒊𝑪 𝒅𝒕 = 0
𝟎
𝑽 𝑽
− ∗ 𝑫𝑻𝒔 + (𝑰 − ) ∗ (𝟏 − 𝑫)𝑻𝒔 =0
𝑹 𝑹

𝑽
(𝟏 − 𝑫)𝑰 − =𝟎
𝑹
Relation between average output voltage and average input voltage
Effect of inductor Equivalent Series Resistance (ESR) (parasitic resistance) on BOOST FACTOR

Boost factor is less for high

𝑹
value of 𝑹𝑳 or high value of
𝑹𝑳 while keeping R constant
 BITS Pilani
Pilani Campus

EEE / INSTR F 342 ( Power Electronics)

Module -2 (DCM of DC – DC Converter )
Lecture - 7
Out Line :
 Recap
 DCM of Buck Converter

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 DISCONTINOUS CONDUCTION MODE (DCM)

What are the possible reasons for DCM?

(1) A large switching ripple in inductor current or capacitor voltage
(2) Light load operation (High value of resistance/impedance at load). The Light
load condition generally arises when load is removed frequently.
(3) Low switching frequency

Is it desirable? Yes, sometimes the converters are purposely designed for DCM
operation

Some properties of DCM operated converters:

(1) The conversion ratio ,M becomes load-dependent
(2) The output impedance of the converter increases
(3) Control of output may be lost when load is removed
Inductor Ripple DOES NOT depends on Load Resistance (R)

𝑽
𝑰=
𝑹
Inductor Ripple DOES NOT depends on Load Resistance (R)

𝑽
𝑰=
𝑹

Inductor Ripple depends,

(1) Applied voltages
(2) Inductance value
(3) Conduction time of Transistor, 𝑫𝑻𝒔

Note: Inductor Ripple depends on

Voltages BUT NOT on Currents.

Clearly, Inductor ripple does not

depends on load resistance (R).
Lets Analyze “How the Inductor current and Diode Current Change” with Reduction in
Load Power (Increase in load Resistance, R)?

Boundary condition b/w CCM and DCM

What would happen if load resistance (R)

further increases?
Note: Diode is second-quadrant operation switch
DCM Operation of Buck Converter

For CCM

Boundary of CCM and DCM

For DCM

For DCM
 DCM Operation of Buck Converter (continued…)
For DCM

𝑲 = 𝑲𝒄𝒓𝒊𝒕 (𝑫)

𝑲 < 𝑲𝒄𝒓𝒊𝒕 (𝑫)

For a given DC-DC converter with constant values of L, R, Ts, the

parameter K is also a constant and 𝑲𝒄𝒓𝒊𝒕 (𝑫) depends on duty
ratio (D).
Relation BETWEEN Dimension-less Parameters (K,K’(D)) with Duty Ratio, D

Note: 𝑩𝒖𝒄𝒌 𝒄𝒐𝒏𝒗𝒆𝒓𝒕𝒆𝒓 𝒐𝒑𝒆𝒓𝒂𝒕𝒆𝒔 𝒊𝒏 𝑪𝑪𝑴 𝒊𝒇 𝑲 > 𝑲𝒄𝒓𝒊𝒕 (𝑫)

 Critical Resistance (at the boundary of CCM and DCM)
DCM OPERATION

𝑲 < 𝑲𝒄𝒓𝒊𝒕 (𝑫)

For given duty ration, the Critical Resistance,

𝑹 > 𝑹𝒄𝒓𝒊𝒕 𝑫
𝟐𝑳
𝑹𝒄𝒓𝒊𝒕 𝑫 =
(𝟏 − 𝑫)𝑻𝒔

Conclusion: Load Resistance more than CRITICAL RESISTANCE leads to DCM

operation
Analysis of Conversion Ratio M(D,K) in DCM mode

+
𝑣𝐷 (𝑡)
-
Principles:
Inductor volt-second (Flux-linkage) balance
𝑻𝒔
𝟏 𝑻𝒔
න 𝒗𝑳 𝒅𝒕 = 0 < 𝒗𝑳 > න 𝒗𝑳 𝒅𝒕 = 0
𝟎 𝑻𝒔 𝟎

Capacitor Amp-second (Charge) balance

𝑻𝒔 𝟏 𝑻𝒔
න 𝒊𝑪 𝒅𝒕 = 0 < 𝒊𝑪 > න 𝒊𝑪 𝒅𝒕 = 0
𝑻𝒔 𝟎
𝟎
Small-ripple Approximation:
(a) Capacitor Voltage ripple can be neglected

𝒗 = 𝑽 + 𝒗𝒓𝒊𝒑𝒑𝒍𝒆
𝒗≈𝑽
(b) Inductor current ripple is quite high therefore can not be neglected

𝒊𝑳 = 𝑰 + 𝒊𝑳𝒓𝒊𝒑𝒑𝒍𝒆
𝒊𝑳𝒓𝒊𝒑𝒑𝒍𝒆 𝒊𝒔 𝒍𝒂𝒓𝒈𝒆
𝒊𝑳 ≠ 𝑰
Analysis of Buck Converter for a cycle:
(1) Time interval is
𝟎 < 𝒕 < 𝑫𝟏 𝑻𝒔 (𝑻𝑹𝑨𝑵𝑺𝑰𝑺𝑻𝑶𝑹 𝑶𝑵, 𝑫𝑰𝑶𝑫𝑬 𝑶𝑭𝑭)

𝒗≈𝑽
𝒗𝑳 = 𝑽𝒈 − 𝐕
𝑽
𝒊𝑪 ≈ 𝒊𝑳 −
𝑹

NOTE the time interval is 𝟎 < 𝒕 < 𝑫𝟏 𝑻𝒔

𝒃𝒆𝒍𝒐𝒏𝒈𝒔 𝒕𝒐 𝑶𝑵 𝒕𝒊𝒎𝒆 𝒐𝒇 𝑻𝒓𝒂𝒏𝒔𝒊𝒔𝒕𝒐𝒓
Analysis of Buck Converter for a cycle:
(2) Time interval is 𝑫𝟏 𝑻𝒔 < 𝒕 < (𝑫𝟏 + 𝑫𝟐 )𝑻𝒔 𝑻𝑹𝑨𝑵𝑺𝑰𝑺𝑻𝑶𝑹 𝑶𝑭𝑭, 𝑫𝑰𝑶𝑫𝑬 𝑶𝑵

𝒗≈𝑽 𝑽
𝒗𝑳 = 𝟎 − 𝐕 𝒊𝑪 ≈ 𝒊𝑳 −
𝑹

NOTE the time interval is 𝑫𝟏 𝑻𝒔 < 𝒕 < (𝑫𝟏 + 𝑫𝟐 )𝑻𝒔

𝒃𝒆𝒍𝒐𝒏𝒈𝒔 𝒕𝒐 𝑶𝑭𝑭 𝒕𝒊𝒎𝒆 𝒐𝒇 𝑻𝒓𝒂𝒏𝒔𝒊𝒔𝒕𝒐𝒓
Analysis of Buck Converter for a cycle:

(2) Time interval is (𝑫𝟏 +𝑫𝟐 )𝑻𝒔 < 𝒕 < 𝑻𝒔 𝑻𝑹𝑨𝑵𝑺𝑰𝑺𝑻𝑶𝑹 𝑶𝑭𝑭, 𝑫𝑰𝑶𝑫𝑬 𝑶𝑭𝑭

This is the time when

Diode become
reverse-biased
𝒂𝒕 𝒕 = (𝑫𝟏 + 𝑫𝟐 )𝑻𝒔

𝒗𝑳 = 𝟎
𝒊𝑳 = 𝟎
𝑽
𝒊𝑪 ≈ −
𝑹

NOTE the time interval is(𝑫𝟏 +𝑫𝟐 )𝑻𝒔 < 𝒕 < 𝑻𝒔

𝒃𝒆𝒍𝒐𝒏𝒈𝒔 𝒕𝒐 𝑶𝑭𝑭 𝒕𝒊𝒎𝒆 𝒐𝒇 𝑻𝒓𝒂𝒏𝒔𝒊𝒔𝒕𝒐𝒓 𝒂𝒈𝒂𝒊𝒏
 Inductor volt-second (Flux-linkage) balance: First equation
𝑻𝒔
න 𝒗𝑳 𝒅𝒕 = 0
𝟎

(𝑽𝒈 − 𝑽)𝑫𝟏 𝑻𝒔 − 𝑽𝑫𝟐 𝑻𝒔 + 𝟎. 𝑫𝟑 𝑻𝒔 = 𝟎

This is the time when
𝑽 𝑫𝟏 Diode become
reverse-biased
= = 𝐌(𝐃) 𝒂𝒕 𝒕 = (𝑫𝟏 + 𝑫𝟐 )𝑻𝒔
𝑽𝒈 𝑫𝟏 + 𝑫𝟐

𝑫𝟏 𝒊𝒔 𝒌𝒏𝒐𝒘𝒏 𝒃𝒖𝒕 𝑫𝟐 𝒊𝒔 𝒖𝒏𝒌𝒏𝒐𝒘𝒏 𝒕𝒉𝒆𝒓𝒆𝒇𝒐𝒓𝒆,

𝑫𝟐 𝒔𝒉𝒐𝒖𝒍𝒅 𝒃𝒆 𝒆𝒍𝒆𝒎𝒊𝒏𝒂𝒕𝒆𝒅
Note: We know the time-interval for which transistor is ON and also the time-interval for
which transistor is OFF but don’t know the instant at which both Diode and Transistor turn-
off.
Note: Average Inductor Current is equal to Average load current in
Buck Converter

Ideally,
Average input or average transistor current
Average inductor (output) current =
𝑫
 Capacitor Amp-second (Flux-balance) balance: second equation

𝑻𝒔
න 𝒊𝑪 𝒅𝒕 = 0
𝟎

𝒅𝒊𝑳 𝑽𝒈 − 𝑽
=
𝒅𝒕 𝑳
Peak inductor current (𝒊𝑳𝒑 )= Slop X time
𝒅𝒊𝑳 𝑽𝒈 −𝑽
= 𝑫 𝑻 = 𝑫𝟏 𝑻𝒔
𝒅𝒕 𝟏 𝒔 𝑳
𝟏 𝑻 𝑖𝐶 (𝑡)
Average inductor current, 𝑻 ‫𝒕𝒅 𝑳𝒊 𝒔 𝟎׬‬
𝒔

𝟏 𝑻𝒔 𝟏
න 𝒊 𝒅𝒕 = 𝒊 (𝑫 + 𝑫𝟐 )𝑻𝒔
𝑻𝒔 𝟎 𝑳 𝟐 𝑳𝒑 𝟏

𝑽 𝟏 𝑽𝒈 − 𝑽
𝑰= = ( 𝑫𝟏 𝑻𝒔 )(𝑫𝟏 + 𝑫𝟐 )
𝑹 𝟐 𝑳
𝑽 𝟏 𝑽𝒈 −𝑽
Second equation, = ( 𝑫𝟏 𝑻𝒔 )(𝑫𝟏 + 𝑫𝟐 )
𝑹 𝟐 𝑳

First equation 𝑽 𝑫𝟏
=
𝑽𝒈 𝑫𝟏 + 𝑫𝟐
Eliminate 𝑫𝟐 (𝑼𝒏𝒌𝒏𝒐𝒘𝒏)

𝑽 𝑫𝟏
First equation, =
𝑽𝒈 𝑫𝟏 + 𝑫𝟐
𝑽 𝟏 𝑽𝒈 −𝑽
Second equation, = ( 𝑫𝟏 𝑻𝒔 )(𝑫𝟏 + 𝑫𝟐 )
𝑹 𝟐 𝑳

𝑽 𝟐 𝟐𝑳
𝑴 𝑫, 𝑲 = = Here, 𝑲 =
𝑽𝒈 𝑹𝑻𝒔
𝟒𝑲
𝟏+ 𝟏+
𝑫𝟐𝟏

Note: This conversion ratio, M(D,K) is valid for, 𝑲 < 𝑲𝒄𝒓𝒊𝒕 𝒐𝒓 𝑹 >
𝑹𝒄𝒓𝒊𝒕 i.e for DCM conditions
Conversion ratio, M(D,K) versus Duty ratio (D), here D is
equal to 𝐃𝟏

𝑽 𝟐
𝑴 𝑫, 𝑲 = =
𝑽𝒈
𝟒𝑲
𝟏+ 𝟏+ 𝟐
𝑫𝟏

𝟐𝑳
Here, 𝑲 =
𝑹𝑻𝒔
Buck Converter : DCM
Ripple increases with decrease in L, increase in Ts , and decrease in avg.
current. ( change in values to the avg. current )

In DCM , a third state exist -- in this neither transistor nor diode conduct,
inductor current comes to zero , this can not reverse because of diode in series.
T1 = Switch is ON, Diode is OFF
T2 = Switch is OFF, Diode is ON
T3 = Switch is OFF, Diode is OFF
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Applying Volt. – Sec. Balance or Avg. Ind. Volt. Equal to zero

T1 + T2+ T3 = TS
=> Out put
> d voltage in DCM is
greater than that
d + d2 < 1 of CCM

Resolving d2 in terms of d
I0 = IL = 1/2 * IP (d+d2)
IP = d2. Ts .V0 / L

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 I0 = IL = 1/2 * IP (d+d2) = V0 / R
IP = d2. Ts .V0 / L
1/2 * d2. Ts .V0 (d+d2) / L = V0 / R On simplifying
d2. (d+d2) = 2L / TS R = K (Conduction Parameters) - - -
On simplifying the quadratic equation of d2

Voltage Gain

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

On the Border of DCM & CCM
d + d2 = 1 , => d2(d+d2) = (1-d) & K = 2.L / R.Ts So

When K < (1-d) or Kcri ---- Operation is DCM and if

When K > (1-d) or Kcri ---- Operation is CCM
So, Kcri = (1-d) ---- On the verge of CCM Plot of Kcri. Vs D

Blue portion K< Kcri. , So

mode of operation DCM.

Yellow portion K > Kcri. , So

mode of operation CCM.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Plot of Kcri. Vs D , Vs Voltage Gain

Voltage Gain is more in DCM,

Salient features of DCM

1. Zero (Low) Turn ON losses

– since current starts from zero
so zero turn ON loss.
2. Soft Diode recoverery. ---
Diode current gets zero during
off period
3. Low ckt. Inductance
4. High Inductor current
ripple ---- Disadvantage

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

EEE / INSTR F 342 ( Power Electronics)

Module -2 (DCM of DC – DC Converter )
Lecture - 8
Out Line :
 Recap
 DCM of Boost Converter

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Boost Converter : DCM

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Applying Volt. – Sec. Balance or Avg. Ind. Volt. Equal to zero

VG T1 + (VG – V0 ) T2 = 0

(d+ d2) VG = V0 d2
=> Out put voltage in
V0 / VG = d2 / (d+ d2) >1/(1- d) DCM is greater than that
d + d2 < 1 of CCM

Resolving d2 in terms of d

I0 = V0 / R = 1/2 * IP .d2
IP = d. Ts .VG / L

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

I0 = 1/2 * IP d2 = V0 / R
IP = d. Ts .V0 / L
On simplifying
K (d+d2) = d. d2. d2 ; where K= 2L /TS R (Conduction Parameters)
On simplifying the quadratic equation of d2 and relating with K

Voltage Gain

>1/(1- d)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

On the Border of DCM & CCM
d + d2 = 1 , => K(d+d2) = d(d2)2 ; d2 = (1-d) & K = 2.L / R.Ts So

When K < d.(1-d)2 or Kcri ---- Operation is DCM and if

When K > Kcri ---- Operation is CCM
So, K= Kcri = d.(1-d)2 ---- On the verge of CCM
Plot of Kcri. Vs D

Blue portion K< Kcri. , So

mode of operation DCM.

White portion K > Kcri. , So

mode of operation CCM.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Conversion ratio, M(D,K) versus Duty ratio (D), here D is equal to 𝐃𝟏

𝟒𝑫𝟐𝟏
𝑽 𝟏+ 𝟏+ 𝑲
𝑴 𝑫, 𝑲 = =
𝑽𝒈 𝟐

𝟐𝑳
Here, 𝑲 =
𝑹𝑻𝒔

Conclusion: DCM operation of boost

converter leads to increase in output
voltage. The conversion ratio is almost
linear in DCM mode and can be
approximated by,
𝟏 𝑫
M(D,K)= + 𝟏
𝟐 𝑲
Plot of Kcri. Vs D , Vs Voltage Gain

Voltage Gain is more in DCM,

Salient features of DCM

1. Zero (Low) Turn ON losses

– since current starts from zero
so zero turn ON loss.
2. Soft Diode recoverery. ---
Diode current gets zero during
off period
3. Low ckt. Inductance
4. High Inductor current
ripple ---- Disadvantage

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Boost Converter Operation in DCM
Inductor volt-second (Flux-linkage) balance

OFF-Time equivalent circuit:

ON-Time equivalent circuit: OFF-Time equivalent circuit:
Transistor OFF, Diode ON
Transistor ON, Diode OFF Transistor OFF, Diode OFF
Boost Converter Operation in CCM
On-Time equivalent Circuit of Boost Converter Operation in DCM
OFF-Time equivalent Circuit of Boost Converter Operation in DCM
Analysis of Boost Converter for a complete time-period
(1) Time interval is 𝟎 < 𝒕 < 𝑫𝟏 𝑻𝒔 (𝑻𝑹𝑨𝑵𝑺𝑰𝑺𝑻𝑶𝑹 𝑶𝑵, 𝑫𝑰𝑶𝑫𝑬 𝑶𝑭𝑭)

𝒗𝑳 = 𝑽𝒈
𝑽
𝒊𝑪 ≈ 𝟎 − 𝒗≈𝑽
𝑹
NOTE the time interval is 𝟎 < 𝒕 < 𝑫𝟏 𝑻𝒔
𝒃𝒆𝒍𝒐𝒏𝒈𝒔 𝒕𝒐 𝑶𝑵 𝒕𝒊𝒎𝒆 𝒐𝒇 𝑻𝒓𝒂𝒏𝒔𝒊𝒔𝒕𝒐𝒓
Analysis of Boost Converter for a cycle:
(2) Time interval is 𝑫𝟏 𝑻𝒔 < 𝒕 < (𝑫𝟏 + 𝑫𝟐 )𝑻𝒔 𝑻𝑹𝑨𝑵𝑺𝑰𝑺𝑻𝑶𝑹 𝑶𝑭𝑭, 𝑫𝑰𝑶𝑫𝑬 𝑶𝑵

𝒗𝑳 = 𝑽 𝒈 − 𝐕
𝑽 𝒗≈𝑽
𝒊𝑪 ≈ 𝒊𝑳 −
𝑹
NOTE the time interval is 𝑫𝟏 𝑻𝒔 < 𝒕 < (𝑫𝟏 + 𝑫𝟐 )𝑻𝒔
𝒃𝒆𝒍𝒐𝒏𝒈𝒔 𝒕𝒐 𝑶𝑭𝑭 𝒕𝒊𝒎𝒆 𝒐𝒇 𝑻𝒓𝒂𝒏𝒔𝒊𝒔𝒕𝒐𝒓
Analysis of Boost Converter for a cycle:

(2) Time interval is (𝑫𝟏 +𝑫𝟐 )𝑻𝒔 < 𝒕 < 𝑻𝒔 𝑻𝑹𝑨𝑵𝑺𝑰𝑺𝑻𝑶𝑹 𝑶𝑭𝑭, 𝑫𝑰𝑶𝑫𝑬 𝑶𝑭𝑭

This is the time when

Diode become
reverse-biased
𝒂𝒕 𝒕 = (𝑫𝟏 + 𝑫𝟐 )𝑻𝒔

𝒗𝑳 = 𝟎
𝒊𝑳 = 𝟎
𝑽
𝒊𝑪 ≈ −
𝑹
NOTE the time interval is(𝑫𝟏 +𝑫𝟐 )𝑻𝒔 < 𝒕 < 𝑻𝒔
𝒃𝒆𝒍𝒐𝒏𝒈𝒔 𝒕𝒐 𝑶𝑭𝑭 𝒕𝒊𝒎𝒆 𝒐𝒇 𝑻𝒓𝒂𝒏𝒔𝒊𝒔𝒕𝒐𝒓 𝒂𝒈𝒂𝒊𝒏
 Inductor volt-second (Flux-linkage) balance
𝑻𝒔
න 𝒗𝑳 𝒅𝒕 = 0
𝟎

𝑽𝒈 𝑫𝟏 𝑻𝒔 + (𝑽𝒈 − 𝑽)𝑫𝟐 𝑻𝒔 + 𝟎. 𝑫𝟑 𝑻𝒔 = 𝟎

𝑽 𝑫𝟏 + 𝑫𝟐
= = 𝐌(𝐃)
𝑽𝒈 𝑫𝟐

𝑫𝟏 𝒊𝒔 𝒌𝒏𝒐𝒘𝒏 𝒃𝒖𝒕 𝑫𝟐 𝒊𝒔 𝒖𝒏𝒌𝒏𝒐𝒘𝒏 𝒕𝒉𝒆𝒓𝒆𝒇𝒐𝒓𝒆,

𝑫𝟐 𝒔𝒉𝒐𝒖𝒍𝒅 𝒃𝒆 𝒆𝒍𝒆𝒎𝒊𝒏𝒂𝒕𝒆𝒅
Note: We know the time-interval for which transistor is ON and also the time-interval for
which transistor is OFF but don’t know the instant at which both Diode and Transistor turn-
off.
Note: Average Diode Current is equal to Average load current in Boost Converter
Average diode current or average output current
Ideally, Average inductor (input) current= (𝟏−𝑫)
DCM Operation of Boost Converter Waveform for DCM
For CCM

Boundary of CCM and DCM

For DCM

I is the average current of inductor

DCM Operation of Boost Converter
Boundary of CCM and DCM (This condition gives critical value of R and K)

𝟐𝑳
𝑲= = 𝑫𝑫′𝟐 = 𝑫(𝟏 − 𝑫)𝟐 = 𝑲𝒄𝒓𝒊𝒕 (𝑫)
𝑹𝑻𝒔
For DCM
𝟐𝑳
𝑭𝒐𝒓 𝑪𝑪𝑴, > 𝑫(𝟏 − 𝑫)𝟐
𝟐𝑳 𝑹𝑻𝒔
< 𝑫(𝟏 − 𝑫)𝟐 𝑲 > 𝑲𝒄𝒓𝒊𝒕 (𝑫)
𝑹𝑻𝒔
𝑲 < 𝑲𝒄𝒓𝒊𝒕 (𝑫)
DCM Operation of Boost Converter
Critical value of Load Resistance,

𝟐𝑳
𝑹= = 𝑹𝒄𝒓𝒊𝒕 (D)
𝑫(𝟏−𝑫)𝟐 𝑻𝒔
For DCM

𝑭𝒐𝒓 𝑪𝑪𝑴,
𝑹 > 𝑹𝒄𝒓𝒊𝒕 (D) 𝑹 < 𝑹𝒄𝒓𝒊𝒕 (D)

𝑲 < 𝑲𝒄𝒓𝒊𝒕 (𝑫) 𝑲 > 𝑲𝒄𝒓𝒊𝒕 (𝑫)

 𝑲𝒄𝒓𝒊𝒕 𝒗𝒆𝒓𝒔𝒖𝒔 𝑫𝒖𝒕𝒚 𝑫 𝒇𝒐𝒓 𝑩𝒐𝒐𝒔𝒕 𝑪𝒐𝒏𝒗𝒆𝒓𝒕𝒆𝒓

𝑲𝒄𝒓𝒊𝒕 (𝑫)

𝟐𝑳
𝑲= = 𝑫𝑫′𝟐 = 𝑲𝒄𝒓𝒊𝒕 (D)
𝑹𝑻𝒔
There are two values for 𝑲 = 𝑲𝒄𝒓𝒊𝒕 (D)

𝑲 > 𝑲𝒄𝒓𝒊𝒕 (𝑫) For CCM

𝑲 < 𝑲𝒄𝒓𝒊𝒕 (𝑫) For DCM

Note: 𝑩𝒐𝒐𝒔𝒕 𝒄𝒐𝒏𝒗𝒆𝒓𝒕𝒆𝒓 𝒐𝒑𝒆𝒓𝒂𝒕𝒆𝒔 𝒊𝒏 𝑪𝑪𝑴 𝒏𝒆𝒂𝒓 𝒕𝒐 𝑫 = 𝟎 𝒂𝒏𝒅 𝑫 =

𝟏 𝒂𝒏𝒅 To keep the operation in CCM for all duty-ratio (D), the parameter
K≥4/27=0.15.
Analysis of Boost Converter: Principles and Small-ripple
Approximation

Inductor volt-second (Flux-linkage) balance

𝑻𝒔
𝟏 𝑻𝒔
න 𝒗𝑳 𝒅𝒕 = 0 < 𝒗𝑳 > න 𝒗𝑳 𝒅𝒕 = 0
𝟎 𝑻𝒔 𝟎
Capacitor Amp-second (Charge) balance
𝑻𝒔
න 𝒊𝑪 𝒅𝒕 = 0 𝟏 𝑻𝒔
𝟎 < 𝒊𝑪 > න 𝒊𝑪 𝒅𝒕 = 0
𝑻𝒔 𝟎

Small-ripple Approximation:
(a) Capacitor Voltage ripple can be neglected
𝒗 = 𝑽 + 𝒗𝒓𝒊𝒑𝒑𝒍𝒆 𝒗≈𝑽
(b) Inductor current ripple is quite high therefore can not be neglected
𝒊𝑳 = 𝑰 + 𝒊𝑳𝒓𝒊𝒑𝒑𝒍𝒆 𝒊𝑳 ≠ 𝑰 𝒊𝑳𝒓𝒊𝒑𝒑𝒍𝒆 𝒊𝒔 𝒍𝒂𝒓𝒈𝒆
 Capacitor Amp-second (Flux-balance) balance
𝑻𝒔
𝒅𝒊𝑳 𝑽𝒈
න 𝒊𝑪 𝒅𝒕 = 0 =
𝟎 𝒅𝒕 𝑳

Peak inductor OR peak diode current (𝒊𝑳𝒑 𝒐𝒓 𝒊𝑫𝒑 )=

Slop X time
𝒅𝒊𝑳 𝑽𝒈
= 𝑫 𝑻 = 𝑫𝟏 𝑻𝒔
𝒅𝒕 𝟏 𝒔 𝑳
Charge balance in a complete time-period

𝑻𝒔 𝑻𝒔
𝟏
න 𝒊𝑫 𝒅𝒕 = න 𝒊𝑫 𝒅𝒕 = 0 = 𝒊𝑫𝒑 𝑫𝟐 𝑻𝒔
𝟎 𝟎 𝟐
𝟏 𝑻𝒔
Average diode current, ‫𝒕𝒅 𝒊 ׬‬
𝑻𝒔 𝟎 𝑫 𝑽 𝟏 𝑽𝒈
𝑽 𝟏 𝑽𝒈 Second equation, = ( 𝑫𝟏 𝑻𝒔 )𝑫𝟐
𝑰 = = ( 𝑫𝟏 𝑻𝒔 )𝑫𝟐 𝑹 𝟐 𝑳
𝑹 𝟐 𝑳 𝑽 𝑫𝟏 + 𝑫𝟐
First equation =
𝑽𝒈 𝑫𝟐
Eliminate 𝑫𝟐 (𝑼𝒏𝒌𝒏𝒐𝒘𝒏)
𝑽 𝑫𝟏 + 𝑫𝟐
First equation, =
𝑽𝒈 𝑫𝟐
𝑽 𝟏 𝑽𝒈
Second equation, = ( 𝑫𝟏 𝑻𝒔 )𝑫𝟐
𝑹 𝟐 𝑳

𝟒𝑫𝟐𝟏
𝑽 𝟏+ 𝟏+ 𝑲
𝑴 𝑫, 𝑲 = = 𝟐𝑳
𝑽𝒈 𝟐 Here, 𝑲 = 𝑹𝑻
𝒔

Note: This conversion ratio, M(D,K) is valid for, 𝑲 < 𝑲𝒄𝒓𝒊𝒕 𝑫 𝒐𝒓 𝑹 > 𝑹𝒄𝒓𝒊𝒕
For DCM conditions
Conversion ratio, M(D,K) versus Duty ratio (D), here D is equal to 𝐃𝟏

𝟒𝑫𝟐𝟏
𝑽 𝟏+ 𝟏+ 𝑲
𝑴 𝑫, 𝑲 = =
𝑽𝒈 𝟐

𝟐𝑳
Here, 𝑲 =
𝑹𝑻𝒔

Conclusion: DCM operation of boost

converter leads to increase in output
voltage. The conversion ratio is almost
linear in DCM mode and can be
approximated by,
𝟏 𝑫
M(D,K)= + 𝟏
𝟐 𝑲
 BITS Pilani
Pilani Campus

EEE / INSTR F 342 ( Power Electronics)

Module -2 (DCM of DC – DC Converter )
Lecture - 9
Out Line :
 Recap
 DCM of Buck Boost Converter

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Buck Boost Converter : DCM

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Applying Volt. – Sec. Balance or Avg. Ind. Volt. Equal to zero

VG T1 + (V0 ) T2 = 0

(d) VG = -V0 d2
=> Out put voltage in
V0 / VG = - d / d2 >d/(1- d) DCM is greater than that
1-d < 1 of CCM

Resolving d2 in terms of d

I0 = V0 / R = 1/2 * IP .d2
IP = d. Ts .VG / L

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

I0 = 1/2 * IP d2 = V0 / R
IP = d. Ts .V0 / L
On simplifying
K = (d2)2 ; where K= 2L /TS R (Conduction Parameters)
On simplifying the quadratic equation of d2 and relating with K

Voltage Gain

>d/(1- d)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

On the Border of DCM & CCM
d + d2 = 1 , => K= (d2)2 ; d2 = (1-d) & K = 2.L / R.Ts So

When K < (1-d)2 or Kcri ---- Operation is DCM and if

When K > Kcri ---- Operation is CCM
So, Kcri = (1-d)2 ---- On the verge of CCM
Plot of Kcri. Vs D

Blue portion K< Kcri. , So

mode of operation DCM.

White portion K > Kcri. , So

mode of operation CCM.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Plot of Kcri. Vs D , Vs Voltage Gain

Voltage Gain is more in DCM,

Salient features of DCM

1. Zero (Low) Turn ON losses

– since current starts from zero
so zero turn ON loss.
2. Soft Diode recoverery. ---
Diode current gets zero during
off period
3. Low ckt. Inductance
4. High Inductor current
ripple ---- Disadvantage

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

SUMMARY OF BASIC DC-DC CONVERTER (CCM+DCM)
 BITS Pilani
Pilani Campus

Lecture – 10
DC-DC Converter (SMPS)
Out Line : L 10

 Recap of Lect. 9
Analysis of Ideal Converter- Under DCM
 Analysis of isolated converter

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Converter’s Mode of Operation : CCM / DCM

Ripple increases with decrease in L, increase in Ts , and decrease in

avg. current. ( change in values to the avg. current )
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Buck Converter : DCM
Ripple increases with decrease in L, increase in Ts , and decrease in avg.
current. ( change in values to the avg. current )

In DCM , a third state exist -- in this neither transistor nor diode conduct,
inductor current comes to zero , this can not reverse because of diode in series.
T1 = Switch is ON, Diode is OFF
T2 = Switch is OFF, Diode is ON
T3 = Switch is OFF, Diode is OFF
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Applying Volt. – Sec. Balance or Avg. Ind. Volt. Equal to zero

T1 + T2+ T3 = TS
=> Out put
> d voltage in DCM is
greater than that
d + d2 < 1 of CCM

Resolving d2 in terms of d
I0 = IL = 1/2 * IP (d+d2)
IP = d2. Ts .V0 / L

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 I0 = IL = 1/2 * IP (d+d2) = V0 / R
IP = d2. Ts .V0 / L
1/2 * d2. Ts .V0 (d+d2) / L = V0 / R On simplifying
d2. (d+d2) = 2L / TS R = K (Conduction Parameters) - - -
On simplifying the quadratic equation of d2

Voltage Gain

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

On the Border of DCM & CCM
d + d2 = 1 , => d2(d+d2) = (1-d) & K = 2.L / R.Ts So

When K < (1-d) or Kcri ---- Operation is DCM and if

When K > (1-d) or Kcri ---- Operation is CCM
So, Kcri = (1-d) ---- On the verge of CCM Plot of Kcri. Vs D

Blue portion K< Kcri. , So

mode of operation DCM.

Yellow portion K > Kcri. , So

mode of operation CCM.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Plot of Kcri. Vs D , Vs Voltage Gain

Voltage Gain is more in DCM,

Salient features of DCM

1. Zero (Low) Turn ON losses

– since current starts from zero
so zero turn ON loss.
2. Soft Diode recoverery. ---
Diode current gets zero during
off period
3. Low ckt. Inductance
4. High Inductor current
ripple ---- Disadvantage

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Boost Converter : DCM

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Applying Volt. – Sec. Balance or Avg. Ind. Volt. Equal to zero

VG T1 + (VG – V0 ) T2 = 0

(d+ d2) VG = V0 d2
=> Out put voltage in
V0 / VG = d2 / (d+ d2) >1/(1- d) DCM is greater than
d + d2 < 1 that of CCM

Resolving d2 in terms of d

I0 = V0 / R = 1/2 * IP .d2
IP = d. Ts .VG / L

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

I0 = 1/2 * IP d2 = V0 / R
IP = d. Ts .V0 / L
On simplifying
K (d+d2) = d. d2. d2 ; where K= 2L /TS R (Conduction Parameters)
On simplifying the quadratic equation of d2 and relating with K

Voltage Gain

>1/(1- d)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

On the Border of DCM & CCM
d + d2 = 1 , => K(d+d2) = d(d2)2 ; d2 = (1-d) & K = 2.L / R.Ts So

When K < d.(1-d)2 or Kcri ---- Operation is DCM and if

When K > Kcri ---- Operation is CCM
So, Kcri = d.(1-d)2 ---- On the verge of CCM
Plot of Kcri. Vs D

Blue portion K< Kcri. , So

mode of operation DCM.

White portion K > Kcri. , So

mode of operation CCM.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Plot of Kcri. Vs D , Vs Voltage Gain

Voltage Gain is more in DCM,

Salient features of DCM

1. Zero (Low) Turn ON losses

– since current starts from zero
so zero turn ON loss.
2. Soft Diode recoverery. ---
Diode current gets zero during
off period
3. Low ckt. Inductance
4. High Inductor current
ripple ---- Disadvantage

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Buck Boost Converter : DCM

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Applying Volt. – Sec. Balance or Avg. Ind. Volt. Equal to zero

VG T1 + (V0 ) T2 = 0

(d) VG = -V0 d2
=> Out put voltage in
V0 / VG = - d / d2 >d/(1- d) DCM is greater than
1-d < 1 that of CCM

Resolving d2 in terms of d

I0 = V0 / R = 1/2 * IP .d2
IP = d. Ts .VG / L

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

I0 = 1/2 * IP d2 = V0 / R
IP = d. Ts .V0 / L
On simplifying
K = (d2)2 ; where K= 2L /TS R (Conduction Parameters)
On simplifying the quadratic equation of d2 and relating with K

Voltage Gain

>d/(1- d)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

On the Border of DCM & CCM
d + d2 = 1 , => K= (d2)2 ; d2 = (1-d) & K = 2.L / R.Ts So

When K < (1-d)2 or Kcri ---- Operation is DCM and if

When K > Kcri ---- Operation is CCM
So, Kcri = (1-d)2 ---- On the verge of CCM
Plot of Kcri. Vs D

Blue portion K< Kcri. , So

mode of operation DCM.

White portion K > Kcri. , So

mode of operation CCM.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Plot of Kcri. Vs D , Vs Voltage Gain

Voltage Gain is more in DCM,

Salient features of DCM

1. Zero (Low) Turn ON losses

– since current starts from zero
so zero turn ON loss.
2. Soft Diode recoverery. ---
Diode current gets zero during
off period
3. Low ckt. Inductance
4. High Inductor current
ripple ---- Disadvantage

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Lecture – 10
Isolated DC-DC Converter (SMPS)
 Introduction : Isolated Converter
The input voltage is normally derived from the on line- ½
or full wave rectifier, and the output Voltage is a very
small fraction of the rectified dc input voltage. As a result,
transformer must be added between the power stage and
the output for the purpose of voltage scaling.

 Flyback
Forward
PushPull

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Isolated Converter
•We use Ferrite Core– High Freq. operation, CRGO– is used for line
frequ. Operation.
•Uni-directional Core Excitation – Operate in 1 st Quadrant, 0 – Vdc
( e.g. Flyback & Forward converter ) – only + portion of B-H Loop is
used,
• Bi-directional Core Excitation -- Operate in 1st & 3rd Quadrant,
+Vdc to -ve Vdc ( Pushpull , Halfbridge, Fullbridge) – both the
portion of B-H Loop is used,
In classical / primitive Converter (Non-isolated ) The input and output
stages have same reference. So, if the supply is grounded the same
ground is available to the load – disadvantage .
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
The more efficient way of providing isolation between input & output is
Use of transformer (Shell Type).
The transformer use may provide the flexibility in the design, and
multiple outputs.
Reduces the component stresses that develops when the voltage
conversion ratio is far from unity.
The leakage Inductances L1 & L2 are usally not crucial to the general
operation of power Electronics Ckts.
But are important when considering switching Transients.
Note : that in ac Power system applications, the leakage inductance is
normally important parameters.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
•For periodic voltage and current operation for transformer ckt. The
magnetic flux in the core must return to its starting values at the end of
each switching period. Otherwise accumulation of of flux in the core
will saturate the core . A saturated core can’t support a voltage across
a winding and this would lead the device currents that are the beyond
the design limit of the ckt.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Flyback Converter
It’s a Buck-Boost derived topology, very commonly used in low
power DC supply .
• Switch on and off states (assuming incomplete core demagnetization-or
- presence of some finite value of flux all the time)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Fly back Converter
 Derived From Buck-Boost
 Preferred for the application < 200W
 Out put is isolated from input source
 Flexibility of getting higher voltage gain
 Multiple out puts can be derived

Flux Continuity has to maintain

Volt- sec. / Flux-Sec. balance has to be satisfied
Volt / turn ratio has to same

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Flyback Converter- Analysis
* Transformer (Ferrite Cored) –assumed to be practical by considering
the magnetizing branch in parallel. Neglecting the other non idealities
e.g. Leakage reactance winding resistance –core loss etc.
•In the switching operation – resetting of the core ( demagnetizing – or
bringing back the flux to the initial state) has to be ensured, converter
work satisfactorily. – Flux – Sec. balance in the core has to be satisfied
• CCM operation in Buck-Boost converter is corresponds to the
incomplete demagnetization of the inductor core in flyback converter .
So the flux in the core increases linearly as shown in waveform.
• The energy is stored in Lm when the switch is closed and
transferred to load when the switch is open.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Flyback Converter- Waveforms

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Note that the relation between input and output for the flyback converter is similar
to that of the buck-boost converter but includes the additional term for the
transformer ratio.
** Note : the voltage input and output relationship can be arrived by the use of
volt. Sec. balance / Avg. inductor voltage equal to zero.

Other waveform of interest

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
From power balance
The average source current Is is related to the average of
the magnetizing inductance current ILm

The maximum and minimum values of inductor current are obtained from

Note: VS and Vd are Source voltage

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Prob.
A fly back converter has the following circuit parameters:
Vs = 24 V
N1/N2 = 3.0
Lm = 500 µH
R=5
C =200 µF
f =40 kHz
Vo = 5 V
Determine (a) the required duty ratio D; (b) the average, maximum, and
minimum values for the current in Lm; and (c) the output voltage ripple. Assume
that all components are ideal.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Soln.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 BITS Pilani
Pilani Campus

Lecture – 14
Isolated DC-DC Converter (SMPS)
 Introduction : Isolated Converter
The input voltage is normally derived from the on line- ½
or full wave rectifier, and the output Voltage is a very
small fraction of the rectified dc input voltage. As a result,
transformer must be added between the power stage and
the output for the purpose of voltage scaling.

 Flyback
Forward
PushPull

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 FLYBACK
CONVETER
FLYBACK CONVERTER IS BASED ON NON-ISOLATED BUCK-BOOST CONVERETR
(Development of FLYBACK CONVERTER)

Working

Two inductor
winding

Flyback Transformer (check the polarity)

(Unlike ideal transformer, current does not flow from both windings
simultaneously)
Actual FLYBACK Converter
Steady-state Analysis
of
Flyback Converter
ON-Time of Transistor: Subinterval #1

SUBINTERVAL#1
 ON-Time of Transistor: Subinterval #1

Applying Small-ripple approximation,

𝒗𝑳 = 𝑽𝒈
𝑽
𝒊𝑪 ≈ −
𝑹

𝒊𝒈 ≈ 𝑰

𝑰 𝒊𝒔 𝒂𝒗𝒆𝒓𝒂𝒈𝒆 𝒗𝒂𝒍𝒖𝒆 (< 𝒊 >) of current through magnetizing ind (LM)

OFF-Time of Transistor: Subinterval #2

SUBINTERVAL#2
OFF-Time of Transistor: Subinterval #2
𝑽
−
𝒏𝑳𝑴 ∆𝑖𝐿𝑀
𝑖𝐿𝑀 𝑽𝒈
𝑳𝑴

Applying Small-ripple approximation,

𝑽
𝒗𝑳 ≈ −
𝒏 𝑰 𝑽
𝒊𝑪 ≈ −
𝒏 𝑹

𝒊𝒈 = 𝟎
Inductor Volt-second balance

𝑽
𝑽𝒈 𝑫𝑻𝒔 + (- ) 𝟏 − 𝑫 𝑻𝒔 = 𝟎
𝒏

𝑽 𝑫
𝑴 𝑫 = =𝒏
𝑽𝒈 (𝟏 − 𝑫)
 Capacitor Amp-second balance

𝑽 𝑰 𝑽
− (𝑫𝑻𝒔 )+ ( − ) 𝟏 − 𝑫 𝑻𝒔 = 𝟎
𝑹 𝒏 𝑹
𝒏 𝑽
𝑰=
(𝟏 − 𝑫) 𝑹
Note: This is DC component or average component of magnetizing
current of 𝑳𝑴 referred to primary
DC component/Average Input Current

DC component/Average Input Current

𝟏 𝑻𝒔
< 𝒊𝒈 > = න 𝒊𝒈 𝒅𝒕
𝑻𝒔 𝟎

< 𝒊𝒈 > = 𝑰 𝑫𝑻𝒔 + 0. 𝟏 − 𝑫 𝑻𝒔

< 𝒊𝒈 > = 𝑰 𝑫
Linear Equivalent Model/circuit of Flyback converter

𝑽 𝑫 𝒏 𝑽
=𝒏 𝑰=
< 𝒊𝒈 > = 𝑰 𝑫 𝑽𝒈 (𝟏 − 𝑫)
(𝟏 − 𝑫) 𝑹
< 𝒊𝒈 > = 𝑰 𝑫 𝟏−𝑫 𝑽 (𝟏 − 𝑫) 𝑽
𝑫𝑽𝒈 = 𝑰=
𝒏 𝒏 𝑹
Power ratings
Typical power levels:

• Forward (100 – 300 W): Restricted duty cycle, third winding for reset

• Flyback (<100 W): Low-power, high-peak currents, output capacitor stress, low part
counts

• Half-bridge (<750 W)

• Full-bridge (>750 W)

Design and utilisation of magnetics tends to be the limiting factor.

 Isolated Converter
•We use Ferrite Core– High Freq. operation, CRGO– is used for line
frequ. Operation.
•Uni-directional Core Excitation – Operate in 1 st Quadrant, 0 – Vdc
( e.g. Flyback & Forward converter ) – only + portion of B-H Loop is
used,
• Bi-directional Core Excitation -- Operate in 1st & 3rd Quadrant,
+Vdc to -ve Vdc ( Pushpull , Halfbridge, Fullbridge) – both the
portion of B-H Loop is used,
In classical / primitive Converter (Non-isolated ) The input and output
stages have same reference. So, if the supply is grounded the same
ground is available to the load – disadvantage .
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
The more efficient way of providing isolation between input & output is
Use of transformer (Shell Type).
The transformer use may provide the flexibility in the design, and
multiple outputs.
Reduces the component stresses that develops when the voltage
conversion ratio is far from unity.
The leakage Inductances L1 & L2 are usally not crucial to the general
operation of power Electronics Ckts.
But are important when considering switching Transients.
Note : that in ac Power system applications, the leakage inductance is
normally important parameters.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
•For periodic voltage and current operation for transformer ckt. The
magnetic flux in the core must return to its starting values at the end of
each switching period. Otherwise accumulation of of flux in the core
will saturate the core . A saturated core can’t support a voltage across
a winding and this would lead the device currents that are the beyond
the design limit of the ckt.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Flyback Converter
It’s a Buck-Boost derived topology, very commonly used
in low power DC supply .
Switch on and off states (assuming incomplete core demagnetization-or
- presence of some finite value of flux all the time)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Fly back Converter
 Derived From Buck-Boost
 Preferred for the application < 200W
 Out put is isolated from input source
 Flexibility of getting higher voltage gain
 Multiple out puts can be derived

Flux Continuity has to maintain

Volt- sec. / Flux-Sec. balance has to be satisfied
Volt / turn ratio has to same

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Flyback Converter- Analysis
* Transformer (Ferrite Cored) –assumed to be practical by considering
the magnetizing branch in parallel. Neglecting the other non idealities
e.g. Leakage reactance winding resistance –core loss etc.
•In the switching operation – resetting of the core ( demagnetizing – or
bringing back the flux to the initial state) has to be ensured, converter
work satisfactorily. – Flux – Sec. balance in the core has to be satisfied
• CCM operation in Buck-Boost converter is corresponds to the
incomplete demagnetization of the inductor core in flyback converter .
So the flux in the core increases linearly as shown in waveform.
• The energy is stored in Lm when the switch is closed and
transferred to load when the switch is open.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Flyback Converter- Waveforms

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Note that the relation between input and output for the flyback
converter is similar to that of the buck-boost converter but includes the
additional term for the transformer ratio.
** Note : the voltage input and output relationship can be arrived by
the use of volt. Sec. balance / Avg. inductor voltage equal to zero.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 From power balance
The average source current Is is related to the average of the
magnetizing inductance current ILm

The maximum and minimum values of inductor current are obtained

from

Note: VS and Vd are Source voltage

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 Prob.
A fly back converter has the following circuit parameters:
Vs = 24 V ; N1/N2 = 3.0 ; Lm = 500 µH
R = 5 ; C =200 µF ; f =40 kHz ; Vo = 5 V

Determine (a) the required duty ratio D; (b) the average,

maximum, and minimum values for the current in Lm; and
(c) the output voltage ripple. Assume that all components are
ideal.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Soln.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Out Line :

 Recap
Analysis of isolated Forward DC-DC converter

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

FORWARD CONVETER
Development of FORWAD CONVERTER

Non-isolated buck converter

(another configuration) Gate

Source Drain

Add transformer
to isolate

Add Diode
To protect
secondary winding
Development of FORWAD CONVERTER (with practical transformer)
Practical transformer

Gate

Source Drain

This is magnetization inductance not winding

𝑣1

Here we have positive waveform of voltage for

magnetizing inductance.

𝑡
DCM/CMM
No other path available to decrease In this circuit, Magnetizing energy keeps
current through magnetizing inductance on increasing in 𝑳𝑴 each cycle hence we
DCM
to balance the flux during off-time. need a auxiliary reset winding.
 Actual FORWARD CONVERTER (Working)

Auxiliary Reset winding

For a common choice of 𝒏𝟏 = 𝒏𝟐 , the value of duty ratio (D) is limited to the range 𝟎 ≤ 𝑫 <
𝟎. 𝟓.
 FORWARD CONVERTER
Secondary winding
Primary winding

Auxiliary Reset winding

Note: The magnetizing inductance, 𝑳𝑴 in conjunction with diode 𝑫𝟏 must operate in DCM and
Output inductance L in conjunction with 𝑫𝟑 can operate either in DCM or CCM
FORWARD CONVERTER: Discontinuous magnetizing current

Note:
The magnetizing inductance, 𝑳𝑴 in conjunction
with diode 𝑫𝟏 must operate in DCM
and
Output inductance L in conjunction with 𝑫𝟑
can operate either in DCM or CCM
 Analysis of FORWARD CONVERTER in CCM
For different subintervals (ON time and OFF time of transistor)
FORWARD CONVERTER: Sub-interval 1 (On-Time of Transistor)

Draw also,
(1) Waveform of voltage across inductor, L
(2) Peak value of inductor current
(3) Current through capacitor
Sub-interval 1: ON-Time of transistor
𝑣𝐿 = 𝑉𝑔

𝑉
𝑖𝐶 = 𝐼𝐿 −
𝑅
𝑖𝑔 = 𝑖𝑀 + 𝐼′1
FORWARD CONVERTER: sub-interval 2 (OFF-Time of
Transistor)

Draw also,
(1) Waveform of voltage across inductor, L
Sub-interval 2: OFF-Time of transistor (2) Peak value of inductor current
(3) Current through capacitor
𝑛1
𝑣𝐿 = 𝑣1 = − 𝑉
𝑛2 𝑔
𝑉
𝑖𝐶 = 𝐼𝐿 −
𝑅
𝑛1
𝑖𝑔 = −𝐼2 = − 𝐼
𝑛2 𝑀
FORWARD CONVERTER: sub-interval 3 (OFF-Time of
Transistor)

Draw also,
(1) Waveform of voltage across inductor, L
Sub-interval 3: OFF-Time of transistor (2) Peak value of inductor current
(3) Current through capacitor

𝑣𝐿 = 0
𝑉
𝑖𝐶 = 𝐼𝐿 −
𝑅
𝑖𝑔 = 0
 Limitation of Duty Ratio (D) (correction done in slide)

𝒏𝟏
𝑽𝒈 𝑫𝑻𝒔 + − 𝑽𝒈 𝑫𝟐 𝑻𝒔 + 𝟎. 𝑫𝟑 𝑻𝒔 = 𝟎
𝒏𝟐
𝒏𝟐
𝑫𝟐 = 𝑫
𝒏𝟏
𝑨𝒍𝒔𝒐 𝒘𝒆 𝒉𝒂𝒗𝒆, 𝑫𝑻𝒔 + 𝑫𝟐 𝑻𝒔 + 𝑫𝟑 𝑻𝒔 = 𝑻𝒔

𝑫 + 𝑫𝟐 + 𝑫𝟑 = 𝟏
𝑫𝟑 = 𝟏 − 𝑫 − 𝑫𝟐 𝑫𝟑 𝒄𝒂𝒏 𝒏𝒐𝒕 𝒃𝒆 𝒏𝒆𝒈𝒂𝒕𝒊𝒗𝒆
𝟏 − 𝑫 − 𝑫𝟐 ≥ 𝟎 𝟏
𝑫≤ 𝒏𝟐
𝒏𝟐 𝟏+
𝟏−𝑫− 𝑫≥𝟎 𝒏𝟏
𝒏𝟏
𝑫 ≤0.5 for 𝒏𝟏 = 𝒏𝟐
Magnetizing Current must be zero on the
completion of each cycle.

𝑫 ≤0.5 for 𝒏𝟏 = 𝒏𝟐

𝑫 >0.5 for 𝒏𝟏 = 𝒏𝟐
FORWARD CONVERTER: Conversion Ratio in CCM mode (correction done in slide)

Average voltage of inductor, L is zero for a complete cycle

However average inductor current is not zero.
Average voltage of diode=Average voltage of load resistance
Average voltage of diode,
𝟏 𝑻𝒔
< 𝒗𝑫𝟑 > = න 𝒊𝑫 𝒅𝒕
𝑻𝒔 𝟎
𝒏𝟑
< 𝒗𝑫𝟑 >= 𝑽= 𝑽𝒈 𝑫
𝒏𝟏
 Voltage Stress on switch

𝟏 𝒏𝟏
𝑫≤ 𝒏𝟐 𝑴𝒂𝒙 𝒗𝑸𝟏 = 𝑽𝒈 (𝟏 + )
𝟏+ 𝒏𝟐
𝒏𝟏
Note: Voltage Stress on switch increases as duty ratio decreases. For 𝒏𝟏 = 𝒏𝟐 , the switch stress is 2
times of Vg during subinterval-2.
Forward Converter

Derived from Buck; idealized to assume that the transformer is ideal (not possible in
practice)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

The energy is stored in Lm when the switch is open and transferred
to load when the switch is closed.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Forward Converter: in Practice

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Switching waveforms (assuming incomplete core demagnetization)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Push-Pull Converter (Derived from Buck Converter)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Forward Converter

Derived from Buck; idealized to assume that the transformer is ideal (not possible in
practice)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

The energy is stored in Lm when the switch is open and transferred
to load when the switch is closed.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Forward Converter: in Practice

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Switching waveforms (assuming incomplete core demagnetization)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 MODULE-2 (Part-2)
STEADY-STATE EQUIVALENT CIRCUIT MODELLING
Development of Equivalent Circuit of Power Converter
Actual Circuit of Converter Equivalent circuit of Converter

Ideal or non-ideal switching converter Ideal or non-ideal switching converter

(Nonlinear Circuit) (Linear Circuit)

Current and voltage source Ideal DC Transformer

In final DC equivalent circuit, no capacitor and inductor or loss-less

components available

Important points:
(1) The basic functions of converter can be represented by equivalent circuit.
(2) DC-transformer is used to model the ideal function of the dc-dc converter.
(3) The equivalent circuit correctly represents the relation b/w voltages and currents of the converter
(4) The model can be refined by adding on-resistance and forward drop of the semiconductor
switches, inductor ESR, copper losses.
(5) The equivalent model can be used find voltages, currents, losses and efficiency of the non-ideal
converter.
Note: This transformation is based on dc-dc converter operating at steady-state.
Any switching converter has three ports (Power input, Power and Control input)
Input power is processed by control input and then the processed
power supplied at output to load.

The switching converter can be modelled using DC-transformer.

What is the DC-transformer ?
DC-transformer model
Ideally, Input power is processed by control input and then the processed power supplied at output to load at 100 %.
This implies that,
𝐼𝑛𝑝𝑢𝑡 𝑝𝑜𝑤𝑒𝑟 𝑜𝑓 𝑐𝑜𝑛𝑣𝑒𝑟𝑡𝑒𝑟 = 𝑂𝑢𝑡𝑝𝑢𝑡 𝑝𝑜𝑤𝑒𝑟 𝑜𝑓 𝑐𝑜𝑛𝑣𝑒𝑟𝑡𝑒𝑟
Contains loss-less
𝑃𝑖𝑛 = 𝑃𝑜𝑢𝑡 components (L, C, Switches)

𝑉𝑔 𝐼𝑔 = 𝑉𝐼
Ideal DC-transformer model (Continued..)
Relation between conversion ratio, M(D)
is output current here
and currents.
Example: For Buck-converter in CCM,
𝑰𝒈 = 𝑫𝑰 = 𝑴 𝑫 𝑰
For Boost-converter,
𝑰
𝑰𝒈 = =𝑴 𝑫 𝑰
(𝟏 − 𝑫)

Relation between conversion ratio, M(D)

and voltages
Example: For Buck-converter in CCM,
𝑽 = 𝑫𝑽𝒈 = 𝑴 𝑫 𝑽𝒈
For Boost-converter, Note: In general, a PWM converter operating in CCM and having
𝑽𝒈 equal number of independent capacitors and inductors has
𝑽= = 𝑴 𝑫 𝑽𝒈 equilibrium conversion ratio, M(D) as a function of duty-ratio and
(𝟏 − 𝑫) independent of load resistance.
DC-transformer model (Continued..)
For Buck-converter in CCM, For Buck-converter in CCM,
𝑽 = 𝑫𝑽𝒈 = 𝑴 𝑫 𝑽𝒈 𝑰𝒈 = 𝑫𝑰 = 𝑴 𝑫 𝑰
For Boost-converter, For Boost-converter,
𝑽𝒈 𝑰
𝑽= = 𝑴 𝑫 𝑽𝒈 𝑰𝒈 = =𝑴 𝑫 𝑰
(𝟏 − 𝑫) (𝟏 − 𝑫)

Equivalent circuit as a DC-Transformer

Equivalent circuit using dependent sources
Concept of Ideal DC-Transformer
Ideal DC-Transformer

Ideal DC-Transformer
Concept of Ideal DC-Transformer: simplified equivalent circuit referred to secondary side
Ideal DC-Transformer

𝑹
𝑽 = 𝑴 𝑫 𝑽𝟏
(𝑴𝟐 𝑫 𝑹𝟏 + 𝑹)

Note:
AC Transformer rules are applicable for the ideal DC transformer as well.
DC-transformer model boost converter (CCM mode) with ESR in L: Analysis using inductor volt-second
balance and capacitor Amp-sec balance

Using inductor voltage-sec (flux-linkage) balance Using capacitor Amp-sec (charge) principle
principle
Average voltage of inductor is zero Average current of capacitor is zero
𝑉
< 𝑣𝐿 > = 𝑉𝑔 − 𝐼𝑅𝐿 − 1 − 𝐷 𝑉 = 0 < 𝑖𝐶 > = 1 − 𝐷 𝐼 − = 0
𝑅
DC-transformer model of boost converter (CCM mode) with ESR in L
Efficiency calculation of the boost converter (CCM mode) with ESR in L
Apply voltage division,
𝑽𝒈 𝑹 𝑽𝒈 𝟏
𝑽= =
(𝟏 − 𝑫) [𝑹 + 𝑹𝑳 𝑹𝑳
𝟐 ] (𝟏 − 𝑫) [𝟏 + ]
𝟏−𝑫 𝟏 − 𝑫 𝟐𝑹
Apply Ohm’s Law,
𝑽𝒈
𝟏−𝑫
(𝟏 − 𝑫)𝑰 =
𝑹𝑳
𝑹+ 𝟐
𝟏−𝑫

𝑽𝒈
𝑰=
𝟏 − 𝑫 𝟐 𝑹 + 𝑹𝑳

Efficiency of converter
𝑶𝒖𝒕𝒑𝒖𝒕 𝒑𝒐𝒘𝒆𝒓 𝑽 ∗ 𝟏−𝑫 𝑰 𝑽(𝟏−𝑫)
𝜼 = = 𝑽𝒈 =
𝑰𝒏𝒑𝒖𝒕 𝒑𝒐𝒘𝒆𝒓 𝟏−𝑫 𝑰 𝑽𝒈
(𝟏−𝑫)
EFFICIENCY OF NON-IDEAL BOOST CONVERETR (L+ESR) versus DUTY-RATIO (D)
𝑽𝒈 𝟏 𝑽(𝟏−𝑫)
𝑽= 𝜼 %= *100
(𝟏 − 𝑫) [𝟏 + 𝑹𝑳 𝑽𝒈
]
𝟏 − 𝑫 𝟐𝑹
Example of Directly Replaceable DC-DC converter containing inductor having ESR with ideal
DC transformer (1:M(D))

(1) Ideal DC-DC converter (2) BOOST converter (L+ESR)

Equivalent circuit
Equivalent circuit
Example of Directly Replaceable DC-DC converter containing inductor having ESR with ideal
DC transformer (1:M(D))
What about the following circuits; are these circuits directly replaceable by ideal DC Transformer (1:M(D)) ?

Non-ideal L
Non-ideal Diode

Non-ideal Switch

Non-ideal C
 Development of equivalent circuit of non-ideal boost converter (CCM)
Non-ideal inductor (𝑳, 𝑹𝑳 )
Non-ideal Diode (𝑽𝑫 , 𝑹𝑫 )

Non-ideal Switch (𝑹𝒐𝒏 )

Transistor OFF, Diode ON

Transistor ON, Diode OFF

𝒗𝑳 = 𝑽𝒈 − 𝒊𝑹𝑳 − 𝒊𝑹𝒐𝒏 𝒗𝑳 = 𝑽𝒈 − 𝒊𝑹𝑳 − 𝑽𝑫 − 𝒊𝑹𝑫 − 𝒗

𝒗 𝒗
𝒊𝑪 = 𝟎 − 𝒊𝑪 = 𝒊 −
𝑹 𝑹
Small-ripple approximation, Small-ripple approximation,

𝒗𝑳 ≈ 𝑽𝒈 − 𝑰𝑹𝑳 − 𝑰𝑹𝒐𝒏 𝒗𝑳 ≈ 𝑽𝒈 − 𝑰𝑹𝑳 − 𝑽𝑫 − 𝑰𝑹𝑫 − 𝑽

𝒊𝑪 ≈ 𝟎 −
𝑽 𝑽
𝑹 𝒊𝑪 ≈ 𝑰 −
𝑹
 What would you do when converter is not directly
replaceable by its equivalent ideal DC transformer (in
order to develop the complete equivalent circuit) ?

Ans:
(1) Average voltage of the inductor is zero.
This will give one equation to develop a part of equivalent circuit.

(2) Average current of the capacitor is zero.

This will give another equation to develop remaining part of equivalent circuit.

To design equivalent circuit follow the STEPS as discussed in next slides

Step#1 Write down the inductor voltage equation for complete cycle for steady-state and capacitor current
equations for complete cycle for steady-state (which are the average equations).
𝒗𝑳 ≈ 𝑽𝒈 − 𝑰𝑹𝑳 − 𝑰𝑹𝒐𝒏

Average equations
𝟏 𝑻𝒔
< 𝒗𝑳 > = න 𝒗 𝒅𝒕
𝑻𝒔 𝟎 𝑳
𝟏 𝑫𝑻𝒔 𝒗 𝟏 𝑻𝒔 𝒗𝑳 ≈ 𝑽𝒈 − 𝑰𝑹𝑳 − 𝑽𝑫 − 𝑰𝑹𝒐𝒏 − 𝑽
= ‫𝟎׬‬ 𝑳 𝒅𝒕 + ‫𝒕𝒅 𝒗 ׬‬
𝑻𝒔 𝑫𝑻𝒔 𝑳
𝑻 𝒔
𝟏
= [𝑫𝑻𝒔 𝒗𝑳_𝒐𝒏 +(𝟏 − 𝑫)𝑻𝒔 𝒗𝑳𝒐𝒇𝒇 ]
𝑻𝒔
𝒊𝑪 ≈ 𝟎 −
𝑽 𝑽
If < 𝒗𝑳 > =0 then volt-sec is balanced 𝑹 𝒊𝑪 ≈ 𝑰 −
𝑹
𝟏 𝑻𝒔
< 𝒊𝑪 > = න 𝒊 𝒅𝒕
𝑻𝒔 𝟎 𝑪
𝟏 𝑫𝑻𝒔 𝒊 𝟏 𝑻𝒔
= ‫𝟎׬‬ 𝑪 𝒅𝒕 + 𝑻 ‫𝒕𝒅 𝑪𝒊 𝑻𝑫׬‬
𝑻 𝒔 𝒔
𝒔 < 𝒗𝑳 > = 𝑽𝒈 − 𝑰𝑹𝑳 − 𝑰𝑹𝒐𝒏 𝐃 + 𝑽𝒈 − 𝑰𝑹𝑳 − 𝑽𝑫 − 𝑰𝑹𝑫 − 𝑽 𝟏 − 𝐃 = 𝟎
𝟏
= [𝑫𝑻𝒔 𝒊𝑪_𝒐𝒏 +(𝟏 − 𝑫)𝑻𝒔 𝒊𝑪𝒐𝒇𝒇 ] Equation #1
𝑻𝒔
If < 𝒊𝑪 > =0 then current-sec is balanced 𝑽𝒈 − 𝑰𝑹𝑳 − 𝑫𝑰𝑹𝒐𝒏 − 𝑽𝑫 (𝟏 − 𝑫) − 𝑰𝑹𝑫 (𝟏 − 𝑫) − 𝑽(𝟏 − 𝑫) = 𝟎
𝑽 𝑽
< 𝒊𝑪 > = − 𝐃 + 𝑰 − 𝟏−𝐃 =𝟎
𝑹 𝑹
Equation #2 𝑽
𝑰(𝟏 − 𝑫) − = 𝟎
𝑹
Step#2 Develop the circuit using the average equations
𝑽
𝑽𝒈 − 𝑰𝑹𝑳 − 𝑫𝑰𝑹𝒐𝒏 − 𝑽𝑫 (𝟏 − 𝑫) − 𝑰𝑹𝑫 (𝟏 − 𝑫) − 𝑽(𝟏 − 𝑫) = 𝟎 𝑰(𝟏 − 𝑫) − =𝟎
𝑹

Step#3 Combine the circuits

Step#4 Replace dependent sources by ideal DC transformer
Step#4 Draw the equivalent circuit referred to primary/secondary

Referred to primary
Step#4 Solve the circuit
Efficiency of converter
Input Non-idealities: lossy part of converter 𝑶𝒖𝒕𝒑𝒖𝒕 𝒑𝒐𝒘𝒆𝒓
Output 𝜼 =
𝑰𝒏𝒑𝒖𝒕 𝒑𝒐𝒘𝒆𝒓
𝑽𝑫 𝑰′
= Efficiency is high for
𝑽𝒈 𝑰 these terms tend to
𝑽𝑫′ zero
=
𝑽𝒈
𝟏 − 𝑫 𝑽𝑫
𝟏−
𝑽𝒈
=
𝑹 + 𝑫𝑹𝒐𝒏 + 𝟏 − 𝑫 𝑹𝑫
(𝟏 + 𝑳 )
𝟏 − 𝑫 𝟐𝑹
𝑹(𝟏 − 𝑫)𝟐
𝑽(𝟏 − 𝑫) = [𝑽 − 𝟏 − 𝑫 𝑽𝑫 ]
𝑹(𝟏 − 𝑫)𝟐 + 𝑹𝑳 + 𝑫𝑹𝒐𝒏 + (𝟏 − 𝑫)𝑹𝑫 𝒈 For High Efficiency

Conversion ratio M(D), 𝟏−𝑫 𝑽𝑫

(a) ≈𝟎
𝑽 𝟏 𝟏 − 𝑫 𝑽𝑫 𝟏 𝑽𝒈
= 𝟏− 𝑽𝒈
𝑽𝒈 (𝟏 − 𝑫) 𝑽𝒈 𝑹𝑳 + 𝑫𝑹𝒐𝒏 + (𝟏 − 𝑫)𝑹𝑫
(𝟏 +
𝟏 − 𝑫 𝟐𝑹
) ≫ 𝑽𝑫
(𝟏 − 𝑫)
𝑹𝑳 +𝑫𝑹𝒐𝒏 + 𝟏−𝑫 𝟐𝑹𝑫
(b) )≈𝟎
Note: the loss elements(𝑅𝑜𝑛, 𝑅𝐷, 𝑉𝐷, 𝑅𝐿 ) decreases the M(D) 𝟏−𝑫 𝟐𝑹
𝟐 𝑹 ≫ (𝑹 +𝑫𝑹 𝟐
1 𝟏−𝑫 𝑳 𝒐𝒏 + 𝟏 − 𝑫 𝑹𝑫 )
below the ideal value .
1−𝐷
 Transistor current waveform for different size of inductor

(a) Very large size

inductor (∆𝒊𝑳 = 𝟎)

(b) Small size inductor

(∆𝒊𝑳 = 𝟏. 𝟏 𝑰)

(c) Very small size inductor

(∆𝒊𝑳 = 𝟐 𝑰)

Note: Transistor loss occurs during ON-time only.

𝑬𝒇𝒇𝒆𝒄𝒕𝒊𝒗𝒆 𝒓𝒆𝒔𝒊𝒕𝒂𝒏𝒄𝒆 𝒐𝒇 𝒕𝒓𝒂𝒏𝒔𝒊𝒔𝒕𝒐𝒓 = 𝑫𝑹𝒐𝒏 𝒂𝒏𝒅 𝑷𝒍𝒐𝒔𝒔_𝒕𝒓𝒂𝒏𝒔𝒊𝒔𝒕𝒐𝒓 = 𝑰𝟐𝒓𝒎𝒔 𝑫𝑹𝒐𝒏 ≥ 𝑰𝟐𝒂𝒗𝒈 𝑫𝑹𝒐𝒏
EFFECT OF INDUCTOR CURRENT RIPPLE ON MOSFET CONDUCTION LOSS