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    Rom Interface

    Uploaded by

    Roshini M S
    This document describes a VHDL entity for a ROM interface. The entity has ports for a clock, reset, enable signals, and data inputs and outputs. The architecture contains a state machine with 5 states that controls the bus selection, wait signal, and data output based on the clock, reset and other input signals.

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    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd

    Rom Interface

    Uploaded by

    Roshini M S
    13 views2 pages
    This document describes a VHDL entity for a ROM interface. The entity has ports for a clock, reset, enable signals, and data inputs and outputs. The architecture contains a state machine with 5 states that controls the bus selection, wait signal, and data output based on the clock, reset and other input signals.

    Original Title

    rom_interface

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    © © All Rights Reserved

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    This document describes a VHDL entity for a ROM interface. The entity has ports for a clock, reset, enable signals, and data inputs and outputs. The architecture contains a state machine with 5 states that controls the bus selection, wait signal, and data output based on the clock, reset and other input signals.

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Download as txt, pdf, or txt
    13 views2 pages

    Rom Interface

    Uploaded by

    Roshini M S
    This document describes a VHDL entity for a ROM interface. The entity has ports for a clock, reset, enable signals, and data inputs and outputs. The architecture contains a state machine with 5 states that controls the bus selection, wait signal, and data output based on the clock, reset and other input signals.

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Download as txt, pdf, or txt
    of 2

    library ieee ;

    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;

    entity my_rom_interface is
    port (
    rst_rom : in std_logic;
    clk_rom : in std_logic;
    rom_en_int : in std_logic;

    im_reqn : in std_logic;

    rom_data_in : in std_logic_vector(31 downto 0);

    wait_processor : out std_logic;


    bus_sel : out std_logic;
    dd_ins_data : out std_logic_vector(31 downto 0)

    );

    end my_rom_interface ;

    architecture my_rom_interface_a of my_rom_interface is

    type state_type is (S0,S1,S2,S3,S4);

    signal state_rom : state_type;

    signal bus_sel_o : std_logic;

    begin

    bus_sel <= bus_sel_o after 10 ns;


    --
    --bus_sel <= bus_sel_o;

    rom_p : process (clk_rom,rst_rom,state_rom)


    begin

    if clk_rom'event and clk_rom = '1' then

    if rst_rom = '0' then

    wait_processor <= '1';


    bus_sel_o <= '0';
    state_rom <= S0;
    dd_ins_data <= (others => '0');

    else
    case state_rom is

    when S0 =>
    if rom_en_int = '1' then

    wait_processor <= '0';


    bus_sel_o <= '1';

    state_rom <= S1;

    end if;

    when S1 =>

    state_rom <= S2;

    when S2 =>

    bus_sel_o <= '0';


    dd_ins_data <= rom_data_in;

    if im_reqn = '0' then


    state_rom <= S3; -- ins memory
    access
    else
    state_rom <= S0;
    wait_processor <= '1';

    end if;

    when S3 =>

    state_rom <= S4;

    when S4 =>

    wait_processor <= '1';


    state_rom <= S0;

    when others =>


    null;

    end case;

    end if;
    end if;
    end process rom_p;

    end my_rom_interface_a;

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