SYFgtj MZ2 Ds X6 TRXC ZSog 91 Yk JZW 30 IUBtl 8 JAb J
SYFgtj MZ2 Ds X6 TRXC ZSog 91 Yk JZW 30 IUBtl 8 JAb J
SYFgtj MZ2 Ds X6 TRXC ZSog 91 Yk JZW 30 IUBtl 8 JAb J
Datasheet
Features
• 800 V avalanche rugged power MOSFET allowing wide range VAC input range
to be covered
• Embedded HV startup and sense-FET
DIP-7
• Current mode PWM controller
S O16 narrow • Minimized system input power consumption:
– Less than 30 mW @ 230 VAC in no-load condition
DC Input Voltage DC Output Voltage
– Less than 400 mW @ 230 VAC with 250 mW load
• Limiting current with adjustable set point
-
• Jittered switching frequency to reduce the EMI filter cost:
– 60 kHz ±4 kHz (L type)
DRAIN COMP
– 115 kHz ±8 kHz (H type)
VIPER26 • Embedded error amplifier
GND VDD LIM FB • Hysteretic thermal shutdown
• Built-in soft-start for improved system reliability
• Protections with automatic restart: overload/short-circuit (OLP), feedback loop
disconnection
Application
• Auxiliary power supply for appliances
• Power metering
Product status link
• LED drivers
VIPER26
• SMPS for set-top boxes, DVD players and recorders
Product label
Description
The VIPER26 device is a smart high voltage converter that integrates an 800 V
avalanche-rugged power MOSFET with PWM current mode control. The power
MOSFET with 800 V breakdown voltage allows an extended input voltage range to
be applied, as well as the size of the DRAIN snubber circuit to be reduced.
This IC meets the most stringent energy-saving standards with very low consumption
and burst mode operation under light load.
The design of flyback, buck and buck boost converters is supported. The integrated
HV startup, sense-FET, error amplifier and oscillator with jitter allow complete
application designs with a minimum number of components.
1 Pin settings
16
1
8
DRAIN
N.C. DRAIN
VDD DRAIN
N.A. DRAIN
VDD N.C.
LIM
LIM N.C.
FB N.C.
FB COMP
COMP N.C.
Note: The copper area for heat dissipation has to be designed under the DRAIN pins.
Pin number
Name Function
DIP7 SO16N
Ground and MOSFET source. Connection of the source of the internal MOSFET and controller
1 1-2 GND
ground reference.
- 3 N.C. Not connected. This pin can be soldered to GND.
Not available for user. This pin is mechanically connected to the controller die pad of the frame. In
- 4 N. A.
order to improve noise immunity, it is highly recommended to connect it to GND (pin 1,2).
Controller Supply. An external storage capacitor has to be connected across this pin and GND. The
pin, internally connected to the high voltage current source, provides the VDD capacitor charging
2 5 VDD
current at startup and during fault conditions. A small bypass capacitor (0.1 μF typ.) in parallel, placed
as close as possible to the IC, is also recommended for noise filtering purposes.
Drain current limitation. This pin allows setting the drain current limitation to a lower value than the
default IDlim value. The limit can be reduced by connecting an external resistor between this pin and
3 6 LIM GND. In case of high electrical noise, a capacitor may be connected between this pin and GND; the
capacitor value must be lower than 470 nF in order to not impact the functionality of the pin. The pin
can be left open if the default drain current limitation, IDlim, is used.
Direct feedback. It is the inverting input of the internal transconductance E/A, which is internally
referenced to 3.3 V with respect to GND. In a non-isolated converter, the output voltage information is
4 7 FB
directly fed into the pin through a voltage divider. In primary regulation, the FB voltage divider is
connected to the VCC. The E/A is disabled by soldering FB to GND.
Compensation. It is the output of the internal E/A. A compensation network is placed between this
pin and GND to achieve stability and good dynamic performance of the control loop. In case of
5 8 COMP
isolated secondary side regulation, the internal E/A must be disabled and the COMP directly driven
by the optocoupler to control the DRAIN peak current setpoint.
Not internally connected. These pins must be left floating in order to ensure a safe clearance
- 9-12 N.C.
distance.
MOSFET drain. The internal high voltage current source sinks current from this pin to charge the
VCC capacitor at startup. These pins are mechanically connected to the internal metal PAD of the
7,8 13-16 DRAIN MOSFET in order to facilitate heat dissipation. On the PCB, the copper area must be placed under
these pins in order to decrease the total junction-to-ambient thermal resistance, thus facilitating the
power dissipation.
Max. value
Symbol Parameter Unit
SO16N DIP-7
1. When mounted on a standard, single side FR4 board with minimum copper area.
2. When mounted on a standard, single side FR4 board with 100 mm2 of Cu (35 µm thick).
RthJA/(RthJA@A=100mm2)
1.500
1.375
SO16N
DIP-7
1.250
1.125
1.000
0.875
0.750
0 25 50 75 100 125 150 175 200 225
*Copper tickness is 35 µm
A(mm2)
Voltage
IDRAIN = 1 mA; VCOMP = GND;
VDRAIN_START Drain-source start voltage - - 90 V
TJ = 25°C
IDDch1 Charging current during startup VDRAIN = 100 to 640 V; VDD = 4 V -0.6 - -1.8 mA
Current
IDD0 Operating supply current, not switching FOSC = 0 kHz; VCOMP = GND - - 0.6
IDDoff Operating supply current with VDD < VDDoff VDD < VDDoff - - 0.35
IDDol Open loop failure current threshold VDD = VDDclamp; VCOMP = 3.3 V 4 - -
Error amplifier
VREF_FB FB reference voltage - 3.2 3.3 3.4 V
Current limitation
IDLIM Drain current limitation ILIM = -10 µA; VCOMP = 3.3 V; TJ = 25 °C 0.66 0.7 0.74 A
Overload
tOVL Overload time - - 50 - ms
Oscillator section
VIPER26L 54 60 66
FOSC Switching frequency kHz
VIPER26H 103 115 127
FOSC = 60 kHz - ±4 -
FD Modulation depth kHz
FOSC = 115 kHz - ±8 -
Thermal shutdown
TSD Thermal shutdown temperature threshold - 150 160 - °C
1.00 1.00
0.80
0.80
0.60
0.60
0.40
0.40
0.20
0.20
0.00
0.00 -50 0 50 100 150
-50 0 50 100 150
Figure 7. GM vs. TJ Figure 8. VREF_FB vs. TJ
GM / GM@25C VREF_FB / VRE_FB@25C
2.00 2.00
1.80 1.80
1.60 1.60
1.40 1.40
1.20 1.20
1.00 1.00
0.80 0.80
0.60 0.60
0.40 0.40
0.20 0.20
0.00 0.00
-50 0 50 100 150 -50 0 50 100 150
Figure 9. ICOMP vs. TJ Figure 10. Operating supply current (no switching) vs TJ
ICOMP / ICOMP@25C IDD0 / IDD0@25C
2.00 2.00
1.80 1.80
1.60 1.60
1.40 1.40
1.20 1.20
1.00 1.00
0.80 0.80
0.60 0.60
0.40 0.40
0.20 0.20
0.00 0.00
-50 0 50 100 150 -50 0 50 100 150
Figure 11. Operating supply current (switching) vs TJ Figure 12. IDLIMvs. RLIM
IDD1 / IDD1@25C IDLIM/ IDLIM@100KOhm
2.00 1.20
1.80
1.00
1.60
1.40 0.80
1.20
1.00 0.60
0.80
0.40
0.60
0.40 0.20
0.20
0.00 0.00
-50 0 50 100 150 0 20 40 60 80 100 120
Figure 13. Power MOSFET on-resistance vs TJ Figure 14. Power MOSFET breakdown voltage vs TJ
RDSON/ RDSON@25C BVDSS/ BVDSS@25C
5.00 2.00
4.50 1.80
4.00 1.60
3.50 1.40
3.00 1.20
2.50 1.00
2.00 0.80
1.50 0.60
1.00 0.40
0.50 0.20
0.00 0.00
-50 0 50 100 150 -50 0 50 100 150
100
10
1
0.1 1 10 100 1000
VDS [V]
Figure 16. SOA SO16N package Figure 17. SOA DIP7 package
When mounted on a standard single side FR4 board with 100 mm² of When mounted on a standard single side FR4 board with 100 mm² of
Cu (35μm thick) Cu (35μm thick)
ID[A] I [A]
D
1.0E+01 1.0E+01
1.0E+00 1.0E+00
1.0E-01 1.0E-01
is is
ea ea
ar on) 1.0E-02 ar on)
(
this ds
1.0E-02 (
this ds R
n in x R
a ion in ax
atio M at M
er by er by
1.0E-03 Op ited 1.0E-03 Op ited
lim lim 1us
1us
10us 1.0E-04
10us
1.0E-04
100us 100us
1.0E-07 1.0E-07
1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+04
VDS[V] VDS[V]
VDDCSon
VDDoff
IDRAIN time
time
TJ
TSD
TSD - THYST
time
Normal operation Shut down after over temperature Normal operation
4 Typical circuits
D1 R1 L1
AC IN
VIPer26
FB DRAIN R3
C6
CONTROL
C1 C2
VDD
D4
COMP LIM GND R4
C3 R2
C4
R6
(Optional)
C5
AC IN L2 Vout
D3 C7
R5 C8
GND
C3 R3
BR
C6
- + D1
D2 R2 GND
C1 C2 R5
AC IN
C4
VIPer26
VDD DRAIN OPTO R6 R7
FB CONTROL
REF
R4 OPTO
(Optional) C5
R8
C3 R3
BR
C7
- + D1
C1 C2 D2 R2 GND
AC IN
C4
R4 VIPer26
VDD DRAIN
FB CONTROL
R5
C5
R6
(Optional) C6
R7
AC IN R1 L1 D3 Vout
C3 R2
C7
BR
- + D1
D2
GND
C1 C2
AC IN C4
R3 VIPer26
VDD DRAIN
FB CONTROL
R4
C5
R5
(Optional) C6
R6
AC IN R1 L1 D3 Vout
C3 R3
BR
C7
- + D1
C1 C2 D2 R2 GND
AC IN
C4
R4 VIPer26
VDD DRAIN
FB CONTROL
R5
C5
R6
(Optional) C6
R7
+
PWM
OLP
FB -
LOGIC
E/A OTP
VREF_FB +
RSENSE
COMP GND
Adapter (1) Open Frame (2) Adapter (1) Open Frame (2)
18 W 20 W 10 W 12 W
5 Power section
The power section is implemented with an n-channel power MOSFET with a breakdown voltage of 800 V min.
and a typical RDS(on) of 7 Ω. It includes a SenseFET structure to allow virtually lossless current sensing and a
thermal sensor.
The gate driver of the power MOSFET is designed to supply a controlled gate current during turn ON and turn
OFF in order to minimize common mode EMI. During UVLO conditions, an internal pull-down circuit holds the
gate low in order to ensure that the power MOSFET cannot be turned ON accidentally.
The high voltage current generator is supplied by the DRAIN pin. On initial startup of the converter, it is enabled
when the voltage across the input bulk capacitor reaches the VDRAIN_START threshold, sourcing the IDDch1 current
(see Table 6. Supply section). As the VDD voltage reaches the VDDon start-up threshold, the power section starts
switching and the high voltage current generator is turned OFF. The VIPer26 is powered by the external source.
After the start-up, the auxiliary winding or the diode connected to the output voltage must power the VDD capacitor
with a voltage higher than the VDDCSon threshold (see Table 6).
During the switching, the internal current source is disabled and the consumptions are minimized. If a fault occurs,
switching is stopped and the device is self biased by the internal high voltage current source; it is activated
between the levels VDDCSon and VDDon delivering the current IDDch2 to the VDD capacitor during the MOSFET
OFF time, see Figure 25.
At converter power-down, the VDD voltage drops and the converter activity stops as it falls below the VDDoff
threshold (see Table 6).
VDDCSon
VDDoff
VDRAIN time
IDD time
IDDch2
IDDch1
time
Power-on Normal operation Power-off
7 Oscillator
The switching frequency is internally fixed at 60 kHz (VIPER26LN or LD) or 115 kHz (VIPER26HN or HD).
In both cases, the switching frequency is modulated by approximately ±4 kHz (60 kHz version) or ±8 kHz (115
kHz version) at 230 Hz (typical) rate, so that the resulting spread-spectrum action distributes the energy of each
harmonic of the switching frequency over a number of sideband harmonics, having the same net energy but with
smaller amplitudes.
8 Soft startup
During the converter start-up phase, the soft-start function progressively increases the cycle-by-cycle drain
current limit, up to the default value IDlim. This way, the drain current is further limited and the output voltage is
progressively increased, therefore reducing the stress on the secondary diode. The soft-start time is internally
fixed to tSS (see typical value on Table 7. Controller section) and the function is activated for any converter start-
up attempt or a fault event.
This function helps prevent transformer saturation during start-up and short-circuit.
The VIPer26 includes a current mode PWM controller: cycle by cycle the drain current is sensed through the
integrated resistor RSENSE and the voltage is applied to the non inverting input of the PWM comparator, see
Figure 24. Block diagram. As soon as the sensed voltage is equal to the voltage derived from the COMP pin, the
power MOSFET is switched OFF.
In parallel with the PWM operations, the comparator OCP, see Figure 24, checks the level of the drain current and
switch OFF the power MOSFET in case the current is higher than the threshold IDlim, see Table 7. Controller
section.
The level of the drain current limit, IDlim, can be reduced depending on the sunk current from the pin LIM. The
resistor RLIM, between LIM and GND pins, fixes the current sunk and therefore the level of the current limit, IDlim,
see Figure 12. IDLIMvs. RLIM.
When the LIM pin is left open or if the RLIM has a high value (i.e., > 80 kΩ), the current limit is fixed to its default
value, IDlim, as reported in Table 7.
The device can be used both in non-isolated and in isolated topology. In case of non-isolated topology, the
feedback signal from the output voltage is applied directly to the FB pin as inverting input of the internal error
amplifier with reference voltage, VREF_FB, see Table 7. Controller section.
The output of the error amplifier sources and sinks the current, ICOMP, to and from the compensation network
connected on the COMP pin. This signal is then compared in the PWM comparator with the signal coming from
the SenseFET; the power MOSFET is switched off when the two values are the same on a cycle by cycle basis.
See Figure 24. Block diagram and Figure 26. Feedback circuit.
When the power supply output voltage is equal to the error amplifier reference voltage, VREF_FB, a single resistor
has to be connected from the output to the FB pin. For higher output voltages, the external resistor divider is
needed. If the voltage on FB pin is accidentally left floating, an internal pull-up protects the controller.
The output of the error amplifier is externally accessible through the COMP pin and it is used for the loop
compensation: usually an RC network.
As shown in Figure 26, the internal error amplifier has to be disabled in isolated power supplies (FB pin shorted to
GND). In this case, an internal resistor is connected between an internal reference voltage and the COMP pin,
see Figure 26. The current loop has to be closed on the COMP pin through the opto-transistor in parallel with the
compensation network. The VCOMP dynamic range is between VCOMPL and VCOMPH, as shown in Figure 27.
When the voltage VCOMP drops below the voltage threshold VCOMPL, the converter enters burst mode, see
Section 11 Burst mode.
When the voltage VCOMP rises above the VCOMPH threshold, the peak drain current will reach its limit, as well as
the deliverable output power.
VREF
COMP
IDRAIN
I Dlim
IDlim_bm
VCOMP
VCOMPL VCOMPH
11 Burst mode
When the voltage VCOMP drops below the threshold, VCOMPL, the power MOSFET is kept in the OFF state and
the consumption is reduced to IDD0 current, as given in Table 6. Supply section. In reaction to the energy delivery
interruption, the VCOMP voltage increases and, as soon as it exceeds the threshold VCOMPL + VCOMPL_HYS, the
converter starts switching again with consumption level equal to IDD1 current. This ON-OFF operation mode,
referred to as “burst mode” (see Figure 28), reduces the average frequency, which can fall down even to a few
hundreds hertz, thus minimizing all frequency-related losses and making it easier to comply with energy saving
regulations. During burst mode, the drain current limit is reduced to the value IDlim_bm (given in Table 7. Controller
section) in order to avoid audible noise issues.
VCOMPL +VCOMPL_HYS
VCOMPL
time
IDD
IDD1
IDD0
IDRAIN time
IDlim_bm
time
Burst Mode
The overload protection is implemented automatically through the integrated up-down counter. Every cycle, it is
incremented or decremented depending on whether the current logic detects the limit condition or not. The limit
condition is the peak drain current, IDlim given in Table 7. Controller section, or the one set by the user through the
RLIM resistor, as shown in Figure 12. IDLIMvs. RLIM.
After the reset of the counter, if the peak drain current is continuously equal to the level IDlim, the counter will be
incremented until the fixed time, tOVL, after which the power MOSFET switch ON is disabled. It is activated again,
through the soft start, after the tRESTART time, see Figure 29. Timing diagram: OLP sequence and the relevant
time values in Table 7.
In case of an overload or short-circuit event, the power MOSFET switching is stopped after a time that depends
on the counter and whose maximum can equal tOVL. The protection occurs in the same way until the overload
condition is removed, see Figure 29.
This protection ensures restart attempts of the converter with low repetition rate, so that it works safely with
extremely low power throughput and avoids IC overheating in case of repeated overload events.
If the overload is removed before the protection tripping, the counter will be decremented cycle by cycle down to
zero and the IC will not be stopped.
VDDon
VDDCSon
IDRAIN
time
IDLIM
If the power supply is built in fly-back topology and the VIPer26 is supplied by an auxiliary winding, as shown in
Figure 30. FB pin connection for non-isolated flyback and Figure 31. FB pin connection for isolated fly-back, the
converter is protected against feedback loop failure or accidental disconnections of the winding.
Regarding the Figure 30 and Figure 31 schematics for non-isolated flyback and isolated flyback, if RH is opened
or RL is shorted, the VIPer26 works at its drain current limitation. The output
voltage, VOUT, will increase and so will the auxiliary voltage, VAUX, which is coupled with the output according to
the secondary-to-auxiliary turns ratio.
As the auxiliary voltage increases up to the internal VDD active clamp, VDDclamp (value given in Table 7. Controller
section) and the clamp current injected on VDD pin exceeds the open loop failure current threshold, IDDol (value
given in Table 7), a fault signal is internally generated.
In order to distinguish an actual malfunction from a bad auxiliary winding design, both the above conditions (drain
current equal to the drain current limitation and VDD current higher than IDDol through VDD clamp) have to be
verified to reveal the fault.
If RL is opened or RH is shorted, the output voltage, VOUT, will be clamped to the reference voltage VREF_FB in
case of non isolated flyback or to the external TL voltage reference in case of isolated flyback).
C VAUX
VDD
VDD
VOUT
V PWM stop
COMPL
+
RH BUS
FB
from R
- SENSE
E/A
+
RL V
REF_FB
to PWM
nR +
COMP
Rs
Cp
Cs
C
VDD
VAUX
V
REF_FB
R V PWM st op
comp COMPL
+
-
SW
BUS
FB Disable d
- from R
SENSE
VOUT
E/A
+
V to PWM
REF_FB
nR +
Ropto
R
H
COMP
R3
U5
Rc Cc
Cc omp
TL
R
L -
14 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
Dim. mm
Notes
Min. Typ. Max.
A - - 5.33 -
A1 0.38 - - -
A2 2.92 3.30 4.95 -
b 0.36 0.46 0.56 -
b2 1.14 1.52 1.78 -
c 0.20 0.25 0.36 -
D 9.02 9.27 10.16 -
E 7.62 7.87 8.26 -
E1 6.10 6.35 7.11 -
e - 2.54 - -
eA - 7.62 - -
eB - - 10.92 -
L 2.92 3.30 3.81 -
M - 2.508 6-8
N 0.40 0.50 0.60 -
N1 - - 0.60 -
O - 0.548 - 7-8
mm
Dim.
Min. Typ. Max.
A 1.75
A1 0.1 0.25
A2 1.25
b 0.31 0.51
c 0.17 0.25
D 9.8 9.9 10
E 5.8 6 6.2
E1 3.8 3.9 4
e 1.27
h 0.25 0.5
L 0.4 1.27
k 0 8
ccc 0.1
15 Order code
VIPER26LN
DIP-7 Tube
VIPER26HN
VIPER26HD Tube
VIPER26HDTR Tape and reel
SO16N
VIPER26LD Tube
VIPER26LDTR Tape and reel
Revision history
Contents
1 Pin settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical and thermal ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of tables
Table 1. Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 4. Avalanche characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 6. Supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 7. Controller section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 8. VIPer26 typical power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 9. DIP-7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. SO16 narrow mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
List of figures
Figure 1. Connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. Rth versus area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. IDLIM vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. FOSC vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. VDRAIN_START vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. HCOMP vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. GM vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 8. VREF_FB vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 9. ICOMP vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 10. Operating supply current (no switching) vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 11. Operating supply current (switching) vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 12. IDLIMvs. RLIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 13. Power MOSFET on-resistance vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 14. Power MOSFET breakdown voltage vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 15. Power MOSFET capacitance variation vs VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 16. SOA SO16N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 17. SOA DIP7 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 18. Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 19. Buck converter (VOUT>VDDCSon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 20. Flyback converter (isolated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 21. Flyback converter (primary regulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 22. Flyback converter (non isolated, VOUT ≥ VDDCSon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 23. Flyback converter (non isolated, VOUT < VDDCSon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 24. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 25. Power ON and power OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 26. Feedback circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27. COMP pin voltage versus IDLIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 28. Load-dependent operating modes: timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 29. Timing diagram: OLP sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 30. FB pin connection for non-isolated flyback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 31. FB pin connection for isolated fly-back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 32. DIP-7 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 33. SO16 narrow package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27