Freescale Semiconductor Document Number: MC34119

Technical Data Rev. 3.0, 12/2006

Low Power Audio Amplifier

The 34119 is a low power audio amplifier integrated circuit
34119
intended for telephone applications, such as in speakerphones. It
provides differential speaker outputs to maximize output swing at low
supply voltages (2.0 V minimum). Coupling capacitors to the speaker
are not required. Open loop gain is 80 dB, and the closed loop gain LOW POWER AUDIO AMPLIFIER
is set with two external resistors. A Chip Disable pin permits powering
down and/or muting the input signal.

Features
• Wide Operating Supply Voltage Range (2.0 V to 16 V), Allows
Telephone Line Powered Applications
• Low Quiescent Supply Current (2.7 mA Typ) for Battery Powered
Applications D SUFFIX
• Chip Disable Input to Power Down the IC EF SUFFIX (PB-FREE)
98ASB42564B
• Low Power--Down Quiescent Current (65 µA Typ)
8-PIN SOICN
• Drives a Wide Range of Speaker Loads (8.0 Ω and Up)
• Output Power Exceeds 250 mW with 32 Ω Speaker
ORDERING INFORMATION
• Low Total Harmonic Distortion (0.5% Typ)
• Gain Adjustable from <0 dB to >46 dB for Voice Band Device
Temperature
Package
• Requires Few External Components Range (TA)
• Pb-Free Packaging Designated by Suffix Code EF MC34119D/R2
-20°C to 70°C 8 SOICN
MCZ34119EF/R2

34199 CC
6
V01
Audio VIN 5
4
Input
3
FC1

V02
8

2
1 CD Chip
FC2
7 Disable

GND

Figure 1. 34119 Simplified Application Diagram

Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM

INTERNAL BLOCK DIAGRAM

VCC
7

VIN 4 --
#1 5 V01
FC1 3 +
4.0 k
4.0 k

50 k --
125 k #2 8 V02
FC2 2 +

50 k Bias
1 CD
Circuit

7
GND

Figure 2. 34119 Simplified Internal Block Diagram

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2 Freescale Semiconductor
 PIN CONNECTIONS

PIN CONNECTIONS

CD 1 8 V02

FC2 2 7 GND

FC1 3 6 VCC

VIN 4 5 V01

Figure 3. 34119 Pin Connections

Table 1. 34119 Pin Definitions

Pin Number Pin Name Definition

1 CD Chip Disable -- Digital input. A Logic “0” (<0.8 V) sets normal operation. A logic “1” (≥2.0 V) sets the power down
mode. Input impedance is nominally 90 kΩ.

2 FC2 A capacitor at this pin increases power supply rejection, and affects turn--on time. This pin can be left open if
the capacitor at FC1 is sufficient.

3 FC1 Analog ground for the amplifiers. A 1.0 µF capacitor at this pin (with a 5.0 µF capacitor at Pin 2) provides
(typically) 52 dB of power supply rejection. Turn--on time of the circuit is affected by the capacitor on this pin.
This pin can be used as an alternate input.

4 VIN Amplifier input. The input capacitor and resistor set low frequency rolloff and input impedance. The feedback
resistor is connected to this pin and VO1.

5 V01 Amplifier Output #1. The dc level is ≈ (VCC - 0.7 V)/2.

6 VCC DC supply voltage (+2.0 V to +16 V) is applied to this pin.

7 GND Ground pin for the entire circuit.

8 V02 Amplifier Output #2. This signal is equal in amplitude, but 180° out--of--phase with that at VO1. The dc level is
≈ (VCC -- 0.7 V)/2.

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ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings Symbol Min Max Unit

ELECTRICAL RATINGS

Supply Voltage VCC 2.0 16 VDC

Voltage @ CD (Pin 1) VCD 0.0 VCC VDC
Load Impedance (at VIN) RL 8.0 - Ω

Peak Load Current IL - ±200 mA

Differential Gain (5.0 kHz Bandwidth) AVD 0.0 46 dB

THERMAL RATINGS

Ambient Temperature TA -20 70 °C

THERMAL RESISTANCE

Peak Package Reflow Temperature During Reflow (1), (2) TPPRT Note 2 °C

Notes
1. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
2. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.

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4 Freescale Semiconductor
 ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions -1.0 V ≤ VCC ≤ 18 V, - 20°C ≤ TA ≤ 70°C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit

AMPLIFIERS

Output DC Level @ VO1, VO2, VCC = 3.0 V, RL = 16 (RF = 75 k) VO(3) 1.0 1.15 1.25 V
VCC = 6.0 V VO(6) - 2.65 -
VCC = 12 V VO(12) - 5.65 -

Output Level V
High (IOUT = -75 mA, 2.0 V ≤ VCC ≤ 16 V) VOH - VCC - 1.0 -
Low (IOUT = 75 mA, 2.0 V ≤ VCC ≤ 16 V) VOL - 0.16 -

Output DC Offset Voltage (VO1 - VO2) ∆VO mV

(VCC = 6.0 V, RF = 75 kΩ, RL = 32Ω) -30 0.0 30

Input Bias Current @ VIN (VCC = 6.0 V) IIB - -100 -200 nA

Equivalent Resistance kΩ
@ FC1 (VCC = 6.0 V) RFC1 100 150 220
@ FC2 (VCC = 6.0 V) RFC2 18 25 40

CHIP DISABLE

Input Voltage V
Low VIL - - 0.8
High VIH 2.0 - -
Input Resistance (VCC = VCD = 16 V) RCD 50 90 175 kΩ

POWER SUPPLY

Power Supply Current

(VCC = 3.0 V, RL = ∞, CD = 0.8 V) ICC3 - 2.7 4.0 mA
(VCC= 16 V, RL = ∞, CD = 0.8 V) ICC16 - 3.3 5.0 mA
(VCC = 3.0 V, RL = ∞, CD = 2.0 V) ICCD - 65 100 µA

TYPICAL TEMPERATURE PERFORMANCE (-20°C < TA < 70°C)

Input Bias Current @ VIN IIN - ±40 - pA/°C

Total Harmonic Distortion THD - ±0.003 - %/°C
(VCC = 6.0 V, RL = 32Ω, POUT = 125 mW, f = 1.0 kHz)

Power Supply Current ICC µA/°C

(VCC = 3.0 V, RL = ∞, CD = 0 V - -2.5 -
(VCC = 3.0 V, RL = ∞, CD = 2.0 V) - -0.03 -

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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions -1.0 V ≤ VCC ≤ 18 V, - 20°C ≤ TA ≤ 70°C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit

AMPLIFIERS

AC Input Resistance (@ VIN) RI - > 30 - MΩ

Open Loop Gain (Amplifier #1, f < 100 Hz) AVOL1 80 - - dB
Closed Loop Gain (Amplifier #2, VCC = 6.0 V, f = 1.0 kHz, RL = 32Ω) AV2 -0.35 0.0 0.35 dB
Gain Bandwidth Product GBW - 1.5 - MHz
Output Power mW
VCC = 3.0 V, RL = 16Ω, THD ≤ 10% POUT3 55 - -
VCC = 6.0 V, RL = 32Ω, THD ≤ 10% POUT6 240 - -
VCC = 12 V, RL = 100Ω, THD ≤ 10%% POUT12 400 - -

Total Harmonic Distortion (f = 1.0 kHz) THD %

(VCC = 6.0 V, RL = 32Ω, POUT = 125 mW) - 0.5 1.0
(VCC ≥ 3.0 V, RL = 8.0Ω, POUT = 20 mW) - 0.5 -
(VCC ≥ 12 V, RL = 32Ω, POUT = 200 mW) - 0.6 -

Power Supply Rejection (VCC = 6.0 V, ∆VCC = 3.0 V) PSRR dB

(C1 = ∞, C2 = 0.01 µF) 50 - -
(C1 = 0.1 µF, C2 = 0, f = 1.0 kHz) - 12 -
(C1 = 1.0 µF, C2 = 5.0 µF, f = 1.0 kHz) - 52 -

Differential Muting (VCC = 6.0 V, 1.0 kHz ≤ f ≤ 20 kHz, CD = 2.0 V) GMT - > 70 - dB

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 ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES

ELECTRICAL PERFORMANCE CURVES

60

PSRR, POWER SUPPLY REJECTION (dB)

C1 ≥ 1.0 µF
100 0
36 50

∅, EXCESS PHASE (DEGREES)

80 Phase 72 C1 = 0.1 µ F
108 40
60 144
AVOL (dB)

30
180
Gain
40
20 C1 = 0

20
10

0 0
100 1.0 k 10 k 100 k 1.0 M 200 1.0 k 10 k 20 k
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
(C2= 5.0µF)

Figure 4. Amplifier #1 Open Loop Gain and Phase Figure 7. Power Supply Rejection versus Frequency

60
36 C1 = 5.0 µ F
Rf = 150 k, RI = 6.0 k PSRR, POWER SUPPLY REJECTION (dB)
50
32 C1 = 1.0 µF
DIFFERENTIAL GAIN (dB)

40
24 Rf = 75 k, RI = 3.0 k
C1 = 0.1 µF
30
Rf
0.1
16
Input -- VO1 20
RI #1
+ VO
VO2
8 10
#2
C1 = 0
0
0 200 1.0 k 10 k 20 k
100 1.0 k 10 k 20 k
f, FREQUENCY (Hz) f, FREQUENCY (Hz)
(C2= 1.0µ F)
Figure 5. Differential Gain versus Frequency Figure 8. Power Supply Rejection versus Frequency

60 60
C1 ≥ 1.0 µF
PSRR, POWER SUPPLY REJECTION (dB)
PSRR, POWER SUPPLY REJECTION (dB)

50 50
C1 = 0.1 µF
C1 = 5.0 µF
40 40

30 30

20 C1 = 0 C1 = 1.0 µF
20

10 10 C1 = 0.1 µF

0 0
200 1.0 k 10 k 20 k 200 1.0 k 10 k 20 k
f, FREQUENCY (Hz) f, FREQUENCY (Hz)
(C2= 10 µF) (C2= 0)
Figure 6. Power Supply Rejection versus Frequency Figure 9. Power Supply Rejection versus Frequency

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Freescale Semiconductor 7
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES

10

THD, TOTAL HARMONIC DISTORTION (%)

1000

8.0 VCC = 3.0 V,

DEVICE DISSIPATION (mW)

800 VCC = 12 V RL = 16 Ω
VCC = 6.0 V
6.0 VCC = 3.0 V, VCC = 6.0 V,
600 RL = 32 Ω
RL = 8.0 Ω

4.0
400
VCC = 16 V, VCC = 6.0 V,
VCC = 3.0 V RL = 32 Ω VCC = 12 V,
RL = 16 Ω RL = 32 Ω
200 2.0

0
0 0 100 200 300 400 500
0 30 60 90 120 150
LOAD POWER (mW) POUT, OUTPUT POWER (mW)
(f= 1.0kHz,AVD = 34 dB)

Figure 10. Device Dissipation, 8.0Ω Load Figure 13. Distortion versus Power

10

THD, TOTAL HARMONIC DISTORTION (%)

1200
VCC = 16 V
1000 VCC = 12 V 8.0 VCC = 3.0 V,
DEVICE DISSIPATION (mW)

RL = 16 Ω VCC = 3.0 V,
RL = 8.0 Ω
800 6.0 VCC = 6.0 V,
RL = 32 Ω
600 VCC = 6.0 V
4.0 VCC = 16 V,
RL = 32 Ω Limit
400
2.0
200 VCC = 3.0 V

0 VCC = 6.0 V, RL = 16 Ω VCC = 12 V, RL = 32 Ω

0 0 100 200 300 400 500
0 100 200 300 400
POUT , OUTPUT POWER (mW)
LOAD POWER (mW) (f= 3.0kHz,AVD = 34 dB)
Figure 11. Device Dissipation, 16 Ω Load Figure 14. Distortion versus Power

10
THD, TOTAL HARMONIC DISTORTION (%)

1200
VCC = 3.0 V,
VCC = 16 V VCC = 12 V RL = 16 Ω
1000 8.0
DEVICE DISSIPATION (mW)

VCC = 3.0 V,
RL = 8.0 Ω
800 6.0 VCC = 6.0 V,
RL = 32 Ω
600 VCC = 16 V,
4.0
RL = 32 Ω Limit
400 VCC = 6.0 V, VCC = 12 V,
VCC = 6.0 V
2.0 RL = 16 Ω Limit RL = 32 Ω
200
VCC = 3.0 V
0
0 0 100 200 300 400 500
0 100 200 300 400 500
POUT , OUTPUT POWER (mW)
LOAD POWER (mW)
(f= 1,3.0kHz,AVD = 12 dB)
Figure 12. Device Dissipation, 32 Ω Load Figure 15. Distortion versus Power

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8 Freescale Semiconductor
 ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES

500
RL = 32 Ω

1.0 V/DIV
OUTPUT
400
LOAD POWER (mW)

RL = 16 Ω
300

200
RL = 8.0 Ω

80 mV/DIV
100

INPUT
TA = 25°C--Derate at higher temperatures
0
0 2.0 4.0 6.0 8.0 10 12 14 16
20 µ s/DIV
VCC, SUPPLY VOLTAGE (V)

Figure 16. Maximum Allowable Load Power Figure 19. Large Signal Response

4.0 1.5
RL = ∞
I CC , POWER SUPPLY CURRENT (mA)

1.4
CD = 0
3.0
1.3
VCC --VOH (V)
1.2
2.0
1.1
2.0 ≤ VCC ≤16 V
1.0 1.0

CD = VCC 0.9 TA = 25°C

0 0.8
0 2.0 4.0 6.0 8.0 10 12 14 16 0 40 80 120 160 200
VCC, SUPPLY VOLTAGE (V) ILOAD, LOAD CURRENT (mA)
Figure 17. Power Supply Current Figure 20. VCC-VOH @ V01, V02 versus load Current

1.4
20 mV/DIV
OUTPUT

1.2 TA = 25°C
VOL, OUTPUT LOW LEVEL (V)

VCC = 2.0 V
1.0

0.8

0.6 VCC = 3.0 V

0.4
1.0 mV/DIV
INPUT

0.2 VCC 6.0 V

0
20 µ s/DIV 0 40 80 120 160 200
ILOAD, LOAD CURRENT (mA)

Figure 18. Small Signal Response Figure 21. VOL @ V01, V02 versus Load Current

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Freescale Semiconductor 9
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES

200
36

AVD, DIFFERENTIAL GAIN (dB)

160 32

120 24
ICD , ( A)

80 16

40 8.0
Valid for VCD ≤ VCC
0 0
0 4.0 8.0 12 16 100 1.0 k 10 k 20 k
VCD, CHIP DISABLE VOLTAGE (V) f, FREQUENCY (Hz)

Figure 22. Input Characteristics @ CD (Pin 1) Figure 25. Frequency Response of Figure 24

1000 pF
6 VCC
100 k 1000 pF

0.1 3.0 k 100 k

4
-- 5 0.05 0.05
#1 6 VCC
3 Speaker
+
0.1 4.0 k 5.1 k 5.1 k
4.0 k
Input 4
-- 5
50 k -- 3 #1
5.0 µF 125 k #2
8 + Speaker
2 0.1 4.0 k
+ 4.0 k
Input
50 k Bias 1 50 k
Disable 5.0 µF 2 -- 8
Circuit 125 k #2
+
50 k Bias 1
7 GND Disable
Circuit
Differential Gain = 34 dB
7
Frequency Response: See figure 5
Input Impedance 125 k Ω GND
PSRR 50 dB
Figure 26. Audio Amplifier with Bandpass
Figure 23. Small Signal Response

75 k 36
AVD, DIFFERENTIAL GAIN (dB)

0.05 0.05 6 VCC 32

5.1 k 5.1 k
4 24
-- 5
3 #1
+ Speaker
0.1 4.0 k 16
4.0 k
Input
50 k
5.0 µF -- 8
8.0
2 125 k #2
+
50 k Bias 1
Disable 0
Circuit 100 1.0 k 10 k 20 k
7 f, FREQUENCY (Hz)
GND
Figure 27. Frequency Response of Figure 26
Figure 24. Audio Amplifier with Bass Suppression

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10 Freescale Semiconductor
 ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES

Rf 75 k
6 VCC (+1.0 V to +8.0 V)
CI RI
0.1 3.0 k VIN 4
Audio Input -- 5 VO1
FC1 3 #1 Speaker
+
4.0 k
4.0 k

50 k -- 8 VO2
2 125 k #2
FC2 +
50 k Bias 1 CD
Circuit 4700
20 k
7 Chip Disable
VEE 20 k
(--1.0 V to --8.0 V) 10 k
VCC

NOTE: If VCC and VEE are not symmetrical about ground then FC1 must be
connected through a capacitor to ground as shown on the front page. VEE
Figure 28. Split Supply Operation

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Freescale Semiconductor 11
FUNCTIONAL DESCRIPTION
INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 34119 is a low power audio amplifier capable of low differential gain is set by two external resistors. Pins FC1 and
voltage operation (VCC = 2.0 V minimum), such as that FC2 allow control of the amount of power supply and noise
encountered in line-powered speakerphones. The circuit rejection, as well as providing alternate inputs to the
provides a differential output (VO1-VO2) to the speaker to amplifiers. The CD pin permits power down of the IC for
maximize the available voltage swing at low voltages. The muting purposes and to conserve power.

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

AMPLIFIERS capacitors must charge up through the internal 50 k and

Referring to the Internal Block Diagram on page 2, the 125 k. resistors. The graph of Figure 29 indicates the turn-on
internal configuration consists of two identical operational time upon application of VCC of +6.0 V. The turn-on time is
amplifiers. Amplifier #1 has an open loop gain of ≥80 dB (at ≈60% longer for VCC = 3.0 V, and ≈20% less for VCC = 9.0 V.
f ≤ 100 Hz), and the closed loop gain is set by external Turn-off time is <10 µs upon removal of VCC.
resistor RF and RI. The amplifier is unity gain stable, and has
a unity gain frequency of approximately 1.5 MHz. In order to
adequately cover the telephone voice band (300 Hz to 3400 360
Hz), a maximum closed loop gain of 46 is recommended.
Amplifier #2 is internally set to a gain of - 1.0 (0 dB). 300
t, TURN--ON TIME (ms)
The outputs of both amplifiers are capable of sourcing and
240 C1 = 5.0 µF
sinking a peak current of 200 mA. The outputs can typically
swing to within ≈0.4 V above ground, and to within ≈1.3 V
180
below VCC, at the maximum current. See Figures 20 and 21
for VOH and VOL curves.
120
The output dc offset voltage (VO1 - VO2) is primarily a
function of the feedback resistor (RF), and secondarily due to C1 = 1.0 µF
60
the amplifiers’ input offset voltages. The input offset voltage VCC switching from
of the two amplifiers will generally be similar for a particular 0 V to 6.0 V
0
IC, and therefore nearly cancel each other at the outputs. 0 2.0 4.0 6.0 8.0 10
Amplifier #1’s bias current, however, flows out of VIN (Pin 4) C2, CAPACITANCE (µF)
and through RF, forcing VO1 to shift negative by an amount Figure 29. Turn-On Time versus C1 and C2 at Power-On
equal to [RF ⋅ IIB]. VO2 is shifted positive an equal amount.
The output offset voltage, specified in the Electrical CHIP DISABLE
Characteristics, is measured with the feedback resistor
The Chip Disable (Pin 1) can be used to power down the
shown in the Typical Applications Circuit, and therefore takes
IC to conserve power, or for muting, or both. When at a Logic
into account the bias current as well as internal offset
“0” (0 V to 0.8 V), the 34119 is enabled for normal operation.
voltages of the amplifiers. The bias current is constant with
When Pin 1 is at a Logic “1” (2.0 V to VCC V), the IC is
respect to VCC.
disabled. If Pin 1 is open, that is equivalent to a Logic “0,”
although good design practice dictates that an input should
FC1 AND FC2 never be left open. Input impedance at Pin 1 is a nominal
Power supply rejection is provided by the capacitors (C1 90 kΩ. The power supply current (when disabled) is shown in
and C2 in the Typical Applications Circuit) at FC1 and FC2. Figure 17.
C2 is somewhat dominant at low frequencies, while C1 is Muting, defined as the change in differential gain from
dominant at high frequencies, as shown in the graphs of normal operation to muted operation, is in excess of 70 dB.
Figures 6 to 9. The required values of C1 and C2 depend on The turn-off time of the audio output, from the application of
the conditions of each application. A line powered the CD signal, is <2.0 µs, and turn-on time is 12 ms-15 ms.
speakerphone, for example, will require more filtering than a Both times are independent of C1, C2, and VCC.
circuit powered by a well regulated power supply. The
When the 34119 is disabled, the voltages at FC1 and FC2
amount of rejection is a function of the capacitors, and the
equivalent impedance looking into FC1 and FC2 (listed in the do not change as they are powered from VCC. The outputs,
Electrical Characteristics as RFC1 and RFC2). VO1 and VO2, change to a high impedance condition,
removing the signal from the speaker. If signals from other
In addition to providing filtering, C1 and C2 also affect the sources are to be applied to the outputs (while disabled), they
turn-on time of the circuit at power-up, since the two must be within the range of VCC and Ground.

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12 Freescale Semiconductor
 FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION

POWER DISSIPATION Figures 10 to 12, along with Figures 13 to 15 (distortion

Figures 10 to 12 indicate the device dissipation (within the curves), and a peak working load current of ±200 mA, define
IC) for various combinations of VCC, RL, and load power. the operating range for the 34119. The operating range is
further defined in terms of allowable load power in Figure 16
The maximum power which can safely be dissipated within
for loads of 8.0Ω, 16Ω and 32Ω. The left (ascending) portion
the MC34119 is found from the following equation:
which 10% distortion occurs. The center flat portion of each
curve is defined by the maximum output current capability of
PD = (140°C - TA)/θJA the 34119. The right (descending) portion of each curve is
defined by the maximum internal power dissipation of the IC
where TA is the ambient temperature; and θJA is the package at 25°C. At higher ambient temperatures, the maximum load
thermal resistance (100°C/W for the standard DIP package, power must be reduced according to the above equations.
and 180°C/W for the surface mount package.) Operating the device beyond the current and junction
The power dissipated within the 34119, in a given temperature limits will degrade long term reliability.
application, is found from the following equation:
LAYOUT CONSIDERATIONS
PD = (VCC x ICC) + (IRMS x VCC) - (RL x IRMS2) Normally a snubber is not needed at the output of the
34119, unlike many other audio amplifiers. However, the PC
where ICC is obtained from Figure 17; and IRMS is the RMS board layout, stray capacitances, and the manner in which
current at the load; and RL is the load resistance. the speaker wires are configured, may dictate otherwise.
Generally, the speaker wires should be twisted tightly, and
not more than a few inches in length.

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TYPICAL APPLICATIONS

TYPICAL APPLICATIONS

RF
75 k
6 VCC

CI
RI
0.1 VIN
Audio 3.0 k 4
-- 5 VO1
Input #1
FC1 3 Speaker
+
4.0 k
C1 4.0 k
1.0 µ F
C2* 50 k
5.0 µ F -- 8 VO2
2 125 k #2
+
FC2
50 k Bias 1 CD Chip
Circuit Disable

7
* = Optional GND
RF
Differential Gain = 2 x
RI This device contains 45 active transistors.

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14 Freescale Semiconductor
 PACKAGING
PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.

D SUFFIX
EF SUFFIX (PB-FREE)
PLASTIC PACKAGE
98ASB42564B
ISSUE U

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Freescale Semiconductor 15
REVISION HISTORY

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES

2.0 11/2006 • Converted to the current Freescale format

• Implemented Revision History page
• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from
Maximum Ratings on page 4. Added note with instructions from www.freescale.com
• Updated the Package drawing to the current revision
3.0 12/2006 • Restated note Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC
standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels
(MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter
the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. on
page 4

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Analog Integrated Circuit Device Data

16 Freescale Semiconductor
How to Reach Us: RoHS-compliant and/or Pb-free versions of Freescale products have the functionality
and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free
Home Page: counterparts. For further information, see http://www.freescale.com or contact your
www.freescale.com Freescale sales representative.

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MC34119
Rev. 3.0
12/2006