MAHARASHTRASTATEBOARDOFTECHNICALEDUCATION,

MUMBAI.

A PROJECT REPORT
ON

“Build R-S Flip Flop”

DIPLOMA
IN

ELECTRONICS AND COMPUTER ENGINEERING

Submitted by,
MR. Sanskar Tushar Sutar
MR. Om Amol Patil
MR. Ritesh Rupesh Sutar
MR. Devaj Mahadev Patil

UNDER THE GUIDANCE OF

Mr.S.M.ADAVKAR

DEPARTMENT OF ELECTRONICS AND COMPUTER ENGINEERING

SANT GAJANAN MAHARAJ RURAL POLYTECHNIC
MAHAGAON
ACADEMIC YEAR 2023-2024
 ACADEMICYEAR2023-2024
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
ACADEMIC YEAR2023-2024

“SANT GAJANAN MAHARAJ RURAL POLYTECHNIC”

A/P–MAHAGAON,SITE–CHINCHEWADI,TAL-GADHINGLAJ,DIST-KOLHAPUR

Certificate
This is to certify that the following student of Third semester of Diplomain Electronic
and Computer of Institute SANT GAJANAN RURAL POLYTECHNIC,MAHAGAON-
416503.(CODE-0965)has completed micro-projecton“Build A R-S Flip Flop”satisfactory in
subject code 22320 for academic year 2023 to 2024 as prescribed in the curriculum.

Roll No. Enrollment No. Seat No. Name of Student

14. 2209650084 208738 MR. SANSKAR TUSHAR SUTAR

17. 2209650087 208741 MR. OM AMOL PATIL

23. 2209650093 208747 MR. RITESH RUPESH SUTAR

42. 2209650119 208766 MR.DEVRAJ MAHADEV PATIL

DATE: PLACE:-MAHAGAON

Mr.S.M.ADAVKAR Mr.M.P.PATIL Mrs.R.S.PATIL

(Project Guide) (Head of department) (Principal)
 INDEX
SR.NO NAME PAGE NO.
PART
A
1 1.0 Brief Introduction 1
2 2.0 Aim of the Micro project 1
3 3.0 Intended Course Outcomes 1

4 4.0 Literature Review 1

5 5.0 Proposed Methodology 1
6 6.0 Resources Required 2
7 7.0 Action Plan 2

PART B
8 1.0 Rationale 3
9 2.0 Course Outcomes Addressed 3
10 3.0 Literature Review 3
11 4.0 Actual Methodology 3
12 5.0 Actual Resources Used 4

13 6.0 Information of Flip flops

 RS Flip Flop 4
 Debounce circuit 6
6
 Clocked RS Flip Flop
 D Flip Flop 8
 JK Flip Flop 9
 Characteristics of JK Flip Flop 10
 Master Salve JK Flip Flop 10

14 7.0 Skill Developed / Learning Out of 12

this Micro Project
16 8.0 Conclusion 12
17 9.0 Reference 12

1
 In digital circuits, the flip-flop is a kind of bitable multivibrator. It is a sequential circuit/an electronic
circuit which has two stable states represents a "one" and the other represents a"zero". Such data
storage can be used for storage of state, and such a circuit is described assequential logic in electronics.
When used in a finite-state machine, the output and next state depend not only on its current input, but
also on its current state (and hence, previous inputs). It can also beused for counting of pulses, and for
synchronizing variably-timed input signals to somereference timing signal. Flip flops are devices used in
the digital field for a variety of purposes. When properlyconnected, flip-flops may be used to store
data temporarily, to multiply or divide, to count operations, or to receive and transfer information.

1. The Basic aim of the project is to Understand The Flip Flops .

2. To design an efficient model with low cost.

C
1. Use NAND Gate (IC 7400) ,Clock.

2. The objective of this course is to become familiar with the architecture and theinstruction set of
all flip flops .

3. Understand the architecture of flip flops.

Flip flops being a storage element occupies a significant space in digital circuit design such
as Resistor , counter and finite state machine. In view of its huge applications , it is important to
understand its operation in details obtaining a high level of insight into its various performances
metrics such as speed, power dissipation ,hold-time ,set-up time and area . Thus, there is a significant
research effort on FF which revealed various techniques for its performances improvement and
optimization.

A design methodology for sequential logic circuits using controllable flip-flops is proposed. The flip-
flop setup time and propagation delay is controlled with a process, voltage and temperature (PVT)
detector using an additional setup time and delay control (SDC) input. With this SDC enable, it is
possible to enhance the circuit timing performance when PVT variations are detected. The PVT
detector is based in the propagation delay of digital buffers.When an increase in the propagation delay
is detected in the digital logic, the SDC flip-flop input is enabled to reduce its setup time and Clk-Q
propagation delay. When the PVT conditions are maintained under the selected threshold, the SDC
control remains disabled, saving power. The proposed flip-flop and PVT detector are designed and
characterized in a TSMC 28 nm bulk CMOS technology.

1
 Sr. No Name of Resources Specification Qty Remark
1. IC 7400 1 Used
2. Power Supply 5V 1 Used
3. Resistor 330 Ohm 2 Used
4. LED Red 2 Used
:

1. Search the project. 24-7-23 7-8-23

Sanskar

2. To select the title 21-8-23 4-9-23 Devraj

project.

3. Collect the 11-9-23 18-9-23 Ritesh

information about
project.

4. Collect the data from 25-9-23 9-10-23

Om
all the group member.

5. Then we select the 9-10-23 19-10-23 Sanskar

important information
from thedata with the
help guide.

6. Collect All circuit 16-10-23 23-10-23

Ritesh
diagram of flip flops

7. Find the Truth tableof 23-10-23 30-10-23 Sanskar

flip flops

8. Then show the soft 4-11-23 9-11-23

Om
copy of project report
to the subjectteacher
and correct the
correction.

2
 A Cir

Flip Flop have a circuit inside it contain gates and can generate specific output , it makea complex
circuit much simpler.

It can perform the functions of the set / reset flip flop and has the advantage that thereare no
ambiguous states.

1. Use NAND Gate (IC 7400) ,Clock.

2. The objective of this course is to become familiar with the architecture and theinstruction set of
all flip flops .

3. Understand the architecture of flip flops..

Flip flops being a storage element occupies a significant space in digital circuit design such as Resistor
, counter and finite state machine. In view of its huge applications , it is important to understand its
operation in details obtaining a high level of insight into its various performances metrics such as
speed, power dissipation ,hold-time ,set-up time and area . Thus, there is a significant research effort
on FF which revealed various techniques for its performances improvement and optimizatio

Ac
A design methodology for sequential logic circuits using controllable flip-flops is proposed. The flip-
flop setup time and propagation delay is controlled with a process, voltage and temperature (PVT)
detector using an additional setup time and delay control (SDC) input. With this SDC enable, it is
possible to enhance the circuit timing performance when PVT variations are detected. The PVT
detector is based in the propagation delay of digital buffers.When an increase in the propagation delay
is detected in the digital logic, the SDC flip-flop input is enabled to reduce its setup time and Clk-Q
propagation delay. When the PVT conditions are maintained under the selected threshold, the SDC
control remains disabled, saving power. The proposed flip-flop and PVT detector are designed and
characterized in a TSMC 28 nm bulk CMOS technology.

3
 -

Sr. No. Name Of Specification Qty Remarks

Resources

1. IC 7400 1 Used

2. Power Supply 5V 1 Used

3. Resistor 330 Ohm 2 Used

4. LED Red 2 Used

RS flip-flop is the simplest possible memory element. It cannot be constructed from twoNAND
gates or two NOR gates. Let us neither understand the operation of the RS flip- flop using NOR
gates as shown below using the truth table for ‘A NOR B ‘gate. The inputs R and S are referred to
as the Reset and set input, respectively. The outputs Q and Q' are complements of each other and
are referred to as the normal and complement outputs, respectively. The binary state ofthe flip -
flop is taken to be the value of the normal output. When Q=1 and Q'=0, it is in the set state (or 1-
state).When Q=0 and Q'=1,in is in the Reset/clear state (or 0-state).

- S=1 and R=0: The output of the bottom NOR gate is equal to zero, Q'=0. Hence both
- Inputs to the top NOR gate are equal to 0, thus, Q=1. Hence, the input combinationS=1 and
R=0 leads to the flip-flop being set to Q=1.
- S=0 and R=1: Similar to the arguments above, the outputs become Q=0 and Q'=1. Wesay that
the flip-flop is reset.

4
5
 :-

An elementary example using this flip-flop is the debounce circuit. Suppose a piece of
electronics is to change state under the action of a mechanical switch. When this switch is moved
from position S to R (S=0, R=1), the contacts make and break several times at R before settling
to good contact. It is desirable that the electronics should respond to the first contact andthen
remain stable, rather than switching back and forth as the circuit makes and breaks. This is achieved
by RS flip-flop which is reset to Q=0 bythe first signal R=1 and remains in a fixed state until the
switch is moved back to position S, when the signal S=1 sets the flip-flop toQ=1

It is sometimes desirable in sequential logic circuits to have a bitable RS flip-flop that only
changes state when certain conditions are met regardless of the condition of eitherthe Set or the
Reset inputs. By connecting a 2-input AND gate in series with each input terminal of the neither
RS NOR Flip-flop a Gated RS Flip-flop can be created. This extraconditional input is called an
"Enable" input and is given the prefix of "EN" as shown below. When the Enable input "EN" = 0,
the outputs of the two AND gates are also at logic level 0, (AND Gate principles) regardlessof
the condition of the two inputs S and R, latching the two outputs Q and Q’ into their last known
state. When the enable input "EN"
= 1, the circuit responds as a normal RS bitable flip-flop with the two AND gates becoming
transparent to the Set and Reset signals. This Enable input can also be connected to a clock
timing signal adding clock synchronization to the flip-flop creatingwhat is sometimes called a
"Clocked SR Flip-flop".
So a Gated/Clocked RS Flip-flop operates as a standard bitable latch but the outputs are only
activated when logic "1" is applied to its EN input and deactivated by logic "0". The property of
this flip-flop is summarized in its characteristic table where Qi is the logic state of the previous
output and Qn+1 is that of the next output and the clock inputbeing at logic 1 for all the R and S
input combinations.

6
7
An RS flip-flop is rarely used in actual sequential logic because of its undefined outputs forinputs R=
S= 1. It can be modified to form a more useful circuit called D flip-flop, where Dstands for data.
The D flip-flop has only a single data input D as shown in the circuit diagram. That data input is
connected to the S input of an RS flip-flop, while the inverse of D is connected to the R input. To
allow the flip-flop to be in a holding state, a D-flip flop hasa second input called Enable, EN. The
Enable-input is AND-ed with the D-input.
• When EN=0, irrespective of D-input, the R =S = 0 and the state is held.

• When EN= 1, the S input of the RS flip-flop equals the D input and R is the inverse of D.Hence,
output Q follows D, when EN= 1.
• When EN returns to 0, the most recent input D is ‘remembered'.

The circuit operation is summarized in the characteristic table for EN=1.

8
The JK flip flop (JK means Jack Kirby, a Texas instrument engineer, who invented it) is the most
versatile flip-flop, and the most commonly used flip flop. Like the RS flip-flop, it has two data
inputs, J and K, and an EN/clock pulse input (CP). Note that in the following circuit diagram
NAND gates are used instead of NOR gates. It has no undefined states, however. The
fundamental difference of this device is the feedback paths to the AND gates of the input, i.e. Q
isAND-ed with K and CP and Q’with J and CP.

9


• If one input(J or K) is at logic 0, and the other is at logic 1, then the output is set orreset (by
Jand K respectively), just like the RS flip-flop.
If both inputs are 0, then it remains in the same state as it was before the clock pulse
occurred;again like the RS flip flop. CP has no effect on the output.

If both inputs are high, however the flip-flop changes state whenever a clock pulse occurs; i.e.,
theclock pulse toggles the flip-flop again and again until the CP goes back to 0 as shown in the
shaded rows of the characteristic table above. Since this condition is undesirable, it should be
eliminated by an improvised form of this flip-flop as discussed in the next section.

Although JK flip-flop is an improvement on the clocked SR flip-flop it still suffers from timing
problems called "race" if the output Q changes state before the timing pulse of the clock input
has time to go "OFF", so the timing pulse period (T) must be kept as short as possible (high
frequency). As this is sometimes not possible with modern TTLIC's the much improved Master-
Slave J-K Flip-Flop was developed. This eliminates allthe timing problems by using two SR flip-
flops connected together in series, one for the"Master" circuit, which triggers on the leading edge
of the clock pulse and the other, the"Slave" circuit, which triggers on the falling edge of the clock
pulse.

The master-slave JK flip flop consists of two flip flops arranged so that when the clock pulse
enables the first, or master, it disables the second, or slave. When the clock changes state again
(i.e., on its falling edge) the output of the master latch is transferredto the slave latch.
Again, toggling is accomplished by the connection ofthe output with the input AND gates.

10
11
Develop the circuit for various types of Flip Flops using NAND Gate IC 7400. And According to
the Truth Table of Different type of Flip Flops . We use the flip flops forStore Data . It is the Basic
Storage element in Sequential Logic.

We knew more about the behavior of several of latches and flip-flops. It was a lengthy lab, but it worth it.
They amount of knowledge and everything falling into a place was amazing. Pretty sure Iknow more about
the flip-flap and latches and understand them more than ever.
1. Flip-flop can be used as a memory element and also as a delay element
2. Flip- flop is also used in the making of counter / timer.
3. Using Flip-flop, we can eliminate keyboard denounce.
4. In various type of register also we use flip-flop.

1. http://www.play-hookey.com/digital/rs_nand_latch.html
2. http://www.play-hookey.com/digital/clocked_rs_latch.html
3. http://us.st.com/stonline/books/pdf/docs/1879.pdf

12