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    OS

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    Priyanshu Paramjit Dash

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    OS

    Uploaded by

    Priyanshu Paramjit Dash
    11 views2 pages

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    11 views2 pages

    OS

    Uploaded by

    Priyanshu Paramjit Dash

    Copyright:

    © All Rights Reserved
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    ‘acon a sgl 4 B.Tech Sixth Semester (End-Sem) Examination - April 2023 Concepts in Operating System Branch: ETC/ERE Thee 24, Hearn Maximum Marks: 50 Anawer any five questions, The figures io the right-hand margin indicate marks. WG Cram tho hry va ttn. Poa the CPU utliaation factor and the average waiting (5) {We te bien ehetn lcs ne oped with» Cae en eae wating Pre Anil Time CPU See te ry ° 2 B 3 7 © 6 2 D 8 3 B 9 2 F 2 2 1 FitstCom Fits Server, Y. Shemtest- Resanining. Tine Pest 7) (oases » iva ith 10 proces nthe Reedy Que. 1! round robin scheduling algorithm a 6) 7 itl whoring reed ok 6 mirinocmds, what mst be the time quantum ec tar ool eas soncachond to apt ita barn at the CPU after 1 second? FATE natT manag. Song wa geexation of tnary emaghore tat eliminates busy (8 rt ni ey rte oh ta Ay Coneier tw srenvoam PS jee) 22 accessing the shared variables X and ¥ protected by two binary (5) emathunen SK noel SY vempoctivly, both aitalizd to 1. Complete the tate od cot ene, Lite tain orion wc Wha the process can pate the shared siablesconrecly ehbone ended roe “whilsCeraey {TwhleCeraay T— (entry scion) | (entry section) X=K41 | ove on Y=¥-m) | X=" 10, (exit mein) | (ext wtion) poopy 11 Roataheaten wi nent derdoe x plewatation single CPU computer systems (6) comput mall mini EP mpes non, 1 Kxylnin, whos, thems muted yor world une fo implementing it on a ‘single-CPU computer en Cm ind ition nd enti ater te O8 shold peo a win the more i ar thoes Pes gh ure mt wilt phenking on igh CPU emp Jie a eaine wl neon aus ae OS shh meting a ‘Aisin the tne thn heme Whyte te veins th mnie nde npn. Ca dents be prem © ‘enh sar wi cn Fin ame that 4 (a) What is priority (®) Define and describe the algorithm Fesources are bei register contains B Physical addresses for the logical addresses (b) Consider a system ages, which are mapped to 3 physical Physical frame 2, page any physical frame. The demand paging syst ote 2 entries. The TLB cache also uses the LRG . ‘ Assume that the TLB cache is empty before ch i. Optima ii, LRU } 7 (FF What is the difference between cxamples. 6) What is thrashing? § ing used. Mention (8) Consider a computer syste up to IMB physi re mt 28 bit lgical address and 4KB page sv, “Th, ical memory, A; ee nea 10384. The page table entree ana Page | Frame ~O as t}on 2 9 3 7 4 5 5 : 6 i 7 : 1002, 5122, 13256, and 24576, With & bit addresses and i6-byte pages. A Process in this frames pbs te Frame 0, page 2 maps to frame Land pres Process may not use more than 3 physical fr tem uses the LRU Paged system with a 64-bit address space, 4B Page size, Per Page table entry. Find out the page table size 4 ha ‘CAN and C-SCAN disk scheduling algorithm? Es Hxplain with an example, Fe tabi tt the actual process size is only 32KB, e system supports age table base system has 4 logical 2 ate following manner: logical page O mary te is not mapped to rames. On a page fault, the Policy to evict a page. The MMU has a TLE ne that can Policy to store the most recently used mappings 60. 512GB RAM, and ial 8 bits per entry in that table for ‘he same system. What will be the size of the inverred Page table, PF Consider the page reference String 0, 1, 3, 6, 2,4, 5, 2, 6 0,3, 2,5, 4,1, 0. The number of would be the number of page faults generated for cach ot the following ixplain with proper )

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