BCS302 Unit-3 (Part-III)

PSIT, Kanpur
Computer Organization and Architecture (BCS302)

Unit - 3 (Part – III)
 Horizontal & Vertical Microprogramming
 Pipelining
Horizontal & Vertical Microprogramming
Relative differences between Horizontal & Vertical Microprogramming are listed below:
Compiled by- Durgesh Pandey (CSED)

PSIT, Kanpur
Pipelining
To improve the performance of CPU, we have two options:
1. Improve the hardware by introducing faster circuits
2. Arrange the hardware such that more than one operation can be performed at the same time.
 Pipelining is a technique of decomposing a sequential process into suboperations, with each sub-process being executed
in a special dedicated segment that operates concurrently with all other segments.
 Pipelining is a process of arrangement of hardware elements of the CPU such that its overall performance is increased by
the simultaneous execution of more than one instruction.
For example, suppose that we want to perform the combined multiply and add operations with a stream of numbers.
Ai * B i + Ci for i = 1, 2, 3, . . . , 7
Each suboperation is to be implemented in a segment within a pipeline. Each segment has one or two registers and a
combinational circuit as shown in Fig. 9-2. The multiplier and adder are combinational circuits. The suboperations performed in
each segment of the pipeline are as follows:
R1 ← Ai, R2 ← Bi Input Ai and Bi
R3 ← R1 * R2, R4 ← Ci Multiply and input Ci
R5 ← R3 + R4 Add Ci to product
Figure 9-2 Example of pipeline processing

Ai Bi Ci
NOTE: The five registers are loaded with new data every clock pulse. The effect of each clock is shown in the following table
(*MM Table 9-1).
TABLE 9-1 Content of Registers in Pipeline (Example)
 The first clock pulse transfers A1 and B1 into R1 and R2.

 The second clock pulse transfers the product of R1 and R2 into R3 and C1 into R4. The same clock pulse transfers A2 and B2
into R1 and R2.
 The third clock pulse operates on all three segments simultaneously i.e. it takes three clock pulses to fill up the pipe and
retrieve the first output from R5.
 From there on, each clock produces a new output and moves the data one step down the pipeline; as long as new input data
flow into the system.
 When no more input data are available, the clock must continue until the last output emerges out of the pipeline.
PSIT, Kanpur
The general structure of a four-segment pipeline is illustrated in *MM Fig. 9-3. Each segment consists of:
 A combinational circuit Si that performs a suboperation over the data stream flowing through the pipe and
 Separated by registers Ri that holds the intermediate results between the stages.
Figure 9-3 Four-segment pipeline
Information flows between adjacent stages under the control of a common clock applied to all the registers simultaneously.
The behavior of a pipeline can be illustrated with a space-time diagram that shows the segment utilization as a function of
time.
The space-time diagram of a four-segment pipeline is demonstrated in the following figure (*MM Fig. 9-4).
Figure 9-4 Space-time diagram for pipeline
NOTE: Horizontal axis displays the time in clock cycles and the vertical axis gives the segment number.
We define a task as the total operation performed going through all the segments in the pipeline.
So, the first task T1 is completed after the fourth clock cycle. From then on, the pipe completes a task every clock cycle.
No matter how many segments are there in the system, once the pipeline is full, it takes only one clock period to obtain an
output.
Performance measure
 For pipelined architecture,

 Consider the case where a k-segment pipeline with a clock cycle time tp is used to execute n tasks.
 The first task T1 requires a time = k.tp to complete its operation since there are k segments in the pipe.
 The remaining n - 1 tasks, completed after a time = (n - 1).tp (emerge from the pipe at the rate of one task per clock
cycle).
Therefore, to complete n tasks using a k-segment pipeline requires:
Total execution time = [k + (n - 1)].tp

For example, the diagram of *MM Fig. 9-4 shows four segments and six tasks.
The time required to complete all the operations is 4 + (6 - 1) = 9 clock cycles, as indicated in the diagram.
 For non-pipelined architecture,

 For the same case with a clock cycle time tn
We have,
Total execution time
= Total number of instructions * Time taken to execute one instruction = n.tn

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Speedup
The speedup of a pipeline processing over an equivalent non-pipeline processing is defined by the ratio
S = n.tn / (k + n - 1).tp
As the number of tasks increases, n becomes much larger than k - 1, and k + n - 1 approaches the value of n.
Under this condition, the speedup becomes S = tn / tp
If we assume that the time it takes to process a task is the same in the pipeline and non-pipeline circuits, we will have
tn = k.tp
Including this assumption, the speedup reduces to
S = k.tp / tp = k
This shows that the theoretical “maximum speedup that a pipeline can provide is k, where k is the number of segments in
the pipeline”.
To clarify the meaning of the speedup ratio, consider the following numerical example.
Question:
A pipeline has 4 segments and executes 100 tasks in sequence with a clock cycle time 20 ns.
1. The pipeline system will take how much total time to complete the execution?
2. What will be the speedup if the time it takes to process the task is the same in the pipeline and non-pipeline
circuits?
Solution:
Given that the time it takes to process a suboperation in each segment be equal to tp = 20 ns. The pipeline has k = 4 segments and
executes n = 100 tasks in sequence.
The pipeline system will take (k + n - 1).tp = (4 + 99) * 20 = 2060 ns to complete.
Answer.
Assuming that tn = k.tp = 4 * 20 = 80 ns,
a non-pipelined system requires n * k.tp = 100 * 80 = 8000 ns to complete the 100 tasks.
The speedup ratio is equal to 8000/2060 = 3 .88. Answer.
As the number of tasks increases, the speedup will approach 4, which is equal to the number of segments in the pipeline.
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BCS302 Unit-3 (Part-III)

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PSIT, Kanpur

Computer Organization and Architecture (BCS302)

Horizontal & Vertical Microprogramming

Compiled by- Durgesh Pandey (CSED)

Figure 9-2 Example of pipeline processing

TABLE 9-1 Content of Registers in Pipeline (Example)

 The first clock pulse transfers A1 and B1 into R1 and R2.

Figure 9-3 Four-segment pipeline

 For pipelined architecture,

Total execution time = [k + (n - 1)].tp

 For non-pipelined architecture,

Compiled by- Durgesh Pandey (CSED)

Compiled by- Durgesh Pandey (CSED)

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