SN54/74LS190

PRESETTABLE BCD/DECADE SN54/74LS191

UP/DOWN COUNTERS
PRESETTABLE 4-BIT BINARY PRESETTABLE BCD / DECADE
UP/DOWN COUNTERS UP/ DOWN COUNTERS
PRESETTABLE 4-BIT BINARY
The SN54 / 74LS190 is a synchronous UP/ DOWN BCD Decade (8421) UP/ DOWN COUNTERS
Counter and the SN54/ 74LS191 is a synchronous UP / DOWN Modulo-16
Binary Counter. State changes of the counters are synchronous with the LOW POWER SCHOTTKY
LOW-to-HIGH transition of the Clock Pulse input.
An asynchronous Parallel Load (PL) input overrides counting and loads the
data present on the Pn inputs into the flip-flops, which makes it possible to use
the circuits as programmable counters. A Count Enable (CE) input serves as
J SUFFIX
the carry / borrow input in multi-stage counters. An Up / Down Count Control
CERAMIC
(U/D) input determines whether a circuit counts up or down. A Terminal Count CASE 620-09
(TC) output and a Ripple Clock (RC) output provide overflow/underflow 16
indication and make possible a variety of methods for generating 1
carry / borrow signals in multistage counter applications.
• Low Power . . . 90 mW Typical Dissipation
• High Speed . . . 25 MHz Typical Count Frequency
N SUFFIX
• Synchronous Counting PLASTIC
• Asynchronous Parallel Load
16 CASE 648-08
• Individual Preset Inputs
1
• Count Enable and Up / Down Control Inputs
• Cascadable
• Input Clamp Diodes Limit High Speed Termination Effects
D SUFFIX
SOIC
16
CASE 751B-03
CONNECTION DIAGRAM DIP (TOP VIEW) 1

VCC P0 CP RC TC PL P2 P3
16 15 14 13 12 11 10 9 ORDERING INFORMATION
SN54LSXXXJ Ceramic
NOTE:
SN74LSXXXN Plastic
The Flatpak version
has the same pinouts SN74LSXXXD SOIC
(Connection Diagram) as
the Dual In-Line Package.

1 2 3 4 5 6 7 8 LOGIC SYMBOL
P1 Q1 Q0 CE U/D Q2 Q3 GND
11 15 1 10 9

PIN NAMES LOADING (Note a)

PL P0 P1 P2 P3
HIGH LOW 5 U/D RC 13
CE Count Enable (Active LOW) Input 1.5 U.L. 0.7 U.L. 4 CE
CP Clock Pulse (Active HIGH going edge) Input 0.5 U.L. 0.25 U.L.
14 CP TC 12
U/D Up/Down Count Control Input 0.5 U.L. 0.25 U.L. Q0 Q1 Q2 Q3
PL Parallel Load Control (Active LOW) Input 0.5 U.L. 0.25 U.L.
Pn Parallel Data Inputs 0.5 U.L. 0.25 U.L.
Qn Flip-Flop Outputs (Note b) 10 U.L. 5 (2.5) U.L. 3 2 6 7
RC Ripple Clock Output (Note b) 10 U.L. 5 (2.5) U.L.
Terminal Count Output (Note b) 10 U.L. 5 (2.5) U.L. VCC = PIN 16
TC
GND = PIN 8
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.

FAST AND LS TTL DATA

5-1
 SN54/74LS190 • SN54/74LS191

STATE DIAGRAMS

0 1 2 3 4 0 1 2 3 4
LS190
UP: TC = Q0 ⋅ Q3 ⋅ (U/D)
15 5 DOWN: TC = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ (U/D) 15 5

14 6 LS191 14 6
UP: TC = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ (U/D)
DOWN: TC = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ (U/D)
13 7 13 7
COUNT UP
COUNT DOWN
12 11 10 9 8 12 11 10 9 8

LS190 LS191

LOGIC DIAGRAMS

CP U/D P0 CE P1 P2 P3 PL
14 5 15 4 1 10 9 11

J CLOCK K J CLOCK K J CLOCK K J CLOCK K

PRESET CLEAR PRESET CLEAR PRESET CLEAR PRESET CLEAR
Q Q Q Q Q Q Q Q

13 12 3 2 6 7

RC TC Q0 Q1 Q2 Q3

VCC = PIN 16 DECADE COUNTER

GND = PIN 8 LS190
= PIN NUMBERS

FAST AND LS TTL DATA

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 SN54/74LS190 • SN54/74LS191

LOGIC DIAGRAMS (continued)

CP U/D P0 CE P1 P2 P3 PL
14 5 15 4 1 10 9 11

J CLOCK K J CLOCK K J CLOCK K J CLOCK K

PRESET CLEAR PRESET CLEAR PRESET CLEAR PRESET CLEAR
Q Q Q Q Q Q Q Q

13 12 3 2 6 7

RC TC Q0 Q1 Q2 Q3

VCC = PIN 16
BINARY COUNTER
GND = PIN 8
LS191
= PIN NUMBERS

FAST AND LS TTL DATA

5-3
 SN54/74LS190 • SN54/74LS191

FUNCTIONAL DESCRIPTION
The LS190 is a synchronous Up / Down BCD Decade Clock (RC) output. The RC output is normally HIGH. When CE
Counter and the LS191 is a synchronous Up / Down 4-Bit is LOW and TC is HIGH, the RC output will go LOW when the
Binary Counter. The operating modes of the LS190 decade clock next goes LOW and will stay LOW until the clock goes
counter and the LS191 binary counter are identical, with the HIGH again. This feature simplifies the design of multi-stage
only difference being the count sequences as noted in the counters, as indicated in Figures a and b. In Figure a, each RC
state diagrams. Each circuit contains four master / slave output is used as the clock input for the next higher stage. This
flip-flops, with internal gating and steering logic to provide configuration is particularly advantageous when the clock
individual preset, count-up and count-down operations. source has a limited drive capability, since it drives only the
Each circuit has an asynchronous parallel load capability first stage. To prevent counting in all stages it is only necessary
permitting the counter to be preset to any desired number. to inhibit the first stage, since a HIGH signal on CE inhibits the
When the Parallel Load (PL) input is LOW, information present RC output pulse, as indicated in the RC Truth Table. A
on the Parallel Data inputs (P0 – P3) is loaded into the counter disadvantage of this configuration, in some applications, is the
and appears on the Q outputs. This operation overrides the timing skew between state changes in the first and last stages.
counting functions, as indicated in the Mode Select Table. This represents the cumulative delay of the clock as it ripples
A HIGH signal on the CE input inhibits counting. When CE is through the preceding stages.
LOW, internal state change are initiated synchronously by the A method of causing state changes to occur simultaneously
LOW-to-HIGH transition of the clock input. The direction of in all stages is shown in Figure b. All clock inputs are driven in
counting is determined by the U/D input signal, as indicated in parallel and the RC outputs propagate the carry / borrow
the Mode Select Table. When counting is to be enabled, the signals in ripple fashion. In this configuration the LOW state
CE signal can be made LOW when the clock is in either state. duration of the clock must be long enough to allow the
However, when counting is to be inhibited, the LOW-to-HIGH negative-going edge of the carry / borrow signal to ripple
CE transition must occur only while the clock is HIGH. through to the last stop before the clock goes HIGH. There is
Similarly, the U / D signal should only be changed when either no such restriction on the HIGH state duration of the clock,
CE or the clock is HIGH. since the RC output of any package goes HIGH shortly after its
Two types of outputs are provided as overflow/underflow CP input goes HIGH.
indicators. The Terminal Count (TC) output is normally LOW The configuration shown in Figure c avoids ripple delays
and goes HIGH when a circuit reaches zero in the count-down and their associated restrictions. The CE input signal for a
mode or reaches maximum (9 for the LS190, 15 for the LS191) given stage is formed by combining the TC signals from all the
in the count-up mode. The TC output will then remain HIGH preceding stages. Note that in order to inhibit counting an
until a state change occurs, whether by counting or presetting enable signal must be included in each carry gate. The simple
or until U / D is changed. The TC output should not be used as inhibit scheme of Figures a and b doesn’t apply, because the
a clock signal because it is subject to decoding spikes. TC output of a given stage is not affected by its own CE.
The TC signal is also used internally to enable the Ripple

MODE SELECT TABLE RC TRUTH TABLE

INPUTS INPUTS RC
MODE
PL CE U/D CP CE TC* CP OUTPUT

H L L Count Up L H
H L H Count Down H X X H
L X X X Preset (Asyn.) X L X H
H H X X No Change (Hold) * TC is generated internally

L = LOW Voltage Level

H = HIGH Voltage Level
X = Don’t Care
= LOW-to-HIGH Clock Transition
= LOW Pulse

FAST AND LS TTL DATA

5-4
 SN54/74LS190 • SN54/74LS191

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High 54, 74 – 0.4 mA
IOL Output Current — Low 54 4.0 mA
74 8.0

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
Guaranteed Input HIGH Voltage for
VIH Input HIGH Voltage 2.0 V
All Inputs
54 0.7 Guaranteed Input
p LOW Voltage
g for
VIL Input LOW Voltage V
74 0.8 All Inputs

VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VOL Output LOW Voltage VIN = VIL or VIH
74 0.35 0.5 V IOL = 8.0 mA per Truth Table

Input HIGH Current

Other Inputs 20 µA VCC = MAX, VIN = 2.7 V
IIH CE 60
Other Inputs 0.1
mA VCC = MAX, VIN = 7.0 V
CE 0.3

Input LOW Current

IIL Other Inputs – 0.4 mA VCC = MAX, VIN = 0.4 V
CE – 1.2
IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX
ICC Power Supply Current 35 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA

5-5
 SN54/74LS190 • SN54/74LS191

AC CHARACTERISTICS (TA = 25°C)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
fMAX Maximum Clock Frequency 20 25 MHz
tPLH Propagation Delay, 22 33
ns
tPHL PL to Output Q 33 50

tPLH 20 32
Data to Output Q ns
tPHL 27 40

tPLH 13 20
Clock to RC ns
tPHL 16 24

tPLH 16 24
Clock to Output Q ns VCC = 5.0
50V
tPHL 24 36
CL = 15 pF
tPLH 28 42
Clock to TC ns
tPHL 37 52

tPLH 30 45
U / D to RC ns
tPHL 30 45

tPLH 21 33
U / D to TC ns
tPHL 22 33

tPLH 21 33
CE to RC ns
tPHL 22 33

AC SETUP REQUIREMENTS (TA = 25°C)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
tW CP Pulse Width 25 ns
tW PL Pulse Width 35 ns
ts Data Setup Time 20 ns VCC = 5.0
50V
th Data Hold Time 5.0 ns
trec Recovery Time 40 ns

DEFINITIONS OF TERMS
SETUP TIME (ts) is defined as the minimum time required for tion. A negative HOLD TIME indicates that the correct logic
the correct logic level to be present at the logic input prior to the level may be released prior to the clock transition from LOW-
clock transition from LOW-to-HIGH in order to be recognized to-HIGH and still be recognized.
and transferred to the outputs.
RECOVERY TIME (trec) is defined as the minimum time
HOLD TIME (th) is defined as the minimum time following the required between the end of the reset pulse and the clock
clock transition from LOW-to-HIGH that the logic level must be transition from LOW-to-HIGH in order to recognize and
maintained at the input in order to ensure continued recogni- transfer HIGH data to the Q outputs.

FAST AND LS TTL DATA

5-6
 SN54/74LS190 • SN54/74LS191

DIRECTION
CONTROL

U/D RC U/D RC U/D RC

ENABLE CE CE CE
CLOCK CP CP CP

Figure a. n-Stage Counter Using Ripple Clock

DIRECTION
CONTROL

U/D RC U/D RC U/D RC

ENABLE CE CE CE
CP CP CP

CLOCK

Figure b. Synchronous n-Stage Counter Using Ripple Carry / Borrow

DIRECTION
CONTROL
ENABLE

U/D U/D U/D

CE CE CE
CP TC CP TC CP TC

CLOCK

Figure c. Synchronous n-Stage Counter with Parallel Gated Carry / Borrow

FAST AND LS TTL DATA

5-7
 SN54/74LS190 • SN54/74LS191

AC WAVEFORMS

1/f MAX
tW
CP 1.3 V 1.3 V CP OR CE 1.3 V 1.3 V

tPHL tPLH tPHL tPLH

RC
Q OR TC 1.3 V 1.3 V 1.3 V 1.3 V

Figure 1 Figure 2

Pn 1.3 V 1.3 V Pn

tPHL tPLH tW

Qn 1.3 V PL 1.3 V

tPLH tPHL

Qn 1.3 V
NOTE: PL = LOW

Figure 3 Figure 4

Pn 1.3 V 1.3 V
PL 1.3 V th(H) th(L)
ts(H) ts(L)
tW trec
PL 1.3 V 1.3 V
CP 1.3 V

Qn Q=P Q=P
Q
* The shaded areas indicate when the input is permitted
* to change for predictable output performance

Figure 5 Figure 6

th(L) th(H)
U/D 1.3 V

tPLH tPHL CP 1.3 V 1.3 V

1.3 V 1.3 V ts(L) ts(H)

TC
tPHL tPLH CE CE MAY (H-L) CE MAY 1.3 V
CHANGE only CHANGE
RC 1.3 V 1.3 V

Figure 7 Figure 8

FAST AND LS TTL DATA

5-8