Scribd Logo
Upload

Welcome to Scribd!

  • 13 views

    Google Resume

    Uploaded by

    Bhargava Ram
    K.BHARGHAVA RAM DINESH has an M.Tech from Manipal Institute of Technology and seeks a position in the semiconductor industry using his analytical skills and technical knowledge. He has experience with projects involving designing an efficient MAC unit using carry select adder and Vedic multiplier in Verilog. He also has experience with a bubble sort algorithm design in Verilog and implementing low power techniques like clock gating and state encoding. He completed an internship at Rashtriya Ispat Nigam Limited and is proficient in digital IC design, physical design, low power techniques, and STA.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Google Resume

    Uploaded by

    Bhargava Ram
    13 views1 page
    K.BHARGHAVA RAM DINESH has an M.Tech from Manipal Institute of Technology and seeks a position in the semiconductor industry using his analytical skills and technical knowledge. He has experience with projects involving designing an efficient MAC unit using carry select adder and Vedic multiplier in Verilog. He also has experience with a bubble sort algorithm design in Verilog and implementing low power techniques like clock gating and state encoding. He completed an internship at Rashtriya Ispat Nigam Limited and is proficient in digital IC design, physical design, low power techniques, and STA.

    Original Description:

    Bur

    Original Title

    Google resume

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    K.BHARGHAVA RAM DINESH has an M.Tech from Manipal Institute of Technology and seeks a position in the semiconductor industry using his analytical skills and technical knowledge. He has experience with projects involving designing an efficient MAC unit using carry select adder and Vedic multiplier in Verilog. He also has experience with a bubble sort algorithm design in Verilog and implementing low power techniques like clock gating and state encoding. He completed an internship at Rashtriya Ispat Nigam Limited and is proficient in digital IC design, physical design, low power techniques, and STA.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    13 views1 page

    Google Resume

    Uploaded by

    Bhargava Ram
    K.BHARGHAVA RAM DINESH has an M.Tech from Manipal Institute of Technology and seeks a position in the semiconductor industry using his analytical skills and technical knowledge. He has experience with projects involving designing an efficient MAC unit using carry select adder and Vedic multiplier in Verilog. He also has experience with a bubble sort algorithm design in Verilog and implementing low power techniques like clock gating and state encoding. He completed an internship at Rashtriya Ispat Nigam Limited and is proficient in digital IC design, physical design, low power techniques, and STA.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    You are on page 1of 1

    K.

    BHARGHAVA RAM DINESH


    M.tech (Manipal Institute Of Technology)

    Career Objective : Master's graduate in hardware design with communication and


    organizational skills. Seeking a position in semiconductor industry to use my
    analytical skills and technical knowledge and contribute to the company success.

    Technical Activites(Internship/Projects)
    7013948669 Design of efficient MAC unit using carry select adder and
    [email protected] Vedic multiplier, Design and implementation unit using

    https://www.linkedin.com/in/ram Verilog. Synthesized and generated gate level netlist using


    -ketha-483b8566/ genus.
    Andhrapradhesh,
    visakhapatnam,530026 Bubble Sort Algorithm
    Design of bubble sort algorithm using Verilog. Synthesized
    EDUCATION generated gate level netlist using genus tool. designed floor
    plan using genus tool and generated timing reports, and
    Masters in Microelectronics (VLSI)
    Manipal institue of technology 2022 - 2024 by using innovus tool generated GDS ll file.
    cgpa : 6.2 (1st sem) Implemented Low Power Techniques
    B.E - electronics and communication Clock gating and state encoding techniques are
    Gayatri vidhya parishad 2014 -2017
    are implemented for mux and finite state machines
    cgpa: 6.63
    Rashtriya Ispat Nigam Limited - Internship - 3months
    Maven institute (2023 - 2024)
    Physical design Learned about the working of telecommunications and
    digital verification
    intercommunication.
    LANGUAGES AND TOOLS
    Publications
    Verilog HDL Virtuoso
    Cadnce design suit xilinx Design and implementation of high speed M.A.C unit -
    intel fpga modelsim perl AICECS 2023 - MIT. (IOP UNITED KINGDOM)
    Genus quartus prime
    mobaxtern tanner tools Current Work Under Progress
    Design and implementation of high speed 64 bit M.A.C unit
    PROFICIENT AREAS (current paper under progress )

    Certification
    Digital IC Design
    Physical Design Cadence EDA tool for chip design/analog RF and design flow
    Rtl to Gds NPTEL exam by IIIT DELHI and scored an elite certificate
    Low Power Techniques
    Intruder robot worKshop participation at IIT BOMBAY
    testing and testability Ethical hacking certificate from Microsoft bizspark
    STA Stood among top 20 positions in chess (gvpt)

    You might also like