Ddco Question Bank

Module 1
1. Simplify the following Boolean expressions, using four-variable K- maps and

design using Nand and Nor gates.
F (A, B, C, D) =AD' + B'C'D + BCD' + BC'D

F (A, B, C, D) = πM (1, 3, 5, 7, 13, 15)
F (w, x, y, z) = ϵm (0, 2, 4, 5, 6, 7, 8, 10, 13, 15)
2. Implement the following Boolean expressions, using Nand and Nor gates.
F (x, y, z) = ∑ (0, 6,8,13,14) + d (2, 4, 10)
3. Design the multiple-level NOR and NAND circuit for the following expression:
F=CD (B + C) A + (BC' + DE')
4. Obtain the truth table of the following functions, and express each function in
sum‐of‐minterms and product‐of‐maxterms form:
(a) (b + cd) (c + bd) (b) (cd + b'c + bd') (b + d)

5. Demonstrate the validity of the following identities by means of truth tables:
i. DeMorgan’s theorem for three variables: (x + y + z)' = x'y'z' and
(xyz)' = x' + y' + z'
ii. The distributive law: x (y + z) = xy + xz
6. Design AND, OR, Xor using NAND and NOR gates.
7. Implement the following Boolean function F, using the two-level forms of logic (a)
NAND-AND, (b) AND-NOR, (c) OR-NAND, and (d) NOR-OR
F (A, B, C, D) = ϵm (0, 4, 8, 9, 10, 11, 12, 14)
8. Simplify the following Boolean function F, together with the don’t-care
conditions d, and then express the simplified function in sum-of-minterms
form:
F (x, y, z) = ϵm (0, 1, 4, 5, 6) + d (2,3,7)
F (A, B, C, D) = ϵm (0, 6, 8, 13, 14) + d (2,4,10)
9. Draw the logic diagram of the digital circuit specified by the following Verilog
description:
module Circuit_A (A, B, C, D, F);

input A, B, C, D;
output F;
wire w, x, y, z, a, d;
or (x, B, C, d);
and (y, a, C);
and (w, z, B);
and (z, y, A);
or (F, x, w);
not (a, A);
not (d, D);
endmodule
10. Using continuous assignments, write a Verilog description of the circuit specified
by the following Boolean functions:
Out_1 = (A + B’) C'(C + D)
Out_2 = (C'D + BCD + CD’) (A' + B)
Out_3 = (AB + C) D + B'C
11. Explain Nand gate, Nor gate and Xor gate with truth table and timing diagram for
three input variables a, b and c respectively.
12. Problems on simplification of expression using Boolean rules.
Note: The design problems may vary. Kindly be thorough with NAND and NOR
implementation.
Module 2
1. Design a combinational circuit to convert BCD to Excess-3 or can ask any design.
2. Design 4-bit parallel adder/ subtractor circuit.
3. Explain carry look ahead adder circuit with block diagram.
4. Explain half adder/subtractor and design full adder using 2 half adders.
5. Explain operation of decoder with truth table and its problems.
6. Explain 4:1 mux with truth table and its problems.
7. Design 4:1 mux using tristate buffer.
8. Explain the operation of JK, SR and D flip flop with Characteristic table and truth table.
9. Explain positive edge triggered D flip flop with truth table.
10. Explain positive edge triggered D flip flop with asynchronous reset with truth table.
Note: All IPCC lab programs should be studied
Module 3
1. With a neat diagram explain the basic operational concepts of computer or explain the
registers of processor.
2. Analyze Big-Endian and little-Endian methods of byte addressing with example.
3. Show how X= A*B+C*D or A+B*C+D is executed using one address, two address and
three address.
4. Define instruction sequencing and branching. Explain conditional flags.
5. What is performance measurement? Explain the overall SPEC rating.
6. Explain processor clock, clock rate, basic performance equation and performance
measurement.
7. Define Addressing mode and explain any 5 with examples.
8. Problem on Addressing mode to find Effective address.
Module 4
1. How the input and output are performed by the processor? Write a program that reads
the line or characters and display it.
2. Differentiate memory mapped I/O and I/O mapped I/O
3. With neat sketches explain various methods for handling multiple interrupts raised by
multiple devices. (or explain how I/O devices are organized in priority structure)
4. Define Interrupt and interrupt hardware. how enabling and disabling of interrupts are
performed.
5. Define exception, describe different kinds of exception.
6. Explain operation of DMA controller with neat block diagram.
7. Define DMA bus arbitration. Explain centralized and distributed bus arbitration.
8. Draw a neat diagram of memory hierarchy in a computer system. Discuss the variation
of size, speed and cost per bit in the hierarchy.
9. What is cache memory. Explain different mapping functions with diagram.
Module 5
1. Write and explain the control sequence for execution of the instruction ADD (R3), R1 on
a single bus processor.
2. Explain the 3-bus organization of a data path with a neat diagram.
3. With neat diagram explain single bus organization of computer and fundamental
concepts.
4. Write and explain the control sequence for execution of an unconditional branch
instruction.
5. Write a note on register transfer and ALU operation.
6. Briefly explain fetching a word from memory and storing a word in memory.
Note: Those who feel difficult can study the below questions but should expect only 12-15
marks for worst condition ( if questions get clubbed)
1. first 6 questions from module 2,
2. questions from 1 to 4 or from 5 to 8 from module 3
3. first 5 questions or questions 6 to 9 from module 4,
4. All 6 questions from module 5,
In module 1 same type of problems can be asked but design might change.

Ddco Question Bank

Uploaded by

Copyright:

Available Formats

Ddco Question Bank

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Ddco Question Bank

Uploaded by

Copyright:

Available Formats

Module 1

1. Simplify the following Boolean expressions, using four-variable K- maps and

F (A, B, C, D) =AD' + B'C'D + BCD' + BC'D

(a) (b + cd) (c + bd) (b) (cd + b'c + bd') (b + d)

module Circuit_A (A, B, C, D, F);

You might also like