Introduction To Circuit Analysis Part 1

Introduction to Circuit Analysis – Part 1
24/08/2021 1
Lecturers
Arwindra Rizqiawan
[email protected]
Lab. Penelitian Konversi Energi Elektrik (Lt. 3)
Course Contents
Minggu Topik Rujukan

1 Introduction to Circuit Analysis & Metoda Tableu Chapter 1 Chua
dan Chapter 5.2
2 Sinusoidal Steady-state Analysis Chapter 10 Sadiku
3 AC Power Analysis Chapter 11

4&5 Three-phase Circuits Chapter 12
5&6 Magnetically Coupled Circuits Chapter 13
7&8 Frequency Response Chapter 14
9 Intro to the Laplace Transform Chapter 15
10&11 Application of the Laplace Transform Chapter 16
11 & 12 Fourier Series Chapter 17
13 Fourier Transform Chapter 18
14 & 15 Two-port Networks Chapter 19
Pengumuman
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Lumped Approximation
• Electromagnetic wave behavior is very complex as functions of space

and time
• The dimension of the physical circuit is small enough so that
electromagnetic waves propagate across the circuit “almost”
instantaneously.
d = largest dimension of the physical circuit

∆t = smallest signal response time of interest = 1/max. frequency of interest
c = 3.10^8 m/sec
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Example: Lumped Circuit
•Electrical power case, f=50 Hz (20 ms)

•Telecommunication case, f=25 kHz
•Determine minimum dimension?
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Lumped Circuit Consequences
• Electrical behavior does not depend on the physical

size, shape, and orientation.
• Only the physical interconnections are relevant.
• Voltages and currents at any terminal of the physical
circuit are well defined.
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Basic Circuit Analysis
• Based on 3 (three) postulates

1. Lumped Approximation
2. Kirchhoff Current Law (KCL)
3. Kirchhoff Voltage Law (KVL)
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Basic Circuit Analysis
• Assumptions
1. All conducting wires are perfect conductors (zero resistance).
2. All circuit interconnections are perfect.
• Consequences
Two terminals joined by a wire is equivalent to a single
terminal.
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Basic circuit: Voltage and Currents
• Voltage is an “across” variable

• Voltage is always measured by connecting a voltmeter
across 2 device terminals or nodes.
• Current is a “through” variable
• Current is always measured by inserting an Ammeter
through 1 point of a device terminal or wire.
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Voltage Polarity and Current Reference Direction
• It is necessary to assign (arbitrarily) a current reference

direction for each terminal current, and an a pair of voltage
polarity reference, across every pair of terminals.
• the current i(t) entering an electrical terminal and the voltage vjk(t)
across a pair of terminals and in a typical electrical circuit can assume a
positive value at one instant of time, and a negative value at another
instant of time
• If the calculated current (resp., voltage) at some instant of time turns
out or be a negative number, it simply means that the actual current
(resp., voltage) is opposite in direction (resp., polarity) to the arbitrarily
assigned reference at that instant of time.
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Possible Reference Assignment
Reference current direction and reference voltage polarity can

be arbitrarily assigned.
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Possible Reference Assignment
When two terminals whose voltage polarity is

being assigned are far apart, we often draw a
doubleheaded arrow to identify the associated
pair of terminals.
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Reference Convention
Although the reference current direction

and the voltage polarity can be arbitrarily
assigned, however we will agree on the
following:
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Gaussian Surface and KCL
• Any closed surface that has an inside and an outside is called

a Gaussian surface.
Gaussian Surface 1:
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Nodes
• Any terminal attached to a device in a circuit where 2

or more terminals are soldered together is called a
node.
• We can always draw a sufficiently small sphere centered at
each node of a circuit such that the sphere is pierced only
by the currents entering the node.
• A sphere is the simplest Gaussian surface.
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KCL
• Applying KCL to a small Gaussian surface enclosing each node

• The algebraic sum of all currents leaving a node is zero.
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KCL
Gaussian Surface 2: Gaussian Surface 3:
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Cut Sets
• A subset of currents from a physically connected circuit

forms a cut set iff the following 2 conditions are satisfied:
• Cutting all “m” terminals (wires) would physically disconnect the

circuit into 2 or more components.
• Cutting only m-1 terminals (wires) from the subset of currents
would not physically disconnect the circuit.
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Cut Sets
• Given any cut set {ia, ib …, im}, we can always draw a Gaussian
surface pierced only by {ia, ib …, im}.
• Once a Gaussian surface is chosen, we define the direction of
each current entering the surface to be the positive
orientation of the cut set.
• A cut set with an assumed positive orientation is said to be an
oriented cut set.
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Cut Sets
Is a cut set
1. It cuts the circuit into 2 parts.

2. Any 3 out of 4 currents in the set will
not cut the circuit.
Is not a cut set
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KCL – Cut Sets
• Applying KCL to a Gaussian surface associated with a

cut set
• The algebraic sum of all currents in a cut set
relative to its assigned positive orientation is zero.
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KCL
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KCL
• The algebraic sum of all currents leaving a gaussian surface

is zero.
• The algebraic sum of all currents leaving a node is zero.
• The algebraic sum of all currents leaving a cut sets is zero.
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Node-to-datum and Branch voltages
• Voltage always involves two positions

• we must always specify a voltage across 2 points in a circuit, called
nodes
• Unless, one of the 2 nodes is the circuit ground node, called the datum
node.
• Such a voltage is called a node-to-datum voltage, and will always be denoted
by ej.
• Any other voltage is called a branch voltage, and will be denoted by
vj.
24/08/2021 25
KVL
• The voltage vjk(t) between any 2 nodes j and k is equal to the

difference between the 2 associated node-to-datum voltages ej and ek,
for all times t.
• Algebraic sum of all voltages around any closed node sequence in any
connected circuit is equal to zero at all times t.
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KVL
between any 2 nodes
closed node sequence
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KVL
24/08/2021 28
KVL
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KVL
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KVL
24/08/2021 31
Loop
• A closed node sequence (na, nb, …, nm) is called a

loop iff, there is a 2-terminal circuit element
connecting each consecutive pair of nodes (nk, nk+1),
where nk is any node in the sequence.
24/08/2021 32
KVL
KVL around Loop
Algebraic sum of all voltages

around any loop in a connected
circuit is equal to zero at all
times t.
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Basic Non-Planar Graph 1
• It is impossible to redraw this circuit

without intersecting wires.
• Hence, we can not define meshes in this
circuit.
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Basic Non-Planar Graph 2
• It is impossible to redraw this circuit

without intersecting wires.
• Hence, we can not define meshes in this
circuit.
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Graph G Planar Test
• Kuratowski’s Theorem:
• A necessary and sufficient condition for G to be a planar graph is that
it does not contain either Basic Nonplanar Graph 1 or Basic Nonplanar
Graph 2, as a subgraph.
• We can define meshes in a circuit iff its associated graph is planar
• A graph G is said to be planar iff G can be redrawn on a plane with no

intersecting branches except at the nodes.
24/08/2021 36
Mesh
• Any loop formed by branches of a circuit is called a mesh iff the loop
encloses no other branches, or wires in its interior.
• There are 4 meshes in this circuit.

• Every mesh is a loop, but not all loops are meshes
24/08/2021 37
From Circuits To Graphs
• The interconnection properties of a circuit can best be

exhibited by way of a graph, called a circuit graph.
• The graph retains all the interconnection properties of the
circuit but suppresses the information on the circuit elements.
• For a given circuit. if we replace each element by its element
graph, the result is a directed circuit graph, or simply a
digraph.
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Digraph representation of 2-terminal element
Digraph representation of 3-terminal element
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Digraph representation of n-terminal element
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Circuit with Different Digraphs
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24/08/2021 43
• Circuits containing n-terminal devices can have many distinct

digraphs, due to different (arbitrary) choices of the datum
terminal for each n-terminal device.
• Although the KCL and KVL equations associated with 2
different digraphs of a given circuit are different, they contain
the same information because each set of equations can be
derived from the other.
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Associated Reference Convention
24/08/2021 45
Two-Port Device Graph
Disconnected graph
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Adding a wire connecting one node

from each separate component does
not change KVL or KCL equations.
24/08/2021 47
Since nodes and are now the

same node, they can be combined
into one node, and the redrawn
digraph is called a hinged graph.
24/08/2021 48

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Introduction to Circuit Analysis – Part 1

Minggu Topik Rujukan

3 AC Power Analysis Chapter 11

• Electromagnetic wave behavior is very complex as functions of space

d = largest dimension of the physical circuit

•Electrical power case, f=50 Hz (20 ms)

•Determine minimum dimension?

• Electrical behavior does not depend on the physical

• Based on 3 (three) postulates

• Voltage is an “across” variable

• It is necessary to assign (arbitrarily) a current reference

Reference current direction and reference voltage polarity can

When two terminals whose voltage polarity is

Although the reference current direction

• Any closed surface that has an inside and an outside is called

• Any terminal attached to a device in a circuit where 2

• Applying KCL to a small Gaussian surface enclosing each node

Gaussian Surface 2: Gaussian Surface 3:

• A subset of currents from a physically connected circuit

• Cutting all “m” terminals (wires) would physically disconnect the

1. It cuts the circuit into 2 parts.

Is not a cut set

• Applying KCL to a Gaussian surface associated with a

• The algebraic sum of all currents leaving a gaussian surface

• Voltage always involves two positions

• The voltage vjk(t) between any 2 nodes j and k is equal to the

between any 2 nodes

closed node sequence

• A closed node sequence (na, nb, …, nm) is called a

KVL around Loop

Algebraic sum of all voltages

• It is impossible to redraw this circuit

• It is impossible to redraw this circuit

• A graph G is said to be planar iff G can be redrawn on a plane with no

• There are 4 meshes in this circuit.

• The interconnection properties of a circuit can best be

Digraph representation of 2-terminal element

Digraph representation of 3-terminal element

Digraph representation of n-terminal element

• Circuits containing n-terminal devices can have many distinct

Adding a wire connecting one node

Since nodes and are now the

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