VHDL Aes Project

VHDL PROJECT
Advanced Encryption Standard (AES)
Groupe 8:
Debby Miressa Mijena, Kassem Khalil
Professor: Dragomir MILOJEVIC
Teaching assistant: Muhammed Ali, Oscar Van
Date: Dec, 2023

Contents
1. Introduction
2. Objective
3. Project Specification
4. Design
5. Methodology
6. Simulation Result
7. Discussion
8. Conclusion
Introduction
The Advanced Encryption Standard (AES) stands as a foundation in modern cryptography,

recognized for its robust security and widespread adoption in securing sensitive information.
Developed by the National Institute of Standards and Technology (NIST), AES replaced the
aging Data Encryption Standard (DES) in 2001, offering a higher level of security with its
symmetric key encryption algorithm.
At the heart of AES lies its symmetric nature, wherein the same key is used for both encryption
and decryption. This characteristic simplifies the implementation process and contributes to the
algorithm's efficiency. AES operates on fixed-size blocks of data, dividing them into 128-bit
blocks for processing. The algorithm supports key lengths of 128, 192, and 256 bits, allowing for
varying levels of security based on the selected key size. The strength of AES lies not only in its
mathematical complexity but also in its adaptability to different key lengths, making it a versatile
choice for various applications.
Running AES on FPGA hardware is advantageous primarily due to the FPGA's capability for
parallel processing, allowing simultaneous execution of multiple operations and significantly
accelerating the AES encryption process. FPGAs offer customization, enabling the creation of
optimized hardware architectures tailored to the AES algorithm's specific requirements. The
reconfigurable nature of FPGAs results in low-latency cryptographic circuits, making them
well-suited for applications requiring quick response times. Moreover, FPGAs are
energy-efficient, providing higher performance with lower power consumption compared to
general-purpose processors. Offloading AES encryption to FPGAs allows for hardware
acceleration, freeing up the main processor for other tasks. Additionally, the scalability of
FPGAs in terms of hardware resources provides flexibility to adapt to varying performance
needs in different applications.
Objective
The goal of this project is to implement only the encryption part of the 128-bit AES algorithm on
the Basys 3 FPGA Board. To construct the encryption part, we needed to implement four key
modules namely: Add_Round_Key, Substitute_Byte, Shift_Rows and Mix_Columns. This report
presents the step by step description of the implementation process starting from the design all
the way to the implementation of the circuit on the FPGA. In addition, we will present the
testbench simulation results for each module as well as for the overall system using a specific
test vector. We will also discuss the challenges faced and respective solutions we provided to
address those problems. Finally, a summary of the findings and insights gained will be presented.
Project Specification
- Implement the 4 AES encryption steps in a separate VHDL module. For each module, test
your implementation by writing a test-bench using the provided test-vectors.
- Using all the 4 modules, implement the AES encryption such that one AES step is executed
in one clock cycle. Write a test-bench to test your implementation using the test-vectors provided
to you.
- Write a module such that the encryption of one of the given test-vectors starts when pressing
the central button. Once the encryption is finished, ”AES” should be displayed on the 7-segment
display. To be able to start the encryption again, the right-button should be pressed. This RST
should be synchronous. Write a test bench to test your implementation.
- Additional functionalities can be added.
In accordance with the project requirements, we chose:

Test Vector:
In Hexadecimal: “6BC1BEE2 2E409F96 E93D7E11 7393172A”

In Binary: “011010111100000110111110111000100010111001000000100111111001
01101110100100111101011111100001000101110011100100110001011100101010”
For Hardware Implementation:
We wanted to add 2 LEDs (led0 and led1) to display the status for the button click events. i.e.
RST and EN respectively.
- When btnR (RST) is clicked, led0 will turn On and when released, led0 will turn Off.
- When btnC (EN) is clicked, led1 will turn On once the encryption is successfully completed
and it will remain On unless RST (btnR) is clicked.
Design
The workflow for AES can be shown in the figure below. Here, the sequence of module
execution is shown clearly. But this sequential approach doesn’t reuse modules, so we need an
efficient representation that will be used in our implementation.
Figure 1: AES Encryption Architectural Flow
In order to describe the transitional behavior from one module to another, we need to model the
modules as states and use a moore state machine to describe the transitional behavior. The figure
below encapsulates the architectural flow shown in Figure 1 much efficiently.
Figure 2: Moore State Machine for AES Encryption Algorithm

Description of the State Symbols:
BGN - Begin
ARK - Add Round Key
SB - Substitute Bytes
SR - Shift Rows
MC - Mix Columns
EXT - Exit
We used round as a transition condition since each critical transitions happen at a specific round.
For instance, the transition to EXT (Exit) State requires the round to be 11, i.e. the final round.
Also, at this round Mix Columns is skipped as shown in Figure 2. Round spans from 1 to 11.
The transitions marked as “x” are “Don’t Care” conditions where the round is not relevant for
that transition.
Methodology
After modeling the module transitions (Top level Model), we now need to implement the main
module block themselves i.e. ARK, SB, SR and MC.
1) Add Round Key (ARK)
At this module, the 128-bit input block is XORed with the respective round key (also 128-bit).
Below, we have the implementation of ARK.
Figure 3: Add Round Keys VHDL Implementation
We have also tested the working of this component using add_round_keys_tb as shown below.
Figure 4: Add_Round_Key TestBench VHDL
Figure 5:Add_Round_Key Module TestBench Simulation
Observation:
From the document of test vectors, after first round key addition, we get a result shown as:
KeyAddition 40BFABF4 06EE4D30 42CA6B99 7A5C5816
Therefore, using the testbench simulation, we confirmed it to be true.
2) Sub Bytes (SB)
At this step, we substitute each byte (8 bit chunks) of the 128-bit input with the one’s given in
S-Box LUT. The implementation of SB is as follows:
Figure 6 : Substitute Bytes Module VHDL Implementation
We have also tested the working of this component using sub_bytes_tb as shown below.
Figure 7: Substitute Bytes TestBench VHDL
Figure 8 : Substitution Module Test bench simulation
Observation:
From the document of test vectors, after first round substitution of bytes, we get a result shown
as:
Round = 1
Substitution 090862BF 6F28E304 2C747FEE DA4A6A47
Therefore, using the testbench simulation, we confirmed it to be true.
3) Shift Rows (SR)
At this step, we shift each row of the 128-bit input block (arranged in 4 rows and transposed)
where each 32 bit (4 bytes) row is shifted by one byte (8-bit) per one shift. Each row is shifted
with different amount depending on the row index. i.e. the first row is not shifted, second row
shifted by one byte, third shifted by two bytes and the last by three bytes. The implementation of
SR is as follows:
Figure 9: Shift Rows VHDL Implementation

Figure 10: ShiftRows module Test bench simulation
4) MixColumns
Figure :MixColumns Module Test bench simulation

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VHDL PROJECT

Advanced Encryption Standard (AES)

Debby Miressa Mijena, Kassem Khalil

Professor: Dragomir MILOJEVIC

Teaching assistant: Muhammed Ali, Oscar Van

Date: Dec, 2023

The Advanced Encryption Standard (AES) stands as a foundation in modern cryptography,

- Additional functionalities can be added.

In accordance with the project requirements, we chose:

In Hexadecimal: “6BC1BEE2 2E409F96 E93D7E11 7393172A”

For Hardware Implementation:

Figure 1: AES Encryption Architectural Flow

Figure 2: Moore State Machine for AES Encryption Algorithm

1) Add Round Key (ARK)

Figure 3: Add Round Keys VHDL Implementation

Figure 5:Add_Round_Key Module TestBench Simulation

Figure 6 : Substitute Bytes Module VHDL Implementation

Figure 8 : Substitution Module Test bench simulation

Figure 9: Shift Rows VHDL Implementation

Figure :MixColumns Module Test bench simulation

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