CV1800B CV1801B Preliminary Datasheet Full en

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CV180ZB/CV1800B/CV1801B
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Preliminary Datasheet
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Version: 0.3.0.0
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Release date: 2022-11-07

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© 2020 CVITEK Co., Ltd. All rights reserved.

No part of this document may be reproduced or transmiited in any form or by any means
without prior written consent of CVITEK Co., Ltd.
CV1835
Specifications are subject to change without notice
Revision History
Revision Date Description

0.1.0.0 2022/06/29 Preliminary release
0.2.0.0 2022/09/04 Remove Random Number Generator
0.3.0.0 2022/11/07
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Part number update
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CV1835
Terms and Conditions
The document and all information contained herein remain the CVITEK Co., Ltd’s
(“CVITEK”）confidential information, and should not disclose to any third party or
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use it in any way without CVITEK’s prior written consent. User shall be liable for any
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damage and loss caused by unauthority use and disclosure.
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CVITEK reserves the right to make changes to information contained in this document
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at any time and without notice.
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All information contained herein is provided in “AS IS” basis, without warranties of
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any kind, expressed or implied, including without limitation mercantability, non-
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infringement and fitness for a particular purpose. In no event shall CVITEK be liable for
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any third party’s software provided herein, User shall only seek remedy against such
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third party. CVITEK especially claims that CVITEK shall have no liable for CVITEK’s work
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result based on Customer’s specification or published shandard.

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CV1835
Table of contents
Revision History .................................................................................................................................. 2

Terms and Conditions ....................................................................................................................... 3
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Table of contents ................................................................................................................................ 4
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Table of contens for figures .......................................................................................................... 16
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Table of contens for tables ............................................................................................................ 19
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Product Overview ..................................................................................................................... 21
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1.1 Overview (CV180ZB/CV1800B/CV1801B) ...................................................................... 21
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1.2 Application Scenarios ............................................................................................................. 21
1.2.1 CV180ZB/CV1800B/CV1801B Intelligent IP Camera Solutions........... 21
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1.3 Architecture................................................................................................................................ 22
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1.3.1 Overview .....................................................................................................................22

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1.3.2 Processor Core .........................................................................................................23

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1.3.3 TPU ............................................................................................................................... 23

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1.3.4 Video Coding (CV180ZB/CV1800B/CV1801B) ........................................... 24

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1.3.5 Video Interface ........................................................................................................ 24

1.3.6 ISP and Image Processing ...................................................................................25
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1.3.7 CV Hardware Acceleration EngineCV .............................................................25

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1.3.8 Audio Encoding and Decoding .........................................................................25

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1.3.9 Network Interface...................................................................................................26

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1.3.10 Security System Module ...................................................................................... 26

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1.3.11 Intelligent Secure Operating Environment .................................................. 26

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1.3.12 Peripheral Interfaces (CV180ZB/CV1800B/CV1801B) ............................. 26

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1.3.13 External Memory Interface ................................................................................. 27

1.3.14 SDK ............................................................................................................................... 27
1.3.15 Chip Physical Specifications............................................................................... 28
1.4 Boot and Upgrade Modes .................................................................................................... 28
1.4.1 Overview .....................................................................................................................28
1.4.2 Boot Mode and Corresponding Signal Latching Value Relationship28
1.4.3 Image Burning Mode............................................................................................ 29
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1.4.4 Secure Boot ...............................................................................................................29

1.5 Address Space Mapping ........................................................................................................30
Hardware Characteristics ....................................................................................................... 35
2.1 Package and Pin Distribution.............................................................................................. 35
2.1.1 Package CV180ZB/CV1800B/CV1801B ......................................................... 35
2.1.2 Pin Distribution CV180ZB/CV1800B/CV1801B .......................................... 36
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2.2 Pin information Description ................................................................................................. 36
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2.3 Welding Process Suggestions.............................................................................................38
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2.4 Moisture Sensitivity Parameters .........................................................................................39
2.4.1 Moisture Barrier Packaging for CVITEK Products ......................................39
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2.5 Electrical Performance Parameters ................................................................................... 42
2.5.1 Power Consumption Parameters ..................................................................... 42
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2.5.2 Temperature and Thermal Resistance Parameters n
(CV180ZB/CV1800B/CV1801B) .........................................................................42
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2.5.3 Destructive Voltage ............................................................................................... 43

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2.5.4 Power Sequencing(CV180ZB/CV1800B/CV1801B) .................................. 43

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2.5.5 The DC/AC Electrical Parameters of the Power Supply ...........................46

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2.5.6 1.8V I/O Electrical Parameters ........................................................................... 47

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2.5.7 18OD33 IO (VDDIO=1.8V) Electrical Parameters ..................................... 47

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2.5.8 18OD33 IO (VDDIO=3.0V) Electrical Parameters ..................................... 49

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2.5.9 Audio GPIO Electrical Parameters ...................................................................50

2.5.10 ETH GPIO Electrical Parameters .......................................................................50
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2.5.11 MIPI Rx Electrical Parameters ............................................................................ 50

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2.5.12 Sub-LVDS Electrical Parameters ....................................................................... 52

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2.5.13 HiSPi Electrical Parameters ................................................................................. 52

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2.5.14 SDIO Electrical Parameters ................................................................................. 53

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2.5.15 2.5.15 VI RAW/BT.656/BT.1120Electrical

Parameters(CV180ZB/CV1800B/CV1801B) ................................................. 53
2.5.16 AUDIO CODEC Electrical Parameters ............................................................. 53
2.6 Timing ........................................................................................................................................... 55
2.6.1 SPI NOR Timing .......................................................................................................55
2.6.2 SPI NAND Timing ................................................................................................... 56
2.6.3 VI Timing .................................................................................................................... 58
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2.6.4 AIAO (I2S/PCM) Timing ........................................................................................58

2.6.5 I2C Timing ..................................................................................................................60
2.6.6 SPI Timing ..................................................................................................................62
2.6.7 MIPI Rx Timing .........................................................................................................63
2.6.8 Sub-LVDS Timing ................................................................................................... 65
2.6.9 HiSPi Timing ..............................................................................................................66
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2.6.10 SDIO/MMC Timing ................................................................................................ 67
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System ......................................................................................................................................... 72
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3.1 Reset .............................................................................................................................................. 72
3.1.1 Overview .....................................................................................................................72
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3.1.2 Reset Control ............................................................................................................72
3.1.3 Reset Configuration Register .............................................................................74
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3.2 Clock.............................................................................................................................................. 78
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3.2.1 Overview .....................................................................................................................78
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3.2.2 Function Block Diagram .......................................................................................79

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3.2.3 Clock Resource and Frequency Division Structure................................... 79

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3.2.4 PLL Configuration ...................................................................................................80

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3.2.5 CLK_DIV Clock Frequency Division Configuration ....................................82

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3.2.6 PLL CRG Register Overview ................................................................................ 84

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3.2.7 PLL CRG Register Overview ................................................................................ 86

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3.2.8 CLK_DIV CRG Register Overview ......................................................................95

3.2.9 CLK_DIV CRG Register Overview ......................................................................96
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3.3 Processor Subsystem ............................................................................................................114

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3.4 Interrupt System .....................................................................................................................115

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3.5 System Controller .................................................................................................................. 116

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3.5.1 Overview ..................................................................................................................116

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3.5.2 Function Description .......................................................................................... 116

3.5.3 System Control Register ....................................................................................117
3.6 DMA Controller .......................................................................................................................123
3.6.1 Overview ..................................................................................................................123
3.6.2 Characteristics....................................................................................................... 124
3.6.4 Working Mode ...................................................................................................... 129
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3.6.5 DMAC Register ......................................................................................................131

3.7 Timer ........................................................................................................................................... 183
3.7.1 Overview ..................................................................................................................183
3.7.3 Function description...........................................................................................183
3.7.4 Operation mode ...................................................................................................184
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3.7.5 Timer register overview ..................................................................................... 184
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3.7.6 Timer register description ................................................................................ 185
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3.8 Watchdog ..................................................................................................................................187
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3.8.1 Overview ..................................................................................................................187
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3.8.2 Charateristics ......................................................................................................... 187
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3.8.4 Working mode ...................................................................................................... 189
3.8.5 WDT register overview .......................................................................................189
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3.8.6 WDT register description ..................................................................................190

3.9 Real time clock ........................................................................................................................ 192
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3.9.1 Overview ..................................................................................................................192

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3.9.2 Features ....................................................................................................................193

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3.9.4 Operation................................................................................................................ 195

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3.9.5 RTC register overview .........................................................................................199

3.9.6 RTC register description ....................................................................................202
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3.10 Power management and low power consumption mode .................................... 228
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3.10.1 Overview ..................................................................................................................228

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3.10.2 Clock control..........................................................................................................229

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3.10.3 DDR low power consumption control .........................................................229

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3.10.4 Voltage regulation...............................................................................................230

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3.11 Chip internal temperature detection............................................................................. 232

3.12 8051 subsystem ...................................................................................................................... 232
3.12.1 Overview ..................................................................................................................232
3.12.4 Working Mode ...................................................................................................... 234
3.12.5 8051 Subsystem Registers Overview ........................................................... 236
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CV1835
3.12.6 8051 Subsystem Registers ............................................................................... 237

Memory Interface ...................................................................................................................250
4.1 DDR Controller ........................................................................................................................250
4.1.1 Overview ..................................................................................................................250
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4.1.4 Working Method ..................................................................................................255
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4.1.5 AXI Register ............................................................................................................ 256
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4.1.6 DDRC Register .......................................................................................................292
4.2 SPI NOR Flash Controller .................................................................................................... 294
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4.2.1 Overview ..................................................................................................................294
4.2.2 Characteristic ......................................................................................................... 294
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4.2.4 Workflow ................................................................................................................. 299
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4.2.5 Register overview .................................................................................................301

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4.2.6 Register Discription .............................................................................................301

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4.3 SPI NAND Flash Controller .................................................................................................305

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4.3.1 Overview ..................................................................................................................305

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4.3.4 Operation Flow ..................................................................................................... 309

4.3.5 Data Structure (NAND Flash/SPI NAND Flash) ........................................311
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4.3.6 Register Overview ................................................................................................312

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4.3.7 Register description ............................................................................................312

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Network interface .................................................................................................................315

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5.1 Ethernet MAC ..........................................................................................................................315

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5.1.1 Overview ..................................................................................................................315

5.1.2 Function description .......................................................................................... 315
5.1.3 Data flow overview ............................................................................................. 315
5.1.4 Single port function configuration description .....................................316
5.1.5 Ethernet transceiver frame management function ................................316
5.1.6 Ethernet packet receiving interrupt management function.............. 316
5.1.7 Configure the working state of PHY chip...................................................317
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5.1.8 Working mode switching ................................................................................. 317

5.1.9 Typical applications ............................................................................................318
5.1.10 Register offset address description ..............................................................318
5.1.11 GMAC register overview ................................................................................... 318
5.1.12 GMAC register description ...............................................................................319
5.2 Ethernet PHY ........................................................................................................................... 323
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5.2.1 Overview ..................................................................................................................323
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5.2.3 Functional block diagram ................................................................................323
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Video and image codec ........................................................................................................324
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6.1 Overalll overview ....................................................................................................................324
6.2 VCU (Video Codec Unit) ...................................................................................................... 324
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6.2.1 Overview ..................................................................................................................324
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6.2.2 Features ....................................................................................................................324
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6.3 JCU (JPEG Codec Unit) .......................................................................................................328

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6.3.1 Overview ..................................................................................................................328

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6.3.2 Features ................................................................................................................... 328

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Video and graphics processing ..........................................................................................332

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7.1 VPSS (sc_top) ........................................................................................................................... 332

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7.1.1 Overview ..................................................................................................................332

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7.2 LDC (Lens Distortion Correction) .....................................................................................333

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7.2.1 Overview ..................................................................................................................333

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AI engine ...................................................................................................................................335
8.1 TPU (Tensor Processing Unit) ............................................................................................335
8.1.1 Overview ..................................................................................................................335
Video interface ........................................................................................................................338
9.1 VI ................................................................................................................................................... 338
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9.1.1 Overview ..................................................................................................................338

9.1.3 Mode function description .............................................................................. 339
9.1.4 Image storage mode .......................................................................................... 344
9.1.5 VI register overview .............................................................................................344
9.1.6 VI register overview .............................................................................................346
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9.2 MIPI Rx ........................................................................................................................................359
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9.2.1 Overview ..................................................................................................................359
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9.2.2 Charateristics ......................................................................................................... 360
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9.2.4 MIPI Rx Register Overview ............................................................................... 375
9.2.5 MIPI RxRegister Overview ................................................................................ 378
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ISP ............................................................................................................................................... 399
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10.1 Function Overview .................................................................................................................399
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10.2 Overview ....................................................................................................................................400

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10.2.1 Function Block Diagram .................................................................................... 400

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10.2.2 Working Mode ...................................................................................................... 403

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10.3 ISP Interruption System .......................................................................................................403

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10.3.2 Interrupt Timing ................................................................................................... 405

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10.4 Module Function ....................................................................................................................406

10.4.1 Color_bar (patgen) .............................................................................................. 406
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10.4.2 Crop ........................................................................................................................... 406

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10.4.3 AE (Auto Exposure) ..............................................................................................407

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10.4.4 AF (Auto Focus) .....................................................................................................407

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10.4.5 DIS (Digital image stabilization) .....................................................................408

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10.4.6 BLC (Black level correction) ..............................................................................408

10.4.7 DG (Digital Gain) ...................................................................................................408
10.4.8 DPC ............................................................................................................................ 408
10.4.9 GE ................................................................................................................................409
10.4.10 LSC (Lens shading correction) ........................................................................ 409
10.4.11 DRC (LTM) ............................................................................................................... 409
10.4.12 WBG (White Balance Gain) ...............................................................................409
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10.4.13 BNR (Bayer Noise Reduction) ......................................................................... 409

10.4.14 DEMOSAIC (CFA) ..................................................................................................410
10.4.15 CCM ........................................................................................................................... 410
10.4.16 Gamma .....................................................................................................................410
10.4.17 Dehaze......................................................................................................................410
10.4.18 CSC .............................................................................................................................411
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10.4.19 3DNR (3-Dimensional Noise Reduction) ................................................... 411
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10.4.20 YNR............................................................................................................................ 411
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10.4.21 LDCI (DCI) ................................................................................................................ 411
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10.4.22 Sharpen.................................................................................................................... 411
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10.4.23 CNR ............................................................................................................................412
10.4.24 CAC (PFC inside CNR) .........................................................................................412
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10.4.25 CLUT (HSV_3D_LUT) ............................................................................................412
10.4.26 RGBCAC ....................................................................................................................412
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10.4.27 PREYEE...................................................................................................................... 412

10.4.28 Hist_V ........................................................................................................................ 412
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10.4.29 CACP ..........................................................................................................................412

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10.4.30 CA2 .............................................................................................................................413

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10.4.31 LCAC .......................................................................................................................... 413

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10.4.32 User Gamma ...........................................................................................................413

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Audio interface ....................................................................................................................... 414

11.1 AIAO............................................................................................................................................ 414
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11.1.1 Overview ..................................................................................................................414

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11.1.2 Features ....................................................................................................................415

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11.1.4 Operation control ................................................................................................ 420

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11.1.5 AIAO register overview ......................................................................................420

11.1.6 AIAO register description ................................................................................. 421
11.2 Audio Codec .............................................................................................................................435
11.2.1 Overview ..................................................................................................................435
11.2.3 Audio Codec register overview ...................................................................... 436
Peripherals equipment ......................................................................................................... 443
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12.1 I2C ................................................................................................................................................ 443

12.1.1 Overview ..................................................................................................................443
12.1.3 Function block diagram .................................................................................... 443
12.1.4 I2C Agreement timing........................................................................................444
12.1.5 Working mode ...................................................................................................... 445
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12.1.6 I2C register overview .......................................................................................... 447
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12.1.7 I2C register description..................................................................................... 449
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12.2 UART ............................................................................................................................................457
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12.2.1 Overview ..................................................................................................................457
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12.2.4 Working mode ...................................................................................................... 460
12.2.5 UART register overview ..................................................................................... 465
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12.2.6 UART register description ................................................................................ 466

12.3 SPI .................................................................................................................................................472
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12.3.1 Overview ..................................................................................................................472

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12.3.4 Working mode ...................................................................................................... 473

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12.3.5 Three kinds of serial peripheral bus sequence diagram ................... 478
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12.3.7 Register Description ........................................................................................... 483

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12.4 SD/SDIO Controller ...............................................................................................................495

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12.4.2 Application Explanation .................................................................................... 503

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12.4.4 Register Description ........................................................................................... 522

12.5 GPIO ............................................................................................................................................ 536
12.5.1 Overview ..................................................................................................................536
12.5.3 Working Mode ...................................................................................................... 536
12.5.4 GPIORegister Overview..................................................................................... 537
12.5.5 GPIO Register Description ................................................................................538
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12.6 USB DRD (Dual Role Device) ............................................................................................ 541

12.6.1 Overview ..................................................................................................................541
12.6.3 USBC Function and Register Description ..................................................543
12.6.4 The Illustration of Host Initialization Program .........................................582
12.6.5 Host Register Description .............................................................................. 583
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12.6.6 Device Initialization Program ..................................................................... 592
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12.6.7 Device Register Description ..........................................................................593
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12.7 SARADC ......................................................................................................................................603
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12.7.1 Overview ..................................................................................................................603
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12.7.2 Features ....................................................................................................................603
12.7.3 Working method ..................................................................................................604
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12.7.4 SARADC register overview ............................................................................... 604
12.7.5 SARADC register description .......................................................................... 604
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12.8 Temperature sensor ..............................................................................................................607

12.8.1 Overview ..................................................................................................................607
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12.8.2 Working method ..................................................................................................607

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12.8.3 Temperature sensor register overview ....................................................... 610

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12.8.4 Temperature sensor register description ...................................................610

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12.9 PWM ............................................................................................................................................614

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12.9.1 Overview ..................................................................................................................614

12.9.2 Features ....................................................................................................................614
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12.9.3 Operation................................................................................................................ 615

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12.9.4 PWM Register Overview ....................................................................................617

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12.9.5 PWM Register Description ............................................................................... 618

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12.10 Key scan................................................................................................................... 622

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12.10.1 Overview ..................................................................................................................622

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12.10.2 Working Method ..................................................................................................622

12.10.3 Basic Setting ...........................................................................................................624
12.10.4 Using FIFO mode..................................................................................................624
12.10.5 Using snapshot array mode .............................................................................624
12.10.6 Key scan Register Overview .............................................................................625
12.10.7 Key scan Register Description ........................................................................ 625
12.11 Wiegand ...................................................................................................................629
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12.11.1 Overview ..................................................................................................................629

12.11.2 Working method ..................................................................................................631
12.11.3 Wiegand Register Overview ............................................................................ 632
12.11.4 Wiegand Register Description ........................................................................633
12.12 IRRX Infrared Interface.......................................................................................638
12.12.1 Overview ..................................................................................................................638
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12.12.3 Working Mode ...................................................................................................... 638
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12.12.4 IRRX Register Overview ..................................................................................... 638
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12.12.5 IRRX Register Description ................................................................................640
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Security Subsystem Module ................................................................................................649
13.1 CryptoDMA ...............................................................................................................................649
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13.1.1 Overview ..................................................................................................................649
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13.1.2 Function Characteristics.................................................................................... 650
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13.1.3 DMA Function Description ...............................................................................650

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13.1.4 Function description of symmetric key algorithm block encryption

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mode......................................................................................................................... 651
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13.1.5 CryptoDMA Register Overview ...................................................................... 653

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13.1.6 CryptoDMA Register Overview ...................................................................... 655

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13.2 Secure Debug Firewall......................................................................................................... 666

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13.2.1 Overview ..................................................................................................................667

13.2.2 Status Inquiry and Password Input Interface (I2C) ................................. 667
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13.2.3 Status Inquiry and Password Input Process ............................................669

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13.3 Efuse Controller ......................................................................................................................669

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13.3.1 Overview ..................................................................................................................670

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13.3.2 Efuse entity address translation and virtual register address .........671
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13.3.3 Efuse Ctrl Register Overview ..........................................................................676

13.3.4 Efuse CTRL Register Overview .......................................................................678
13.3.5 eFuse CTRL Operation Process ..................................................................... 687
Intelligent Secure Operation Environment ................................................................. 689
14.1 Establishment of Trust Chain ........................................................................................... 689
14.2 Data Encryption Security ....................................................................................................690
14.3 Software and Hardware verification ............................................................................. 691
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CV1835
14.4 Secure Storage and Transmission ................................................................................. 691

14.5 Security Update ......................................................................................................................691
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CV1835
Table of contens for figures
Figure 1‑1 intelligent IP camera solutions. .........................................................................................22

Figure 1‑2 CV180ZB/CV1800B/CV1801B architeture................................................................... 23
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Figure 2‑1 CV180ZB/CV1800B/CV1801B package dimensions, top view.............................35
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Figure 2‑2. CV180ZB/CV1800B/CV1801B package dimensions, bottom view.................. 35
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Table 2‑3 CV180ZB/CV1800B/CV1801B pin distribution............................................................36
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Figure 2‑4 Lead-free Reflow Soldering process curve .................................................................. 38
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Figure 2‑5 Vacuum drying packaging information .........................................................................39
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Figure 2‑6 Desiccant packs, humidity card, chip, and tray ...........................................................40
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Figure 2- 7 I2C Timing Diagram .............................................................................................................60
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Figure 2- 8 SPI Timing Diagram .............................................................................................................62
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Figure 3- 1 Reset Management Module Block Diagram ............................................................. 72
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Figure 3- 2 Clock Management Block Diagram .............................................................................. 79

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Figure 3- 3 Clock Source Frequency Division Diagram ................................................................80

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Figure 3- 4 DMAC Hardware Control Fow Diagram ................................................................... 123

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Figure 3- 5 DMA Transmission Structure .........................................................................................125

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Figure 3- 6 Linked List Relative Address and Data Format .......................................................127

Figure 3- 7 Interrupt Status and Source Diagram ........................................................................128
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Figure 3- 8 WatchDog Application block diagram ......................................................................188

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Chart 3- 9 Example of using PWM to control DCDC voltage. .................................................231

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Figure 4- 1 SoC/DRAM Interconnection Diagram .......................................................................251

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Figure 4- 2 Standard SPI Interface Mode Write Operation Sequence ................................ 295
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Figure 4- 3 Standard SPI Interface Mode Read Operation Sequence ................................. 295
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Figure 4- 4 Dual-Input SPI Interface Sequence ............................................................................ 296

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Figure 4- 5 Dual-IO SPI Interface Sequence ...................................................................................296

Figure 4- 6 Quad-Input SPI Interface Sequence .......................................................................... 297
Figure 4- 7 Quad-IO SPI Interface Sequence .................................................................................297
Figure 4- 8 Standard SPI Write Operation Timing ......................................................................306
Figure 4- 9 Standard SPI Read Operation Timing .......................................................................307
Figure 4- 10 SPI Nand x2 Interface Mode Operation Sequence ........................................... 307
Figure 4- 11 SPI Nand x4 Interface Mode Operation Sequence ........................................... 308
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CV1835
Chart 5- 1 GMAC conceptual data stream ......................................................................................316

Chart 5- 2 built-in 10/100 Ethernet PHY chart .............................................................................. 323
Figure 6- 1 VENC function block diagram .....................................................................................326
Figure 8- 1 TPU working mode diagram ......................................................................................... 335
Figure 9- 1 VI function block diagram ..............................................................................................338
Figure 9- 2 DC Synchronous signal mode -vhs mode ............................................................... 342
ed
Figure 9- 3 VI register overview .......................................................................................................... 344
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Figure 9- 4 MIPI Rx Functional Block Diagrams and Position ................................................. 360
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Figure 9- 5 Interface Types Supported by MIPI Rx ......................................................................361
al
Figure 9- 6 Transmission Mechanism of Data Packet .................................................................362
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Figure 9- 7 CSI-2 Long Packet Format ..............................................................................................363
Figure 9- 8 CSI-2 Short Packet Format ............................................................................................. 364
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Figure 9- 9 YUV422 8-bit Frame Format ..........................................................................................366
Figure 9- 10 YUV422-10bit Data Transmission Sequence ........................................................366
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Figure 9- 11 YUV422-10bit Data Packet Transmission Correspondence ........................... 367

Figure 9- 12 YUV422-10bit Frame Format ......................................................................................367
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Figure 9- 13 RAW8 Data Transmission Sequence ........................................................................368

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Figure 9- 14 RAW8 Frame Format ......................................................................................................368

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Figure 9- 15 RAW10 Data Transmission Sequence ..................................................................... 368

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Figure 9- 16 RAW10 Frame Format ................................................................................................... 369

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Figure 9- 17 RAW12Data Transmission Sequenc .........................................................................369

图表 9‑18 RAW16Data Transmission Sequenc .............................................................................. 370
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图表 9‑19 RAW16 Frame Format ..........................................................................................................370

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Figure 9- 20 MIPI Interface Image Format ......................................................................................372

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Figure 9- 21 MIPI Interface Wide Dynamic Data Transfer (using DT) .................................. 373
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Figure 9- 22 MIPI Interface Wide Dynamic Data Transfer (using ID) ................................... 374
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Figure 9- 23 MIPI Interface Wide Dynamic Data Transfer (register setting) ..................... 375
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Figure 9- 24 MIPI Rx PHY Register Overview .................................................................................375

Table 9‑25 MIPI Rx CSI control registers overview ....................................................................... 377
Table 9‑26 MIPI Rx Sub-LVDS control registers overview ......................................................... 378
Figure 10- 1 ISP Overall Structure Diagram ....................................................................................400
Figure 10- 2 Pre_raw_fe and Pre_raw_be Module Diagram ...............................................................401
Figure 10- 3 raw_top Module Diagram .................................................................................................. 402
Figure 10- 4 rgb_top Module Diagram ...................................................................................................402
17
CV1835
Figure 10- 5 yuv_top Module Diagram ............................................................................................... 403

Figure 10- 6 ISP Timing Diagram when Interrupt occurs ......................................................... 406
Figure 10- 7 Image Cutting Diagram ................................................................................................ 407
Figure 12- 1 TI SSP Single Frame Transmission Format .............................................................480
Figure 12- 2 TI SSP Continuous Frame Transmission Format ................................................. 481
Figure 12- 3 NS Microwire Single Frame Transmission Format ............................................. 481
ed
Figure 12- 4 NS Microwire Continuous Frame Transmission Format .................................. 482
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Figure 12- 5 Single Block and Multi Block Read Operation .....................................................501
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Figure 12- 6 Clock Configuration Flow Chart ................................................................................ 505
al
Figure 12- 347 Abort Command Sequence ................................................................................... 511
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Figure 12- 358 Asynchronous Abort Command Procedure ....................................................512
Figure 12- 9 Wiegand 26 Format ........................................................................................................629
e
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Figure 13- 1 Security Subsystem Module ....................................................................................... 649
Figure 13- 2 ECB Mode ........................................................................................................................... 651
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Figure 13- 3 CBC Mode.......................................................................................................................... 652

Figure 13- 4 CTR Mode ...........................................................................................................................653
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Figure 13- 5 eFuse CTRL Module architecture ............................................................................. 671

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Figure 14- 1 Establishment of trust chain ....................................................................................... 690

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CV1835
Table of contens for tables
Table2‑1 Lead-free reflow soldering process parameters ........................................................... 38

Table 2‑2 Humidity classification and floor life ................................................................................ 40
ed
Table 2‑3 Baking temperature and time table .................................................................................. 41
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Table 2‑4 Thermal resistance parameters for CV180ZB/CV1800B/CV1801B .......................42
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Table 2‑5 Temperature-related parameters .......................................................................................42
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Table 2‑6 Destructive voltage parameters (CV180ZB/CV1800B/CV1801B) ......................... 43
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Table 2- 7 The power supply electrical parameters of CV180ZB/CV1800B/CV1801B
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(Recommended Operating Conditions) .............................................................................................. 46
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Table 2- 8 1.8V I/O Electrical Parameters ........................................................................................... 47
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Table 2- 9 18OD33 IO (VDDIO=1.8V) Electrical Parameters ...................................................... 48
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Table 2- 10 18OD33 IO (VDDIO=3.0V) Electrical Parameters ....................................................49
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Table 2- 11 Audio GPIO Electrical Parameters ................................................................................. 50

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Table 2- 12. MIPI D-PHY High Speed(MISH) DifferentialDC Electrical Parameters .......... 51
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Table 2- 13. MIPI D-PHY High Speed(MIHS) Differential AC Electrical Parameters .........51
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Table 2- 14 MIPI D-PHY Low Power(MILP) Differential DC Electrical Parameters ............. 51

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Table 2- 15 MIPI D-PHY Low Power(MILP) Differential AC Electrical Parameters ............ 52

Table 2- 16 Sub-LVDS(SL) Differential DC Electrical Parameters .............................................. 52
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Table 2- 17 Sub-LVDS(SL) Differential AC Electrical Parameters .............................................. 52

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Table 2- 18 HiSPi Differential DC Electrical Parameters ............................................................... 53

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Table 2- 19 Audio CODEC Overall Index ............................................................................................ 53

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Table 2- 20 Audio DAC Electrical Parameters ...................................................................................53

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Table 2- 21 Audio ADC Electrical Parameters ...................................................................................54

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Table 2- 22 SPI NAND Input Timing Requirements ....................................................................... 56

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Table 2- 23 SPI NAND Output Timing Requirements ..................................................................57

Table 2- 24 SPI Timing Requirements ..................................................................................................62
Table 3- 1 PLL Configuration Parameters ...........................................................................................80
Table 3- 2 Interger PLL Configuration Parameters ......................................................................... 81
Table 3- 3 Fractional PLL Configuration Parameters ..................................................................... 82
Table 3- 4 Clock Source and Preset Frequency Division Parameters ......................................83
Table 3- 5 Interrupt Number and Interrupt Source Mapping Table ..................................... 115
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CV1835
Table 3- 6 DMAC Access Space Type................................................................................................ 124

Table 3- 7 Timer register overview (address 0x030A0000) ...................................................... 184
Table 3- 8 WDT register overview (address 0x03010000) .........................................................190
Table 3- 9 RTC_REG register overview (base address: 0x05026000) .................................... 199
Table 4- 1 DDR2 Command Truth Table ...........................................................................................252
Table 4- 2 DDR3 Command Truth Table ...........................................................................................253
ed
Table 5- 1 GMAC register overview ........................................................................................................318
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Table 10- 1 Interrupt Indication Register ........................................................................................403
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Table 11- 1 AIAO subsystem register overview (base address: 0x0410_8000) ................ 420
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Table 11- 2 I2S_TDM_0/1/2/3 register overview (address 0x0410_0000 + n*0x10000)
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............................................................................................................................................................................421
Table 12- 1 SD3.0 Supported Speed and Voltage ....................................................................... 502
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Table 12- 2 SD Register Overview ...................................................................................................... 521
Table 12- 3 Four GPIO Module Base Addresses of the Chip ................................................... 537
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Table 13- 1 Status Query I2C Interface Register Address ......................................................... 668
Figure 13- 2 eFuse entity (row) address and logical (row) address corresponding value
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............................................................................................................................................................................672
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CV1835
Product Overview
1.1 Overview (CV180ZB/CV1800B/CV1801B)
ed
CV180ZB/CV1800B/CV1801B is a high-performance, low-power consumption chip designed
for various consumer monitoring IP cameras, home intelligence, and other products. It
w
integrates an H.264/H.265 video compression encoder and ISP and supports various image
lo
enhancement and correction algorithms such as digital wide dynamic range, 3D noise
al
reduction, defogging, and lens distortion correction to provide professional-grade video
t
image quality to customers.
no
The chip also integrates a self-developed intelligent reference design (human form detection,
e
area detection, motion detection), built-in DDR, and complete peripherals and external
ar
devices, providing a high-integration and concise solution to facilitate customer product
n
development and mass production.
tio
In addition, it also provides secure boot, secure update, and secure encryption and so on to
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provide a series of security solutions for users from development, mass production to
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product application.
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The chip integrates an 8-bit MCU subsystem, which can replace general external MCUs to
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achieve the goal of saving BOM cost and power consumption.

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1.2 Application Scenarios

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1.2.1 CV180ZB/CV1800B/CV1801B Intelligent IP Camera Solutions

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The typical application scenarios for intelligent IP camera solutions are shown in Figure 1-1.
21
CV1835
ed
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Figure 1‑1 intelligent IP camera solutions.
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1.3 Architecture ar
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1.3.1 Overview
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CV1835
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Figure 1‑2 CV180ZB/CV1800B/CV1801B architeture

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1.3.2 Processor Core

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Main processor RISCV C906 @ 1.0Ghz .

o 32KB I-cache, 64KB D-Cache
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o Integrated vector and floating-point processing units (FPU).

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Coprocessor RISCV C906 @ 700Mhz

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o Integrated floating-point processing units (FPU).

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1.3.3 TPU
Built-in CVITEK TPU, integrated intelligent reference design (human form detection,
area detection, motion detection)
23
CV1835
1.3.4 Video Coding (CV180ZB/CV1800B/CV1801B)
H.264 Baseline/Main/High profile

H.265 Main profile
H.264/H.265 both support I-frames and P-frames.
MJPEG/JPEG baseline
ed
H.264/H.265 has maximum encoding resolution : 2880x1620 (5M) (CV1801B)
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H.264/H.265 has maximum encoding resolution : 2688x1520 (4M) (CV1800B)
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H.264/H.265 has maximum encoding resolution : 2304x1296 (3M) (CV180ZB)
al
H.264/H.265 ’s encoding performance:
t
2880x1620@20fps+720x576@20fps (CV1801B)
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2688x1520@25fps+720x576@25fps (CV1800B)
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2304x1296@25fps+720x576@30fps (CV180ZB)
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JPEG ’s maximum encoding and decoding performance:
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2880x1620@20fps (CV1801B)
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2688x1520@25fps (CV1800B)
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2304x1296@30fps (CV180ZB)
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Support multiple bitrate control modes, including CBR/VBR/FIXQP.

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Support Region of Interest (ROI) encoding.

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1.3.5 Video Interface

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The Input
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Support simultaneous one-channel video input (MIPI 4L).

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Support MIPI serial interface.

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Support 8/10/12 bit RGB Bayer video input.

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Support BT.656,BT.601
Support high-definition CMOS sensors such as SONY, OnSemi, OmniVision.
Provide programmable frequency output for the sensor to use as a reference
clock.
Support maximum width: 2304 , maximum resolution: 2304x1296 (CV180ZB)
Support maximum width: 2688 , maximum resolution: 2688x1520 (CV1800B)
Support maximum width: 2880 , maximum resolution: 2880x1620 (CV1801B)
24
CV1835
1.3.6 ISP and Image Processing
Support image or video rotation by 90, 180, or 270 degrees;

Support horizontal(Flip) or vertical(Mirror) flipping of image or video;
Support overlaying two layers of OSD (On-Screen Display) on the video;
Support video scaling down to 1/32 or up to 32 times;
ed
Support 3A algorithm: automatic exposure(AE), automatic white balance(AWB),
and automatic autofocus(AF) ;
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Support fixed-mode noise reduction and bad pixel correction;
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Support correction of lens shading, distortion, and purple fringing;
Support direction-adaptive demosaic algorithm that selects the best demosaic
t
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algorithm based on the image orientation;
Support Gamma correction, dynamic contrast enhancement, and color
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management algorithms;
Support regional adaptive defogging;
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Support bayer denoising, 3D denoising, detail enhancement, and sharpening

enhancement;
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Support local Tone mapping

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Support sensor with wide dynamic range and 2-frame wide dynamic range ;
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Support two-axis digital image stabilization;

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Support lens distortion correction;

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Provide PC-side ISP tuning tools.

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.
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1.3.7 CV Hardware Acceleration EngineCV

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Mixed mode of software and hardware supports partial OpenCV library.

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1.3.8 Audio Encoding and Decoding
Integrated Audio CODEC, supporting 16-bit audio/speech input and output;

Integrated mono microphone input;
Integrated mono output (external amplifier required to drive the speaker);
Internally integrated another microphone direct output channel for easy
implementation of AEC;
25
CV1835
Software audio codec protocols (G.711, G.726, ADPCM);

Software supports audio 3A (AEC, ANR, AGC) functions;
1.3.9 Network Interface
The Ethernet module provides one Ethernet MAC for receiving and transmitting network
ed
data. The Ethernet MAC, combined with the built-in 10/100Mbps Fast Ethernet Transceiver,
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can operate in 10/100Mbps full-duplex or half-duplex mode.
lo
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1.3.10 Security System Module
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Hardware implementation of multiple encryption and decryption algorithms such as
AES/DES/SM4;
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Hardware implementation of hashing algorithms such as HASH (SHA1/SHA256);
Internal integration of 2Kbit eFuse logical space.
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1.3.11 Intelligent Secure Operating Environment

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Supports secure boot, provides secure hardware and software

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protection functions;
Supports data encryption security: data encryption program,
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operation core encryption;

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Supports software and firmware signature verification process:

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confirms software trustworthiness and integrity, including boot and

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loading signature verification program;

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Supports secure storage and transmission: protects external data

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storage and exchange;

Supports secure updates.
1.3.12 Peripheral Interfaces (CV180ZB/CV1800B/CV1801B)
Integrated POR, Power sequence;
26
CV1835
3 single-ended ADCs (3 in MCU domain);

4 I2C interfaces (1 in mcu domain);
3 SPI interfaces;
5 groups of UART (1 in mcu domain) ;
4 groups of (16 channels) PWM;
2 SDIO interfaces:
ed
One supports 3V connection for SD 3.0 Card (supporting a maximum capacity of
SDXC 2TB and speed up to UHS-I);
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One supports 3.0V connection for other SDIO 3.0 devices (supporting speed up to
lo
UHS-I).
al
51 GPIO interfaces (9 in MCU domain);
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Integrated keyscan and Wiegand;
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Integrated MAC PHY supporting 10/100Mbps full-duplex or half-duplex mode;
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One USB Host/device interface.
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1.3.13 External Memory Interface

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Built-in DRAM
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CV180ZB/CV1800B DDR2 16bitx1, with a maximum speed of 1333Mbps ,

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capacity of 512Mbit (64MB)

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CV1801B DDR3 16bitx1, with a maximum speed of 1866Mbps, capacity of

1Gbit (128MB)
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SPI NOR flash interface (1.8V / 3.0V)

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Supports 1, 2, 4-wire mode.

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Maximum support for 256MByte.

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SPI Nand flash interface (1.8V / 3.0V)

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Support 1KB/2KB/4KB page (corresponding maximum capacity

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16GB/32GB/64GB)
Uses the built-in ECC module of the device.
1.3.14 SDK
Linux-5.10-based SDK
27
CV1835
1.3.15 Chip Physical Specifications
Power Consumption
1080P + Video encode + AI : ~ 500mW
Other scenarios : TBD
Operating Voltage
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Core voltage: 0.9V
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IO voltage: 1.8V and 3.0V
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DDR voltage as shown in the table below:
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CV180ZB/CV1800B = 1.8V
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CV1801B = 1.35V
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Package
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QFN package is used, with a package size of 7mmx7mmx0.9mm. The pin
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pitch is 0.35mm, and the total number of pins is 68.
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1.4 Boot and Upgrade Modes

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1.4.1 Overview
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The chip is booted by the built-in ROM (BOOTROM). When the chip is reset, it detects
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whether there is a weak pull-up or weak pull-down on two pins (SPINOR_MOSI,

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SPINOR_WP_X) to determine the type of memory device currently in use.

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For chips with secure boot, software execution or upgrades will be verified during startup
ifi p
and chip upgrades to ensure that the software being executed or upgraded is secure.
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1.4.2 Boot Mode and Corresponding Signal Latching Value

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Relationship
Supports booting from SPI Nor Flash (SPINOR_WP_X pull down, SPINOR_MOSI pull
up)
Supports booting from SPI Nand Flash (SPINOR_WP_X pull down, SPINOR_MOSI pull
down)
28
CV1835
1.4.3 Image Burning Mode
Supports burning image through SD card;

Supports burning image through USB device mode;
If the image already exists in flash, software supports upgrading through the network.
ed
1.4.4 Secure Boot
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Supports secure boot and upgrade;
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AES hardware encryption and decryption ;
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SHA/Secure Efuse security hardware.
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CV1835
1.5 Address Space Mapping
Start Address End Address Space

Space Function
[31:0] [31:0] Size(Byte)
0x01000000 0x018FFFFF reserve

0x01900000 0x01900FFF ap_mailbox 4K
0x01901000 0x01901FFF ap_system_ctrl 4K
ed
0x01902000 0x019EFFFF reserve
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0x01A00000 0x01FFFFFF reserve
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0x02000000 0x02FFFFFF reserve 64K
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0x03000000 0x03000FFF TOP_MISC control register 4K
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0x03001000 0x03001FFF PINMUX control register 4K
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0x03002000 0x03002FFF CLKGEN/PLL control register 4K
e
0x03003000 0x03003FFF RSTGEN control register 4K
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0x03004000 0x03005FFF reserve
0x03006000 0x03006FFF reserve 4K
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0x03007000 0x03008FFF reserve
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0x0300A000 0x0300AFFF 4K
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reserve
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0x0300B000 0x0300FFFF reserve

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0x03010000 0x03010FFF WATCH DOG0 control register 4K

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0x03020000 0x03020FFF GPIO0 control register 4K
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0x03024000 0x0302FFFF reserve

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0x03030000 0x03030FFF WGN0 control register 4K

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0x03040000 0x0304FFFF KEYSCAN control register 64K
0x03050000 0x0305FFFF EFUSE control register 64K
0x03060000 0x03060FFF PWM0 control register 4K
0x030A0000 0x030AFFFF TIMER control register 64K
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CV1835
0x030C0000 0x030CFFFF reserve

0x030D0000 0x030D0FFF reserve 4K
0x030D3000 0x030DFFFF reserve
0x030E0000 0x030EFFFF TEMPSEN control register 64K
0x030F0000 0x030FFFFF SARADC control register 64K
ed
0x04000000 0x0400FFFF I2C0 control register 64K
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lo
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0x04060000 0x0406FFFF SPI_NAND control register 64K
e
0x04070000 0x0407FFFF ETH0 control register
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0x04080000 0x040FFFFF reserve n
0x04100000 0x04107FFF I2S0 control register 64K
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0x04108000 0x0410FFFF I2S Global control register 64K

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0x04110000 0x0411FFFF I2S1 control register 64K

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0x04140000 0x0414FFFF UART0 control register 64K

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0x04180000 0x0418FFFF SPI0 control register 64K
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0x04190000 0x0419FFFF SPI1 control register 64K

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0x041A0000 0x041AFFFF SPI2 control register 64K

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0x041B0000 0x041BFFFF SPI3 control register 64K

0x041C0000 0x041CFFFF UART4 control register 64K
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0x041D0000 0x041DFFFF AUDSRC control register 64K

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0x041E0000 0x042FFFFF reserve

0x04310000 0x0431FFFF SD0 control register 64K
0x04320000 0x0432FFFF SD1 control register
0x04330000 0x0433FFFF DMA control register 64K
0x04340000 0x0434FFFF USB control register 64K
0x04350000 0x043FFFFF reserve
0x04400000 0x0440FFFF ROM 内存空间 64K
0x04410000 0x04FFFFFF reserve
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CV1835
0x05000000 0x05000FFF reserve 4KB

0x05020000 0x05020FFF RTCSYS_Timer control register 4KB
0x05021000 0x05021FFF RTCSYS_GPIO control register 4KB
0x05022000 0x05022FFF RTCSYS_UART control register 4KB
0x05023000 0x05023FFF RTCSYS_INTR control register 4KB
0x05024000 0x05024FFF RTCSYS_MBOX control register 4KB
0x05025000 0x05025FFF RTCSYS_CTRL control register 4KB
ed
0x05026000 0x05026FFF RTCSYS_CORE 4KB
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0x05027000 0x05027FFF RTCSYS_IO control register 4KB
lo
0x05028000 0x05028FFF RTCSYS_OSC control register 4KB
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0x05029000 0x05029FFF reserve 4KB
0x0502A000 0x0502AFFF RTCSYS_32kless control register 4KB
t
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0x0502B000 0x0502BFFF RTCSYS_I2C control register 4KB
0x0502C000 0x0502CFFF RTCSYS_SAR control register 4KB
e
0x0502D000 0x0502DFFF RTCSYS_WDT control register 4KB
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0x0502E000 0x0502EFFF RTCSYS_IRRXcontrol register
n 4KB
0x05200000 0x053FFFFF RTCSYS_SRAM 8KB
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0x05400000 0x057FFFFF RTCSYS_SPINOR 4MB

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0x08004000 0x08005FFF DDR Controler control register 8K

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0x08008000 0x08009FFF DDR AXI Monitor control register 8K

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0x0800A000 0x0800BFFF DDR Global control register 8K

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0x08014000 0x09FFFFFF reserve
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0x0A000000 0x0A07FFFF ISP control register 512K

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0x0A080000 0x0A0803FF sc_top control register 1K

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0x0A080400 0x0A080BFF reserve 2K

0x0A080C00 0x0A080CFF osd enc control register 256B
od de
0x0A080D00 0x0A080FFF reserve 768B

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0x0A081000 0x0A081FFF reserve 4K

0x0A082000 0x0A082FFF img_v control register 4K
0x0A083000 0x0A083FFF img_d control register 4K
0x0A084000 0x0A084FFF sc_d control register 4K
0x0A085000 0x0A085FFF sc_v1 control register 4K
0x0A086000 0x0A086FFF sc_v2 control register 4K
32
CV1835
0x0A08A000 0x0A08AFFF reserve 4K

0x0A08B000 0x0A08BFFF cmdq control register 4K
0x0A08C000 0x0A08CFFF reserve 4K
0x0A08D000 0x0A08DFFF reserve 4K
0x0A08E000 0x0A09FFFF reserve 72K
0x0A0A0000 0x0A0AFFFF reserve 64K
0x0A0A0000 0x0A0BFFFF reserve 64K
ed
0x0A0C0000 0x0A0C1FFF ldc control register 8K
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0x0A0C2000 0x0A0C3FFF VI0/MIPI_RX0 control register 8K
lo
0x0A0C4000 0x0A0C5FFF reserve 8K
al
0x0A0C6000 0x0A0C7FFF reserve 8K
0x0A0C8000 0x0A0C9FFF VIPSYS control register 8K
t
no
0x0A0CA000 0x0A0CFFFF reserve 24K
0x0A0D0000 0x0A0D0FFF CSI_PHY control register 4K
e
0x0A0D1000 0x0A0D1FFF reserve 4K
ar
0x0A0D2000 0x0AFFFFFF reserve n
0x0B000000 0x0B00FFFF JPEG codec control register 64K
tio
0x0B010000 0x0B01FFFF H.264 codec control register 64K

u
0x0B020000 0x0B02FFFF H.265 codec control register 64K

ib
0x0B030000 0x0BFFFFFF reserve

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0x0C000000 0x0FFFFFFF reserve

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0x10000000 0x1FFFFFFF SPI_NOR 内存空间 256M

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0x20000000 0x7FFFFFFF reserve

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0x80000000 0xFFFFFFFF DDR 内存空间 2G

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* Performing read/write operations on the reserved address space may result in

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unpredictable results.
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CV1835
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34
CV1835
Hardware Characteristics
2.1 Package and Pin Distribution
ed
2.1.1 Package CV180ZB/CV1800B/CV1801B
w
lo
CV180ZB/CV1800B/CV1801B uses QFN package with a package size of
al
7mmx7mmx0.9mm. The pin pitch is 0.35mm and there are a total of 68 pins. For detailed
t
package dimensions, please refer to the figure below.
no
e
ar
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u tio
r ib
di V
st
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d il
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n by
Figure 2‑1 CV180ZB/CV1800B/CV1801B package dimensions, top view

tio lic
ca ub
ifi p
od de
M a
M
Figure 2‑2. CV180ZB/CV1800B/CV1801B package dimensions, bottom view

35
CV1835
2.1.2 Pin Distribution CV180ZB/CV1800B/CV1801B
ed
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t
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M
Table 2‑3 CV180ZB/CV1800B/CV1801B pin distribution
2.2 Pin information Description

Please refer to CV180xB_QFN68_PINOUT_CN.xlsx
36
CV1835
ed
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37
CV1835
2.3 Welding Process Suggestions

Please refer to Figure 2-4 for the lead-free reflow soldering process curve.
Please refer to Pure Sn
ed
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d il
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Figure 2‑4 Lead-free Reflow Soldering process curve

n by
tio lic
Please refer to Table 2-1 for the parameters of lead-free reflow soldering process.
ca ub
 The following parameters are only recommended values for reference. Clients need to
ifi p
make relative adjustments according to actual production conditions.

od de
Table2‑1 Lead-free reflow soldering process parameters

M a
M
Area Time Heating Peak temperature Cooling

Rate Rate
preheat zone 60~120sc 1~2oC/sec
(40~150oC)
soak 60~90sec < 1oC/sec
zone(150~200oC)
reflow zone 40~60sec 2~3oC/sec Sn/Ag/Cu 237~247oC
(>熔点 20~30oC) Sn/Cu 247~257oC
Pure Sn 252~262oC
38
CV1835
Area Time Heating Peak temperature Cooling

Rate Rate
cooling zone 1~4oC/sec
(Tmax ~ Tamb)
Due to environmental protection factors, the parameters for leaded reflow soldering are not
currently provided.
ed
w
lo
2.4 Moisture Sensitivity Parameters
al
t
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2.4.1 Moisture Barrier Packaging for CVITEK Products
e
ar
This section establishes the principles for the storage and use of chips (moisture sensitive
products) during welding. The relevant terms are as follows:
n
 Floor life: refers to the maximum allowable time between opening the moisture barrier
tio
packaging and reflow, in an environment with temperature < 30°C/60% RH.

 Shelf life: refers to the normal storage time after the moisture barrier packaging has
u
ib
been sealed.
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di V
st
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2.4.1.1 Package Information

d il
an M
The moisture-proof vacuum package includes (1) chips and tray, (2) desiccant packs, and (3)
n by
humidity indicator cards (HIC).

tio lic
ca ub
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M
Figure 2‑5 Vacuum drying packaging information
39
CV1835
ed
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t
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Figure 2‑6 Desiccant packs, humidity card, chip, and tray
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2.4.1.2 Moisture-sensitive Product Incoming Inspection

u
ib
After opening the vacuum moisture-proof bag before SMT, inspect the humidity card.
r
di V
There are many different styles of humidity cards, but if it shows that it has been exposed to
st
re k-
moisture, it must be baked before SMT use. The relevant time and temperature parameters
d il
for baking are shown in Table 2-3.

an M
If re-packaging after opening, and it has not been exposed for more than 2 hours in
an environment of <30°C/60% RH, it can be vacuum dried and packaged by only replacing
n by
the drying bag. If it exceeds 2 hours, it is recommended to re-bake, replace the drying bag,
tio lic
and then reseal the package.

ca ub
2.4.1.3 Storage and Use. (refer to JEDEC J-STD-033)

ifi p
od de
Shelf life:
The sealed vacuum moisture-proof bag can be stored for at least 12 months in an
M a
environment of 40°C/90% RH.

M
Floor life:
Before SMT, if the humidity card indicates that the components have not been
exposed to moisture after opening in an environment of 30°C/60% RH, it can be
used directly without baking. The time for Level 3 (the floor life classification of
this chip is Level 3) is shown in Table 2-2.
Table 2‑2 Humidity classification and floor life
40
CV1835
ed
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lo
al
2.4.1.4 Rebaking
t
no
If found to have been exposed to moisture after opening, before SMT or before being
resealed in vacuum packaging, they should be baked first. Baking temperature and time can
e
ar
be referred to in Table 2-3.
After baking, shelf life can be recalculated after being sealed in moisture-proof
n
packaging.
tio
If not sealed in moisture-proof packaging after baking, the storage time should refer
u
to the floor life.

r ib
di V
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Table 2‑3 Baking temperature and time table

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41
CV1835
2.5 Electrical Performance Parameters
2.5.1 Power Consumption Parameters
ed
Typical scenario: 1080P + Video Encode + AI ~500mW
w
Other scenarios: TBD
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al
2.5.2 Temperature and Thermal Resistance Parameters
t
no
(CV180ZB/CV1800B/CV1801B)
e
ar
Thermal resistance values ThetaJA, JB, JC of the chip. The results of the actual test
n
conducted on the JEDEC 2s2p PCB are shown in Table 2 and 4.
u tio
Table 2‑4 Thermal resistance parameters for CV180ZB/CV1800B/CV1801B

r ib
PCB Package Theta JA (C/W) Psi Jt Theta Theta JB

di V
st
re k-
Conditio Size(mm) 0 m/s 1 m/s 2 m/s (C/W) JC (C/W)

n (C/W)
d il
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JEDEC 7x7 24.9 19.5 18.3 0.2 9.60 6.61

2s2p PCB
n by
tio lic
ca ub
ifi p
Temperature-related parameters of the chip are shown in Table 2-5.

od de
Table 2‑5 Temperature-related parameters

M a
The minimum The maximum Note

M
working environment -30oC 70oC 1

temperature Tamb
the recommended value for -30oC 85oC ~ 105oC 2
junction temperature (Tjunc) of
the chip
the destructive junction -40oC +125oC 3, 4
temperature
1. The maximum operating temperature in the working environment depends on the

42
CV1835
power consumption and heat dissipation conditions of the scenario, without violating
the premise of junction temperature.
2. The recommended range of junction temperature is mainly considered to avoid thermal
runaway caused by poor heat dissipation conditions at high temperatures, which may
lead to uncontrolled temperature entering the destructive junction temperature range
and damaging the chip. In addition, long-term operation at high temperatures may
slightly accelerate chip aging and reduce its service life.
3. The DRAM used guarantees a junction temperature of only -40°C to 115°C. Content
ed
inside the DRAM cannot be guaranteed to remain intact beyond this range.
w
4. When the chip operates at the destructive junction temperature, it may cause
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irreversible physical damage to the chip.
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2.5.3 Destructive Voltage
t
no
Destructive voltage parameters are shown in Table 2-6. Working above the destructive
e
voltage may cause irreversible physical damage.
ar
n
Table 2‑6 Destructive voltage parameters (CV180ZB/CV1800B/CV1801B)
tio
Parameter Max Unit

u
VDDC Core power 1.05V V

ib
VDD18A_AUD Analog power for Audio ADC/DAC 1.98 V

r
di V
VDD18A_USB_PLL_ETH_CSI Analog power for USB, PLL, ETH, efuse , MIPI 1.98 V
st
re k-
VDD33A_ETH_USB_SD1 Analog power for Ethernet PHY, USB PHY, 3.465 V

IO power for SD1 domain
d il
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VDDIO_SD0_SPI IO power for SPI & SD0 domain 3.465 V

VDDIO_RTC IO power for RTC domain (backup power) 1.98 V
n by
VDDQ IO & DRAM Power for DDR2/DDR3L/DDR3 1.98 V

tio lic
ca ub
2.5.4 Power Sequencing(CV180ZB/CV1800B/CV1801B)

ifi p
In principle, the chip can be divided into the following groups. The power domains
od de
within the same group are powered on/off simultaneously. For different groups, the
M a
M
power on/off time is separated according to the following conditions.
Core power domain

VDDC
1.8V IO domain
VDD18A_AUD (analog)
VDD18A_USB_PLL_ETH_CSI (analog)
43
CV1835
18OD33 IO domain (1.8V domain or 3V domain depending on the voltage)

VDDIO_SD0_SPI (if SD0 need to be connected with SD Card, this must be 3V)
3V domain
VDD33A_ETH_USB_SD1
DR IO & DRAM domain
VDDQ
ed
w
In principle, 0.9V power domain and 1.8V power domain can be powered on at the
lo
same time, or power-on the 0.9V power domain prior to 1.8V power domain. However,
al
the 3V power domain must be powered on after the establishment of 1.8V power
t
no
domain. Violations may cause irreversible damage to the chip. The power-off sequence
is reverse of the power-on sequence.
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Possible risky power-up and power-down behaviors include:

ca ub
1. During power-up, if VDD3 > 2V while VDD18 has not reached 1.8V-10%, it may
ifi p
damage the 3V circuit.

od de
2. During power-down, if VDD3 is lower than 2V while VDD18 has already dropped
M a
below 1.8V-10%.
M
3. During power-up, if VDD18 > 0.7V while VDD09 is still below 0.5V, it may cause
efuse misoperation.
4. During power-down, if VDD09 is below 0.5V while VDD18 is still higher than 0.7V, it
may also cause efuse misoperation.
The chip provides two pins, PWR_SEQ1 and PWR_SEQ2, to co-control the power supply
(VDDIO_RTC domain) switch. SEQ1 is preset to 0.9V and 1.8V, while SEQ2 controls 3V.
44
CV1835
Some plug-in systems may use RC to determine the switch for both 0.9V and 1.8V, but it
is important that the chip's 3V still needs to be controlled by SEQ2 to prevent damage.
During power-up, SEQ1 —>SEQ2

During power-down, SEQ2 —>SEQ1.
ed
PWR_VBAT_DET is used to detect the status of the main power supply. If the voltage is
w
low, the software will receive an interrupt first (such as stopping writing flash to prevent
lo
damage to the file system). If the voltage continues to drop, the RTC module will
al
actively start the power-down program. PWR_VBAT_DET also needs to be logic high to
t
no
start up.
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45
CV1835
2.5.5 The DC/AC Electrical Parameters of the Power Supply
Table 2- 7 The power supply electrical parameters of CV180ZB/CV1800B/CV1801B

(Recommended Operating Conditions)
Parameter Min Typ Max Unit
VDDC Core power 0.81 0.9 0.99 V
ed
VDD18A_AUD Analog power for Audio ADC/DAC 1.62 1.8 1.98 V
w
VDD18A_USB_PLL_ETH_CSI Analog power for Ethernet PHY, USB PHY, PLL, 1.62 1.8 1.98 V
lo
Efuse, MIPI
al
VDD33A_ETH_USB_SD1 Analog power for Ethernet PHY, USB PHY, IO 2.97 3.3 3.465 V
t
power for SD1 domain
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V
VDDIO_SD0_SPI IO power for SD0 & SPI domain 1.71 1.8 1.89 V
e
2.85 3.0/3.3 3.15/3.465
ar
VDDIO_RTC IO power for RTC domain IO & LDO n 1.3V 1.8 +10% V
tio
VDDQ IO & DRAM Power for DDR3L 1.283 1.35 1.417 V
IO & DRAM Power for DDR3 1.425 1.50 1.575
u
IO & DRAM Power for DDR2 1.710 1.80 1.890

r ib
o
Tjunc Junction Temperature (Max reduce from 125C -40 25 115 C
di V
st
due to DRAM) (note)

re k-
d il
Note: The operating junction temperature of the DRAM used is guaranteed to be only between -
an M
40°C to 115°C. Contents inside the DRAM cannot be guaranteed to be intact beyond this
n by
temperature range.
tio lic
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46
CV1835
2.5.6 1.8V I/O Electrical Parameters
For domain (VDD18A_USB_PLL_ETH_CSI, VDDIO_RTC)
Table 2- 8 1.8V I/O Electrical Parameters

VIL Input Low voltage -0.3 0.35xVDDIO V
ed
VIH Input High voltage 0.65*VDDIO 1.98 V
VT (no Threshold voltage when ST[1:0] = 00 0.75 0.91 1.09 V
w
pull) (no schmit trigger) 0.74 0.90 1.08
lo
VT_PU 0.76 0.92 1.10
al
VT_PD
VT+ Threshold voltage when ST[1:0] = 01 0.82 0.97 1.13 V
t
VT- 0.72 0.85 1.02
no
VT+_PU 0.81 0.96 1.12
VT-_PU 0.71 0.84 1.01
e
VT+_PD 0.82 0.98 1.14
ar
VT-_PD 0.73 0.86 1.03
VT+ Threshold voltage when ST[1:0] = 1X 0.87 1.04 1.19 V
n
VT- 0.69 0.80 0.95
tio
VT+_PU 0.86 1.03 1.18

VT-_PU 0.68 0.79 0.94
u
VT+_PD 0.88 1.05 1.20

ib
VT-_PD 0.69 0.81 0.96

r
Il Input leakage (VI = 1.8V or 0V) +/-10u A

di V
st
re k-
IOZ Tri-state output leakage current (VO=1.8V +/-10u A

or 0V)
d il
RPU Pull up resistor 55k 79k 121k Ω

an M
RPD Pull down resistor 51k 87k 169k Ω

VOL Output low voltage 0.45 V
n by
VOH Output high voltage 1.35 V

IOL Low level output current @ VOL (max)
tio lic
DS[1:0] = 00 7.6 12.8 18.0 mA

ca ub
DS[1:0] = 01 15.2 25.3 35.5 mA

DS[1:0] = 10 22.6 37.4 52.2 mA
ifi p
DS[1:0] = 11 29.7 49 67.9 mA

IOH High level output current @ VOH (max)
od de
DS[1:0] = 00 4.8 10.8 18.9 mA

M a
DS[1:0] = 01 9.5 21.5 37.4 mA

M
DS[1:0] = 10 14.3 32.1 55.9 mA

DS[1:0] = 11 18.9 42.4 73.9 mA
2.5.7 18OD33 IO (VDDIO=1.8V) Electrical Parameters
For domain (VDDIO_SD0_SPI, VDDIO_SD1)
47
CV1835
Table 2- 9 18OD33 IO (VDDIO=1.8V) Electrical Parameters

VIL Input Low voltage -0.3 0.58 V
VIH Input High voltage 1.27 2.00 V
VT (no pull) Threshold voltage when ST = 0 0.91 0.97 1.03 V
VT_PU (no schmit trigger) 0.90 0.96 1.02
VT_PD 0.91 0.97 1.06
VT+ (no pull) Threshold voltage when ST = 1 1.03 1.07 1.12 V
VT- (no pull) 0.75 0.83 0.91
ed
VT+_PU 1.02 1.06 1.11
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VT-_PU 0.74 0.82 0.90
VT+_PD 1.03 1.08 1.13
lo
VT-_PD 0.75 0.83 0.92
al
IOZ Tri-state output leakage current (VO=1.8V or 0V) +/-10u A
t
no
e
ar
DS[2:0] = 000 4.9 7.8 11.1 mA
n
DS[2:0] = 001 7.4 11.7 16.4 mA
tio
DS[2:0] = 010 9.8 15.5 21.7 mA
DS[2:0] = 011 12.2 19.2 26.7 mA
u
DS[2:0] = 100 14.6 23.0 31.9 mA

ib
DS[2:0] = 101 17.0 26.6 36.8 mA

DS[2:0] = 110 19.4 30.2 41.6 mA
r
di V
st
DS[2:0] = 111 21.7 33.7 46.2 mA

re k-

DS[2:0] = 000 3.6 6.2 9.5 mA
d il
an M
DS[2:0] = 001 5.4 9.3 14.3 mA

DS[2:0] = 010 7.2 12.4 19.1 mA
DS[2:0] = 011 9.0 15.4 23.8 mA
n by
DS[2:0] = 100 10.8 18.5 28.5 mA

DS[2:0] = 101 12.6 21.6 33.1 mA
tio lic
DS[2:0] = 110 14.4 24.6 37.8 mA

DS[2:0] = 111 16.2 27.7 42.5 mA
ca ub
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M a
M
48
CV1835
2.5.8 18OD33 IO (VDDIO=3.0V) Electrical Parameters
For domain (VDDIO_SD0_SPI, VDDIO_SD1)
Table 2- 10 18OD33 IO (VDDIO=3.0V) Electrical Parameters

ed
VIL Input Low voltage -0.3 0.25*VDDIO V
w
VIH Input High voltage 0.625*VDDIO 3.3 V
VT (no pull) Threshold voltage when ST = 0 0.82 0.95 1.11 V
lo
VT_PU (no schmit trigger) 0.81 0.93 1.09
al
VT_PD 0.83 0.96 1.13
VT+ (no pull) Threshold voltage when ST = 1 1.00 1.10 1.23 V
t
VT- (no pull) 0.75 0.90 1.08
no
VT+_PU 1.00 1.09 1.21
VT-_PU 0.73 0.88 1.05
e
VT+_PD 1.01 1.11 1.25
ar
VT-_PD 0.75 0.91 1.09
Il Input leakage (VI = 3.0V or 0V) n +/-10u A
tio
u
VOL Output low voltage 0.125*VDDIO V

ib
VOH Output high voltage 0.75*VDDIO V

r

di V
st
DS[2:0] = 000 3.1 5.5 8.6 mA

re k-
DS[2:0] = 001 4.7 8.2 12.7 mA

d il
DS[2:0] = 010 6.2 10.8 16.9 mA

an M
DS[2:0] = 011 7.7 13.4 20.8 mA

DS[2:0] = 100 9.3 16.1 24.9 mA
n by
DS[2:0] = 101 10.8 18.7 28.8 mA

DS[2:0] = 110 12.3 21.2 32.6 mA
DS[2:0] = 111 13.8 23.7 36.3 mA
tio lic

DS[2:0] = 000 5.0 7.5 10.5 mA
ca ub
DS[2:0] = 001 7.5 11.2 15.7 mA

ifi p
DS[2:0] = 010 10.1 14.9 21.0 mA

DS[2:0] = 011 12.6 18.6 26.2 mA
od de
DS[2:0] = 100 15.1 22.3 31.4 mA

DS[2:0] = 101 17.6 26.0 36.5 mA
M a
DS[2:0] = 110 20.1 29.8 41.8 mA

M
DS[2:0] = 111 22.6 33.4 46.9 mA
49
CV1835
2.5.9 Audio GPIO Electrical Parameters
Table 2- 11 Audio GPIO Electrical Parameters

VIL Input Low voltage -0.3 0.55 V
VIH Input High voltage 1.2 1.98 V
VT+ Threshold voltage with schmitt trigger 0.8 0.95 1.1 V
ed
VT- 0.65 0.82 0.99
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lo
al
IOL Low level output current @ VOL (max) 4.9 9.9 18.4 mA
IOH High level output current @ VOH (max) 11.3 17.1 26.1 mA
t
no
e
2.5.10 ETH GPIO Electrical Parameters ar
n
tio
Table 2- 12 ETH GPIO Electrical Parameters

u
ib

r
VIL Input Low voltage -0.3 0.3*VDD18A V

di V
st
VIH Input High voltage 0.7*VDD18A 1.98 V

re k-
VT+ Threshold voltage with schmitt trigger 0.84 0.99 1.14 V

d il
VT- 0.66 0.83 1.01

an M
Il Input leakage (VI = 1.8V or 0V) +/-1.3u A

IOZ Tri-state output leakage current (VO=1.8V or 0V) +/-1.3u A
n by

VOH Output high voltage VDD18A-0.4 V
tio lic
IOL Low level output current @ VOL (max) DS=0 8.8 15.7 27.3 mA
Low level output current @ VOL (max) DS=1 10.2 17.8 30.5
ca ub
IOH High level output current @ VOH (max) DS=0 4.0 5.3 7.4 mA
High level output current @ VOH (max) DS=1 4.7 6.2 8.5
ifi p
od de
M a
2.5.11 MIPI Rx Electrical Parameters

M
The MIPI D-PHY High Speed(MIHS) Electrical Parameters are listed in Table 2- 12 and
Table 2- 13.
The MIPI D-PHY Low Power(MILP) Electrical Parameters are listed in Table 2- 14 and
Table 2- 15.
50
CV1835
Table 2- 12. MIPI D-PHY High Speed(MISH) DifferentialDC Electrical Parameters
ed
w
lo
al
t
no
Table 2- 13. MIPI D-PHY High Speed(MIHS) Differential AC Electrical Parameters
e
ar
n
u tio
r ib
di V
st
re k-
d il
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tio lic
ca ub
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M a
M
Table 2- 14 MIPI D-PHY Low Power(MILP) Differential DC Electrical Parameters
51
CV1835
Table 2- 15 MIPI D-PHY Low Power(MILP) Differential AC Electrical Parameters
ed
w
2.5.12 Sub-LVDS Electrical Parameters
lo
al
The electrical parameters are listed Table 2- 16 and Table 2- 17.
t
no
Table 2- 16 Sub-LVDS(SL) Differential DC Electrical Parameters
e
ar
n
u tio
ib
Table 2- 17 Sub-LVDS(SL) Differential AC Electrical Parameters

r
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
2.5.13 HiSPi Electrical Parameters

M a
M
HiSPi is divided into SLVS (HSSL) and HiVCM(HSHI).The electrical parameters are listed
in Table 2- 18 and Table 2- .
52
CV1835
Table 2- 18 HiSPi Differential DC Electrical Parameters
ed
Table 2- 20 HiSPi Differential AC Electrical Parameters
w
lo
al
t
no
e
2.5.14 SDIO Electrical Parameters ar
n
tio
Please refer to 2.5.7 and 2.5.8 for SD0/SD1.

u
r ib
di V
st
re k-
2.5.15 2.5.15 VI RAW/BT.656/BT.1120Electrical

d il
an M
Parameters(CV180ZB/CV1800B/CV1801B)
n by
Please refer to 2.5.7 and 2.5.8 according to the domain of IO.

tio lic
ca ub
2.5.16 AUDIO CODEC Electrical Parameters

ifi p
od de
M a
M
Table 2- 19 Audio CODEC Overall Index

Parameter Min Typ Max Unit Description
Analog Power 1.62 1.8 1.98 V
AVDD
VREF 1.4/1.8 V
*VDD
Table 2- 20 Audio DAC Electrical Parameters
53
CV1835

Full Output 1.55 Vpp Maximum output
Amplitude signal swing
Table 2- 21 Audio ADC Electrical Parameters

ed
Maximum Input 1.75 Vpp Maximum output
Amplitude signal swing
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lo
al
t
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e
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54
CV1835
2.6 Timing
2.6.1 SPI NOR Timing
ed
w
lo
al
t
no
e
ar
n
u tio
Figure 2- 7 SPI NOR Timing Diagram

r ib
di V
st
* IO input timing / IO output timing is IO timing of SPINOR_SDI、SPINOR_SDO、SPINOR_HOLD_X、SPINOR_WP_X

re k-
in 1 x I/O, 2 x I/O and 4x I/O modes.

d il
an M
n by
Table 2- 24 SPI_NOR Timing Requirements

Symbol Description Min Typ Max Unit
tio lic
Tcss Time of CS negative edge to 13.4 - - ns

ca ub
the first clock edge

ifi p
Tclk Clock Cycle 13.4 - - ns

Tsu Input Signal Setup Time 3.5 - - ns
od de
Thd Input Signal Hold Time 0 - - ns

M a
Tov Output Signal Delay - - 2.6 ns

M
TOX Output Signal Hold Time -1.5 - - ns
55
CV1835
2.6.2 SPI NAND Timing
ed
w
lo
al
t
no
e
Figure 2- 8 SPI NAND Input Timing Diagram
ar
n
utio
Table 2- 22 SPI NAND Input Timing Requirements

r ib
Parameter Symbol Min Typ Max Unit

di V
st
Clock Cycle Tck 10.66 170.56 ns

re k-
Data Input Setup Time Td_su 2.00 ns

d il
an M
Data Input Hold Time Td_hd 1.20 ns

n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 2- 9 SPI NAND Output Timing Diagram
56
CV1835
Table 2- 23 SPI NAND Output Timing Requirements

Parameter Symbol Min Typ Max Unit
Clock Cycle Tck 10.66 170.56 ns
Clock High Period Tck_h 5.33 85.28 ns
Clock Low Period Tck_l 5.33 85.28 ns
Output CS Setup Time Tcs_su 10.66 ns
Output CS Hold Time Tcs_hd 10.66 ns
ed
Clock LOW to Output Valid Tq_vld -1.00 2.00 ns
w
lo
al
t
no
e
ar
n
utio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
57
CV1835
2.6.3 VI Timing
The timing of VI is shown as the figure below.
ed
w
lo
al
Figure 2-10 VI Timing Diagram
t
no
Wherein, the VI timing parameters are listed in the table below.
e
ar
Table 2-27 VI Timing Requirements
Symbol Min Typ Max Unit
n
tio
VICLK clock cycle T 6.73 ns

VIDATA setup time Tsu 1.9 ns
u
ib
VIDATA hold time Thd 0.8 ns

r
di V
st
re k-
d il
an M
2.6.4 AIAO (I2S/PCM) Timing

n by
tio lic
The RX timing diagram of I2S and PCM modes for connecting with external Audio
ca ub
Codec is shown as below figure.

ifi p
od de
M a
M
58
CV1835
ed
w
lo
al
t
no
e
ar
n
tio
Figure 2-11 I2S & PCM Rx Timing Diagram

u
r ib
di V
st
re k-
The TX timing diagram of I2S and PCM modes is shown as below figure.
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
59
CV1835
Figure 2-12 I2S & PCM Tx Timing Diagram
The digital timing specifications are listed as below table.
Table 2-28 I2S / PCM Timing Requirements

Symbol Parameter Min Typ Max Unit
TBL BCLK low pulse width (master and slave modes) 40 - - ns
ed
TBH BCLK high pulse width (master and slave modes) 40 - - ns
TLS LRCK setup time to BCLK rising (slave mode) 10 - - ns
w
TLH LRCK hold time from BCLK rising (slave mode) 10 - - ns
TSS SDI setup time to BCLK rising (master and slave modes) 10 - - ns
lo
TSH SDI hold time from BCLK rising (master and slave modes) 10 - - ns
al
TTS BCLK falling to LRCK timing skew (master mode) 0 - 10 ns
TSOD SDO delay time from BCLK falling (master and slave modes) 0 - 10 ns
t
no
e
ar
2.6.5 I2C Timing n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
Figure 2- 7 I2C Timing Diagram

ifi p
od de
Table 2- 29 I2C Timing Requirements

M a
M
60
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ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
61
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2.6.6 SPI Timing
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
Figure 2- 8 SPI Timing Diagram

ca ub
Table 2- 24 SPI Timing Requirements

ifi p
Symbol Description Min Typ Max Unit

od de
Fclk SCK frequency - 46.8 MHz

M a
Tcss Time of CS negative edge to 21.4 - - ns

M
the first clock edge

Tclk Clock cycle 21.4 - - ns
Tsu Input setup time 9.5 - - ns
Thd Input hold time 0 - - ns
Tov Input delay - - 3 ns
TOX Output hold time -3 - - ns
62
CV1835
2.6.7 MIPI Rx Timing
The speed range of MIPI Rx is : 0.08Gbps≤Data Rate≤1.5Gbps
A. 0.08Gbps≤Data Rate≤1.5Gbps
The timing is shown as Figure 2-15, and the timing requirements are listed in Table 2-
ed
31.
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
Figure 2- 15 Timing Diagram of MIPI Rx Clock when

tio lic
0.08gbps ≤ Data Rate ≤ 1.5gbps

ca ub
ifi p
od de
M a
M
Table 2- 31 Timing parameters of MIPI Rx at 0.08Gbps ≤ Data Rate ≤ 1.5Gbps
63
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
64
CV1835
2.6.8 Sub-LVDS Timing
The Sub-LVDS clock data timing diagram is shown in the figure below, and the timing
requirements are listed in Table 2-32.
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
Figure 2- 16. Sub-LVDS Data Rate Timing Diagram

an M
Table 2- 32. Sub-LVDS Timing Requirements

n by
tio lic
ca ub
ifi p
od de
M a
M
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CV1835
2.6.9 HiSPi Timing
The HiSPi clock data timing diagram is shown in the figure below, and the timing
requirements are listed in Table 2-33.
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
Figure 2- 17. HiSPi Clock Data Timing Diagram

n by
tio lic
Table 2- 33. HiSPi Timing Requirements

ca ub
ifi p
od de
M a
M
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CV1835
2.6.10 SDIO/MMC Timing
The data input and output timing of single edge is shown in Figure 2-18.
ed
w
lo
al
t
no
e
ar
n
u tio
ib
Figure 2- 18 SDIO / MMC Single Edge (SDR) Data Input/ Output Timing Diagram
r
di V
st
re k-
d il
an M
n by
Table 2- 34 SDIO / MMC Single Edge Defalut Speed (DS) Mode Timing Requirements
tio lic
Parameter Symbol Min Typ Max Unit Note

Clock CLK
ca ub
Clock frequency Data fPP 0 - 26 MHz fpp=1/tpp

ifi p
transfer Mode CL≤30pF

od de
Clock frequenyc fOD 0 - 400 KHz CL≤30pF

Idenfification Mode
M a
M
Clock high time tWH 10 - - ns CL≤30pF

Clock low time tWL 10 - - ns CL≤30pF
Clock rise time tTLH - - 10 ns CL≤30pF
Clock fall time tTHL - - 10 ns CL≤30pF
Inputs CMD, DAT ( referenced to CLK)
Input set-up time tISU 6 - - ns CL≤30pF
Input hold time tIH 8.3 - - ns CL≤30pF
Outputs CMD, DAT ( referenced to CLK)
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Output set-up time tOSU 5 - - ns CL≤30pF
Output hold time tOH 5 - - ns CL≤30pF
Table 2- 35 SDIO/MMC Single Edge High speed (HS) Mode Timing Requirements
ed
w
Clock CLK
lo
Clock frequency Data fpp 0 - 52 MHz fpp=1/tpp
al
transfer Mode CL≤30pF
t
Clock high time tWH 6.5 - - ns CL≤30pF
no
Clock low time tWL 6.5 - - ns CL≤30pF
e
Clock rise time tTLH - - 3 ns CL≤30pF
Clock fall time tTHL - - 3
ar ns CL≤30pF
n
Inputs CMD, DAT ( referenced to CLK)
tio
Input set-up time tISU 6 - - ns CL≤30pF

u
Input hold time tIH 2.5 - - ns

ib
CL≤30pF
r
Outputs CMD, DAT ( referenced to CLK)

di V
st
Output set-up time tOSU 6 - - ns

re k-
CL≤30pF
d il
Output hold time tOH 3 - - ns CL≤30pF

an M
n by
The timing of double edge data input/output is shown as the figure below.
tio lic
ca ub
ifi p
od de
M a
M
68
CV1835
ed
w
lo
al
t
no
e
ar
n
tio
Figure 2- 19 SDIO / MMC Double Edge DDR50 Mode Data Input/ Output Timing
Diagram
u
ib
Table 2- 36 SDIO/MMC Double Edge e DDR50 Mode Timing Requirements

r
di V
st
re k-

d il
Clock CLK
an M
Clock frequency Data fP 0 - 52 MHz fpp=1/tpp

transfer Mode
n by
CL≤30pF
Inputs DAT ( referenced to CLK)
tio lic
Input delay time during tIDLYddr 1.5 - 7 ns CL≤20pF

data transfer
ca ub
Outputs DAT ( referenced to CLK)

ifi p
Output set-up time tOSU 3 - - ns CL≤20pF

od de
Output hold time tOH 2.5 - - ns CL≤20pF

M a
M
The timing diagram of HS200 and SDR104 data input/output is shown as the figure
below.
69
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
Figure 2- 20 SDIO/MMC HS200 and SDR104 Mode Data Command Input/Output

ib
Timing Diagram
r
di V
st
re k-
Table 2- 37 SDIO/MMC HS200 and SDR104 Mode Output Parameters

d il

an M
Output set-up time tOSU 1.4 - - ns C DEVICE ≤6pF

n by
Output hold time tOH 0.8 - - ns

tio lic
Table 2- 38 SDIO/MMC HS200 and SDR104 Mode Input Parameters

ca ub

ifi p
od de
Phase difference between device TX tPH 0 - 2 UI Unit Interval (UI) is one bit
M a
CMD/DAT and RX CLK nominal time. For 200Mhz,

UI=5ns
M
Input valid data window tVW 0.575 - - UI TVW=2.88ns at 200MHz
70
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
71
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System
3.1 Reset
ed
3.1.1 Overview
w
lo
The reset management module manages the reset sequence of the whole chip、
al
subsystem and functional modules.
t
no
3.1.2 Reset Control
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
Figure 3- 1 Reset Management Module Block Diagram

ca ub
ifi p
3.1.2.1 Power on Reset

od de
M a
Power on reset (POR) is generated by the real-time clock(RTC) module. Refer to section
M
3.9 real time clock for details.
3.1.2.2 System Hard Reset
The system hard reset is generated by Reset Ctrl Level 2, which is used to reset all
subsystems and functional modules of the chip. The reset sources are from:
 Power on reset
 Watchdog reset
72
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 Overheating protection reset

 External reset pin (RSTN)
- Built in debounce circuit, the effective signal of high and low level of RSTN
must reach 6.56ms.
3.1.2.3 Soft Reset
ed
Soft reset control is triggered by configuring the corresponding reset configuration
w
register (Reset CRG). It is realized in Reset Ctrl Level 3. It includes -
lo
al
 System soft reset: reset the whole chip, except for a few circuits and
RTC internal circuits
t
no
 Reset of processor subsystem: reset the processor and processor subsystem
Function subsystem reset: reset each function subsystem and function module
e

ar
 Function module reset: reset each function module
n
tio
3.1.2.4 Soft Reset of Processor Subsystem

u
ib
SOFT_AC_RSTN_0 is used to generate reset to the processor and subsystem. After the
r
configuration register is written to 0, the reset controller will wait for 24us delay before
di V
st
re k-
triggering the corresponding processor reset. During this period, the processor should
d il
an M
stop accessing the bus to avoid the bus hanging after reset. After triggering reset, the
corresponding reset signal will be automatically released after 8us, and the processor
n by
and processor subsystem will complete the reset and start up.
tio lic
3.1.2.5 Soft Reset of Function Subsystem and Function Module

ca ub
ifi p
SOFT_RSTN_0~3 are used to generate reset to each function module. The reset signal
od de
will not be cleared automatically. Therefore, after the software configures the
M a
corresponding register as 0 to trigger the reset, it also needs to be configured as 1 to

M
release the reset. Before reset, make sure that the built-in DMA access to the bus and
processor access to the module are idle. Otherwise, the reset will fail and cause system
hang up.
73
CV1835
3.1.3 Reset Configuration Register
3.1.3.1 Overview of Reset Configuration Register
Base address 0x03003000

Name Address Description
Offset
ed
SOFT_RSTN_0 0x000 soft-reset ctrl register 0
w
lo
SOFT_RSTN_3 0x00c soft-reset ctrl register 3
al
SOFT_CPUAC_RSTN 0x020 CPU auto clear soft-reset ctrl register
SOFT_CPU_RSTN 0x024 CPU soft-reset ctrl register
t
no
e
3.1.3.2 Description of Reset Configuration Register
ar
n
tio
SOFT_RSTN_0
u
Offset Address: 0x000

ib
Bits Name Access Description Reset

r
di V
1:0 Reserved
st
re k-
2 reg_soft_reset_x_ddr R/W DDR system software reset 0x1

(active low)
d il
an M
3 reg_soft_reset_x_h264c R/W H264 IP software reset (active 0x1

low)
n by
4 reg_soft_reset_x_jpeg R/W JPEG IP software reset (active 0x1

low)
5 reg_soft_reset_x_h265c R/W H265 IP software reset (active 0x1
tio lic
low)
ca ub
6 reg_soft_reset_x_vipsys R/W VIP system software reset 0x1

(active low)
ifi p
7 reg_soft_reset_x_tdma R/W TPU_DMA IP software reset 0x1

(active low)
od de
8 reg_soft_reset_x_tpu R/W TPU IP software reset (active 0x1

M a
low)
M
9 reg_soft_reset_x_tpusys R/W TPU system software reset 0x1

(active low)
10 Reserved
11 reg_soft_reset_x_usb R/W USB IP software reset (active 0x1
low)
12 reg_soft_reset_x_eth0 R/W ETH0 IP software reset (active 0x1
low)
13 Reserved R/W 0x1
14 reg_soft_reset_x_nand R/W NAND IP software reset (active 0x1
low)
15 Reserved R/W 0x1
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CV1835

16 reg_soft_reset_x_sd0 R/W SD0 IP software reset (active 0x1
low)
17 Reserved
18 reg_soft_reset_x_sdma R/W SDMA IP software reset (active 0x1
low)
19 reg_soft_reset_x_i2s0 R/W I2S0 IP software reset (active 0x1
low)
ed
low)
w
low)
lo
al
low)
23 reg_soft_reset_x_uart0 R/W UART0 IP software reset (active 0x1
t
low)
no
low)
e
ar
low)
26 reg_soft_reset_x_uart3 R/W UART3 IP software reset (active
n 0x1
low)
tio
27 reg_soft_reset_x_i2c0 R/W I2C0 IP software reset (active 0x1
low)
u

ib
low)
r

di V
st
low)
re k-

d il
low)
an M

low)
n by
SOFT_RSTN_1
tio lic

ca ub
0 reg_soft_reset_x_pwm0 R/W PWM0 IP software reset (active 0x1

ifi p
low)
od de
low)
M a
M
low)
low)
7:4 Reserved
8 reg_soft_reset_x_spi0 R/W SPI0 IP software reset (active 0x1
low)
low)
low)
low)
75
CV1835

12 reg_soft_reset_x_gpio0 R/W GPIO0 IP software reset (active 0x1
low)
low)
low)
15 reg_soft_reset_x_efuse R/W EFUSE IP software reset (active 0x1
low)
ed
16 reg_soft_reset_x_wdt R/W WDT0 IP software reset (active 0x1
low)
w
17 reg_soft_reset_x_ahb_rom R/W ROM IP software reset (active 0x1
lo
low)
18 reg_soft_reset_x_spic R/W SPIC IP software reset (active 0x1
al
low)
t
19 reg_soft_reset_x_tempsen R/W TEMPSEN IP software reset 0x1
no
(active low)
20 reg_soft_reset_x_saradc R/W SARADC IP software reset (active 0x1
low)
e
ar
25:21 Reserved
26 reg_soft_reset_x_combo_phy0 R/W USB_PHY IP software reset
n 0x1
(active low)
tio
28:27 Reserved
29 reg_soft_reset_x_spi_nand R/W NAND IP software reset (active 0x1
u
low)
ib
30 reg_soft_reset_x_se R/W SE IP software reset (active 0x1

r
low)
di V
st
re k-
31 Reserved
d il
SOFT_RSTN_2
an M

n by

9:0 Reserved
tio lic

low)
ca ub

low)
ifi p
12 reg_soft_reset_x_system R/W SYSTEM software reset (active 0x1

od de
low)
13 reg_soft_reset_x_timer R/W TIMER IP software reset (active 0x1
M a
low)
M
14 reg_soft_reset_x_timer0 R/W TIMER0 IP software reset (active 0x1

low)
low)
low)
low)
low)
low)
76
CV1835

low)
low)
22 reg_soft_reset_x_wgn0 R/W WGN0 IP software reset (active 0x1
low)
low)
ed
low)
w
25 reg_soft_reset_x_keyscan R/W KEYSCAN IP software reset 0x1
lo
(active low)
26 Reserved
al
27 reg_soft_reset_x_auddac R/W AUDDAC IP software reset (active 0x1
t
low)
no
28 reg_soft_reset_x_auddac_apb R/W AUDDAC APB software reset 0x1
(active low)
e
29 reg_soft_reset_x_audadc R/W AUDADC IP software reset (active 0x1
ar
low)
30 Reserved n
31 reg_soft_reset_x_vcsys R/W VCSYS SYS software reset (active 0x1
tio
low)
u
SOFT_RSTN_3
ib
Offset Address: 0x00c

r
di V

st
re k-
0 reg_soft_reset_x_ethphy R/W ETHPHY IP software reset (active 0x1

low)
d il
an M
1 reg_soft_reset_x_ethphy_apb R/W ETHPHY APB REG software reset 0x1

(active low)
n by
2 reg_soft_reset_x_audsrc R/W AUDSRC IP software reset (active 0x1

low)
3 reg_soft_reset_x_vip_cam0 R/W VIP CAM0 IP software reset 0x1
tio lic
(active low)
ca ub
4 reg_soft_reset_x_wdt1 R/W WDT1 IP software reset (active 0x1

low)
ifi p
5 reg_soft_reset_x_wdt2 R/W WDT2 IP software reset (active 0x1

low)
od de
31:6 Reserved
M a
M
SOFT_CPUAC_RSTN
Write Lock: SOFT_CPUAC_RSTN_wr_lock
0 reg_auto_clear_reset_x_cpucor R/W CPUCORE0 auto_clear_reset 0x1
e0 (active low)
e1 (active low)
e2 (active low)
e3 (active low)
77
CV1835

4 reg_auto_clear_reset_x_cpusys R/W CPUSYS0 auto_clear_reset (active 0x1
0 low)
1 low)
2 low)
31:7 Reserved
ed
SOFT_CPU_RSTN
w
lo
0 reg_soft_reset_x_cpucore0 R/W CPUCORE0 soft reset (active low) 0x0
al
t
no
4 reg_soft_reset_x_cpusys0 R/W CPUSYS0 soft reset (active low) 0x0
e
ar
31:7 Reserved n
tio
3.2 Clock
u
r ib
di V
st
re k-
3.2.1 Overview
d il
an M
The clock management module manages the chip clock. It includes –

n by
 Management and control of clock input

 PLL clock source and related frequency multiply and division configuration
tio lic
 Clock frequency division and control

ca ub
 Generate clock for each module

ifi p
 Management and control for each clock

od de
M a
M
78
CV1835
3.2.2 Function Block Diagram
ed
w
lo
al
t
no
e
ar
n
u tio
Figure 3- 2 Clock Management Block Diagram

r ib
di V
st
re k-
XTAL_ XIN is reference clock of PLL and should be connected with 25MHz crystal. RTC_
d il
XIN is the reference clock of RTC and should be connected with 32.768KHz crystal.
an M
n by
3.2.3 Clock Resource and Frequency Division Structure

tio lic
The system clock mainly comes from external XTAL、PLLs and external input clocks. As
ca ub
shown in Figure 3-3, each IP generally has clock source from XTAL or PLLs. After passing
ifi p
through the frequency division circuit, clocks are generated and selected to be the clock
od de
of IPs or subsystems.
M a
M
79
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
Figure 3- 3 Clock Source Frequency Division Diagram

an M
n by
3.2.4 PLL Configuration

tio lic
As shown in Table 3-1, the chip has built-in 9 PLLs (excluding Analog IP built-in PLL),
ca ub
which are categorized into integer frequency multiplication and fractional frequency
ifi p
multiplication.
od de
Table 3- 1 PLL Configuration Parameters

M a
M
PLL 配置寄存器下电控制寄存器预设频率 PLL 型态

FPLL fpll_csr fpll_pwd (default On) 1500MHz 整数倍频
MIPIMPLL mipimpll_csr mipimpll_pwd (default On) 900MHz 整数倍频
MPLL mpll_csr mpll_pwd (default On) 1000MHz 整/分数倍频

mpll_ssc_syn_ctrl
mpll_ssc_syn_set
mpll_ssc_syn_span
mpll_ssc_syn_setp
TPLL tpll_csr tpll_pwd (default On) 1400MHz 整/分数倍频
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CV1835
PLL 配置寄存器下电控制寄存器预设频率 PLL 型态

tpll_ssc_syn_ctrl
tpll_ssc_syn_set
tpll_ssc_syn_span
tpll_ssc_syn_setp
APLL apll_csr apll_pwd(default On) 1050MHz 整/分数倍频
apll_ssc_syn_ctrl
ed
apll_ssc_syn_set
w
apll_ssc_syn_span
apll_ssc_syn_setp
lo
al
CAM0PLL cam0pll_csr cam0pll_pwd(default On) 1050MHz 整/分数倍频
cam0pll_ssc_syn_ctrl
t
no
cam0pll_ssc_syn_set
cam0pll_ssc_syn_span
e
cam0pll_ssc_syn_setp
ar
CAM1PLL cam1pll_csr cam1pll_pwd(default On)n 1025MHz 整/分数倍频
tio
cam1pll_ssc_syn_set
cam1pll_ssc_syn_span
u
ib
cam1pll_ssc_syn_setp
r
DISPPLL disppll_csr disppll_pwd(default On) 1200MHz 整/分数倍频

di V
st
re k-
disppll_ssc_syn_ctrl
d il
disppll_ssc_syn_set
an M
disppll_ssc_syn_span
disppll_ssc_syn_setp
n by
tio lic
3.2.4.1 Integer Frequency Multiplication PLL

ca ub
The process of integer PLL adjustment is as follows.

ifi p
1. Turn off clocks generated from this PLL or select others stable clock to be the
od de
clocks’ source.
M a
2. Configure*_pll_CSR register, configured according to integer PLL parameter table

M
3. Clear *_pll_pwd
Table 3- 2 Interger PLL Configuration Parameters
PLL 参数范围注意事项
PLL_REF 25MHz~2500MHz
PLL_VCO 800MHz~2500MHz
Pre_div_sel 1~127 PLL_VCO = PLL_REF*Div_sel/Pre_div_sel
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CV1835
Div_sel 6~127 PLL_FOUT = PLL_VCO/Post_div_sel

Post_div_sel 1~127
Ictrl 0~7 0.2< 1.84*(1+Mode)*(1+Ictrl)/2/Div_sel <=0.35
Mode 0~3
ed
3.2.4.2 Fractional Frequency Multiplication PLL
w
lo
The process of fractional PLL adjustment is as follows.
al
1. Turn off clocks generated from this PLL or select others stable clock to be the
t
clocks’ source.
no
2. Configure *_ssc_syn_src_en to enable the synthesizer clock
e
3. Configure *_ssc_syn_set according to PLL frequency requirement
ar
4. Toggle *_ssc_syn_up to make the configuration take effect
n
5. Configure *_ pll_csr register, configured according to integer PLL parameter table
tio
6. Clear *_pll_pwd
u
r ib
di V
st
Table 3- 3 Fractional PLL Configuration Parameters

re k-
d il
an M
ssc_freq_in DSIPLL: 1.2GHz Default clock gated , need enable

n by
DDRPLL: 1.5GHz
Others 600MHz
tio lic
ssc_syn_set > 4.x * 2^26 ssc_freq_in*div_sel*2^26/PLL_VCO

ca ub
PLL_REF 100M~2500MHz
ifi p
PLL_VCO 800MHz~2500MHz
od de
Div_sel 6~127 PLL_VCO = PLL_REF*div_sel

M a
Post_div_sel 1~127 FOUT = PLL_VCO/Post_div_sel

M
Ictrl 0~7 0.1< 1.84*(1+Mode)*(1+Ictrl)/2/Div_sel

Mode 0~3 <=0.24
3.2.5 CLK_DIV Clock Frequency Division Configuration
Below is the clock resource table. This table indicates the configurable clock source,
preset clock frequency and frequency division of each clock. The software can switch
82
CV1835
the clock source from XTAL to PLL after boot, and adjust the clock frequency division
configuration.
Table 3- 4 Clock Source and Preset Frequency Division Parameters
PLL DIV_IN0 DIV_IN1

CLK_NAME XTAL DIV SW
SRC/DIV/FREQ SRC SRC
ed
clk_cpu_axi0 Y Y fpll/(3)/500M fpll disppll
clk_cpu_gic Y Y fpll/(5)/300M fpll
w
lo
clk_tpu Y Y fpll/(3)/500M tpll a0pll mipimpll fpll
al
clk_sd0 Y Y fpll/(15)/100M fpll disppll
clk_sd1 Y Y fpll/(15)/100M fpll disppll
t
no
clk_spi_nand Y Y fpll/(8)/187.5M fpll disppll
clk_sdma_aud0 Y Y a0pll/(18)/58.3M a0pll a24m
e
ar

n
tio
clk_pwm Y Y fpll/(10)/150M fpll disppll

u
ib
clk_uart Y Y xtal/(1)/25M xtal disppll

r
clk_axi4 Y Y fpll/(5)/300M fpll disppll

di V
st
re k-
clk_axi6 Y Y fpll/(15)/100M fpll

d il
clk_axi_vip Y Y fpll/(6)/250M mipimpll cam0pll disppll fpll

an M
clk_src_vip_sys_0 Y Y fpll/(6)/250M mipimpll cam0pll disppll fpll

n by
clk_src_vip_sys_1 Y Y fpll/(5)/300M mipimpll cam0pll disppll fpll
clk_axi_video_codec Y Y mipimpll/(2)/450M a0pll mipimpll cam1pll fpll

tio lic
clk_vc_src0 Y Y mipimpll/(2)/450M disppll mipimpll cam1pll fpll

ca ub
clk_spi Y Y fpll/(8)/187.5M fpll

ifi p
clk_i2c Y Y clk_axi6/(1)/100M clk_axi6

od de
clk_src_vip_sys_2 Y Y disppll/(2)/600M mipimpll cam0pll disppll fpll

M a
clk_audsrc Y Y a0pll/(18)/58.3M a0pll a24m

M
clk_ap_debug Y Y fpll/(5)/300M fpll
clk_src_rtc_sys_0 Y Y fpll/(5)/300M fpll
clk_c906_0 Y Y Y fpll/(2)/750M tpll a0pll mipimpll mpll fpll
clk_c906_1 Y Y Y fpll/(3)/500M tpll a0pll disppll mpll fpll
clk_src_vip_sys_3 Y Y mipimpll/(2)/450M mipimpll cam0pll disppll fpll
clk_src_vip_sys_4 Y Y disppll/(3)/400M mipimpll cam0pll disppll fpll
83
CV1835
3.2.5.1 IP/SYS Source and Clock Frequency Division Configuration
1. Turn off the IP clock. If the clock cannot be turned off, it should be configured to the
stable clock first.
A、CPU frequency scaling: Configure clk_sel_0 to switch to SRC1 to avoid too low
frequency.
ed
B、IP frequency scaling: configure clk_byp_0/1 to switch the clock to XTAL.
w
2. Configure the clock source and frequency divider to be adjusted.
lo
3. Configure bit[2] of frequency divider register, and then the clock divider
al
configuration can take effect.
t
4. Select the clock source to the configured clock divider.
no
3.2.5.2 MCLK0/MCLK1
e
1. MCLK0/MCLK1 provide external sensor reference clock.
ar
n
2. Configure CAM0PLL, clk_cam0_src_div, and clk_cam0_src_div to provide the appropriate
tio
MCLK0/MCLK1 output frequency.

u
ib
3.2.5.3 Clk_A24M
r
di V
st
re k-
1. clk_a24m can be used as the audio clock when performance is acceptable.

d il
2. Configure apll_frac_div_ctrl, apll_frac_div_m, and apll_frac_div_n to generate the

an M
required audio clock source.

3. The frequency of clk_a24m is 900MHz * N/M/2.
n by
tio lic
3.2.6 PLL CRG Register Overview

ca ub
ifi p
PLL_G2 base address : 0x03002800

od de
M a

M
Offset
pll_g2_ctrl 0x000 Group2 PLL Ctrl register
pll_g2_status 0x004 Group2 PLL Status register
mipimpll_csr 0x008 MIPIMPLL Ctrl register
apll0_csr 0x00c APLL0 Ctrl register
disppll_csr 0x010 DISPPLL Ctrl register
cam0pll_csr 0x014 CAM0PLL Ctrl register
cam1pll_csr 0x018 CAM1PLL Ctrl register
pll_g2_ssc_syn_ctrl 0x040 Group2 PLL Synthesizer ctrl register
apll_ssc_syn_ctrl 0x050 APLL synthesizer ctrl register
apll_ssc_syn_set 0x054 APLL synthesizer set register
84
CV1835

Offset
disppll_ssc_syn_ctrl 0x060 DISPPLL synthesizer ctrl register
disppll_ssc_syn_set 0x064 DISPPLL synthesizer set register
cam0pll_ssc_syn_ctrl 0x070 CAM0PLL synthesizer ctrl register
cam0pll_ssc_syn_set 0x074 CAM0PLL synthesizer set register
cam1pll_ssc_syn_ctrl 0x080 CAM1PLL synthesizer ctrl register
cam1pll_ssc_syn_set 0x084 CAM1PLL synthesizer set register
apll_frac_div_ctrl 0x090 APLL frac divider ctrl register
ed
apll_frac_div_m 0x094 APLL frac divider M parameter
apll_frac_div_n 0x098 APLL frac divider N parameter
w
mipimpll_clk_csr 0x0a0 MIPIMPLL clock Ctrl register
lo
a0pll_clk_csr 0x0a4 a0pll clock Ctrl register
al
disppll_clk_csr 0x0a8 disppll clock Ctrl register
cam0pll_clk_csr 0x0ac cam0pll clock Ctrl register
t
cam1pll_clk_csr 0x0b0 cam1pll clock Ctrl register
no
clk_cam0_src_div 0x0c0 clk_cam0_src_div
clk_cam1_src_div 0x0c4 clk_cam1_src_div
e
ar
PLL_G6 base address : 0x03002900 n
tio
Offset
u
pll_g6_ctrl 0x000 Group6 PLL Ctrl register

ib
pll_g6_status 0x004 Group6 PLL Status register

r
mpll_csr 0x008 MPLL Ctrl register

di V
st
tpll_csr 0x00c TPLL Ctrl register

re k-
fpll_csr 0x010 FPLL Ctrl register

d il
pll_g6_ssc_syn_ctrl 0x040 Group6 PLL Synthesizer ctrl register

an M
dpll_ssc_syn_ctrl 0x050 dpll synthesizer ctrl register

dpll_ssc_syn_set 0x054 dpll synthesizer set register
n by
dpll_ssc_syn_span 0x058 dpll synthesizer span register

dpll_ssc_syn_step 0x05c dpll synthesizer step register
tio lic
mpll_ssc_syn_ctrl 0x060 mpll synthesizer ctrl register

mpll_ssc_syn_set 0x064 mpll synthesizer set register
ca ub
mpll_ssc_syn_span 0x068 mpll synthesizer span register

ifi p
mpll_ssc_syn_step 0x06c mpll synthesizer step register

tpll_ssc_syn_ctrl 0x070 tpll synthesizer ctrl register
od de
tpll_ssc_syn_set 0x074 tpll synthesizer set register

tpll_ssc_syn_span 0x078 tpll synthesizer span register
M a
M
tpll_ssc_syn_step 0x07c tpll synthesizer step register
85
CV1835
3.2.7 PLL CRG Register Overview
3.2.7.1 PLL_G2 Register Overview
pll_g2_ctrl
ed
w
lo
0 mipimpll_pwd R/W pll power down 0x0
3:1 Reserved
al
4 apll0_pwd R/W pll power down 0x0
t
7:5 Reserved
no
8 disppll_pwd R/W pll power down 0x0
11:9 Reserved
e
12 cam0pll_pwd R/W pll power down 0x0
ar
15:13 Reserved
16 cam1pll_pwd R/W pll power down 0x0
n
tio
31:17 Reserved
u
pll_g2_status
ib

r

di V
st
0 updating_mipimpll_val RO pll setting update status

re k-
1 updating_apll0_val RO pll setting update status

d il
an M
2 updating_disppll_val RO pll setting update status

3 updating_cam0pll_val RO pll setting update status
n by
4 updating_cam1pll_val RO pll setting update status

15:5 Reserved
tio lic
16 mipimpll_lock RO pll lock status

ca ub
17 apll0_lock RO pll lock status

18 disppll_lock RO pll lock status
ifi p
19 cam0pll_lock RO pll lock status

od de
20 cam1pll_lock RO pll lock status

M a
31:21 Reserved
M
mipimpll_csr
6:0 mipimpll_pre_div_sel R/W pll pre_div_sel setting 0x0
7 Reserved
14:8 mipimpll_post_div_sel R/W pll post_div_sel setting 0x0
16:15 mipimpll_sel_mode R/W pll mode setting 0x0
23:17 mipimpll_div_sel R/W pll div_sel setting 0x0
26:24 mipimpll_ictrl R/W pll ictrl setting 0x0
31:27 Reserved
86
CV1835
apll0_csr
6:0 apll0_pre_div_sel R/W pll pre_div_sel setting 0x0
7 Reserved
14:8 apll0_post_div_sel R/W pll post_div_sel setting 0x0
16:15 apll0_sel_mode R/W pll mode setting 0x0
23:17 apll0_div_sel R/W pll div_sel setting 0x0
26:24 apll0_ictrl R/W pll ictrl setting 0x0
ed
31:27 Reserved
w
disppll_csr
lo
al
t
6:0 disppll_pre_div_sel R/W pll pre_div_sel setting 0x0
no
7 Reserved
14:8 disppll_post_div_sel R/W pll post_div_sel setting 0x0
e
16:15 disppll_sel_mode R/W pll mode setting 0x0
ar
23:17 disppll_div_sel R/W pll div_sel setting 0x0
26:24 disppll_ictrl R/W pll ictrl setting 0x0
n
31:27 Reserved
tio
cam0pll_csr
u

ib

r
di V
st
6:0 cam0pll_pre_div_sel R/W pll pre_div_sel setting 0x0

re k-
7 Reserved
d il
14:8 cam0pll_post_div_sel R/W pll post_div_sel setting 0x0

an M
16:15 cam0pll_sel_mode R/W pll mode setting 0x0

23:17 cam0pll_div_sel R/W pll div_sel setting 0x0
n by
26:24 cam0pll_ictrl R/W pll ictrl setting 0x0

31:27 Reserved
tio lic
cam1pll_csr
ca ub

ifi p

6:0 cam1pll_pre_div_sel R/W pll pre_div_sel setting 0x0
od de
7 Reserved
M a
14:8 cam1pll_post_div_sel R/W pll post_div_sel setting 0x0

M
16:15 cam1pll_sel_mode R/W pll mode setting 0x0

23:17 cam1pll_div_sel R/W pll div_sel setting 0x0
26:24 cam1pll_ictrl R/W pll ictrl setting 0x0
31:27 Reserved
pll_g2_ssc_syn_ctrl
0 reg_mipimpll_sel_syn_clk R/W mipimpll gen synthesizer clock 0x1
source
0:450M
87
CV1835

1:900M
1 reg_dsi_ssc_syn_src_en R/W pll synthesizer clock enable 0x0
2 reg_apll_ssc_syn_src_en R/W pll synthesizer clock enable 0x0
3 reg_disppll_ssc_syn_src_en R/W pll synthesizer clock enable 0x0
4 reg_cam0pll_ssc_syn_src_en R/W pll synthesizer clock enable 0x0
5 reg_cam1pll_ssc_syn_src_en R/W pll synthesizer clock enable 0x0
31:6 Reserved
ed
apll_ssc_syn_ctrl
w
lo
0 reg_apll_ssc_syn_sw_up W1T pll synthesizer software update
al
5:1 Reserved
t
6 reg_apll_ssc_syn_fix_div R/W 0x0
no
31:7 Reserved
e
apll_ssc_syn_set
ar
n
31:0 reg_apll_ssc_syn_set R/W pll synthesizer fraction 0x0
tio
setting:
[31:26] integer 6 bits
u
[26:0] decimal 26 bits

r ib
di V
disppll_ssc_syn_ctrl
st
re k-

d il

an M
0 reg_disppll_ssc_syn_sw_up W1T pll synthesizer software update

5:1 Reserved
n by
6 reg_disppll_ssc_syn_fix_div R/W 0x0

31:7 Reserved
tio lic
ca ub
disppll_ssc_syn_set
ifi p

od de
31:0 reg_disppll_ssc_syn_set R/W pll synthesizer fraction 0x0

setting:
M a

M
0 reg_cam0pll_ssc_syn_sw_up W1T pll synthesizer software update
5:1 Reserved
6 reg_cam0pll_ssc_syn_fix_div R/W 0x0
31:7 Reserved
88
CV1835
cam0pll_ssc_syn_set
31:0 reg_cam0pll_ssc_syn_set R/W pll synthesizer fraction 0x0
setting:
ed
w
0 reg_cam1pll_ssc_syn_sw_up W1T pll synthesizer software update
lo
5:1 Reserved
al
6 reg_cam1pll_ssc_syn_fix_div R/W 0x0
t
31:7 Reserved
no
cam1pll_ssc_syn_set
e
ar
31:0 reg_cam1pll_ssc_syn_set R/W pll synthesizer fraction 0x0
n
setting:
tio

u
ib
apll_frac_div_ctrl
r
di V

st
re k-

0 reg_apll_frac_div_clk_en R/W a24m clock src enable 0x0
d il
an M
1 reg_apll_frac_div_en R/W a24m clock div enable 0x0

2 reg_apll_frac_div_up W1T
n by
3 reg_apll_frac_reg_out_en R/W a24m clock output enable 0x0

31:4 Reserved
tio lic
apll_frac_div_m
ca ub

ifi p

21:0 reg_apll_frac_div_m R/W a24m clock freq is 900*N/M/2 0x0
od de
(MHz)
31:22 Reserved
M a
M
apll_frac_div_n
21:0 reg_apll_frac_div_n R/W a24m clock freq is 900*N/M/2 0x0
(MHz)
31:22 Reserved
mipimpll_clk_csr
Offset Address: 0x0a0
89
CV1835

0 reg_mipimpll_pdiv_pd R/W pd post div 0x0
1 reg_mipimpll_d2_pd R/W pd div2 div 0x1
7:5 Reserved
8 reg_mipimpll_pdiv_auto_pd R/W auto pd pdiv clk 0x0
9 reg_mipimpll_d2_auto_pd R/W auto pd div2 clk 0x1
ed
w
lo
31:13 Reserved
al
a0pll_clk_csr
t
no
0 reg_a0pll_pdiv_pd R/W pd post div 0x0
e
ar
1 reg_a0pll_d2_pd R/W pd div2 div 0x1
2 reg_a0pll_d3_pd R/W pd div3 div n 0x1
tio
7:5 Reserved
u
8 reg_a0pll_pdiv_auto_pd R/W auto pd pdiv clk 0x0

ib
9 reg_a0pll_d2_auto_pd R/W auto pd div2 clk 0x1

r

di V
st

re k-

d il
31:13 Reserved
an M
disppll_clk_csr
n by

tio lic
0 reg_disppll_pdiv_pd R/W pd post div 0x0

ca ub
1 reg_disppll_d2_pd R/W pd div2 div 0x1

ifi p

od de

7:5 Reserved
M a
8 reg_disppll_pdiv_auto_pd R/W auto pd pdiv clk 0x0

M
9 reg_disppll_d2_auto_pd R/W auto pd div2 clk 0x1

31:13 Reserved
cam0pll_clk_csr
Offset Address: 0x0ac
0 reg_cam0pll_pdiv_pd R/W pd post div 0x0
1 reg_cam0pll_d2_pd R/W pd div2 div 0x1
90
CV1835

7:5 Reserved
8 reg_cam0pll_pdiv_auto_pd R/W auto pd pdiv clk 0x0
9 reg_cam0pll_d2_auto_pd R/W auto pd div2 clk 0x1
ed
31:13 Reserved
w
lo
cam1pll_clk_csr
al
Offset Address: 0x0b0
t
no
0 reg_cam1pll_pdiv_pd R/W pd post div 0x0
e
ar
4 reg_cam1pll_d7_pd R/W pd div7 div n 0x1
7:5 Reserved
tio
8 reg_cam1pll_pdiv_auto_pd R/W auto pd pdiv clk 0x0
u

ib

r

di V
st
31:13 Reserved
re k-
d il
clk_cam0_src_div
an M
Offset Address: 0x0c0

n by

0 reg_cam0_div_rstn R/W [0] Divider Reset Control 0: 0x1
Assert Reset
tio lic
3:1 Reserved
ca ub
4 reg_cam0_div_dis R/W [4] Divider Reset Control 0: 0x0

Assert Reset
ifi p
7:5 Reserved
od de
9:8 reg_cam0_src R/W [9:8] Clock source 0x0

0: cam0pll
M a
1: cam0pll_d2
M
2: cam0pll_d3
3: mipimpll_d3
15:10 Reserved
21:16 reg_cam0_div R/W [21:16] Clock Divider Factor 0x20
31:22 Reserved
clk_cam1_src_div
0 reg_cam1_div_rstn R/W [0] Divider Reset Control 0: 0x1
Assert Reset
91
CV1835

3:1 Reserved
4 reg_cam1_div_dis R/W [4] divider disable 0x0
7:5 Reserved
9:8 reg_cam1_src R/W [9:8] Clock source 0x0
0: cam0pll
1: cam0pll_d2
2: cam0pll_d3
3: mipimpll_d3
ed
15:10 Reserved
w
21:16 reg_cam1_div R/W [21:16] Clock Divider Factor 0x20
31:22 Reserved
lo
al
t
no
3.2.7.2 PLL_G6 Register Overview
e
ar
n
tio
pll_g6_ctrl
u

ib
0 mpll_pwd R/W pll power down 0x0

r
3:1 Reserved
di V
st
re k-
4 tpll_pwd R/W pll power down 0x0

7:5 Reserved
d il
an M
8 fpll_pwd R/W pll power down 0x0

31:9 Reserved
n by
pll_g6_status
tio lic

ca ub
0 updating_mpll_val RO pll setting update status

ifi p
1 updating_tpll_val RO pll setting update status

2 updating_fpll_val RO pll setting update status
od de
15:3 Reserved
M a
16 mpll_lock RO pll lock status

M
17 tpll_lock RO pll lock status

18 fpll_lock RO pll lock status
31:19 Reserved
mpll_csr
6:0 mpll_pre_div_sel R/W pll pre_div_sel setting 0x0
7 Reserved
14:8 mpll_post_div_sel R/W pll post_div_sel setting 0x0
92
CV1835

16:15 mpll_sel_mode R/W pll mode setting 0x0
23:17 mpll_div_sel R/W pll div_sel setting 0x0
26:24 mpll_ictrl R/W pll ictrl setting 0x0
31:27 Reserved
tpll_csr
ed
6:0 tpll_pre_div_sel R/W pll pre_div_sel setting 0x0
w
7 Reserved
14:8 tpll_post_div_sel R/W pll post_div_sel setting 0x0
lo
16:15 tpll_sel_mode R/W pll mode setting 0x0
al
23:17 tpll_div_sel R/W pll div_sel setting 0x0
26:24 tpll_ictrl R/W pll ictrl setting 0x0
t
no
31:27 Reserved
fpll_csr
e
ar
Bits Name Access Description
n Reset
6:0 fpll_pre_div_sel R/W pll pre_div_sel setting 0x0
tio
7 Reserved
14:8 fpll_post_div_sel R/W pll post_div_sel setting 0x0
u
16:15 fpll_sel_mode R/W pll mode setting 0x0

ib
23:17 fpll_div_sel R/W pll div_sel setting 0x0

r
di V
st
26:24 fpll_ictrl R/W pll ictrl setting 0x0

re k-
31:27 Reserved
d il
an M
pll_g6_ssc_syn_ctrl
n by

0 reg_fpll_sel_syn_clk R/W fpll gen synthesizer clock 0x1
tio lic
source
0:750M
ca ub
1:1.5G
1 reg_ddr_ssc_syn_src_en R/W ddr pll synthesizer clock enable 0x1
ifi p
2 reg_mpll_ssc_syn_src_en R/W mpll synthesizer clock enable 0x0

od de
3 reg_tpll_ssc_syn_src_en R/W tpll synthesizer clock enable 0x0

31:4 Reserved
M a
M
dpll_ssc_syn_ctrl
0 reg_dpll_ssc_syn_sw_up W1T pll synthesizer software update
1 reg_dpll_ssc_syn_en_ssc R/W pll synthesizer ssc enable 0x0
3:2 reg_dpll_ssc_syn_ssc_mode R/W 0x0
4 reg_dpll_ssc_syn_bypass R/W 0x0
5 reg_dpll_ssc_syn_extpulse R/W 0x0
6 reg_dpll_ssc_syn_fix_div R/W 0x0
31:7 Reserved
93
CV1835
dpll_ssc_syn_set
31:0 reg_dpll_ssc_syn_set R/W pll synthesizer fraction 0x0
setting:
dpll_ssc_syn_span
ed
w
15:0 reg_dpll_ssc_syn_span R/W 0x0
lo
31:16 Reserved
al
dpll_ssc_syn_step
t
no
e
23:0 reg_dpll_ssc_syn_step R/W 0x0
ar
31:24 Reserved
n
mpll_ssc_syn_ctrl
tio

u
ib
0 reg_mpll_ssc_syn_sw_up W1T pll synthesizer software update

r
1 reg_mpll_ssc_syn_en_ssc R/W pll synthesizer ssc enable 0x0

di V
st
3:2 reg_mpll_ssc_syn_ssc_mode R/W 0x0

re k-
4 reg_mpll_ssc_syn_bypass R/W 0x1

d il
5 reg_mpll_ssc_syn_extpulse R/W 0x0

an M
6 reg_mpll_ssc_syn_fix_div R/W 0x0

n by
31:7 Reserved
tio lic
mpll_ssc_syn_set
ca ub

ifi p
31:0 reg_mpll_ssc_syn_set R/W pll synthesizer fraction 0x0

setting:
od de

M a
M
mpll_ssc_syn_span
15:0 reg_mpll_ssc_syn_span R/W 0x0
31:16 Reserved
mpll_ssc_syn_step
23:0 reg_mpll_ssc_syn_step R/W 0x0
94
CV1835

31:24 Reserved
tpll_ssc_syn_ctrl
0 reg_tpll_ssc_syn_sw_up W1T pll synthesizer software update
1 reg_tpll_ssc_syn_en_ssc R/W pll synthesizer ssc enable 0x0
ed
3:2 reg_tpll_ssc_syn_ssc_mode R/W 0x0
4 reg_tpll_ssc_syn_bypass R/W 0x1
w
5 reg_tpll_ssc_syn_extpulse R/W 0x0
lo
6 reg_tpll_ssc_syn_fix_div R/W 0x0
al
31:7 Reserved
t
no
tpll_ssc_syn_set
e
ar
31:0 reg_tpll_ssc_syn_set R/W pll synthesizer fraction 0x0
setting: n
tio
u
tpll_ssc_syn_span
ib

r

di V
st
15:0 reg_tpll_ssc_syn_span R/W 0x0

re k-
31:16 Reserved
d il
an M
tpll_ssc_syn_step
n by

tio lic
23:0 reg_tpll_ssc_syn_step R/W 0x0

31:24 Reserved
ca ub
ifi p
od de
3.2.8 CLK_DIV CRG Register Overview

M a
M
Clock Gen base address : 0x03002000

Offset
clk_en_0 0x000 clock enable register 0
clk_en_3 0x00c clock enable register 3
95
CV1835

Offset
clk_sel_0 0x020 clock source selection register 0
clk_byp_0 0x030 clock bypass to xtal register 0
clk_byp_1 0x034 clock bypass to xtal register 1
div_clk_cpu_axi0 0x048 divider register of clk_cpu_axi0
div_clk_tpu 0x054 divider register of clk_tpu
div_clk_sd0 0x070 divider register of clk_sd0
div_clk_100k_sd0 0x078 divider register of clk_100k_sd0
ed
div_clk_sd1 0x07c divider register of clk_sd1
div_clk_100k_sd1 0x084 divider register of clk_100k_sd1
w
div_clk_spi_nand 0x088 divider register of clk_spi_nand
lo
div_clk_500m_eth0 0x08c divider register of clk_500m_eth0
al
div_clk_gpio_db 0x094 divider register of clk_gpio_db
div_clk_sdma_aud0 0x098 divider register of clk_sdma_aud0
t
div_clk_sdma_aud1 0x09c divider register of clk_sdma_aud1
no
div_clk_sdma_aud2 0x0a0 divider register of clk_sdma_aud2
div_clk_sdma_aud3 0x0a4 divider register of clk_sdma_aud3
e
div_clk_cam0_200 0x0a8 divider register of clk_cam0_200
ar
div_clk_axi4 0x0b8 divider register of clk_axi4
div_clk_axi6 0x0bc divider register of clk_axi6
n
div_clk_dsi_esc 0x0c4 divider register of clk_dsi_esc
tio
div_clk_axi_vip 0x0c8 divider register of clk_axi_vip

div_clk_src_vip_sys_0 0x0d0 divider register of clk_src_vip_sys_0
u
div_clk_src_vip_sys_1 0x0d8 divider register of clk_src_vip_sys_1

ib
div_clk_disp_src_vip 0x0e0 divider register of clk_disp_src_vip

r
di V
div_clk_axi_video_codec 0x0e4 divider register of clk_axi_video_codec

st
re k-
div_clk_vc_src0 0x0ec divider register of clk_vc_src0

div_clk_1m 0x0fc divider register of clk_1m
d il
div_clk_spi 0x100 divider register of clk_spi

an M
div_clk_i2c 0x104 divider register of clk_i2c

div_clk_src_vip_sys_2 0x110 divider register of clk_src_vip_sys_2
n by
div_clk_audsrc 0x118 divider register of clk_audsrc

div_clk_pwm_src_0 0x120 divider register of clk_pwm_src_0
tio lic
div_clk_ap_debug 0x128 divider register of clk_ap_debug

ca ub
div_clk_rtcsys_src_0 0x12c divider register of clk_rtcsys_src_0

div_clk_c906_0_0 0x130 divider register of clk_c906_0_0
ifi p

od de
div_clk_c906_1_1 0x13c divider register of clk_c906_1_1

M a

M
3.2.9 CLK_DIV CRG Register Overview
clk_en_0
96
CV1835

0 Reserved R/W 0x1
1 clk_en_0_1 R/W Clock Enable for clk_cpu_axi0 0x1
(1: Enable; 0: Gate)
2 Reserved R/W 0x1
3 clk_en_0_3 R/W Clock Enable for clk_xtal_ap (1: 0x1
Enable; 0: Gate)
4 clk_en_0_4 R/W Clock Enable for clk_tpu (1: 0x1
Enable; 0: Gate)
ed
5 Reserved 0x1
w
6 clk_en_0_6 R/W Clock Enable for clk_ahb_rom (1: 0x1
Enable; 0: Gate)
lo
7 clk_en_0_7 R/W Clock Enable for clk_ddr_axi_reg 0x1
al
8 clk_en_0_8 R/W Clock Enable for clk_rtc_25m (1: 0x1
t
no
Enable; 0: Gate)
9 clk_en_0_9 R/W Clock Enable for clk_tempsen (1: 0x1
Enable; 0: Gate)
e
10 clk_en_0_10 R/W Clock Enable for clk_saradc (1: 0x1
ar
Enable; 0: Gate)
11 clk_en_0_11 R/W Clock Enable for clk_efuse (1: 0x1
n
Enable; 0: Gate)
tio
12 clk_en_0_12 R/W Clock Enable for clk_apb_efuse 0x1

u
13 Reserved
ib
14 clk_en_0_14 R/W Clock Enable for clk_xtal_misc 0x1

r
di V
st

re k-
15 Reserved R/W 0x1

d il
16 Reserved R/W 0x1

an M
17 Reserved R/W 0x1

n by
18 clk_en_0_18 R/W Clock Enable for clk_axi4_sd0 0x1

19 clk_en_0_19 R/W Clock Enable for clk_sd0 (1: 0x1
tio lic
Enable; 0: Gate)
ca ub
20 clk_en_0_20 R/W Clock Enable for clk_100k_sd0 0x1

ifi p
21 clk_en_0_21 R/W Clock Enable for clk_axi4_sd1 0x1

od de
22 clk_en_0_22 R/W Clock Enable for clk_sd1 (1: 0x1

M a
Enable; 0: Gate)
M
23 clk_en_0_23 R/W Clock Enable for clk_100k_sd1 0x1

24 clk_en_0_24 R/W Clock Enable for clk_spi_nand 0x1
25 clk_en_0_25 R/W Clock Enable for clk_500m_eth0 0x1
26 clk_en_0_26 R/W Clock Enable for clk_axi4_eth0 0x1
28:27 Reserved
29 clk_en_0_29 R/W Clock Enable for clk_apb_gpio 0x1
30 clk_en_0_30 R/W Clock Enable for 0x1
97
CV1835

clk_apb_gpio_intr (1: Enable; 0:
Gate)
31 clk_en_0_31 R/W Clock Enable for clk_gpio_db (1: 0x1
Enable; 0: Gate)
clk_en_1
ed
0 clk_en_1_0 R/W Clock Enable for clk_ahb_sf (1: 0x1
Enable; 0: Gate)
w
1 clk_en_1_1 R/W Clock Enable for clk_sdma_axi 0x1
lo
al
2 clk_en_1_2 R/W Clock Enable for clk_sdma_aud0 0x1
t
no
e
ar
n
6 clk_en_1_6 R/W Clock Enable for clk_apb_i2c (1: 0x1
tio
Enable; 0: Gate)
7 clk_en_1_7 R/W Clock Enable for clk_apb_wdt (1: 0x1
u
Enable; 0: Gate)
ib
8 clk_en_1_8 R/W Clock Enable for clk_apb_pwm (1: 0x1

r
Enable; 0: Gate)
di V
st
9 clk_en_1_9 R/W Clock Enable for clk_apb_spi0 0x1

re k-

d il

an M

n by

tio lic

13 clk_en_1_13 R/W Clock Enable for clk_187p5m (1: 0x1
ca ub
Enable; 0: Gate)
14 clk_en_1_14 R/W Clock Enable for clk_uart0 (1: 0x1
ifi p
Enable; 0: Gate)
od de
15 clk_en_1_15 R/W Clock Enable for clk_apb_uart0 0x1

M a

M
Enable; 0: Gate)
Enable; 0: Gate)
Enable; 0: Gate)
98
CV1835

Enable; 0: Gate)
24 clk_en_1_24 R/W Clock Enable for clk_apb_i2s0 0x1
ed
w
lo
28 clk_en_1_28 R/W Clock Enable for clk_axi4_usb 0x1
al
29 clk_en_1_29 R/W Clock Enable for clk_apb_usb (1: 0x1
t
Enable; 0: Gate)
no
31:30 Reserved
e
clk_en_2
ar
n
0 Reserved
tio
1 clk_en_2_1 R/W Clock Enable for clk_axi4 (1: 0x1

Enable; 0: Gate)
u
2 clk_en_2_2 R/W Clock Enable for clk_axi6 (1: 0x1

ib
Enable; 0: Gate)
r
di V
3 clk_en_2_3 R/W Clock Enable for clk_dsi_esc (1: 0x1

st
re k-
Enable; 0: Gate)
4 clk_en_2_4 R/W Clock Enable for clk_axi_vip (1: 0x1
d il
an M
Enable; 0: Gate)
clk_src_vip_sys_0 (1: Enable; 0:
n by
Gate)
tio lic

ca ub
Gate)
ifi p
clk_disp_src_vip (1: Enable; 0:

Gate)
od de

clk_axi_video_codec (1: Enable;
M a
M
0: Gate)
9 clk_en_2_9 R/W Clock Enable for clk_vc_src0 (1: 0x1
Enable; 0: Gate)
10 clk_en_2_10 R/W Clock Enable for clk_h264c (1: 0x1
Enable; 0: Gate)
11 clk_en_2_11 R/W Clock Enable for clk_h265c (1: 0x1
Enable; 0: Gate)
12 clk_en_2_12 R/W Clock Enable for clk_jpeg (1: 0x1
Enable; 0: Gate)
13 clk_en_2_13 R/W Clock Enable for clk_apb_jpeg 0x1
14 clk_en_2_14 R/W Clock Enable for clk_apb_h264c 0x1
99
CV1835

15 clk_en_2_15 R/W Clock Enable for clk_apb_h265c 0x1
16 clk_en_2_16 R/W Clock Enable for clk_cam0 (1: 0x1
Enable; 0: Gate)
17 clk_en_2_17 R/W Clock Enable for clk_cam1 (1: 0x1
Enable; 0: Gate)
ed
clk_csi_mac0_vip (1: Enable; 0:
Gate)
w
lo
clk_csi_mac1_vip (1: Enable; 0:
Gate)
al
20 clk_en_2_20 R/W Clock Enable for clk_isp_top_vip 0x1
t
no
21 clk_en_2_21 R/W Clock Enable for clk_img_d_vip 0x1
22 clk_en_2_22 R/W Clock Enable for clk_img_v_vip 0x1
e
ar
23 clk_en_2_23 R/W Clock Enable for clk_sc_top_vip 0x1
n
tio
24 clk_en_2_24 R/W Clock Enable for clk_sc_d_vip 0x1
u
25 clk_en_2_25 R/W Clock Enable for clk_sc_v1_vip 0x1

ib

r
di V
st

re k-

d il

an M
28 clk_en_2_28 R/W Clock Enable for clk_ldc_vip (1: 0x1

Enable; 0: Gate)
n by
29 clk_en_2_29 R/W Clock Enable for clk_bt_vip (1: 0x1

Enable; 0: Gate)
30 clk_en_2_30 R/W Clock Enable for clk_disp_vip 0x1
tio lic

ca ub
31 clk_en_2_31 R/W Clock Enable for clk_dsi_mac_vip 0x1

ifi p
clk_en_3
od de

M a

M
0 clk_en_3_0 R/W Clock Enable for clk_lvds0_vip 0x1

1 clk_en_3_1 R/W Clock Enable for clk_lvds1_vip 0x1
2 clk_en_3_2 R/W Clock Enable for clk_csi0_rx_vip 0x1
3 clk_en_3_3 R/W Clock Enable for clk_csi1_rx_vip 0x1
4 clk_en_3_4 R/W Clock Enable for clk_pad_vi_vip 0x1
5 clk_en_3_5 R/W Clock Enable for clk_1m (1: 0x1
Enable; 0: Gate)
100
CV1835

6 clk_en_3_6 R/W Clock Enable for clk_spi (1: 0x1
Enable; 0: Gate)
7 clk_en_3_7 R/W Clock Enable for clk_i2c (1: 0x1
Enable; 0: Gate)
8 clk_en_3_8 R/W Clock Enable for clk_pm (1: 0x1
Enable; 0: Gate)
9 clk_en_3_9 R/W Clock Enable for clk_timer0 (1: 0x1
Enable; 0: Gate)
ed
Enable; 0: Gate)
w
lo
Enable; 0: Gate)
al
Enable; 0: Gate)
t
no
Enable; 0: Gate)
Enable; 0: Gate)
e
ar
Enable; 0: Gate)
n
tio
Enable; 0: Gate)
17 clk_en_3_17 R/W Clock Enable for clk_apb_i2c0 0x1
u

ib

r
di V
st

re k-

d il

an M

n by

22 clk_en_3_22 R/W Clock Enable for clk_wgn (1: 0x1
tio lic
Enable; 0: Gate)
23 clk_en_3_23 R/W Clock Enable for clk_wgn0 (1: 0x1
ca ub
Enable; 0: Gate)
ifi p
Enable; 0: Gate)
od de

Enable; 0: Gate)
M a
26 clk_en_3_26 R/W Clock Enable for clk_keyscan (1: 0x1

M
Enable; 0: Gate)
27 clk_en_3_27 R/W Clock Enable for clk_ahb_sf1 (1: 0x1
Enable; 0: Gate)
28 Reserved
Gate
30 clk_en_3_30 R/W Clock Enable for clk_pad_vi1_vip 0x1
31 clk_en_3_31 R/W Clock Enable for clk_cfg_reg_vip 0x1
101
CV1835
clk_en_4
0 clk_en_4_0 R/W Clock Enable for clk_cfg_reg_vc 0x1
1 clk_en_4_1 R/W Clock Enable for clk_audsrc (1: 0x1
Enable; 0: Gate)
2 clk_en_4_2 R/W Clock Enable for clk_apb_audsrc 0x1
ed
3 Reserved
4 clk_en_4_4 R/W Clock Enable for clk_pwm_src (1: 0x1
w
Enable; 0: Gate)
lo
5 clk_en_4_5 R/W Clock Enable for clk_ap_debug(1: 0x1
al
Enable; 0: Gate)
t
clk_rtcsys_src_0 (1: Enable; 0:
no
Gate)
7 clk_en_4_7 R/W Clock Enable for clk_pad_vi2_vip 0x1
e
ar
8 clk_en_4_8 R/W Clock Enable for clk_csi_be_vip 0x1
n
9 clk_en_4_9 R/W Clock Enable for clk_vip_ip0_en 0x1
tio

u

ib
13 clk_en_4_13 R/W Clock Enable for clk_c906_0_en 0x1

r
di V
14 clk_en_4_14 R/W Clock Enable for clk_c906_1_en 0x1

st
re k-

clk_src_vip_sys_3_en
d il

an M
clk_src_vip_sys_4_en
17 clk_en_4_17 R/W Clock Enable for clk_ive_vip_en 0x1
n by
18 clk_en_4_18 R/W Clock Enable for clk_raw_vip_en 0x1

19 clk_en_4_19 R/W Clock Enable for clk_osdc_vip_en 0x1
tio lic
20 clk_en_4_20 R/W Clock Enable for clk_fbc_vip_en 0x1

ca ub
21 clk_en_4_21 R/W Clock Enable for clk_cam0_vip_en 0x1

31:22 Reserved
ifi p
clk_sel_0
od de

M a

M
22:0 Reserved
23 clk_sel_0_23 R/W Clock Select for C906's clock 0x0
clk_c906_0
1: Select div_clk_c906_0_0 as
clock source
clock source
24 clk_sel_0_24 R/W Clock Select for C906's clock 0x0
clk_c906_1
clock source
102
CV1835

clock source
31:25 Reserved
clk_byp_0
0 Reserved 0x1
1 clk_byp_0_1 R/W Clock Bypass to xtal for clock 0x1
ed
clk_cpu_axi0
w
2 Reserved R/W 0x1
lo
3 clk_byp_0_3 R/W Clock Bypass to xtal for TPU's 0x1
clock clk_tpu
al
4 Reserved 0x1
t
5 Reserved 0x1
no
6 clk_byp_0_6 R/W Clock Bypass to xtal for SD's 0x1
clock clk_sd0
e
7 clk_byp_0_7 R/W Clock Bypass to xtal for SD's 0x1
ar
clock clk_sd1
8 clk_byp_0_8 R/W Clock Bypass to xtal for 0x1
n
SPI_NAND's clock clk_spi_nand
tio
9 clk_byp_0_9 R/W Clock Bypass to xtal for ETH0's 0x1

clock clk_500m_eth0
u
10 Reserved
ib
11 clk_byp_0_11 R/W Clock Bypass to xtal for AUDIO's 0x1

r
di V
clock clk_aud0
st
re k-

clock clk_aud1
d il
an M

clock clk_aud2
n by
clock clk_aud3
15 clk_byp_0_15 R/W Clock Bypass to xtal for PWM's 0x1
tio lic
clock clk_pwm_src
ca ub
16 clk_byp_0_16 R/W Clock Bypass to xtal for TOP's 0x1

clock clk_cam0_200
ifi p
18:17 Reserved
od de

FABRIC_AXI4's clock clk_axi4
M a

M
FABRIC_AXI6's clock clk_axi6

VIP_SYS's clock clk_dsi_esc
VIP_SYS's clock clk_axi_vip
VIP_SYS's clock
clk_src_vip_sys_0
VIP_SYS's clock
clk_src_vip_sys_1
103
CV1835

VIP_SYS's clock
clk_disp_src_vip
Video_subsys's clock
clk_axi_video_codec
Video_subsys's clock clk_vc_src0
29:28 Reserved
ed
30 clk_byp_0_30 R/W Clock Bypass to xtal for SPI's 0x1
clock clk_spi
w
31 clk_byp_0_31 R/W Clock Bypass to xtal for IIC's 0x1
lo
clock clk_i2c
al
clk_byp_1
t
no
0 Reserved
e
ar
VIP_SYS's clock
clk_src_vip_sys_2
n
tio
AUDSRC's clock clk_audsrc

u
Video_subsys's clock clk_vc_src2

ib

r
di V
clk_ap_debug
st
re k-

clk_src_rtc_sys_0
d il
6 clk_byp_1_6 R/W Clock Bypass to xtal for c906_0 0x1

an M
7 clk_byp_1_7 R/W Clock Bypass to xtal for c906_1 0x1

n by
VIP_SYS's clock
clk_src_vip_sys_3
tio lic

ca ub
VIP_SYS's clock
clk_src_vip_sys_4
ifi p
31:10 Reserved
od de
div_clk_cpu_axi0
M a

M

31:0 div_clk_cpu_axi0 R/W [0] Divider Reset Control 0: 0x00000
Assert Reset 1: De-assert Reset 001
[3] Select Divide Factor from
Register 0: Select initial value
1: Select Divide Factor from
this register
[20:16] Clock Divider Factor
[9:8] clk_src
0 : fpll
1 : disppll
104
CV1835
div_clk_tpu
31:0 div_clk_tpu R/W [0] Divider Reset Control 0: 0x00000
this register
ed
[9:8] clk_src
w
0 : tpll
lo
1 : apll
2 : mipimpll
al
3 : fpll
t
no
div_clk_sd0
e
ar
31:0 div_clk_sd0 R/W [0] Divider Reset Control 0: 0x00000
Assert Reset 1: De-assert Reset
n 001
tio
u
this register
ib

r
[9:8] clk_src
di V
st
0 : fpll
re k-
1 : disppll
d il
an M
div_clk_100k_sd0
n by

31:0 div_clk_100k_sd0 R/W [0] Divider Reset Control 0: 0x00000
tio lic

ca ub

ifi p
this register
od de

M a
div_clk_sd1
M

31:0 div_clk_sd1 R/W [0] Divider Reset Control 0: 0x00000
this register
[9:8] clk_src
0 : fpll
1 : disppll
105
CV1835
div_clk_100k_sd1
31:0 div_clk_100k_sd1 R/W [0] Divider Reset Control 0: 0x00000
this register
ed
w
div_clk_spi_nand
lo
al
31:0 div_clk_spi_nand R/W [0] Divider Reset Control 0: 0x00000
t
no
e
ar
this register
n
[9:8] clk_src
tio
0 : fpll
1 : disppll
u
ib
div_clk_500m_eth0
r

di V
st

re k-
31:0 div_clk_500m_eth0 R/W [0] Divider Reset Control 0: 0x00000

d il

an M

n by

this register
tio lic

ca ub
div_clk_gpio_db
ifi p

od de
31:0 div_clk_gpio_db R/W [0] Divider Reset Control 0: 0x00000

M a
M

this register
div_clk_sdma_aud0
31:0 div_clk_sdma_aud0 R/W [0] Divider Reset Control 0: 0x00000
106
CV1835

this register
[9:8] clk_src
0 : apll
1 : a24k
ed
div_clk_sdma_aud1
w
lo
al
t
no
this register
e
ar
[9:8] clk_src
0 : apll
1 : a24k
n
tio
div_clk_sdma_aud2
u

ib

r

di V
st

re k-

d il

an M

this register
n by

[9:8] clk_src
tio lic
0 : apll
1 : a24k
ca ub
div_clk_sdma_aud3
ifi p

od de

M a

M

this register
[9:8] clk_src
0 : apll
1 : a24k
div_clk_cam0_200
107
CV1835

31:0 div_clk_cam0_200 R/W [0] Divider Reset Control 0: 0x00000
this register
[9:8] clk_src
ed
0 : xtal
1 : disppll
w
div_clk_axi4
lo
al
t
31:0 div_clk_axi4 R/W [0] Divider Reset Control 0: 0x00000
no
e
ar
this register
n
tio
[9:8] clk_src
0 : fpll
u
1 : disppll
ib
div_clk_axi6
r
di V
st
Offset Address: 0x0bc

re k-

d il
31:0 div_clk_axi6 R/W [0] Divider Reset Control 0: 0x00000

an M

n by

tio lic
this register
ca ub
div_clk_dsi_esc
ifi p

od de

31:0 div_clk_dsi_esc R/W [0] Divider Reset Control 0: 0x00000
M a

M

this register
div_clk_axi_vip
31:0 div_clk_axi_vip R/W [0] Divider Reset Control 0: 0x00000
108
CV1835

this register
[9:8] clk_src
0 : mipimpll
1 : cam0pll
ed
2 : disppll
3 : fpll
w
div_clk_src_vip_sys_0
lo
Offset Address: 0x0d0
al
t
31:0 div_clk_src_vip_sys_0 R/W [0] Divider Reset Control 0: 0x00000
no
e
ar
this register
n
tio
[9:8] clk_src
0 : mipimpll
u
1 : cam0pll
ib
2 : disppll
3 : fpll
r
di V
st
re k-
d il

an M

n by

tio lic

ca ub
this register
ifi p
[9:8] clk_src
od de
0 : mipimpll
1 : cam0pll
M a
2 : disppll
M
3 : fpll
div_clk_disp_src_vip
Offset Address: 0x0e0
31:0 div_clk_disp_src_vip R/W [0] Divider Reset Control 0: 0x00000
this register
109
CV1835
div_clk_axi_video_codec
31:0 div_clk_axi_video_codec R/W [0] Divider Reset Control 0: 0x00000
this register
ed
[9:8] clk_src
w
0 : apll
lo
1 : mipimpll
2 : cam1pll
al
3 : fpll
t
no
div_clk_vc_src0
Offset Address: 0x0ec
e
ar
31:0 div_clk_vc_src0 R/W [0] Divider Reset Control 0: 0x00000
Assert Reset 1: De-assert Reset
n 101
tio
u
this register
ib

r
[9:8] clk_src
di V
st
0 : apll
re k-
1 : mipimpll
d il
2 : cam1pll
an M
3 : fpll
n by
div_clk_1m
Offset Address: 0x0fc
tio lic

31:0 div_clk_1m R/W [0] Divider Reset Control 0: 0x00000
ca ub

ifi p

od de

this register
M a

M
div_clk_spi
31:0 div_clk_spi R/W [0] Divider Reset Control 0: 0x00000
this register
110
CV1835
div_clk_i2c
31:0 div_clk_i2c R/W [0] Divider Reset Control 0: 0x00000
this register
ed
w
lo
al
t
no
e
ar
this register
n
[9:8] clk_src
tio
0 : mipimpll
1 : cam0pll
u
2 : disppll
ib
3 : fpll
r
di V
st
div_clk_audsrc
re k-

d il

an M
31:0 div_clk_audsrc R/W [0] Divider Reset Control 0: 0x00000

n by

tio lic

this register
ca ub

[9:8] clk_src
ifi p
0 : apll
od de
1 : a24k
M a
div_clk_pwm_src_0
M

31:0 div_clk_pwm_src R/W [0] Divider Reset Control 0: 0x00000
this register
[9:8] clk_src
0 : fpll
1 : disppll
111
CV1835
div_clk_ap_debug
31:0 div_clk_ap_debug R/W [0] Divider Reset Control 0: 0x00000
this register
ed
w
div_clk_rtcsys_src_0
lo
al
31:0 div_clk_src_rtc_sys_0 R/W [0] Divider Reset Control 0: 0x00000
t
no
e
ar
this register
n
tio
div_clk_c906_0_0
u

ib
31:0 div_clk_c906_0_0 R/W [0] Divider Reset Control 0: 0x00000

r

di V
st
re k-
[1] High Wide Control (when

Divider Factor is odd) 0: Low
d il
level of the clock is wider 1:

an M
High level of the clock is wider

n by

tio lic
this register
[3] Select High Wide Control
ca ub
from Register 0: Select initial

value 1: Select High Wide from
ifi p
this register
od de

[9:8] clk_src
M a
0 : tpll
M
1 : apll
2 : mipimpll
3 : mpll
div_clk_c906_0_1
112
CV1835

this register
[9:8] clk_src
0 : fpll
div_clk_c906_1_0
ed
w
[1] High Wide Control (when
lo
Divider Factor is odd) 0: Low
level of the clock is wider 1:
al
High level of the clock is wider
t
no
this register
e
ar
[3] Select High Wide Control
from Register 0: Select initial
value 1: Select High Wide from
n
tio
this register
u
[9:8] clk_src
ib
0 : tpll
1 : apll
r
di V
st
2 : mipimpll
re k-
3 : mpll
d il
an M
div_clk_c906_1_1
n by

tio lic

ca ub

ifi p
this register
od de

[9:8] clk_src
M a
0 : fpll
M
this register
[9:8] clk_src
113
CV1835

0 : mipimpll
1 : cam0pll
2 : disppll
3 : fpll
ed
w
lo
al
this register
t
no
[9:8] clk_src
0 : mipimpll
1 : cam0pll
e
ar
2 : disppll
3 : fpll
n
u tio
r ib
di V
3.3 Processor Subsystem

st
re k-
d il
an M
The chip adopts RISCV C906 processor, which has the following characteristics.
 The maximum operating frequency of the processor can reach 1.0 GHz
n by
 Integrated with a vector execution unit and a floating-point coprocessor.

tio lic
 Integrate L1 Cache which includes 32KB Instruction Cache and 64KB Data Cache
ca ub
 Support MMU（Memory Management Unit）

ifi p
 Integrated interrupt controller inside the processor.

od de
 Support JTAG debugging interface

M a
M
The coprocessor RISCV C906 @ 700Mhz

 Integrated with a floating-point unit (FPU).
114
CV1835
3.4 Interrupt System
The chip’s interrupt source is shown in the following table.
Table 3- 5 Interrupt Number and Interrupt Source Mapping Table

中断号中断源中断号中断源中断号中断源
ed
16 TEMPSENS 中断 48 UART4 中断 80 Timer1 中断
w
17 RTC Alarm 中断 49 I2C0 中断 81 Timer2 中断
lo
18 RTC Longpress 中断 50 I2C1 中断 82 Timer3 中断
al
19 VBAT DET 中断 51 I2C2 中断 83 Timer4 中断
t
20 52 84
no
JPEG 中断 I2C3 中断 Timer5 中断
21 H264 中断 53 I2C4 中断 85 Timer6 中断
e
22 H265 中断 54 SPI1 中断 86 Timer7 中断
ar
23 VC SBM 中断 55 SPI2 中断
n 87 peri_firewall 中断
24 56 88
tio
ISP 中断 SPI3 中断 hsperi_firewall 中断
25 SC_TOP 中断 57 SPI4 中断 89 ddr_fw 中断
u
26 58 90
ib
CSI_MAC0 中断 Watch Dog1 中断 rom_firewall 中断

r
27 59 91
di V
CSI_MAC1 中断 KEYSCAN 中断 SPACC 中断

st
re k-
28 LDC 中断 60 GPIO0 中断 92 TRNG 中断

d il
29 61 93
an M
System DMA 中断 GPIO1 中断 ddr_axi_mon 中断

30 USB 中断 62 GPIO2 中断 94 ddr_pi_phy 中断
n by
31 Ethnet0 中断 63 GPIO3 中断 95 SPI_NOR 中断

tio lic
32 Ethnet0 中断 64 Wiegand0 中断 96 EPHY 中断

ca ub
33 保留 65 Wiegand1 中断 97 IVE 中断
34 66 98
ifi p
保留 Wiegand2 中断保留
35 67 99
od de
SD0 Wakup 中断 RTC MBOX 中断保留

36 68 100
M a
SD0 中断 SARADC 中断
M
37 SD1 Wakup 中断 69 RTC IRRX 中断 101 mbox 中断
38 SD1 中断 70 RTC GPIO 中断

39 SPI_NAND 中断 71 RTC UART 中断
40 I2S0 中断 72 RTC SPI_NOR 中断
41 I2S1 中断 73 RTC I2C 中断
42 I2S2 中断 74 RTC WDG 中断
43 I2S3 中断 75 TPU 中断
44 UART0 中断 76 TDMA 中断
115
CV1835
中断号中断源中断号中断源中断号中断源
45 UART1 中断 77 保留
46 UART2 中断 78 保留
47 UART3 中断 79 Timer0 中断
ed
3.5 System Controller
w
lo
al
3.5.1 Overview
t
no
The system controller controls the chip through registers, including system soft reset,
e
clock control and so on. Reset and clock have been described in other chapters. This
ar
chapter describes the configuration and status registers of some other system function
n
modules.
u tio
ib
3.5.2 Function Description

r
di V
st
re k-
d il
3.5.2.1 Global Reset Enablement

an M
n by
System global soft reset, debug reset and watch dog reset could be issued by
configuring reg_sw_root_reset_en register. Details are explained in
tio lic
reg_sw_root_reset_en.
ca ub
ifi p
3.5.2.2 System DMA Channel Mapping

od de
There are 8 channels in this DMA, and 0 ~7 dma request interfaces are configured
M a
M
respectively. The dma requests interfaces from 0 to 7 could be mapped to one of the
peripheral interfaces in the following table by the system control registers
sdma_dma_ch_remap0 and sdma_dma_ch_remap1. A peripheral interface should not
be assigned to multiple channels.
Configuration steps:
116
CV1835
Configure DMA channel image register sdma_dma_ch_remap0, sdma_dma_ch_remap1.

Then write 1 to update_dma_remap_0_3 and update_dma_remap_4_7 to make the
mapping effective.
编号 DMA 界面编号 DMA 界面
0 dma_rx_req_i2s0 24 dma_rx_req_i2c0
1 dma_tx_req_i2s0 25 dma_tx_req_i2c0
ed
w
lo
al
t
no
8 dma_rx_req_n_uart0 32 dma_rx_req_i2c4
9 dma_tx_req_n_uart0 33 dma_tx_req_i2c4
e
10 dma_rx_req_n_uart1 34 dma_rx_req_tdm0
ar
11 dma_tx_req_n_uart1 35 dma_tx_req_tdm0
12
n
dma_rx_req_n_uart2 36 dma_rx_req_tdm1
tio
13 dma_tx_req_n_uart2 37 dma_req_audsrc
14 dma_rx_req_n_uart3 38 dma_req_spi_nand
u
15 dma_tx_req_n_uart3 39 dma_req_spi_nor
ib
16 dma_rx_req_spi0 40 dma_rx_req_n_uart4
r
di V
st
17 dma_tx_req_spi0 41 dma_tx_req_n_uart4
re k-
18 dma_rx_req_spi1 42 dma_req_spi_nor1
d il
an M
19 dma_tx_req_spi1
20 dma_rx_req_spi2
n by
21 dma_tx_req_spi2
22 dma_rx_req_spi3
tio lic
23 dma_tx_req_spi3
ca ub
ifi p
od de
3.5.2.3 DDR AXI Urgent/Qos Configuration

M a
M
The DDR AXI priority could be controlled by ddr_axi_urgent_o, ddr_axi_urgen,

ddr_axi_qos_0 and ddr_axi_qos_1. Refer to the DDR controller section for details.
3.5.3 System Control Register
3.5.3.1 System Control Register Overview
Bass address 0x03000000
117
CV1835

Offset
conf_info 0x004 conf_info
sys_ctrl_reg 0x008 sys_ctrl_reg
usb_phy_ctrl_reg 0x048 usb_phy_ctrl_reg
sdma_dma_ch_remap0 0x154 sdma_dma_ch_remap0
sdma_dma_ch_remap1 0x158 sdma_dma_ch_remap1
top_timer_clk_sel 0x1a0 top_timer_clk_sel
top_wdt_ctrl 0x1a8 top_timer_clk_sel
ddr_axi_urgent_ow 0x1b8 ddr_axi_urgent_ow
ed
ddr_axi_urgent 0x1bc ddr_axi_urgent
ddr_axi_qos_0 0x1d8 ddr_axi_qos_0
w
ddr_axi_qos_1 0x1dc ddr_axi_qos_1
lo
sd_pwrsw_ctrl 0x1f4 sd_pwrsw_ctrl
al
sd_pwrsw_time 0x1f8 sd_pwrsw_time
ddr_axi_qos_ow 0x23c ddr_axi_qos_ow
t
sd_ctrl_opt 0x294 additional control register for sd
no
sdma_dma_int_mux 0x298 Mux sdma channel interrupt to different processors
e
3.5.3.2 System Control Register Overview
ar
n
u tio
r ib
conf_info
di V
st

re k-

d il
7:0 boot_sel RO [2:0] boot device selection

an M
0: SPI_NAND
1: reserved
n by
2: SPI_NOR
3: reserved
[7:3] : resreved
tio lic
8 io_sta_usbid RO IO status from USBID PAD

ca ub
9 io_sta_usbvbus RO IO status from USB_VBUS_DET PAD

ifi p
23:10 Reserved
31:24 io_sta_trap RO io_sta_trap[0] : io_boot_rom_din
od de
io_sta_trap[1] : io_boot_dev0_din
io_sta_trap[2] : io_boot_dev1_din
M a
M
io_sta_trap[3] : io_trap_sd0_pwr_din
io_sta_trap[4] : io_pkg_type0_din
io_sta_trap[7] : io_trap_zq_din
sys_ctrl_reg
1:0 Reserved
5:2 reg_sw_root_reset_en R/W bit0 : wdt reset enable 0x0
bit1 : cdbgrstreq enable
118
CV1835

bit2 : reserved
bit3 : reg_soft_reset_x_system enable
31:6 Reserved
usb_phy_ctrl_reg
0 reg_usb_phy_external_vbusvalid R/W external vbus status 0x0
ed
1 reg_usb_drive_vbus R/W drive vbus power 0x0
4:2 Reserved
w
5 toreg_usb_id_en RO usb id pullup status
lo
6 reg_usb_phy_idpad_c_ow R/W usb id overwrite enable 0x0
al
7 reg_usb_phy_idpad_c_sw R/W usb id overwrite value 0x0
8 io_usb_phy_idpad_c RO usb id external IO pin status
t
no
9 toreg_usb_phy_idpad_c RO usb id pin status
31:10 Reserved
e
ar
sdma_dma_ch_remap0
n
tio
5:0 reg_dma_remap_ch0 R/W dma channel 0 mapping 0x0

7:6 Reserved
u

ib
15:14 Reserved
r
di V
st

re k-
23:22 Reserved
d il

an M
30 Reserved
31 update_dma_remp_0_3 W1T write 1 to update dma channel0~3
n by
mapping
tio lic
sdma_dma_ch_remap1
ca ub

5:0
ifi p
reg_dma_remap_ch4 R/W dma channel 4 mapping 0x0

7:6 Reserved
od de

15:14 Reserved
M a
M

23:22 Reserved
30 Reserved
31 update_dma_remp_4_7 W1T write 1 to update dma channel4~7
mapping
top_timer_clk_sel
7:0 reg_timer_clk_sel R/W timer0~7 clock selection. 0: xtal 0x0
119
CV1835

clock,1:32k clock
31:8 Reserved
top_wdt_ctrl
2:0 reg_wdt_rst_sys_en R/W enable wdt0~wdt2 to reset system 0x7
3 Reserved
ed
6:4 reg_wdt_rst_cpu_en R/W enable wdt0~wdt2 to reset cpu 0x0
7 Reserved
w
10:8 reg_wdt_clk_sel R/W top_wdt clock selection. 0: xtal 0x0
lo
clock,1:32k clock
al
31:11 Reserved
t
ddr_axi_urgent_ow
no
e
0 reg_awurgent_m1_ow R/W ddr axi port1 awurgent overwrite 0x1
ar
enable
1 reg_arurgent_m1_ow R/W ddr axi port1 arurgent overwrite enable 0x1
n
tio
enable
u

ib
enable
r

di V
st

re k-
enable
d il

an M

enable
n by

tio lic
enable
ca ub
31:12 Reserved
ifi p
ddr_axi_urgent
od de

M a
0 reg_awurgent_m1 R/W ddr axi port1 awurgent overwrite value 0x0

M
1 reg_arurgent_m1 R/W ddr axi port1 arurgent overwrite value 0x0

120
CV1835

31:12 Reserved
ddr_axi_qos_0
3:0 reg_awqos_m1 R/W ddr axi port1 awqos setting 0x0
7:4 reg_arqos_m1 R/W ddr axi port1 arqos setting 0x0
ed
w
lo
al
ddr_axi_qos_1
t
no
Offset Address: 0x1dc
e
ar
11:8 reg_awqos_m6 R/W ddr axi port6 awqos setting
n 0x0
tio
31:16 Reserved
u
sd_pwrsw_ctrl
ib
Offset Address: 0x1f4

r

di V
st
0 reg_en_pwrsw R/W 18/33 IO power switch enable 0x0

re k-
1 reg_pwrsw_vsel R/W 18/33 IO power switch enable 0x1

d il
0: 3.3v
an M
1: 1.8v
2 reg_pwrsw_disc R/W 18/33 IO power switch discharge enable 0x0
n by
3 reg_pwrsw_auto R/W 18/33 IO power switch auto protect 0x1

enable
tio lic
31:4 Reserved
ca ub
sd_pwrsw_time
ifi p

od de
15:0 reg_tpwrup R/W 18/33 IO power switch, power up 0x1f4

protection time is 500x40ns = 20us
M a
31:16 reg_tpwrdn R/W 18/33 IO power switch, power down 0x1f4

M
protection time is 500x40ns = 20us
ddr_axi_qos_ow
0 reg_awqos_m1_ow R/W ddr axi port1 awqos overwrite enable 0x1
1 reg_arqos_m1_ow R/W ddr axi port1 arqos overwrite enable 0x1
121
CV1835

31:12 Reserved
sd_ctrl_opt
ed
w
0 reg_sd0_carddet_ow R/W sd0 card detect over write enable 0x0
lo
1 reg_sd0_carddet_sw R/W sd0 card detect over write value 0x0
7:2 Reserved
al
8 reg_sd1_carddet_ow R/W sd1 card detect over write enable 0x0
t
9 reg_sd1_carddet_sw R/W sd1 card detect over write value 0x0
no
15:10 Reserved
16 reg_sd0_pwr_en_polarity R/W off chip sd0 pwr en polarity 0x0
e
0: SD_LDO power ctrl high is power
ar
on , low is power off
1: SD_LDO power ctrl high is power
n
off , low is power on
tio
31:17 Reserved
u
sdma_dma_int_mux
ib

r

di V
st
8:0 reg_dma_int_mux_cpu0 R/W This register is used to mux separate 0x1FF

re k-
sdma channel interrupts to CPU0.

d il
These are enable bits corresponding to

an M
{intr_cmnreg,intr_ch[7:0]}
9 Reserved
n by
18:10 reg_dma_int_mux_cpu1 R/W This register is used to mux separate 0x0

tio lic

ca ub
19 Reserved
28:20 reg_dma_int_mux_cpu2 R/W This register is used to mux separate 0x0
ifi p

od de

M a
31:29 Reserved
M
122
CV1835
3.6 DMA Controller
3.6.1 Overview
DMA (Direct Memory Access) can transfer data directly between the memory and the
device. This mechanism can greatly reduce CPU access time and improve data
ed
transmission rate. It is very suitable for big data transmission. When the chip works, it
w
often needs multi-channel data transmission. Each channel needs a DMA hardware to
lo
al
support, and the DMAC (DMA controller) is responsible for the control of multi-channel.
The following figure shows the DMAC hardware control flow. The source and
t
no
destination could be from different AXI Buses.
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 3- 4 DMAC Hardware Control Fow Diagram
123
CV1835
3.6.2 Characteristics
The characteristics of DMAC are as follows.

a. Up to 8 DMA channels can be established at the same time.
b. The data source and data destination can be set as memory or device.
c. Only one way transport configuration is allowed.
ed
d. Provide DMA transmission pause, resume, and cancellation.。
w
e. Support DMA Burst length configuration.
lo
f. Provide DMA channel priority configuration.
al
g. When channel data is transmitted between devices, flow control can be controlled
t
no
by devices.
e
ar
h. Support hardware linked list function.
i. Channel locking is supported. Other channel requests will be ignored before
n
tio
channel locking is completed.

u
r ib

di V
st
re k-
d il
an M
3.6.3.1 Peripheral Request Line

n by
8 groups of DMA channels are built in DMA. Peripheral requests of each channel need
tio lic
to be configured to map to peripheral devices. Please refer to 3.5.2.4 System DMA

ca ub
Channel Mapping to configure before DMA channel is enabled.

ifi p
3.6.3.2 Access Space

od de
M a
Table 3- 6 DMAC Access Space Type

M
Space Type Description

Memory SRAM
Non secure DDR space
Peripherals UART0~UART3
I2C0~I2C4
SPI0~SPI3
SPI_NAND
I2S0~I2S3
124
CV1835
3.6.3.3 Basic Transmission
DMA data transmission is set by block transmission, which is completed by burst

transmission. The length of burst transmission can be set. However, what often happens
is that the block data volume is not perfectly an integer multiple of the burst
transmission length. The length of the last transaction of transmission is less than the
ed
set burst transmission length. In this case, it will need to use a single transmission
w
request to complete.
lo
al
The source and destination of the maximum 8 DMA channels can be in the following
t
four combinations.：
no
a. memory to memory
e
b. memory to device
c. Device to memory
ar
n
d. Device to device
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 3- 5 DMA Transmission Structure
The individual data transmission amount can be calculated from the values written by
the following registers.
 Transmission data amount from the source (bytes):
125
CV1835
src_single_size_bytes = CHx_CTL.SRC_TR_WIDTH/8
 Burst transmission data amount from the source(bytes):
src_burst_size_bytes = CHx_CTL.SRC_MSIZE * src_single_size_bytes
 Target transmission data amount(bytes):
dst_single_size_bytes = CHx_CTL.DST_TR_WIDTH/8
 Target burst transmission data amount(bytes):
ed
dst_burst_size_bytes = CHx_CTL.DST_MSIZE * dst_single_size_bytes
w
lo
The control right of transmission process can be controlled by DMA controller or
al
source device or destination device. When block of data is transmitted, the amount
t
no
of data transmitted is calculated as follows.
e
ar
 The DMA controller controls the transmission process:
blk_size_bytes_dma = CHx_BLOCK_TS.BLOCK_TS * src_single_size_bytes
n
tio
 The source device controls the transmission process:

blk_size_bytes_src = (number of block burst transmissions from source
u
ib
device * src_burst_size_bytes) + (number of independent transmission of

r
di V
st
source device block * src_single_size_bytes)

re k-
 The target device controls the transmission process:

d il
an M
blk_size_bytes_dst = (number of block burst transmissions from target

n by
device * dst_burst_size_bytes) + (number of independent transmission of

target device block * dst_single_size_bytes)
tio lic
ca ub
3.6.3.4 Linked-List Transmission

ifi p
Linked list transmission is used in block transmission which needs to carry out multiple
od de
discontinuous addresses. After each block data, there will be a linked list information to
M a
M
store the information of the next node, so that the data transmission can directly carry
out the block transmission of the next discontinuous space without the intervention of
CPU. Figure 3-6 shows the configuration format of linked list information, which must
conform to the information format to enter the linked list transmission work.
126
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
Figure 3- 6 Linked List Relative Address and Data Format

tio lic
3.6.3.5 Interrupt and Status

ca ub
The interrupt sources of DMAC are as follows.

ifi p
a. the completion of DMA transfer

od de
b. the completion of block transfer

M a
M
c. the completion of single transfer

d. internal error
e. the halt in channel or the termination of channels
127
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
Figure 3- 7 Interrupt Status and Source Diagram

ifi p
od de
M a
M
3.6.3.6 Channel Security Configuration
Channel security can be realized by awprot value and arprot value of each channel.
According to AXI protocol, when the channel is a secure channel, arprot or awprot value
should be 0x0, otherwise it is a non secure channel.
128
CV1835
3.6.4 Working Mode
3.6.4.1 Clock and Reset
The clock of DMAC passes through CLK_EN_1[1] after writing 0x1; the clock can work
normally. Writing 0x0 in REG_SOFT_RESET_X_SDMA_INIT can reset DMAC and writing
ed
0x1 to release reset.
w
lo
3.6.4.2 Initialization
al
After reset, it can be initialized following the steps below.
t
no
1. Peripheral Configuration: in the chapter of System DMA Channel Mapping,
the configuration method of DMA peripheral request line is described, and
e
ar
the mapping should be configurated according to the scenario.
n
2. Confirm that the channel is closed: write 0x0 to DMA_ChEnReg and confirm
tio
that the channel is closed.

u
3. Confirm the interrupt source: writing 0x0 to the register

ib
DMAC_COMMONREG_INTSIGNAL_ENABLEREG and
r
di V
st
CHx_INSTATUS_ENABLEREG to turn off all interrupt sources, and then writes

re k-
d il
0x1 to the required interrupt source to enable.

an M
4. Configure the channel priority: when multiple channels transmit data at the
n by
same time, it will determine the passing order based on the priority level.
The higher value configed in register CH_PRIOR , the higher priority the
tio lic
transmission is.
ca ub
ifi p
od de
3.6.4.3 Basic Transmission

M a
M
Up to 8 channels can be transmitted at the same time. After initialization, DMAC

channel must be enabled before data transmission starts. Refer to the following steps
for data transmission from internal memory to internal memory.
 Read register DMAC_ChEnReg to get the idle channel.
 Write 0x0 to channel register SRC_MULTBLK_TYPE and DST_MULTBLK_TYPE
respectively to configure for continuous block transmission.
129
CV1835
 Write 0x0 to the register TT_FC to configure the channel for memory to
memory data transmission.
 Write the transmitted information to the register CHx_SAR, CHx_ADR and
CHx_BLOCK_TS, CHx_CTL.
 Write 0x1 to the register DMAC_ChEnReg to enable the selected DMA channel.
 The software can obtain the status of BLOCK_TFR_DONE by interrupting or
ed
polling. When its value rises to 1, it means that the data transmission has been
w
completed. Afterwards, write 0x0 to DMAC_ChEnReg to close the channel and
lo
restore it to an idle channel.
al
t
3.6.4.4 Linked List Transmission
no
Linked list transmission does not limit the number of nodes. Except for the ending node,
e
ar
each node must have information pointing to the next node. The linked list
n
transmission can be completed by referring to the following steps.
tio
1. Read register DMAC_ChEnReg to get the idle channel.

u
2. Write 0x3 to channel register SRC_MULTBLK_TYPE and DST_MULTBLK_TYPE

ib
respectively to configure for linked list transmission.

r
di V
st
3. Configure register CHx_LLP, CHx_CTL.ShadowReg_Or_LLI_Valid and

re k-
d il
CHx_CTL.LLI_Last. Write the information needed to point to the first node.

an M
4. Write 0x1 to the register DMAC_ChEnReg to enable the selected DMA

n by
channel.
5. The software can obtain the status of BLOCK_TFR_DONE by interrupting or
tio lic
polling. When its value rises to 1, it means that the data transmission of the
ca ub
ending node has been completed. Afterwards, write 0x0 to DMAC_ChEnReg

ifi p
to close the channel and restore it to an idle channel.

od de
M a
M
3.6.4.5 Interrupt Handling
The processing after the interrupt is triggered are as follows.

1. Find out the interrupt source: read the register CHx_INTSTATUS and
DMAC_INSTATUSREG to get the interrupt source whose value is 0x1. When
an interrupt occurs, it will be recorded as 0x1 in the corresponding selected
130
CV1835
bit. If multiple interrupts occur at the same time, the software will serve
based on its priority.
2. Clear interrupt: write 0x1 to CHx_INTCLEARREG or the selected bit of

DMAC_INTCLEARREG. At this time, the recorded interrupt status of
CHx_INTSTATUS and DMAC_INSTATUSREG will return to 0x0 to record the
ed
next interrupt condition.
w
lo
al
3.6.5 DMAC Register
t
no
e
ar
DMAC_IDREG
n
tio
63:0 DMAC_IDREG RO DMAC ID Number
u
ib
DMAC_COMPVERREG
r
di V
st

re k-

d il
31:0 DMAC_COMPVER RO DMAC Component Version Number.

an M
DMAC_CFGREG
n by

tio lic

0 DMAC_EN R/W This bit is used to enable the 0x0
ca ub
DW_axi_dmac.
■ 0: DW_axi_dmac disabled
ifi p
■ 1: DW_axi_dmac enabled
od de
NOTE: If this bit DMAC_EN bit is cleared

while any channel
M a
is still active, then this bit still returns 1

M
to indicate that there

are channels still active until
DW_axi_dmac hardware has
terminated all activity on all channels,
at which point this bit
returns zero (0).
1 INT_EN R/W This bit is used to globally enable the 0x0
interrupt generation.
■ 0: DW_axi_dmac Interrupts are
disabled
■ 1: DW_axi_dmac Interrupt logic is
enabled.
31:2 Reserved
131
CV1835
DMAC_CHENREG
0 CH1_EN R/W This bit is used to enable the 0x0
DW_axi_dmac Channel-1.
■ 0: DW_axi_dmac Channel-1 is
disabled
enabled
ed
The bit 'DMAC_ChEnReg.CH1_EN' is
automatically cleared
w
by hardware to disable the channel
lo
after the last AMBA
transfer of the DMA transfer to the
al
destination has
completed. Software can therefore poll
t
no
this bit to determine
when this channel is free for a new
DMA transfer.
e
ar
n
disabled
tio
enabled
u

ib
r

di V
st
after the last AMBA

re k-

destination has
d il
an M

n by
DMA transfer.
tio lic
ca ub
disabled
ifi p
enabled
od de

M a

M
after the last AMBA

destination has
DMA transfer.
disabled
enabled
132
CV1835

after the last AMBA
destination has
ed
DMA transfer.
w
lo
disabled
al
enabled
t
no
e
after the last AMBA
ar
destination has
n
tio
u
DMA transfer.
ib

r
di V
st
re k-
disabled
d il
enabled
an M

n by

after the last AMBA
tio lic

destination has
ca ub

ifi p

DMA transfer.
od de

M a
M
disabled
enabled
after the last AMBA
destination has
133
CV1835

DMA transfer.
disabled
enabled
ed
after the last AMBA
w
lo
destination has
al
t
DMA transfer.
no
8 CH1_EN_WE WO DW_axi_dmac Channel-1 Enable Write 0x0
Enable bit.
e
Read back value of this register bit is
ar
always '0'.
n
tio
Enable bit.
u
always '0'.
r ib

di V
st
Enable bit.
re k-

d il
always '0'.
an M

n by
Enable bit.
always '0'.
tio lic
ca ub

Enable bit.
ifi p

always '0'.
od de
M a

M
Enable bit.
always '0'.

Enable bit.
always '0'.

Enable bit.
134
CV1835

always '0'.
16 CH1_SUSP R/W Channel-1 Suspend Request. 0x0

Software sets this bit to 1 to request
channel suspend. If this
bit is set to 1, DW_axi_dmac suspends
all DMA data
transfers from the source gracefully
until this bit is cleared.
ed
There is no guarantee that the current
dma transaction will
w
complete. This bit can also be used in
lo
conjunction with
CH1_Status.CH_SUSPENDED to cleanly
al
disable the
channel without losing any data. In this
t
no
case, software first
sets CH1_SUSP bit to 1 and polls
CH1_Status.CH_SUSPENDED till it is set
e
to 1. Software can
ar
then clear CH1_EN bit to 0 to disable
the channel.
n
■ 0: No Channel Suspend Request.
tio
■ 1: Request for Channel Suspend.

Software can clear CH1_SUSP bit to 0,
u
after DW_axi_dmac
ib
sets CH1_Status.CH_SUSPENDED bit to

1, to exit the
r
di V
st
channel suspend mode.

re k-
Note: CH_SUSP is cleared when channel

is disabled.
d il
an M

n by

all DMA data
tio lic

ca ub

ifi p

od de
conjunction with
M a
disable the
M

to 1. Software can
the channel.
after DW_axi_dmac
1, to exit the
135
CV1835

is disabled.
all DMA data
ed
w
lo
conjunction with
al
disable the
t
no
e
ar
to 1. Software can
n
the channel.
tio
u

ib
after DW_axi_dmac
r
di V
1, to exit the
st
re k-

d il
is disabled.
an M

n by

tio lic
all DMA data

ca ub

ifi p

od de
conjunction with
M a
M
disable the
to 1. Software can
the channel.
after DW_axi_dmac
136
CV1835

1, to exit the
is disabled.
all DMA data
ed
w
lo
al
conjunction with
t
disable the
no
e
ar
to 1. Software can
n
tio
the channel.
u

ib

after DW_axi_dmac
r
di V

st
re k-
1, to exit the
d il

an M
is disabled.
n by

tio lic

all DMA data
ca ub

ifi p

od de

conjunction with
M a
M
disable the
to 1. Software can
the channel.
after DW_axi_dmac
137
CV1835

1, to exit the
is disabled.
ed
all DMA data
w
lo
al
conjunction with
t
no
disable the
e
ar
n
to 1. Software can
tio
the channel.
u
ib

r
di V
after DW_axi_dmac
st
re k-

1, to exit the
d il

an M

is disabled.
n by

tio lic

ca ub
all DMA data

ifi p

od de

M a
M
conjunction with
disable the
to 1. Software can
the channel.
138
CV1835

after DW_axi_dmac
1, to exit the
is disabled.
24 CH1_SUSP_WE WO This bit is used as a write enable to the 0x0
Channel-1 Suspend
bit. The read back value of this register
ed
bit is always 0.
w
Channel-2 Suspend
lo
bit is always 0.
al
Channel-3 Suspend
t
no
bit is always 0.
e
Channel-4 Suspend
ar
bit is always 0.
n
tio
Channel-5 Suspend
u
bit is always 0.
ib

Channel-6 Suspend
r
di V
st

re k-
bit is always 0.
d il
Channel-7 Suspend
an M

bit is always 0.
n by

Channel-8 Suspend
tio lic

bit is always 0.
ca ub
32 CH1_ABORT R/W Channel-1 Abort Request. 0x0

ifi p
channel abort. If this bit

od de
is set to 1, DW_axi_dmac disables the

channel immediately.
M a
Aborting the channel might result in AXI

M
Protocol violation as
DW_axi_dmac does not make sure that
all AXI transfers
initiated on the master interface are
completed.Aborting the
channel is not recommended and
should be used only in
situations where a particular channel
hangs due to no
response from the corresponding AXI
slave interface and
software wants to disable the channel
without resetting the
139
CV1835

entire DW_axi_dmac. It is
recommended to try channel
disabling first and then only opt for
channel aborting.
■ 0: No Channel Abort Request.
■ 1: Request for Channel Abort.
DW_axi_dmac clears this bit to 0 once
the channel is
aborted (when it sets
ed
CH1_Status.CH_ABORTED bit to 1).
w
lo
al
t
no
all AXI transfers
e
ar
n
tio
hangs due to no
u

ib
slave interface and

r
di V

st
re k-
d il

an M
channel aborting.
n by

tio lic
the channel is
ca ub

ifi p

od de

M a
M

all AXI transfers
hangs due to no
slave interface and
140
CV1835

channel aborting.
the channel is
ed
w
lo
al
t
no
e
all AXI transfers
ar
n
tio
u
hangs due to no
ib

slave interface and
r
di V

st
re k-

d il

an M

channel aborting.
n by

tio lic

the channel is
ca ub

ifi p

od de

M a

M
all AXI transfers
hangs due to no
slave interface and
141
CV1835

channel aborting.
ed
the channel is
w
lo
al
t
no
e
ar
all AXI transfers
n
tio
u

ib
hangs due to no
r
di V
slave interface and

st
re k-

d il
an M

n by
channel aborting.
tio lic

ca ub
the channel is
ifi p

od de

M a

M

all AXI transfers
hangs due to no
142
CV1835

slave interface and
channel aborting.
ed
the channel is
w
lo
al
t
no
e
ar
all AXI transfers
n
tio
u

ib

hangs due to no
r
di V

st
re k-
slave interface and

d il

an M
n by

channel aborting.
tio lic

ca ub

the channel is
ifi p

od de
40 CH1_ABORT_WE R/W This bit is used to write enable the 0x0

M a
Channel-1 Abort bit.

M
The read back value of this register bit is

always 0.
always 0.
always 0.
143
CV1835

always 0.
always 0.
always 0.
ed
w
lo
always 0.
al
t
always 0.
no
63:48 RSVD_DMAC_CHENREG RO DMAC_CHENREG Reserved bits
e
ar
DMAC_INTSTATUSREG
n
tio
0 CH1_IntStat RO Channel 1 Interrupt Status Bit.

u
ib

r

di V
st

re k-

d il
an M

n by
15:8 Reserved
16 CommonReg_IntStat RO Common Register Interrupt Status Bit.
tio lic
31:17 Reserved
ca ub
DMAC_COMMONREG_INTCLEARREG
ifi p

od de

0 Clear_SLVIF_CommonReg_DEC_ERR WO Slave Interface Common Register 0x0
M a
_IntStat Decode Error Interrupt

M
clear Bit.
This bit is used to clear the
corresponding channel interrupt
status bit
(SLVIF_CommonReg_DEC_ERR_IntStat
in
DMAC_CommonReg_IntStatusReg.
1 Clear_SLVIF_CommonReg_WR2RO_ WO Slave Interface Common Register Write 0x0
ERR_IntStat to Read only Error
Interrupt clear Bit.
144
CV1835

status
bit(SLVIF_CommonReg_WR2RO_ERR_In
tStat in
2 Clear_SLVIF_CommonReg_RD2WO_ WO Slave Interface Common Register Read 0x0
ERR_IntStat to Write only Error
ed
status
bit(SLVIF_CommonReg_RD2WO_ERR_In
w
tStat in
lo
3 Clear_SLVIF_CommonReg_WrOnHol WO Slave Interface Common Register Write 0x0
al
d_ERR_IntStat On Hold Error
t
no
status
e
bit(SLVIF_CommonReg_WrOnHold_ERR
ar
_IntStat in
n
7:4 Reserved
tio
8 Clear_SLVIF_UndefinedReg_DEC_ER WO Slave Interface Undefined register 0x0

R_IntStat Decode Error Interrupt
u
clear Bit.
ib

r
di V
st
status
re k-
bit(SLVIF_UndefinedReg_DEC_ERR_IntSt
at in
d il
an M
31:9 Reserved
n by
DMAC_COMMONREG_INTSTATUS_ENA
tio lic
BLEREG
ca ub

ifi p
0 Enable_SLVIF_CommonReg_DEC_ER R/W Slave Interface Common Register 0x0

od de
R_IntStat Decode Error Interrupt

Status Enable Bit.
M a
This bit is used to enable the

M
corresponding channel
interrupt status bit
in DMAC_CommonReg_IntStatusReg.
1 Enable_SLVIF_CommonReg_WR2RO R/W Slave Interface Common Register Write 0x0
_ERR_IntStat to Read only Error
Interrupt Status Enable Bit.
(SLVIF_CommonReg_WR2RO_ERR_IntSt
at in
145
CV1835

2 Enable_SLVIF_CommonReg_RD2WO R/W Slave Interface Common Register Read 0x0
_ERR_IntStat to Write only Error
(SLVIF_CommonReg_RD2WO_ERR_IntSt
at in
ed
3 Enable_SLVIF_CommonReg_WrOnH R/W Slave Interface Common Register Write 0x0
old_ERR_IntStat On Hold Error
w
lo
al
(SLVIF_CommonReg_WrOnHold_ERR_In
t
tStat in
no
7:4 Reserved
e
8 Enable_SLVIF_UndefinedReg_DEC_E R/W Slave Interface Undefined register 0x0
ar
RR_IntStat Decode Error Interrupt
Status enable Bit.
n
tio
u
(SLVIF_UndefinedReg_DEC_ERR_IntStat
ib
in
r
di V
st
31:9 Reserved
re k-
d il
DMAC_COMMONREG_INTSIGNAL_ENA
an M
BLEREG
n by

tio lic
0 Enable_SLVIF_CommonReg_DEC_ER R/W Slave Interface Common Register 0x0

ca ub
R_IntSignal Decode Error Interrupt

Signal Enable Bit.
ifi p

propagation of corresponding
od de
channel interrupt status bit

M a
in
M
DMAC_CommonReg_IntStatusReg) to
generate a port level
interrupt.
1 Enable_SLVIF_CommonReg_WR2RO R/W Slave Interface Common Register Write 0x0
_ERR_IntSignal to Read only Error
Interrupt Signal Enable Bit.
(SLVIF_CommonReg_WR2RO_ERR_IntSt
at in
146
CV1835

interrupt.
2 Enable_SLVIF_CommonReg_RD2WO R/W Slave Interface Common Register Read 0x0
_ERR_IntSignal to Write only Error
(SLVIF_CommonReg_RD2WO_ERR_IntSt
at in
ed
w
interrupt.
3 Enable_SLVIF_CommonReg_WrOnH R/W Slave Interface Common Register Write 0x0
lo
old_ERR_IntSignal On Hold Error
al
t
no
channel interrupt status
bit(SLVIF_CommonReg_WrOnHold_ERR
e
_IntStat in
ar
n
interrupt.
tio
7:4 Reserved
8 Enable_SLVIF_UndefinedReg_DEC_E R/W Slave Interface Undefined register 0x0
u
RR_IntSignal Decode Error Interrupt

ib
Signal Enable Bit.

r
di V
st
re k-
channel interrupt status

bit(SLVIF_UndefinedReg_DEC_ERR_IntSt
d il
an M
at in
n by
interrupt.
31:9 Reserved
tio lic
ca ub
DMAC_COMMONREG_INTSTATUSREG
ifi p

od de
0 SLVIF_CommonReg_DEC_ERR_IntSt RO Slave Interface Common Register

at Decode Error Interrupt
M a
Status Bit.
M
Decode Error generated by

DW_axi_dmac during register
access. This error occurs if the register
access is to an
invalid address in the common register
space (0x000 to
0x0FF) resulting in error response by
DW_axi_dmac slave
interface.
■ 0: No Slave Interface Decode Errors.
■ 1: Slave Interface Decode Error
detected.
147
CV1835

The Error Interrupt status is generated if
the corresponding
Status Enable bit in
DMAC_CommonReg_IntStatus_Enable
register bit is set to 1. This bit is cleared
to 0 on writing 1 to
the corresponding channel interrupt
clear bit in
DMAC_COMMONREG_INTCLEARREG on
ed
enabling the
channel (required when the interrupt is
w
not enabled).
lo
1 SLVIF_CommonReg_WR2RO_ERR_In RO Slave Interface Common Register Write
tStat to Read Only Error
al
Interrupt Status bit.
This error occurs if write operation is
t
performed to a Read
no
Only register in the common register
space (0x000 to
e
0x0FF).
ar
■ 0: No Slave Interface Write to Read
Only Errors.
n
■ 1: Slave Interface Write to Read Only
tio
Error detected.
Error Interrupt status is generated if the
u
corresponding
ib

r
di V
st

re k-
d il
clear bit in
an M
enabling the
n by

not enabled).
tio lic
2 SLVIF_CommonReg_RD2WO_ERR_I RO Slave Interface Common Register Read

ntStat to Write only Error
ca ub
Interrupt Status bit.

This error occurs if Read operation is
ifi p
performed to a Write
Only register in the common register
od de
space (0x000 to
M a
0x0FF).
M
■ 0: No Slave Interface Read to Write

Only Errors.
■ 1: Slave Interface Read to Write Only
Error detected.
Error Interrupt status is generated if the
corresponding
clear bit in
148
CV1835

enabling the
not enabled).
Values:
■ 0x1
(Active_CommonReg_RD2WO_ERR):
Slave
Interface Read to Write Only Error
detected
ed
■ 0x0
(Inactive_CommonReg_RD2WO_ERR):
w
No Slave
lo
Interface Read to Write Only Errors
3 SLVIF_CommonReg_WrOnHold_ERR RO Slave Interface Common Register Write
al
_IntStat On Hold Error
Interrupt Status Bit.
t
This error occurs if an illegal write
no
operation is performed on
a common register; this happens if a
e
write operation is
ar
performed on a common register except
DMAC_RESETREG with DMAC_RST field
n
set to 1 when
tio
DW_axi_dmac is in Hold mode.
■ 0: No Slave Interface Common
u
Register Write On Hold

ib
Errors.
■ 1: Slave Interface Common Register
r
di V
st
Write On Hold Error

re k-
detected.
Error Interrupt Status is generated if the
d il
corresponding
an M

n by

tio lic

clear bit in
ca ub
enabling the
ifi p

not enabled).
od de
7:4 Reserved
M a
8 SLVIF_UndefinedReg_DEC_ERR_IntS RO Slave Interface Undefined register

M
tat Decode Error Interrupt

Signal Enable Bit.
access is to
undefined address range (>0x8FF if 8
channels are
configured, >0x4FF if 4 channels are
configured etc.)
resulting in error response by
DW_axi_dmac slave interface.
■ 0: No Slave Interface Decode Errors.
149
CV1835

■ 1: Slave Interface Decode Error
detected.
Error Interrupt Status is generated if the
corresponding
ed
clear bit in
w
enabling the
lo
not enabled).
al
31:9 Reserved
t
no
DMAC_RESETREG
e
ar
0 DMAC_RST R/W DMAC Reset Request bit 0x0
Software writes 1 to this bit to reset the
n
DW_axi_dmac and
tio
polls this bit to see it as 0.

DW_axi_dmac resets all the
u
modules except the slave bus interface

ib
module and clears

r
this bit to 0.
di V
st
NOTE: Software is not allowed to write

re k-
0 to this bit.
d il
31:1 Reserved
an M
CHx_SAR
n by

tio lic

63:0 SAR R/W Current Source Address of DMA 0x0
ca ub
transfer.
Updated after each source transfer. The
ifi p
SINC fields in the

CHx_CTL register determines whether
od de
the address
M a
increments or is left unchanged on

M
every source transfer

throughout the block transfer.
CHx_DAR
63:0 DAR R/W Current Destination Address of DMA 0x0
transfer.
Updated after each destination transfer.
The DINC fields in
the CHx_CTL register determines
whether the address
150
CV1835

increments or is left unchanged on
every destination transfer
CHx_BLOCK_TS
21:0 BLOCK_TS R/W Block Transfer Size. 0x0
ed
The number programmed into
BLOCK_TS field indicates the
w
total number of data of width
lo
CHx_CTL.SRC_TR_WIDTH to
be transferred in a DMA block transfer.
al
Block Transfer Size = BLOCK_TS+1
t
When the transfer starts, the read-back
no
value is the total
number of data items already read from
the source
e
peripheral, regardless of who is the flow
ar
controller. When the
source or destination peripheral is
n
assigned as the flow
tio
controller, the value before the transfer

starts saturates at
u
DMAX_CHx_MAX_BLK_SIZE, but the

ib
actual block size can

be greater.
r
di V
st
31:22 Reserved
re k-
d il
CHx_CTL
an M

n by

0 SMS R/W Source Master Select. 0x0
tio lic
Identifies the Master Interface layer

from which the source
ca ub
device (peripheral or memory) is

accessed.
ifi p
■ 0: AXI master 1
■ 1: AXI Master 2
od de
1 Reserved
M a
2 DMS R/W Destination Master Select. 0x0

M
Identifies the Master Interface layer

from which the
destination device (peripheral or
memory) is accessed.
■ 0: AXI master 1
■ 1: AXI Master 2
3 Reserved
4 SINC R/W Source Address Increment. 0x0
Indicates whether to increment the
source address on every
source transfer. If the device is fetching
data from a source
peripheral FIFO with a fixed address,
151
CV1835

then set this field to 'No
change'.
■ 0: Increment
■ 1: No Change
5 Reserved
6 DINC R/W Destination Address Increment. 0x0
Indicates whether to increment the
destination address on
every destination transfer. If the device
ed
is writing data from a
source peripheral FIFO with a fixed
w
address, then set this
lo
field to 'No change'.
■ 0: Increment
al
■ 1: No Change
t
7 Reserved
no
10:8 SRC_TR_WIDTH R/W Source Transfer Width. 0x0
Mapped to AXI bus arsize, this value
e
must be less than or
ar
equal to DMAX_M_DATA_WIDTH.
13:11 DST_TR_WIDTH R/W Destination Transfer Width. 0x0
Mapped to AXI bus awsize, this value
n
must be less than or
tio
equal to DMAX_M_DATA_WIDTH.
17:14 SRC_MSIZE R/W Source Burst Transaction Length. 0x0
u
Number of data items, each of width

ib
CHx_CTL.SRC_TR_WIDTH, to be read
r
from the source

di V
st
every time a source burst transaction

re k-
request is made from

d il
the corresponding hardware or

an M
software handshaking
interface. The maximum value of
n by
DST_MSIZE is limited by
DMAX_CHx_MAX_MULT_SIZE.
21:18 DST_MSIZE R/W Destination Burst Transaction Length. 0x0
tio lic
Number of data items, each of width

ca ub
CHx_CTL.DST_TR_WIDTH, to be written
to the destination
ifi p
every time a destination burst

transaction request is made
od de
from the corresponding hardware or

M a
interface.Note: This Value is not related

M
to the AXI awlen

signal.
25:22 AR_CACHE R/W AXI 'ar_cache' signal 0x0
29:26 AW_CACHE R/W AXI 'aw_cache' signal 0x0
30 NonPosted_LastWrite_En R/W Non Posted Last Write Enable 0x0
This bit decides whether posted writes
can be used
■ 0: Posted writes may be used
throughout the block
transfer.
■ 1: Posted writes may be used till the
152
CV1835

end of the block
(inside a block) and the last write in the
block must be
non-posted. This is to synchronize block
completion
interrupt generation to the last write
data reaching the
end memory/peripheral.
31 Reserved
ed
34:32 AR_PROT R/W AXI 'ar_prot' signal 0x0
37:35 AW_PROT R/W AXI 'aw_prot' signal 0x0
w
38 ARLEN_EN R/W Source Burst Length Enable 0x0
lo
If this bit is set to 1, DW_axi_dmac uses
the value of
al
CHx_CTL.ARLEN as AXI Burst length for
source data
t
no
transfer till the extent possible;
remaining transfers use
maximum possible burst length.
e
ar
any possible value
that is less than or equal to
n
DMAX_CHx_MAX_AMBA_BURST_LENG
tio
TH as AXI Burst
length for source data transfer.
u
46:39 ARLEN R/W Source Burst Length 0x0

ib
AXI Burst length used for source data

transfer. The specified
r
di V
st
burst length is used for source data

re k-
transfer till the extent

possible; remaining transfers use
d il
an M
maximum possible value

that is less than or equal to
n by
TH.
The maximum value of ARLEN is limited
tio lic
by
ca ub
TH
47 AWLEN_EN R/W Destination Burst Length Enable 0x0
ifi p

od de
the value of
CHx_CTL.AWLEN as AXI Burst length for
M a
destination data
M
transfer till the extent possible;

remaining transfers use
maximum possible burst length.
any possible value
which is less than or equal to
TH as AXI Burst
length for destination data transfer.
55:48 AWLEN RO Destination Burst Length
AXI Burst length used for destination
data transfer. The
specified burst length is used for
153
CV1835

destination data transfer till
the extent possible; remaining transfers
use maximum
possible value that is less than or equal
to
TH.
The maximum value of AWLEN is limited
by
ed
TH.
w
56 SRC_STAT_EN R/W Source Status Enable 0x0
Enable the logic to fetch status from
lo
source peripheral of
al
channel x pointed to by the content of
CHx_SSTATAR
t
register and stores it in CHx_SSTAT
no
register. This value is
written back to the CHx_SSTAT location
e
of linked list at end
ar
of each block transfer if
DMAX_CHx_LLI_WB_EN is set to 1
n
and if linked list based multi-block
tio
transfer is used by either
source or destination peripheral.
57 DST_STAT_EN R/W Destination Status Enable 0x0
u
Enable the logic to fetch status from

ib
destination peripheral of
r
di V
channel x pointed to by the content of

st
re k-
CHx_DSTATAR
register and stores it in CHx_DSTAT
d il
register. This value is

an M
written back to the CHx_DSTAT location

of linked list at end
n by
of each block transfer if

DMAX_CHx_LLI_WB_EN is set to 1
tio lic
and if linked list based multi-block

transfer is used by either
ca ub
source or destination peripheral.

58 IOC_BlkTfr R/W Interrupt On completion of Block 0x0
ifi p
Transfer
This bit is used to control the block
od de
transfer completion
interrupt generation on a block by block
M a
basis for shadow

M
register or linked list based multi-block

transfers. Writing 1 to
this register field enables
CHx_IntStatusReg.BLOCK_TFR_DONE_In
tStat field if this
interrupt generation is enabled in
CHx_IntStatus_EnableReg
register and the external interrupt
output is is asserted if this
interrupt generation is enabled in
CHx_IntSignal_EnableReg
register.
154
CV1835

61:59 Reserved
62 SHADOWREG_OR_LLI_LAST R/W Last Shadow Register/Linked List Item. 0x0
Indicates whether shadow register
content or the linked list
item fetched from the memory is the
last one or not.
■ 0: Not last Shadow Register/LLI
■ 1: Last Shadow Register/LLI
63 SHADOWREG_OR_LLI_VALID R/W Shadow Register content/Linked List 0x0
ed
Item valid.
Indicates whether the content of
w
shadow register or the
lo
linked list item fetched from the
al
memory is valid.
■ 0: Shadow Register content/LLI is
t
invalid.
no
■ 1: Last Shadow Register/LLI is valid.
e
ar
CHx_CFG
n
tio
1:0 SRC_MULTBLK_TYPE RO Source Multi Block Transfer Type.
u
These bits define the type of multi-block

ib
transfer used for

source peripheral.
r
di V
st
■ 00: Contiguous
re k-
■ 01: Reload
■ 10: Shadow Register
d il
an M
■ 11: Linked List

If the type selected is Contiguous, the
CHx_SAR register is
n by
loaded with the value of the end source

address of previous
tio lic
block + 1 at the end of every block for

multi-block transfers. A
ca ub
new block transfer is then initiated.

If the type selected is Reload, the
ifi p
CHx_SAR register is
od de
reloaded from the initial value of SAR at

the end of every
M a
block for multi-block transfers. A new

M
block transfer is then

initiated.
If the type selected is Shadow Register,
the CHx_SAR
register is loaded from the content of its
shadow register if
CHx_CTL.ShadowReg_Or_LLI_Valid bit is
set to 1 at the
end of every block for multi-block
transfers. A new block
transfer is then initiated.
If the type selected is Linked List, the
CHx_SAR register is
155
CV1835

loaded from the Linked List if
CTL.ShadowReg_Or_LLI_Valid bit is set
to 1 at the end of
every block for multi-block transfers. A
new block transfer is
then initiated.
CHx_CTL and CHx_BLOCK_TS registers
are loaded from
their initial values or from the contents
ed
of their shadow
registers (if
w
set to
lo
1) or from the linked list (if
al
CTL.ShadowReg_Or_LLI_Valid
bit is set to 1) at the end of every block
t
for multi-block
no
transfers based on the multi-block
transfer type programmed
e
for source and destination peripherals.
ar
Contiguous transfer on both source and
destination
n
peripheral is not a valid multi-block
tio
transfer configuration.
This field does not exist if the
configuration parameter
u
DMAX_CHx_MULTI_BLK_EN is not
ib
selected; in that case,

r
di V
the read-back value is always 0.

st
re k-
Values:
■ 0x0 (CONTINGUOUS): Contiguous
d il
Multiblock Type used

an M
for Source Transfer

■ 0x1 (RELOAD): Reload Multiblock
n by
Type used for Source

Transfer
tio lic
■ 0x2 (SHADOW_REGISTER): Shadow

Register based
ca ub
Multiblock Type used for Source

Transfer
ifi p
■ 0x3 (LINKED_LIST): Linked List based

Multiblock Type
od de
used for Source Transfer

M a
3:2 DST_MULTBLK_TYPE R/W Destination Multi Block Transfer Type. 0x0

M
These bits define the type of multi-block

transfer used for
destination peripheral.
■ 00: Contiguous
■ 01: Reload
■ 10: Shadow Register
■ 11: Linked List
If the type selected is Contiguous, the
CHx_DAR register is
loaded with the value of the end source
address of previous
block + 1 at the end of every block for
multi-block transfers. A
156
CV1835

new block transfer is then initiated.
If the type selected is Reload, the
CHx_DAR register is
reloaded from the initial value of DAR at
the end of every
block for multi-block transfers. A new
block transfer is then
initiated.
If the type selected is Shadow Register,
ed
the CHx_DAR
register is loaded from the content of its
w
shadow register if
lo
set to 1 at the
al
end of every block for multi-block
transfers. A new block
t
transfer is then initiated.
no
If the type selected is Linked List, the
CHx_DAR register is
e
loaded from the Linked List if
ar
CTL.ShadowReg_Or_LLI_Valid bit is set
to 1 at the end of
n
every block for multi-block transfers. A
tio
new block transfer is
then initiated.
CHx_CTL and CHx_BLOCK_TS registers
u
are loaded from

ib
their initial values or from the contents

r
di V
of their shadow
st
re k-
registers (if
d il
set to
an M
1) or from the linked list (if

CTL.ShadowReg_Or_LLI_Valid
n by
bit is set to 1) at the end of every block

for multi-block
transfers based on the multi-block
tio lic
transfer type programmed

ca ub
for source and destination peripherals.

Contiguous transfer on both source and
ifi p
destination
peripheral is not a valid multi-block
od de
transfer configuration.
M a
M
DMAX_CHx_MULTI_BLK_EN is not
selected; in that case,
the read-back value is always 0.
Values:
■ 0x0 (CONTINGUOUS): Contiguous
Multiblock Type used
for Destination Transfer
■ 0x1 (RELOAD): Reload Multiblock
Type used for
Destination Transfer
■ 0x2 (SHADOW_REGISTER): Shadow
Register based
157
CV1835

Multiblock Type used for Destination
Transfer
■ 0x3 (LINKED_LIST): Linked List based
Multiblock Type
used for Destination Transfer
31:4 Reserved
34:32 TT_FC R/W Transfer Type and Flow Control. 0x0
The following transfer types are
supported.
ed
■ Memory to Memory
■ Memory to Peripheral
w
■ Peripheral to Memory
lo
■ Peripheral to Peripheral
al
Flow Control can be assigned to the
DW_axi_dmac, the
t
source peripheral, or hte destination
no
peripheral.
Values:
■ 0x0 (MEM_TO_MEM_DMAC):
e
Transfer Type is memory
ar
to memory and Flow Controller is
DW_axi_dmac
n
■ 0x1 (MEM_TO_PER_DMAC): Transfer
tio
Type is memory to
peripheral and Flow Controller is
u
DW_axi_dmac
ib
■ 0x2 (PER_TO_MEM_DMAC): Transfer

r
Type is peripheral
di V
st
to memory and Flow Controller is

re k-
DW_axi_dmac
d il
■ 0x3 (PER_TO_PER_DMAC): Transfer

an M
Type is peripheral
to peripheral and Flow Controller is
n by
DW_axi_dmac
■ 0x4 (PER_TO_MEM_SRC): Transfer
Type is peripheral to
tio lic
Memory and Flow Controller is Source

ca ub
peripheral
■ 0x5 (PER_TO_PER_SRC): Transfer
ifi p
peripheral and Flow Controller is Source
od de
peripheral
■ 0x6 (MEM_TO_PER_DST): Transfer
M a
Type is memory to
M

Destination peripheral
■ 0x7 (PER_TO_PER_DST): Transfer
Destination peripheral
35 HS_SEL_SRC R/W Source Software or Hardware 0x0
Handshaking Select.
This register selects which of the
handshaking interfaces
(hardware or software) is active for
source requests on this
158
CV1835

channel.
■ 0: Hardware handshaking interface.
Software-initiated
transaction requests are ignored.
■ 1: Software handshaking interface.
Hardware-initiated
If the source peripheral is memory, then
this bit is ignored.
ed
36 HS_SEL_DST R/W Destination Software or Hardware 0x0
Handshaking Select.
w
This register selects which of the
lo
handshaking interfaces
(hardware or software) is active for
al
destination requests on
this channel.
t
no
■ 0: Hardware handshaking interface.
Software-initiated
e
■ 1: Software handshaking interface.
ar
Hardware-initiated
n
If the destination peripheral is memory,
tio
then this bit is

ignored.
u
37 SRC_HWHS_POL RO Source Hardware Handshaking Interface

ib
Polarity.
■ 0: ACTIVE HIGH
r
di V
st
■ 1: ACTIVE LOW
re k-
38 DST_HWHS_POL RO Destination Hardware Handshaking

Interface Polarity.
d il
an M
■ 0: ACTIVE HIGH
■ 1: ACTIVE LOW
n by
39 SRC_PER R/W Assigns a hardware handshaking 0x0

interface (0 -
DMAX_NUM_HS_IF-1) to the source of
tio lic
Channelx if the
CHx_CFG.HS_SEL_SRC field is 0;
ca ub
otherwise, this field is

ignored. The channel can then
ifi p
communicate with the source

od de
peripheral connected to that interface

through the assigned
M a
hardware handshaking interface.

M
Reset Value = 1
Note: For correct DW_axi_dmac
operation, only one
peripheral (source or destination)
should be assigned to the
same handshaking interface.
43:40 Reserved
44 DST_PER R/W Assigns a hardware handshaking 0x0
interface (0 -
DMAX_NUM_HS_IF-1) to the
destination of Channelx if the
CHx_CFG.HS_SEL_DST field is 0;
otherwise, this field is
159
CV1835

ignored. The channel can then
communicate with the
destination peripheral connected to
that interface through the
assigned hardware handshaking
interface.
Reset Value = 1
Note: For correct DW_axi_dmac
operation, only one
ed
peripheral (source or destination)
should be assigned to the
w
same handshaking interface.
48:45 Reserved
lo
51:49 CH_PRIOR R/W Channel Priority 0x0
al
A priority of 7 is the highest priority, and
0 is the lowest. This
t
no
field must be programmed within the
following range:
0: DMAX_NUM_CHANNELS-1
e
A programmed value outside this range
ar
will cause erroneous
behavior.
n
52 LOCK_CH R/W Channel Lock bit 0x0
tio
When the channel is granted control of

the master bus
u
interface and if the CHx_CFG.LOCK_CH

ib
bit is asserted,
then no other channels are granted
r
di V
st
control of the master bus

re k-
interface for the duration specified in

CHx_CFG.LOCK_CH_L. Indicates to the
d il
master bus
an M
interface arbiter that this channel wants

exclusive access to
n by
the master bus interface for the

duration specified in
tio lic
CHx_CFG.LOCK_CH_L.
ca ub
DMAX_CHx_LOCK_EN is set to False; in
ifi p
this case, the

read-back value is always 0.
od de
Locking the channel locks AXI Read

M a
Address, Write Address

M
and Write Data channels on the

corresponding master
interface.
Note: Channel locking feature is
supported only for memoryto-
memory transfer at Block Transfer and
DMA Transfer
levels. Hardware does not check for the
validity of channel
locking setting, hence the software
must take care of
enabling the channel locking only for
memory-to-memory
160
CV1835

transfers at Block Transfer or DMA
Transfer levels. Illegal
programming of channel locking might
result in unpredictable
behavior.
54:53 LOCK_CH_L R/W Channel Lock Level 0x0
This bit indicates the duration over
which
CHx_CFG.LOCK_CH bit applies.
ed
■ 00: Over complete DMA transfer
■ 01: Over DMA block transfer
w
■ 1x: Reserved
lo
al
DMAX_CHx_LOCK_EN is set to False; in
that case, the
t
no
read-back value is always 0.
58:55 SRC_OSR_LMT R/W Source Outstanding Request Limit 0x0
■ Maximum outstanding request
e
supported is 16.
ar
■ Source Outstanding Request Limit =
SRC_OSR_LMT + 1
n
62:59 DST_OSR_LMT R/W Destination Outstanding Request Limit 0x0
tio
■ Maximum outstanding request

supported is 16.
u
■ Source Outstanding Request Limit =

ib
DST_OSR_LMT + 1
r
63 Reserved
di V
st
re k-
CHx_LLP
d il
an M

n by
0 LMS R/W LLI master Select 0x0

This bit identifies the AXI layer/interface
tio lic
where the memory

device that stores the next linked list
ca ub
item resides. - 0: AXI

Master 1
ifi p
■ 1: AXI Master 2
od de
DMAX_CHx_LMS is not set to
M a
M
NO_HARDCODE.
5:1 Reserved
63:6 LOC R/W Starting Address Memory of LLI block 0x0
Starting Address In Memory of next LLI
if block chaining is
enabled. The six LSBs of the starting
address are not stored
because the address is assumed to be
aligned to a 64-byte
boundary.
LLI access always uses the burst size
(arsize/awsize) that is
same as the data bus width and cannot
161
CV1835

be changed or
programmed to anything other than
this. Burst length
(awlen/arlen) is chosen based on the
data bus width so that
the access does not cross one complete
LLI structure of 64
bytes. DW_axi_dmac will fetch the
entire LLI (40 bytes) in
ed
one AXI burst if the burst length is not
limited by other
w
settings.
lo
CHx_STATUSREG
al
t
no
21:0 CMPLTD_BLK_TFR_SIZE RO Completed Block Transfer Size.
This bit indicates the total number of
e
data of width
ar
CHx_CTL.SRC_TR_WIDTH transferred for
the previous
n
block transfer.
tio
31:22 Reserved
46:32 DATA_LEFT_IN_FIFO RO Data Left in FIFO.
u
This bit indicates the total number of

ib
data left in
r
DW_axi_dmac channel FIFO after

di V
st
completing the current

re k-
block transfer.
d il
63:47 Reserved
an M
CHx_SWHSSRCREG
n by

tio lic

0 SWHS_REQ_SRC R/W Software Handshake Request for 0x0
ca ub
Channel Source.
This bit is used to request dma source
ifi p
data transfer if
software handshaking method is
od de
selected for the source of

M a
the corresponding channel.

M
This bit is ignored if software

handshaking is not enabled for
the source of the Channelx. The
functionality of this field
depends on whether the peripheral is
the flow controller or
not.
1 SWHS_REQ_SRC_WE WO Write Enable bit for Software 0x0
Handshake Request for
Channel Source.
2 SWHS_SGLREQ_SRC R/W Software Handshake Single Request for 0x0
Channel Source.
This bit is used to request SINGLE (AXI
162
CV1835

burst length = 1)
dma source data transfer if software
handshaking method is
selected for the source of the
corresponding channel. This
bit is ignored if software handshaking is
not enabled for the
source of the Channelx. The
functionality of this field
ed
depends on whether the peripheral is
the flow controller.
w
3 SWHS_SGLREQ_SRC_WE WO Write Enable bit for Software 0x0
Handshake Single Request for
lo
Channel Source.
al
4 SWHS_LST_SRC R/W Software Handshake Last Request for 0x0
Channel Source.
t
This bit is used to request LAST dma
no
source data transfer if
e
selected for the source of
ar
the corresponding channel.
This bit is ignored if software
n
handshaking is not enabled for
tio
the source of the Channelx or if the
source of Channelx is
not the flow controller.
u
ib
5 SWHS_LST_SRC_WE WO Write Enable bit for Software 0x0

Handshake Last Request for
r
di V
Channel Source.
st
re k-
31:6 Reserved
d il
an M
CHx_SWHSDSTREG
n by

0 SWHS_REQ_DST R/W Software Handshake Request for 0x0
tio lic
Channel Destination.
This bit is used to request dma
ca ub
destination data transfer if

ifi p
selected for the destination

od de
of the corresponding channel.

1 SWHS_REQ_DST_WE WO Write Enable bit for Software 0x0
M a
Handshake Request for

M
2 SWHS_SGLREQ_DST R/W Software Handshake Single Request for 0x0
Channel
Destination.
This bit is used to request SINGLE (AXI
burst length = 1)
dma destination data transfer if
method is selected for the destination
of the corresponding
channel.
3 SWHS_SGLREQ_DST_WE WO Write Enable bit for Software 0x0
Handshake Single Request for
163
CV1835

4 SWHS_LST_DST R/W Software Handshake Last Request for 0x0
This bit is used to request LAST dma
destination data
transfer if software handshaking
method is selected for the
destination of the corresponding
channel.
ed
5 SWHS_LST_DST_WE WO Write Enable bit for Software 0x0
Handshake Last Request for
w
lo
31:6 Reserved
al
CHx_BLK_TFR_RESUMEREQREG
t
no
0 BLK_TFR_RESUMEREQ WO Block Transfer Resume Request during 0x0
e
ar
Linked-List or
Shadow-Register-based multi-block
transfer.
n
31:1 Reserved
u tio
CHx_AXI_IDREG
ib

r
di V
st

re k-
14:0 AXI_READ_ID_SUFFIX R/W AXI Read ID Suffix 0x0

These bits form part of the ARID output
d il
an M
of AXI3/AXI4 master
interface.
15 Reserved
n by
30:16 AXI_WRITE_ID_SUFFIX R/W AXI Write ID Suffix. 0x0

These bits form part of the AWID output
tio lic
of AXI3/AXI4 master
interface.
ca ub
31 Reserved
ifi p
CHx_AXI_QOSREG
od de

M a

M
3:0 AXI_AWQOS R/W AXI AWQOS. 0x0

These bits form the awqos output of
AXI4 master interface.
7:4 AXI_ARQOS R/W AXI ARQOS. 0x0
These bits form the arqos output of
AXI4 master interface.
31:8 Reserved
CHx_SSTAT
164
CV1835

31:0 SSTAT RO Source Status
Source status information retrieved by
hardware from the
address pointed to by the contents of
the CHx_SSTATAR
register.
CHx_DSTAT
ed
w
31:0 DSTAT RO Destination Status
lo
Destination status information retrieved
by hardware from
al
the address pointed to by the contents
t
of the CHx_DSTATAR
no
register.
CHx_SSTATAR
e
ar
n
63:0 SSTATAR R/W Source Status Fetch Address 0x0
tio
Pointer from where hardware can fetch

the source status
u
information, which is registered in the

ib
CHx_SSTAT register
r
and written out to the CHx_SSTAT

di V
st
register location of the LLI

re k-
before the start of the next block if

d il
DMAX_CHx_LLI_WB_EN
an M
= 1 and linked list based multi-block

transfer is enabled for
n by
either source or destination peripheral

of the channel.
Source peripheral should update the
tio lic
source status
ca ub
information, if any, at the location

pointed to by
ifi p
CHx_SSTATAR to utilize this feature.

od de
CHx_DSTATAR
M a

M

63:0 DSTATAR R/W Destination Status Fetch Address 0x0
Pointer from where hardware can fetch
the Destination
status information, which is registered
in the CHx_DSTAT
register and written out to the
CHx_DSTAT register location
of the LLI before the start of the next
block if
DMAX_CHx_LLI_WB_EN = 1 and linked
list based multiblock
165
CV1835

transfer is enabled for either source or
destination
peripheral of the channel.
Destination peripheral should update
the destination status
information, if any, at the location
pointed to by
CHx_DSTATAR to utilize this feature.
ed
CHx_INTSTATUS_ENABLEREG
w
lo
0 Enable_BLOCK_TFR_DONE_IntStat R/W Block Transfer Done Interrupt Status 0x0
al
Enable.
t
0: Disable the generation of Block
no
Transfer Done Interrupt
in CHx_INTSTATUSREG
1: Enable the generation of Block
e
ar
in CHx_INTSTATUSREG
1 Enable_DMA_TFR_DONE_IntStat R/W DMA Transfer Done Interrupt Status 0x0
n
Enable.
tio
0: Disable the generation of DMA

u
in CHx_INTSTATUSREG
ib
1: Enable the generation of DMA

r

di V
st
in CHx_INTSTATUSREG
re k-
2 Reserved
d il
3 Enable_SRC_TRANSCOMP_IntStat R/W Source Transaction Completed Status 0x0

an M
Enable.
0: Disable the generation of Source
n by
Transaction
Complete Interrupt in
CHx_INTSTATUSREG
tio lic
1: Enable the generation of Source

ca ub
Transaction Complete
Interrupt in CHx_INTSTATUSREG
ifi p
4 Enable_DST_TRANSCOMP_IntStat R/W Destination Transaction Completed 0x0

Status Enable.
od de
0: Disable the generation of Destination

Transaction
M a
complete Interrupt in
M
CHx_INTSTATUSREG
1: Enable the generation of Destination
Transaction
complete Interrupt in
CHx_INTSTATUSREG
5 Enable_SRC_DEC_ERR_IntStat R/W Source Decode Error Status Enable. 0x0
Decode Error
1: Enable the generation of Source
Decode Error
6 Enable_DST_DEC_ERR_IntStat R/W Destination Decode Error Status Enable. 0x0
166
CV1835

Decode Error
Decode Error
7 Enable_SRC_SLV_ERR_IntStat R/W Source Slave Error Status Enable. 0x0
Slave Error Interrupt
ed
in CHx_INTSTATUSREG
1: Enable the generation of Source Slave
w
Error Interrupt
in CHx_INTSTATUSREG
lo
8 Enable_DST_SLV_ERR_IntStat R/W Destination Slave Error Status Enable. 0x0
al
Slave Error
t
no
Slave Error
e
ar
9 Enable_LLI_RD_DEC_ERR_IntStat R/W LLI Read Decode Error Status Enable. 0x0
0: Disable the generation of LLI Read
n
Decode Error
tio
1: Enable the generation of LLI Read
u
Decode Error
ib
10 Enable_LLI_WR_DEC_ERR_IntStat R/W LLI WRITE Decode Error Status Enable. 0x0
r
di V
0: Disable the generation of LLI WRITE

st
re k-
Decode Error
d il
1: Enable the generation of LLI WRITE

an M
Decode Error
n by
11 Enable_LLI_RD_SLV_ERR_IntStat R/W LLI Read Slave Error Status Enable. 0x0

0: Disable the generation of LLI Read
tio lic
Slave Error
ca ub
1: Enable the generation of LLI Read

ifi p
in CHx_INTSTATUSREG
12 Enable_LLI_WR_SLV_ERR_IntStat R/W LLI WRITE Slave Error Status Enable. 0x0
od de
0: Disable the generation of LLI WRITE

Slave Error
M a
M
1: Enable the generation of LLI WRITE
Slave Error
13 Enable_SHADOWREG_OR_LLI_INVA R/W Shadow register or LLI Invalid Error 0x0
LID_ERR_IntStat Status Enable.
0: Disable the generation of Shadow
Register or LLI
Invalid Error Interrupt in
CHx_INTSTATUSREG
1: Enable the generation of Shadow
Register or LLI
Invalid Error Interrupt in
167
CV1835

CHx_INTSTATUSREG
14 Enable_SLVIF_MULTIBLKTYPE_ERR_I R/W Slave Interface Multi Block type Error 0x0
ntStat Status Enable.
0: Disable the generation of Slave
Interface Multi Block
type Error Interrupt in
CHx_INTSTATUSREG
1: Enable the generation of Slave
ed
type Error Interrupt in
CHx_INTSTATUSREG
w
15 Reserved
lo
16 Enable_SLVIF_DEC_ERR_IntStat R/W Slave Interface Decode Error Status 0x0
Enable.
al
Interface Decode Error
t
no
Interface Decode Error
e
ar
17 Enable_SLVIF_WR2RO_ERR_IntStat R/W Slave Interface Write to Read Only Error 0x0
Status Enable.
n
tio
Interface Write to Read

only Error Interrupt in
u
CHx_INTSTATUSREG
ib

Interface Write to Read
r
di V
st
Only Error Interrupt in

re k-
CHx_INTSTATUSREG
18 Enable_SLVIF_RD2RWO_ERR_IntSta R/W Slave Interface Read to write Only Error 0x0
d il
an M
t Status Enable.
Interface Read to Write
n by
only Error Interrupt in

CHx_INTSTATUSREG
tio lic

Interface Read to Write
ca ub
Only Error Interrupt in

CHx_INTSTATUSREG
ifi p
19 Enable_SLVIF_WRONCHEN_ERR_Int R/W Slave Interface Write On Channel 0x0

od de
Stat Enabled Error Status

Enable.
M a

M
Interface Write On
Channel enabled Error Interrupt in
CHx_INTSTATUSREG
Interface Write On
Channel enabled Error Interrupt in
CHx_INTSTATUSREG
20 Enable_SLVIF_SHADOWREG_WRON R/W Shadow Register Write On Valid Error 0x0
_VALID_ERR_IntStat Status Enable.
0: Disable the generation of Shadow
Register Write On
Valid Error Interrupt in
CHx_INTSTATUSREG
168
CV1835

1: Enable the generation of Shadow
register Write On
Valid Error Interrupt in
CHx_INTSTATUSREG
21 Enable_SLVIF_WRONHOLD_ERR_Int R/W Slave Interface Write On Hold Error 0x0
Stat Status Enable.
Interface Write On
Hold Error Interrupt in
ed
CHx_INTSTATUSREG
w
Interface Write On Hold
Error Interrupt in CHx_INTSTATUSREG
lo
26:22 Reserved
al
27 Enable_CH_LOCK_CLEARED_IntStat R/W Channel Lock Cleared Status Enable. 0x0
0: Disable the generation of Channel
t
no
LOCK CLEARED
1: Enable the generation of Channel
e
LOCK CLEARED
ar
28 Enable_CH_SRC_SUSPENDED_IntSta R/W Channel Source Suspended Status 0x0
n
t Enable.
tio

Source Suspended
u
ib

Source Suspended
r
di V
st
re k-
29 Enable_CH_SUSPENDED_IntStat R/W Channel Suspended Status Enable. 0x0

d il
an M
Suspended
n by
Suspended Interrupt
in CHx_INTSTATUSREG
tio lic
30 Enable_CH_DISABLED_IntStat R/W Channel Disabled Status Enable. 0x0

ca ub
Disabled Interrupt in
CHx_INTSTATUSREG
ifi p

od de
Disabled Interrupt in
CHx_INTSTATUSREG
M a
31 Enable_CH_ABORTED_IntStat R/W Channel Aborted Status Enable. 0x0

M

Aborted Interrupt in
CHx_INTSTATUSREG
Aborted Interrupt in
CHx_INTSTATUSREG
CHx_INTSTATUS
0 BLOCK_TFR_DONE_IntStat RO Block Transfer Done.
This indicates to the software that the
169
CV1835

DW_axi_dmac has
completed the requested block transfer.
The DW_axi_dmac sets this bit to 1
when the transfer is
successfully completed.
0: Block Transfer not completed.
1: Block Transfer completed.
This bit is cleared to 0 on writing 1 to
the corresponding
ed
channel interrupt clear bit in
CHx_IntClearReg register.
w
1 DMA_TFR_DONE_IntStat RO DMA Transfer Done.
lo
DW_axi_dmac has
al
completed the requested DMA transfer.
The DW_axi_dmac sets this bit to 1
t
along with setting
no
CHx_INTSTATUS.BLOCK_TFR_DONE bit
to 1 when the last
e
block transfer is completed.
ar
0: DMA Transfer not completed.
1: DMA Transfer Completed
n
This bit is cleared to 0 on writing 1
tio
2 Reserved
3 SRC_TRANSCOMP_IntStat RO Source Transaction Completed.
u

ib
the corresponding
r
di V
st
CHx_IntClearReg register or on
re k-
enabling the channel (needed when

interrupt is not enabled.
d il
an M
4 DST_TRANSCOMP_IntStat RO Destination Transaction Completed.

the corresponding
n by

CHx_IntClearReg register or on
tio lic
enabling the channel (needed when

interrupt is not enabled.
ca ub
5 SRC_DEC_ERR_IntStat RO Source Decode Error.

Decode Error detected by Master
ifi p
Interface during source

od de
data transfer. This error occurs if the

access is to invalid
M a
address and a Decode Error is returned

M
from
interconnect/slave. This error condition
causes the
DW_axi_dmac to disable the
gracefully; the DMAC_ChEnReg.CH_EN
bit corresponding
to the channel which received the error
is set to 0.
0: No Source Decode Errors.
1: Source Decode Error detected.
6 DST_DEC_ERR_IntStat RO Destination Decode Error.
170
CV1835

Interface during
destination data transfer. This error
occurs if the access is to
invalid address and a Decode Error is
returned from
causes the
ed
gracefully; the DMAC_ChEnReg.CH_EN
bit corresponding
w
to the channel which received the error
is set to 0.
lo
0: No destination Decode Errors.
al
1: Destination Decode Error Detected
7 SRC_SLV_ERR_IntStat RO Source Slave Error.
t
Slave Error detected by Master Interface
no
during source data
transfer. This error occurs if the slave
e
interface from which
ar
the data is read issues a Slave Error. This
error condition
n
causes the DW_axi_dmac to disable the
tio
corresponding
channel gracefully; the
DMAC_ChEnReg.CH_EN bit
u
corresponding to the channel which

ib
received the error is set

r
di V
to 0.
st
re k-
0: No Source Slave Errors

1: Source Slave Error Detected
d il
8 DST_SLV_ERR_IntStat RO Destination Slave Error.

an M

during destination
n by
data transfer. This error occurs if the

slave interface to which
tio lic
the data is written issues a Slave Error.

This error condition
ca ub

corresponding
ifi p

DMAC_ChEnReg.CH_EN bit
od de
corresponding to the channel which

received the error is set
M a
to 0.
M
0: No Destination Slave Errors

1: Destination Slave Errors Detected
9 LLI_RD_DEC_ERR_IntStat RO LLI Read Decode Error.
Interface during LLI read
operation. This error occurs if the access
is to invalid
from
causes the
171
CV1835

gracefully; the DMAC_ChEnReg.CH_EN1
bit which received
the error is set to 0.
0: NO LLI Read Decode Errors.
1: LLI Read Decode Error detected
10 LLI_WR_DEC_ERR_IntStat RO LLI WRITE Decode Error.
Interface during LLI writeback
ed
operation. This error occurs if the access
is to invalid
w
from
lo
al
causes the
t
no
bit which received
e
ar
0: NO LLI Write Decode Errors.
1: LLI write Decode Error detected.
n
11 LLI_RD_SLV_ERR_IntStat RO LLI Read Slave Error.
tio
during LLI read
operation. This error occurs if the slave
u
interface on which
ib
LLI resides issues a Slave Error. This

r
di V
error condition causes

st
re k-
the DW_axi_dmac to disable the

d il

an M
bit which received

n by
0: No LLI Read Slave Errors.

1: LLI read Slave Error detected.
tio lic
12 LLI_WR_SLV_ERR_IntStat RO LLI WRITE Slave Error.

ca ub
during LLI writeback

operation. This error occurs if the slave
ifi p
interface on
which LLI resides issues a Slave Error.
od de
This error condition

M a
corresponding
M

DMAC_ChEnReg.CH_EN1 bit which
received the error is set to 0.
0: No LLI write Slave Errors.
1: LLI Write SLAVE Error detected.
13 SHADOWREG_OR_LLI_INVALID_ERR RO Shadow register or LLI Invalid Error.
_IntStat This error occurs if
CHx_CTL.ShadowReg_Or_LLI_Valid bit
is seen to be 0 during DW_axi_dmac
Shadow Register / LLI
fetch phase. This error condition causes
the DW_axi_dmac
172
CV1835

to halt the corresponding channel
gracefully; Error Interrupt
is generated if the corresponding
channel error interrupt
mask bit is set to 0 and the channel
waits till software writes
(any value) to
CHx_BLK_TFR_ResumeReqReg to
indicate
ed
valid Shadow Register availability.
In the case of LLI pre-fetching,
w
ShadowReg_Or_LLI_Invalid_ERR
Interrupt is not generated
lo
even if ShadowReg_Or_LLI_Valid bit is
al
seen to be 0 for the
pre-fetched LLI. In this case,
t
DW_axi_dmac re-attempts the
no
LLI fetch operation after completing the
current block transfer
e
and generates
ar
ShadowReg_Or_LLI_Invalid_ERR
Interrupt n
only if ShadowReg_Or_LLI_Valid bit is
tio
still seen to be 0.
0: No Shadow Register / LLI Invalid
errors.
u
1: Shadow Register / LLI Invalid error

ib
detected.
r
di V
14 SLVIF_MULTIBLKTYPE_ERR_IntStat RO Slave Interface Multi Block type Error.

st
re k-
This error occurs if multi-block transfer

type programmed in
d il
CHx_CFG register (SRC_MLTBLK_TYPE

an M
and
DST_MLTBLK_TYPE) is invalid. This error
n by
condition causes
the DW_axi_dmac to halt the
tio lic
gracefully; Error Interrupt is generated if

ca ub
the corresponding
channel error interrupt mask bit is set to
ifi p
0 and the channel

waits till software writes (any value) to
od de
CHx_BLK_TFR_ResumeReqReg to
indicate valid multiblock
M a
transfer type availability.

M
0: No Multi-block transfer type Errors.

1: Multi-block transfer type Error
detected.
15 Reserved
16 SLVIF_DEC_ERR_IntStat RO Slave Interface Decode Error.
access is to invalid
address in Channelx register space
resulting in error
response by DW_axi_dmac slave
173
CV1835

interface.
0: No Slave Interface Decode errors.
1: Slave Interface Decode Error
detected.
17 SLVIF_WR2RO_ERR_IntStat RO Slave Interface Write to Read Only Error.
This error occurs if write operation is
performed to a Read
Only register.
0: No Slave Interface Write to Read Only
ed
Errors.
1: Slave Interface Write to Read Only
w
Error detected.
18 SLVIF_RD2RWO_ERR_IntStat RO Slave Interface Read to write Only Error.
lo
This error occurs if read operation is
al
performed to a Write
Only register.
t
0: No Slave Interface Read to Write Only
no
Errors.
1: Slave Interface Read to Write Only
e
Error detected.
ar
19 SLVIF_WRONCHEN_ERR_IntStat RO Slave Interface Write On Channel
Enabled Error.
n
tio
a register; this happens if a write
u
operation is performed on a
ib
register when the channel is enabled

and if it is not allowed
r
di V
for the corresponding register as per

st
re k-
the DW_axi_dmac
specification.
d il
0: No Slave Interface Write On Channel

an M
Enabled Errors.
1: Slave Interface Write On Channel
n by
Enabled Error
detected.
tio lic
20 SLVIF_SHADOWREG_WRON_VALID_ RO Shadow Register Write On Valid Error.

ERR_IntStat This error occurs if shadow register
ca ub
based multi-block
transfer is enabled and software tries to
ifi p
write to the shadow

register when
od de
1.
M a
0: No Slave Interface Shadow Register

M
Write On Valid
Errors.
1: Slave Interface Shadow Register Write
On Valid Error
detected.
21 SLVIF_WRONHOLD_ERR_IntStat RO Slave Interface Write On Hold Error.
a register; this happens if a write
operation is performed on a
channel register when DW_axi_dmac is
in Hold mode.
174
CV1835

0: No Slave Interface Write On Hold
Errors.
1: Slave Interface Write On Hold Error
detected.
26:22 Reserved
27 CH_LOCK_CLEARED_IntStat RO Channel Lock Cleared.
locking of the
corresponding channel in DW_axi_dmac
ed
is cleared.
0: Channel locking is not cleared.
w
1: Channel locking is cleared.
lo
28 CH_SRC_SUSPENDED_IntStat RO Channel Source Suspended.
al
source data transfer in DW_axi_dmac is
t
no
suspended.
0: Channel source is not suspended
1: Channel Source is suspended.
e
29 CH_SUSPENDED_IntStat RO Channel Suspended.
ar
n
in DW_axi_dmac is suspended.
tio
0: Channel is not suspended.

1: Channel is suspended.
u
30 CH_DISABLED_IntStat RO Channel Disabled.

ib

r
di V
st
in DW_axi_dmac is disabled.
re k-
0: Channel is not disabled.

1: Channel is disabled. Error Interrupt is
d il
an M
generated if
the corresponding bit in
CHx_INTSTATUS_ENABLEReg
n by
is enabled.
31 CH_ABORTED_IntStat RO Channel Aborted.
tio lic

ca ub
in DW_axi_dmac is aborted.
0: Channel is not aborted
ifi p
1: Channel is aborted
od de
CHx_INTSIGNAL_ENABLEREG
M a
M

0 Enable_BLOCK_TFR_DONE_IntSignal R/W Block Transfer Done Interrupt Signal 0x0
Enable.
0: Disable the propagation of Block
Transfer Done
Interrupt to generate a port level
interrupt
1: Enable the propagation of Block
Transfer Done
interrupt
1 Enable_DMA_TFR_DONE_IntSignal R/W DMA Transfer Done Interrupt Signal 0x0
175
CV1835

Enable.
0: Disable the propagation of DMA
Transfer Done
interrupt
1: Enable the propagation of DMA
Transfer Done
interrupt
ed
2 Reserved
3 Enable_SRC_TRANSCOMP_IntSignal R/W Source Transaction Completed Signal 0x0
w
Enable.
lo
0: Disable the propagation of Source
Transaction
al
Complete Interrupt to generate a port
level interrupt
t
no
1: Enable the propagation of Source
Transaction
Complete Interrupt to generate a port
e
level interrupt
ar
4 Enable_DST_TRANSCOMP_IntSignal R/W Destination Transaction Completed 0x0
Signal Enable.
n
0: Disable the propagation of
tio
Destination Transaction
complete Interrupt to generate a port
u
level interrupt
ib
1: Enable the propagation of

Destination Transaction
r
di V
st
complete Interrupt to generate a port

re k-
level interrupt
5 Enable_SRC_DEC_ERR_IntSignal R/W Source Decode Error Signal Enable. 0x0
d il
an M

Decode Error
n by
interrupt
tio lic
Decode Error
ca ub
interrupt
6 Enable_DST_DEC_ERR_IntSignal R/W Destination Decode Error Signal Enable. 0x0
ifi p

od de
Destination Decode Error

M a
interrupt
M

Destination Decode Error
interrupt
7 Enable_SRC_SLV_ERR_IntSignal R/W Source Slave Error Signal Enable. 0x0
to generate a port level interrupt
8 Enable_DST_SLV_ERR_IntSignal R/W Destination Slave Error Signal Enable. 0x0
176
CV1835

Destination Slave Error
interrupt
Destination Slave Error
interrupt
9 Enable_LLI_RD_DEC_ERR_IntSignal R/W LLI Read Decode Error Signal Enable. 0x0
0: Disable the propagation of LLI Read
ed
Decode Error
w
interrupt
1: Enable the propagation of LLI Read
lo
Decode Error
al
interrupt
t
10 Enable_LLI_WR_DEC_ERR_IntSignal R/W LLI WRITE Decode Error Signal Enable. 0x0
no
0: Disable the propagation of LLI WRITE
Decode Error
e
ar
interrupt
1: Enable the propagation of LLI WRITE
n
Decode Error
tio
interrupt
11
u
Enable_LLI_RD_SLV_ERR_IntSignal R/W LLI Read Slave Error Signal Enable. 0x0

ib
0: Disable the propagation of LLI Read

Slave Error
r
di V

st
re k-
interrupt
1: Enable the propagation of LLI Read
d il
Slave Error
an M

interrupt
n by
12 Enable_LLI_WR_SLV_ERR_IntSignal R/W LLI WRITE Slave Error Signal Enable. 0x0

0: Disable the propagation of LLI WRITE
tio lic
Slave Error
ca ub
interrupt
1: Enable the propagation of LLI WRITE
ifi p
Slave Error
od de
interrupt
13 Enable_SHADOWREG_OR_LLI_INVA R/W Shadow register or LLI Invalid Error 0x0
M a
M
LID_ERR_IntSignal Signal Enable.

0: Disable the propagation of Shadow
Register or LLI
Invalid Error Interrupt to generate a
port level interrupt
1: Enable the propagation of Shadow
Register or LLI
Invalid Error Interrupt to generate a
14 Enable_SLVIF_MULTIBLKTYPE_ERR_I R/W Slave Interface Multi Block type Error 0x0
ntSignal Signal Enable.
0: Disable the propagation of Slave
177
CV1835

type Error Interrupt to generate a port
level interrupt
1: Enable the propagation of Slave
type Error Interrupt to generate a port
level interrupt
15 Reserved
16 Enable_SLVIF_DEC_ERR_IntSignal R/W Slave Interface Decode Error Signal 0x0
Enable.
ed
Interface Decode
w
Error Interrupt to generate a port level
lo
interrupt
al
Interface Decode
Error Interrupt to generate a port level
t
no
interrupt
17 Enable_SLVIF_WR2RO_ERR_IntSign R/W Slave Interface Write to Read Only Error 0x0
al Signal Enable.
e
ar
Interface Write to
Read only Error Interrupt to generate a
n
tio

Interface Write to
u
Read Only Error Interrupt to generate a

ib
port level
interrupt
r
di V
st
18 Enable_SLVIF_RD2RWO_ERR_IntSig R/W Slave Interface Read to write Only Error 0x0

re k-
nal Signal Enable.

d il
an M
Interface Read to
Write only Error Interrupt to generate a
n by

Interface Read to
tio lic
Write Only Error Interrupt to generate a

port level
ca ub
interrupt
19 Enable_SLVIF_WRONCHEN_ERR_Int R/W Slave Interface Write On Channel 0x0
ifi p
Signal Enabled Error Signal

od de
Enable.
M a
Interface Write On
M
Channel enabled Error Interrupt to

interrupt
Interface Write On
Channel enabled Error Interrupt to
interrupt
20 Enable_SLVIF_SHADOWREG_WRON R/W Shadow Register Write On Valid Error 0x0
_VALID_ERR_IntSignal Signal Enable.
0: Disable the propagation of Shadow
Register Write On
Valid Error Interrupt to generate a port
178
CV1835

level interrupt
1: Enable the propagation of Shadow
register Write On
Valid Error Interrupt to generate a port
level interrupt
21 Enable_SLVIF_WRONHOLD_ERR_Int R/W Slave Interface Write On Hold Error 0x0
Signal Signal Enable.
Interface Write On
ed
Hold Error Interrupt to generate a port
level interrupt
w
Interface Write On
lo
Hold Error Interrupt to generate a port
al
level interrupt
26:22 Reserved
t
no
27 Enable_CH_LOCK_CLEARED_IntSign R/W Channel Lock Cleared Signal Enable. 0x0
al 0: Disable the propagation of Channel
Lock Cleared
e
ar
interrupt
1: Enable the propagation of Channel
n
Lock Cleared
tio

interrupt
u
28 Enable_CH_SRC_SUSPENDED_IntSig R/W Channel Source Suspended Signal 0x0

ib
nal Enable.
0: Disable the propagation of Channel
r
di V
st
Source
re k-
Suspended Interrupt to generate a port

level interrupt
d il
an M

Source Suspended
n by
interrupt
29 Enable_CH_SUSPENDED_IntSignal R/W Channel Suspended Signal Enable. 0x0
tio lic

Suspended
ca ub

interrupt
ifi p

od de
Suspended
M a
interrupt
M
30 Enable_CH_DISABLED_IntSignal R/W Channel Disabled Signal Enable. 0x0

Disabled Interrupt
Disabled Interrupt
31 Enable_CH_ABORTED_IntSignal R/W Channel Aborted Signal Enable. 0x0
Aborted Interrupt
Aborted Interrupt to
179
CV1835

generate a port level interrupt
CHx_INTCLEARREG
0 Clear_BLOCK_TFR_DONE_IntStat WO Block Transfer Done Interrupt Clear Bit. 0x0
ed
status bit in CH1_INTSTATUSREG
1 Clear_DMA_TFR_DONE_IntStat WO DMA Transfer Done Interrupt Clear Bit. 0x0
w
lo
status bit in CHx_INTSTATUSREG.
al
2 Reserved
t
3 Clear_SRC_TRANSCOMP_IntStat WO Source Transaction Completed Interrupt 0x0
no
Clear Bit.
e
ar
4 Clear_DST_TRANSCOMP_IntStat WO Destination Transaction Completed 0x0
Interrupt Clear Bit.
n
tio

u
5 Clear_SRC_DEC_ERR_IntStat WO Source Decode Error Interrupt Clear Bit. 0x0

ib

r

di V
st

re k-
6 Clear_DST_DEC_ERR_IntStat WO Destination Decode Error Interrupt 0x0

d il
Clear Bit.
an M

n by

7 Clear_SRC_SLV_ERR_IntStat WO Source Slave Error Interrupt Clear Bit. 0x0
tio lic

ca ub

8 Clear_DST_SLV_ERR_IntStat WO Destination Slave Error Interrupt Clear 0x0
ifi p
Bit.
od de

M a
9 Clear_LLI_RD_DEC_ERR_IntStat WO LLI Read Decode Error Interrupt Clear 0x0

M
Bit.
10 Clear_LLI_WR_DEC_ERR_IntStat WO LLI WRITE Decode Error Interrupt Clear 0x0
Bit.
11 Clear_LLI_RD_SLV_ERR_IntStat WO LLI Read Slave Error Interrupt Clear Bit. 0x0
180
CV1835

12 Clear_LLI_WR_SLV_ERR_IntStat WO LLI WRITE Slave Error Interrupt Clear Bit. 0x0
13 Clear_SHADOWREG_OR_LLI_INVALI WO Shadow register or LLI Invalid Error 0x0
D_ERR_IntStat Interrupt Clear Bit.
ed
14 Clear_SLVIF_MULTIBLKTYPE_ERR_In WO Slave Interface Multi Block type Error 0x0
w
tStat Interrupt Clear Bit.
lo
al
15 Reserved
t
no
16 Clear_SLVIF_DEC_ERR_IntStat WO Slave Interface Decode Error Interrupt 0x0
Clear Bit.
e
ar
17 Clear_SLVIF_WR2RO_ERR_IntStat WO Slave Interface Write to Read Only Error 0x0
n
tio

u

ib
18 Clear_SLVIF_RD2RWO_ERR_IntStat WO Slave Interface Read to write Only Error 0x0

r

di V
st

re k-

d il
an M
19 Clear_SLVIF_WRONCHEN_ERR_IntSt WO Slave Interface Write On Channel 0x0

at Enabled Error Interrupt
Clear Bit.
n by

tio lic

20 Clear_SLVIF_SHADOWREG_WRON_ WO Shadow Register Write On Valid Error 0x0
ca ub
VALID_ERR_IntStat Interrupt Clear Bit.

ifi p

od de

21 Clear_SLVIF_WRONHOLD_ERR_IntSt WO Slave Interface Write On Hold Error 0x0
M a
at Interrupt Clear Bit.

M

26:22 Reserved
27 Clear_CH_LOCK_CLEARED_IntStat WO Channel Lock Cleared Interrupt Clear 0x0
Bit.
28 Clear_CH_SRC_SUSPENDED_IntStat WO Channel Source Suspended Interrupt 0x0
Clear Bit.
181
CV1835

29 Clear_CH_SUSPENDED_IntStat WO Channel Suspended Interrupt Clear Bit. 0x0
30 Clear_CH_DISABLED_IntStat WO Channel Disabled Interrupt Clear Bit. 0x0
ed
31 Reserved
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
182
CV1835
3.7 Timer
3.7.1 Overview
ed
The system is equipped with 8 timer modules. It can be used as a timing or counting
w
function, which can provide application program for timing and counting, and can also
lo
provide operating system for implementing system clock.
al
t
no
The timer has the following characteristics:
e
ar
32bit count down timer / counter. n
Support two counting modes: free running mode and user-defined
tio
counting mode
u
The system can read the current counter value.

ib
When the counter value decreases to 0, an interrupt is generated.

r
di V
st
re k-
3.7.3 Function description

d il
an M
Timer is based on a 32 bit count down counter. The value of the counter is subtracted
n by
by 1 on each rising edge of the counting clock. When the counter is counting down to
tio lic
zero, the timer generates an interrupt.

ca ub
Timer has the following two counting modes:

ifi p
Free running mode

od de
The timer counts continuously. When the counter value is reduced to 0, it

M a
automatically turns back to its maximum value and continues to count

M
down. The maximum initial counter value is 0xFFFF_ FFFF。

User-defined counting mode
The timer continues to count. When the counter value is reduced to 0, the
timer reloads the initial counter value from the TimerNLoadCount (N = 1 ~
8) register and continues to count down.
The method of loading the initial counter value to the timer is as follows：
By writing TimerNLoadCount (N = 1 ~ 8) register, the initial counter value of timer can
183
CV1835
be loaded.
3.7.4 Operation mode
ed
Step 1 Write TimerNLoadCount (N = 1 ~ 8) register to load the initial counter value for
timer.
w
lo
Step 2 Set TimerNControlReg [2:0] (N = 1 ~ 8) register, select timer counting mode,
al
mask timer interrupt and enable timer to start counting down.
t
no
3.7.4.2 Interupt processing
e
When the timer generates an interrupt, the operation steps are as follows:
ar
Step 1 read TimerNEOI (N = 1 ~ 8) register and clear timerN interrupt.
n
tio
Step 2 executes the process waiting for the interrupt.

Step 3 After the process of is completed, the interrupted program is resumed.
u
r ib
3.7.4.3 Clock selection

di V
st
re k-
d il
The system timer can use either a 25MHz or 32KHz clock for counting, which can be
an M
selected using the "reg_timer_clk_sel" register.

n by
3.7.5 Timer register overview

tio lic
ca ub
The timer register is accessed through the bus.

ifi p
An overview of the timer register is shown in table 3.7.

od de
M a
Table 3- 7 Timer register overview (address 0x030A0000)

M

Offset
Timer1LoadCount 0x000 Value to be loaded into Timer1
Timer1CurrentValue 0x004 Current Value of Timer1
Timer1ControlReg 0x008 Control Register for Timer1
Timer1EOI 0x00c Clears the interrupt from Timer1
Timer1IntStatus 0x010 Contains the interrupt status for Timer1
Timer2 Registers 0x014~ 0x024 共 5 个寄存器，内容与 Timer1 相同。
Timer4 Registers 0x03c~ 0x04c 共 5 个寄存器，内容与 Timer1 相同。
184
CV1835

Offset
Timer8 Registers 0x08c~ 0x09c 共 5 个寄存器，内容与 Timer1 相同。
TimersIntStatus 0x0a0 Contains the interrupt status of all timers in the
component.
TimersEOI 0x0a4 Returns all zeroes (0) and clears all active interrupts.
TimersRawIntStatus 0x0a8 Contains the unmasked interrupt status of all timers in
ed
the component.
w
lo
al
t
3.7.6 Timer register description
no
e
Timer1LoadCount
ar
n
tio
u
31:0 Timer1LoadCount R/W Timer1 Load Count Register 0x0

ib
Value to be loaded into Timer1. This is

r
the value from which counting

di V
st
commences. Any value written to this

re k-
register is loaded into the associated

d il
timer.
an M
Timer1CurrentValue
n by

tio lic
31:0 Timer1CurrentValue RO Timer1 Current Value

ca ub
Current Value of Timer1. This register is

supported only when timer_1_clk is
ifi p
synchronous to pclk. Reading this

register when using independent clocks
od de
results in an undefined value.

M a
M
Timer1ControlReg
2:0 Timer1ControlReg R/W [2] Timer interrupt mask for Timer1 0x0
0 – not masked
1 – masked
[1] Timer mode for Timer1

0 – free-running mode
1 – user-defined count mode
[0] Timer enable bit for Timer1
185
CV1835

0 – disable
1 – enable
31:3 Reserved
Timer1EOI
ed
0 Timer1EOI RO Reading from this register returns all
zeroes (0) and clears the interrupt from
w
Timer1.
31:1 Reserved
lo
al
Timer1IntStatus
t
no
0 Timer1IntStatus RO Contains the interrupt status for Timer1.
e
31:1 Reserved
ar
n
TimersIntStatus
tio

u
ib
7:0 TimersIntStatus RO Contains the interrupt status of all

timers.
r
di V
st
Reading from this register does not

re k-
clear any active interrupts:

0 – either timer_intr or timer_intr_n is
d il
not active after masking

an M

active after masking
n by
31:8 Reserved
tio lic
TimersEOI
ca ub

ifi p
7:0 TimersEOI RO Reading this register returns all zeroes

od de
(0) and clears all active interrupts.

31:8 Reserved
M a
M
TimersRawIntStatus
7:0 TimersRawIntStatus RO The register contains the unmasked
interrupt status of all timers.
not active prior to masking
active prior to masking
31:8 Reserved
186
CV1835
3.8 Watchdog
3.8.1 Overview
ed
The system is equipped with a watchdog module. It is used to send interrupt or reset
w
signal to interrupt or reset the whole system after a certain time when the system is
lo
abnormal.
al
t
3.8.2 Charateristics
no
e
WatchDog has the following characteristics:
ar
a 32bit configurable decrement counter. n
The initial counter value (i.e. timeout period) can be configured.
tio
Support watchdog restart protection to prevent watchdog from being

u
restarted due to misoperation.

r ib
Support reset signal generation.

di V
st
re k-
Support timeout interrupt generation.

d il
an M

n by
The system configures watchdog registers through system bus. In order to monitor
tio lic
system operation, watchdog regularly sends WDT_INTR interrupt request to the system,
ca ub
and WDT_SYS_RST signal is sent out to reset the system when the system does not
ifi p
respond to the interrupt (e.g. system hang).

od de
M a
M
187
CV1835
3.8.3.1 Application block diagram
ed
w
lo
al
t
no
e
ar
n
u tio
Figure 3- 8 WatchDog Application block diagram

r ib
di V
st
re k-
d il
3.8.3.2 Function description

an M
n by
The initial counter value of watchdog is loaded by register WDT_TORR and working
based on a 32bit decrement counter. When the watchdog clock is enabled, the counter
tio lic
value is subtracted by 1 on each rising edge of the counting clock. When the counter is
ca ub
decremented to 0, watchdog will generate an interrupt. Then, at the next rising edge of
ifi p
the counting clock, the counter starts to reload the initial counter value from the
od de
register WDT_TORR and begins to decrement the counter.。

M a
M
If the CPU has not cleared the watchdog interrupt when the counter value is
decremented to 0 for the second time, the Watchdog will send a reset signal
WDT_SYS_RST, the counter stops counting. The user can set the register WDT_CR[1] to
decides whether to send the reset signal WDT_SYS_RST immediately when the counter
value is decremented to 0 for the first time.
188
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3.8.4 Working mode
3.8.4.1 Counting clock frequency configuration
The Watchdog counting clock can be either 25MHz or 32KHz. Use the "reg_wdt_clk_sel"
to select.
ed
3.8.4.2 System initialization configuration
w
lo
After the system is powered on and reset, the watchdog counter is in the stop counting
al
state, and it needs to be initialized and enabled during the system initialization. The
t
no
initialization process of watchdog is as follows:
Step 1 write register WDT_TORR, set the initial value of watchdog counter.
e
ar
Step 2 write register WDT_CR[1], set the watchdog counter timeout response mode.
n
Step 3 write register WDT_CR[0], start watchdog counting.。
tio
3.8.4.3 Interrupt processing

u
r ib
After receiving the interrupt from watchdog, the system should clear its interrupt status
di V
st
re k-
in time.
d il
The process of watchdog interrupt processing is as follows:

an M
Step 1 read register WDT_EOI to clear the interrupt state of watchdog.

n by
Step 2 write 0x76 to register WDT_CRR, restart watchdog.

tio lic
3.8.4.4 Close WatchDog

ca ub
ifi p
Write register WDT_CR[0] to control the state of watchdog:

od de
0 : WDT close。
M a
1 : WDT startup. Only system reset can shut down WDT after startup.
M
3.8.5 WDT register overview
The WDT registers are accessed through the bus. The four base addresses for the WDT
are:
WDT0 : 0x03010000
WDT1 : 0x03011000
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WDT2 : 0x03012000
RTCSYS_WDT : 0x0502D000
An overview of the WDT register is shown in table 3-8.
ed
Table 3- 8 WDT register overview (address 0x03010000)
w
lo
Offset
al
WDT_CR 0x000 Control register
WDT_TORR 0x004 Timeout range register
t
WDT_CCVR 0x008 Current counter value register
no
WDT_CRR 0x00c Counter restart register
WDT_STAT 0x010 Interrupt status register
WDT_EOI 0x014 Interrupt clear register
e
ar
WDT_TOC 0x01C Time Out Count
n
tio
3.8.6 WDT register description

u
r ib
di V
st
re k-
d il
WDT_CR
an M

n by
4:0 WDT_CR R/W [4:2] Reset pulse length. 0x0

This is used to select the number of pclk
tio lic
cycles for which the system reset stays

asserted. The range of values available
ca ub
is 2 to 256 pclk cycles.

000 – 2 pclk cycles
ifi p

od de

M a

M

[1] Response mode.

Selects the output response generated
to a timeout.
0 = Generate a system reset.
1 = First generate an interrupt and if it is
not cleared by the time a second
timeout occurs then generate a system
reset.
190
CV1835
[0] WDT enable.

This bit is used to enable and disable
the WatchDog. When disabled,
the counter does not decrement. Thus,
no interrupts or system resets are
generated.
Once this bit has been enabled, it can
be cleared only by a system reset.
ed
0 = WDT disabled.
1 = WDT enabled.
w
6 TOR_MODE R/W The Mode of Timeout Period 0x0
lo
7 ITOR_MODE R/W The Mode of Timeout Period for 0x0
al
initialization
31:5 Reserved
t
no
WDT_TORR
e
ar
3:0 WDT_TORR R/W [3:0] TOP(TimeOut Period). 0x0
This field is used to select the timeout
n
period from which the watchdog
tio
counter restarts. A change of the

timeout period takes effect only after
u
the next counter restart (kick).

ib
The range of values is limited by 32-bit

width. If TOP is programmed to select a
r
di V
st
range that is greater than the counter

re k-
width, the timeout period is truncated

to fit to the counter width. This affects
d il
an M
only the non-user specified values as

users are limited to these boundaries
during configuration.
n by
The range of values available for a 32-bit

watchdog counter are:
tio lic
TOR_MODE = 0
T = 2^(16 + WDT_TORR)
ca ub
TOR_MODE = 1
T = WDT_TOC <<( WDT_TORR +1)
ifi p
od de
7:4 WDT_ITORR Initial TimeOut Period

ITOR_MODE = 0
M a
T = 2^(16 + WDT_ITORR)
M
ITOR_MODE = 1
T = WDT_TOC <<( WDT_ITORR +1)
31:4 Reserved
WDT_CCVR
31:0 WDT_CCVR RO This register, when read, is the current
value of the internal counter.
191
CV1835
WDT_CRR
7:0 WDT_CRR R/W [7:0] Counter Restart Register 0x0
This register is used to restart the WDT
counter. As a safety feature to prevent
accidental restarts, the value 0x76 must
be written. A restart also clears the
WDT interrupt. Reading this register
returns zero.
ed
31:8 Reserved
w
WDT_STAT
lo
al
0 WDT_STAT RO [0] Interrupt Status Register
t
no
This register shows the interrupt status
of the WDT.
1 = Interrupt is active regardless of
e
polarity.
ar
0 = Interrupt is inactive.
31:1 Reserved
n
tio
WDT_EOI
u
ib

0 WDT_EOI RO [0] Interrupt Clear Register
r
di V
st
Clears the watchdog interrupt. This can

re k-
be used to clear the interrupt without

restarting the watchdog counter.
d il
31:1 Reserved
an M
n by
WDT_TOC
Offset Address: 0x01C
tio lic

15:0 WDT_TOC R/W Time out counter 0x0
ca ub
ifi p
od de
3.9 Real time clock

M a
M
3.9.1 Overview
Real time clock (RTC) is an independent power domain block in the chip. It contains a
32KHz oscillator and a Power-on-reset (POR) module and can be used for date clock
display and alarm clock generation. In addition, the internal hardware finite state
192
CV1835
machine provides the timing sequence control for triggering chip Power-on, Power-off
and system reset.
3.9.2 Features
The features of RTC are listed as below:
ed
Provide system reset source
w
lo
Provide 32768 Hz clock source (mismatch < ± 1%)
al
Provide a 32-bit second counter and hardware calibration circuit, which can
t
achieve a second accuracy level of 5ppm.
no
Supports alarm clock configuration and generates alarm interrupt.
e
Provides 2KB SRAM space for storing software code or temporary data
ar
Supports battery low voltage detection and generates interrupt.
n
Supports waking up the chip from sleep by pressing a button.
tio
Supports triggering chip sleep, reset, or overheating restart by software.

u
Supports Watchdog triggering system reset of the chip.

r ib
Supports waking up the chip from sleep by alarm triggering.

di V
st
re k-
Power-up/down timing, reset time interval can be configured.

d il
Provides 1 ultra-low-power analog clock counter (32 bit to count from

an M
1970~2106 year).
n by
tio lic

ca ub
ifi p
RTC is an always-on power domain module. When RTC is powered-on at the first time,
od de
its POR circuit will generate a low-level pulse, and then the 32KHz oscillator starts to
M a
M
vibrate. After POR turns to high level, RTC enters the initial state and waits for event
trigger.
When the state machine detects that the battery voltage is in a normal state, it starts to
complete the chip power-on process according to the default timing and release the
system reset signal. The software needs to initialize the RTC and configure the initial
count value after the first boot. When the system needs to shut down or enter sleep
mode, the RTC state machine can be triggered to complete the chip power-off process
193
CV1835
according to the configured timing by configuring the system control register

(RTC_CTRL).
When chip is at power-off or sleep-mode state, RTC will still keep operating and the
necessary software code or user data can be stored in RTC SRAM and also information
register (RTC_INFO0~3, RTC_NOPOR_INFO0~3); The second counter will keep counting,
ed
and at the same time the state machine keep detecting any key event trigger chip
w
power-on or wake-up from sleep. After system resumes or reboots, software can judge
lo
the chip status by reading back RTC status registers or the contents written into
al
information registers previously. Two status registers (RTC_ST_ON_REASON,
t
no
RTC_ST_OFF_REASON) are provided to record the triggering condition of last time chip
happens power-down, power-up, or reset respectively. It can provide more detail
e
ar
information, such as whether unexpected events have occurred like force reset, chip
overheat (thermal shutdown), or battery low, power supply drop, etc. In addition, RTC
n
tio
will issue system reset while receives the watchdog event.

u
ib
The RTC second counter is counting by 32KHz clock and is based on a 32-bit adder. The
r
di V
st
counter initial value can be loaded by register RTC_SET_SEC_CNTR_VALUE. The second

re k-
value can be converted into specific year, month, day, hour and minutes.
d il
an M
n by
The 32KHz clock and the second pulse period can be calibrated through a software
process or by enabling a hardware module to perform automatic calibration
tio lic
periodically.
ca ub
ifi p
Software can specify the alarm time by configuring the 32-bit register
od de
RTC_ALARM_TIME and set register bit RTC_ALARM_ENABLE to 1 to enable Alarm

M a
function. When the second counter value RTC_SEC_CNTR_VALUE equals to

M
RTC_ALARM_TIME, an alarm interrupt will be generated. The interrupt status will be

kept until RTC_ ALARM_ENABLE is set to 0.
In addition, RTC provides battery low-voltage detection function. When the battery
voltage is lower than a certain level, an interrupt will be generated. Software can
immediately execute the shutdown procedure and trigger RTC to complete the power-
down process after receiving the interrupt in order to prevent abnormal errors happen.
194
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3.9.4 Operation
3.9.4.1 Counting clock
ed
The maximum counting time of RTC second counter is:
2^32 = 49710 days = 136 years
w
lo
al
3.9.4.2 Reset RTC
t
no
RTC serves as the power-on and power-off control unit of the chip, and it cannot be
e
reset separately by software. Except for the POR at the first power-on, it supports
ar
forcing a full chip reset (including RTC) via the RSTN button in case of an exception.
n
tio
After the RSTN button is released, all RTC registers will return to their default values, and
the state machine will return to the initial state. If the state machine detects that the
u
ib
battery voltage is in a normal state, it will begin to complete the chip power-on process
r
di V
st
and release the system reset signal according to the default timing.
re k-
d il
3.9.4.3 RTC initialization

an M
n by
System needs to initialize RTC after chip is powered-on first time. The 32KHz clock and
second time period need to be calibrated flirtly. The calibration circuit uses 25MHz
tio lic
crystal clock to sample 32KHz clock. In coarse tune mode, the 25MHz crystal clock
ca ub
samples one 32KHz clock cycle period and report the counting results. Then software
ifi p
adjusts the configuration register RTC_ANA_CALIB[8:0] to speed up or slow down the

od de
32KHz clock rate depending on the counting results to improve the accuracy of 32KHz
M a
M
clock. The fine tune procedure can be further proceed after coarse tune complete. Uses
25MHz crystal clock to sample 256 32KHz clock cycles by default. Then software
calculates the average value according to the counting result to obtain the number of
pulses required for counting one second by 32KHz clock. The average value needs to be
write to the register RTC_SEC_PULSE_GEN_INT and RTC_SEC_PULSE_GEN_FRAC to
complete the second calibration process.
The coarse tune calibration process is summarized as follows:

195
CV1835
1. Configure register RTC_ANA_SEL_FTUNE as 0, and set the initial value of

RTC_ANA_CALIB as 0x100.
2. Implement calibration using binary search as follows:
FTUNE = RTC_ANA_CALIB; offset = 0x80
3. Set RTC_FC_COARSE_EN to 1 to start coarse tuning. Poll the value of
RTC_FC_COARSE_TIME until it is greater than the previous reading, then set
ed
RTC_FC_COARSE_EN to 0.
w
4. Read RTC_FC_COARSE_VALUE to obtain the count of one 32KHz clock cycle sampled
lo
by the 25MHz clock.
al
if (RTC_FC_COARSE_VALUE > 770) FTUNE = FTUNE + offset;
t
no
if (RTC_FC_COARSE_VALUE < 755) FTUNE = FTUNE - offset;
Write the FTUNE value back to the RTC_ANA_CALIB register.
e
ar
offset = offset >> 1;
5. When the value of RTC_FC_COARSE_VALUE is between 755 and 770, the accuracy of
n
tio
the 32KHz clock has reached within ±1% of 32,768Hz, and coarse tuning is completed.
Otherwise, wait for 0.5ms and repeat steps 3-5, up to a maximum of 8 times.
u
r ib
di V
st
re k-
The fine tune calibration process is summarized as follows:

d il
an M
n by
1. Configure the register RTC_SEL_SEC_PULSE to 0. Configure RTC_FC_FINE_EN to 1 to

start fine-tuning.
tio lic
2. Poll the value of RTC_FC_FINE_TIME until it is greater than the previous read value.
ca ub
3. Read RTC_FC_FINE_VALUE to obtain the count of 256 32KHz clock cycles sampled by
ifi p
the 25MHz clock.

od de
4. The frequency of the 32KHz clock can be obtained from the following equation:
M a
Frequency = 256 / (RTC_FC_FINE_VALUE x 40ns)

M
For example: 256 / (195310 x 40) = 32768.4194357

5. Take the integer part, 32768, and write it to the register RTC_SEC_PULSE_GEN_INT.
Take the fractional part, 8-bit = 0.4194357 x 256 = 107, and write it to the register
RTC_SEC_PULSE_GEN_FRAC.
6. Configure RTC_FC_FINE_EN to 0 to end fine-tuning.
196
CV1835
The clock calibration process can be performed by software as a one-time or periodic

execution, depending on the system's needs. In addition to the software calibration
process, RTC also supports automatic calibration performed periodically by hardware.
RTC needs to be further initialized after clock calibration. Only the necessary
initialization are listed below. Most of the other parameter registers need to be
ed
configured only when the timing intervals of power sequence needs to be optimized.
w
Otherwise, they are generally recommended to use the default value.
lo
al
1. Configure the RTC_POR_DB_MAGIC_KEY register with the value 0x5AF0 to enable
t
no
power-on reset (POR) debounce and prevent false triggering of POR caused by brief
voltage drops in the RTC module power supply. The debounce time is about 1ms.
e
ar
2. Set the RTC_SET_SEC_CNTR_VALUE register to initialize the RTC time counter.
n
tio
3. Write 1 to RTC_SET_SEC_CNTR_TRIG to load the initial counter value into the RTC
u
ib
second counter.
r
di V
st
re k-
4. Poll the RTC_SEC_CNTR_VALUE register until the read value equals the value in
d il
an M
RTC_SET_SEC_CNTR_VALUE.
n by
5. Set RTC_PWR_DET_COMP[0] to 1 to enable battery low voltage detection, and

tio lic
configure RTC_PWR_DET_SEL[0] to 1 to generate a low voltage detection interrupt when

ca ub
the battery voltage drops below the threshold value. The threshold value can be
ifi p
adjusted by configuring the RTC_PWR_DET_COMP[12:8] register.

od de
M a
6. After the first power-on, the RTC subsystem must be configured by setting the
M
reg_rtcsys_rstn_src_sel register from the default value of 0 to 1 to maintain the working

state of the RTC subsystem after the chip is powered down (suspend or powerdown). If
this register is set to 0, the RTC subsystem will be reset when the chip is powered down.
7. After the first power-on, the RTC_EN_AUTO_POWER_UP register must be configured

from the default value of 1 to 0. If the default value is maintained, the RTC will
197
CV1835
automatically power up when the chip enters the power-down state (powerdown) and
PWR_VBAT_DET is detected as high.
3.9.4.4 Analog Second Clock Initialization
1. Configure RTC_MACRO_RG_DEFD to 16'hC80 (32000 32KHz clock cycles)
ed
2. Configure RTC_MACRO_DA_SOC_READY to 1
w
3. Configure RTC_MACRO_DA_CLEAR_ALL to 1
lo
al
4. Configure RTC_MACRO_DA_CLEAR_ALL to 0
5. Configure RTC_MACRO_RG_SET_T to the desired Counter value
t
no
6. Configure RTC_MACRO_DA_LATCH_PASS to 1
7. Configure RTC_MACRO_DA_LATCH_PASS to 0
e
ar
8. Configure RTC_MACRO_DA_SOC_READY to 0 n
9. Read RTC_MACRO_RO_T to obtain the counter value.
u tio
ib
3.9.4.5 Interrupt handling

r
di V
st
re k-
RTC can issue alarm interrupt and low voltage interrupt. While receives the alarm
d il
an M
interrupt, set register bit RTC_ALARM_ENABLE to 0 to disable alarm and clear interrupt
state. Specify the new value to register RTC_ALARM_TIME and set RTC_ALARM_ENABLE
n by
to 1 again if a new alarm time is required.

tio lic
3.9.4.6 Suspend and wakeup

ca ub
ifi p
Set register bit req_suspend to 1 can trigger chip enter suspend/sleep mode. Specify
od de
register RTC_EN_PWR_WAKEUP can select the source that can trigger chip wake-up.
M a
Note that the register RTC_PG_REG must be written to 0 before setting req_suspend to
M
retent DDR IO state in order to prevent the mis-operation of DDR interface and protect
DDR contents during chip power-down or power-up period. After chip resumes, write
the register RTC_PG_REG to 1 to release DDR IO retention before accessing DDR.
198
CV1835
3.9.4.7 Power off and power on
By configuring the req_shdn register to 1, the system software can put the chip into a
power-off state (poweroff) including DDR. The RTC_EN_PWR_UP register can be
configured to select the source that triggers the chip to power up and boot (powerup).
ed
3.9.5 RTC register overview
w
lo
The RTC registers consist of multiple parts: RTC_CORE_REG, RTC_MACRO_REG, and
al
RTC_CTRL_REG, with different base addresses, and are all accessed through the bus.
t
no
An overview of RTC_CORE_REG registers is listed in table 3-9.
e
ar
n
Table 3- 9 RTC_REG register overview (base address: 0x05026000)
tio

u
Offset
ib
RTC_ANA_CALIB 0x000 32K 振荡器控制

r
RTC_SEC_PULSE_GEN 0x004
di V
秒脉冲产生器整数位与小数位
st
re k-
RTC_ALARM_TIME 0x008 设定定时报警时间

RTC_ALARM_ENABLE 0x00c 使能报警
d il
RTC_SET_SEC_CNTR_VALUE 0x010
an M
设定秒计数器值
RTC_SET_SEC_CNTR_TRIG 0x014 加载秒计数器值
RTC_SEC_CNTR_VALUE 0x018
n by
读取目前秒计数器值
RTC_INFO0 0x01c 信息寄存器 0
RTC_INFO1 0x020 信息寄存器 1
tio lic

ca ub

RTC_NOPOR_INFO0 0x02c 无复位信息寄存器 0
ifi p
RTC_NOPOR_INFO1 0x030 无复位信息寄存器 1

od de

M a
RTC_DB_PWR_VBAT_DET 0x040 PWR_VBAT_DET 去抖动时间

M
RTC_DB_BUTTON1 0x048 PWR_BUTTON1 去抖动时间

RTC_DB_PWR_ON 0x04c PWR_ON 去抖动时间
RTC_7SEC_RESET 0x050 设定长按 PWR_BUTTON 秒数强制 reset
RTC_THM_SHDN_AUTO_REBOOT 0x064 选择 REQ_THM_SHDN 动作
RTC_POR_DB_MAGIC_KEY 0x068 使能 POR 长时去抖动
RTC_DB_SEL_PWR 0x06c 选择 PWR_BUTTON 去抖动模式
RTC_UP_SEQ0 0x070 上电 PWR_SEQ0 输出时序
RTC_UP_SEQ3 0x07c 上电 PWR_SEQ3 输出时序
RTC_UP_IF_EN 0x080 上电 ISO 解除时序
RTC_UP_RSTN 0x084 上电系统复位解除时序
199
CV1835

Offset
RTC_UP_MAX 0x088 上电流程完成时序
RTC_DN_SEQ0 0x090 下电 PWR_SEQ0 输出时序
RTC_DN_SEQ3 0x09c 下电 PWR_SEQ3 输出时序
RTC_DN_IF_EN 0x0a0 下电 ISO 打开时序
RTC_DN_RSTN 0x0a4 下电系统复位发出时序
ed
RTC_DN_MAX 0x0a8 下电流程完成时序
RTC_PWR_CYC_MAX 0x0b0 Power-cycle 完成时序
w
RTC_WARM_RST_MAX 0x0b4 Warm-reset 完成时序
lo
RTC_EN_7SEC_RST 0x0b8 设定 PWR_BUTTON1 7SEC reset 模式
RTC_EN_PWR_WAKEUP 0x0bc 设定休眠唤醒来源
al
RTC_EN_SHDN_REQ 0x0c0 使能 REQ_SHDN
t
RTC_EN_THM_SHDN 0x0c4 使能 REQ_THM_SHDN
no
RTC_EN_PWR_CYC_REQ 0x0c8 使能 REQ_PWR_CYC
RTC_EN_WARM_RST_REQ 0x0cc 使能 REQ_WARM_RST
e
RTC_EN_PWR_VBAT_DET 0x0d0 使能状态机参考 PWR_VBAT_DET
ar
FSM_STATE 0x0d4 RTC 状态机值
RTC_EN_WDG_RST_REQ 0x0e0 使能 REQ_WDG_RST n
RTC_EN_SUSPEND_REQ 0x0e4 使能 REQ_SUSPEND
tio
RTC_DB_REQ_WDG_RST 0x0e8 REQ_WDG_RST 去抖动时间
RTC_DB_REQ_SUSPEND 0x0ec REQ_SUSPEND 去抖动时间
u
RTC_PG_REG 0x0f0 Power Good 寄存器

ib
RTC_ST_ON_REASON 0x0f8 上电状态寄存器

r
RTC_ST_OFF_REASON 0x0fc 下电状态寄存器

di V
st
RTC_EN_WAKEUP_REQ 0x120 使能 REQ_WAKEUP

re k-
RTC_PWR_WAKEUP_POLARITY 0x128 选择 PWR_WAKEUP 低电平

d il
RTC_DB_SEL_REQ 0x130 选择去抖动模式

an M
RTC_PWR_DET_SEL 0x140 选择低电压检测信号来源

n by
An overview of RTC_MACRO_REG registers is listed in table 3-10.

tio lic
ca ub
Table 3-10 RTC_MACRO_REG register overview(base address 0x05026400)

ifi p

Offset
od de
RTC_PWR_DET_COMP 0x044 低电压检测控制

M a
RTC_MACRO_DA_CLEAR_ALL 0x080 DA_CLEAR_ALL

M
RTC_MACRO_DA_SET_ALL 0x084 DA_SEL_ALL

RTC_MACRO_DA_LATCH_PASS 0x088 DA_LATCH_PASS
RTC_MACRO_DA_SOC_READY 0x08c DA_SOC_READY
RTC_MACRO_PD_SLDO 0x090 PD_SLDO
RTC_MACRO_RG_DEFD 0x094 RG_DEFD
RTC_MACRO_RG_SET_T 0x098 RG_SET_T
RTC_MACRO_RO_CLK_STOP 0x0a0 RO_CLK_STOP
RTC_MACRO_RO_DEFQ 0x0a4 RO_DEFQ
RTC_MACRO_RO_T 0x0a8 RO_T
200
CV1835
An overview of RTC_CTRL registers is listed in table 3-11.
Table 3- 11 RTC_CTRL register overview (base address: 0x03004000)

Offset
ed
rtc_ctrl_unlockkey 0x004 rtc_ctrl_unlockkey
rtc_ctrl0 0x008 rtc_ctrl0
w
rtc_ctrl_status0 0x00c rtc_ctrl_status0
lo
rtc_ctrl_status1 0x010 rtc_ctrl_status1
rtc_ctrl_status2gpio 0x014 rtc_ctrl_status2gpio
al
rtcsys_rst_ctrl 0x018 rtcsys_rst_ctrl
rtcsys_clkmux 0x01c rtcsys_clkmux
t
no
rtcsys_mcu51_ctrl0 0x020 rtcsys_mcu51_ctrl0
rtcsys_pmu 0x028 rtcsys_pmu
e
rtcsys_status 0x02c rtcsys_status
ar
rtcsys_clkbyp 0x030 rtcsys_clkbyp
rtcsys_clk_en 0x034 rtcsys_clk_en
n
rtcsys_wkup_ctrl 0x038 rtcsys_wkup_ctrl
tio
rtcsys_clkdiv 0x03c rtcsys_clkdiv

fc_coarse_en 0x040 fc_coarse_en
u
fc_coarse_cal 0x044 fc_coarse_cal

ib
fc_fine_en 0x048 fc_fine_en

r
fc_fine_period 0x04c fc_fine_period

di V
st
fc_fine_cal 0x050 fc_fine_cal

re k-
rtcsys_pmu2 0x054 rtcsys_pmu2

d il
rtcsys_clkdiv1 0x058 rtcsys_clkdiv1

an M
rtcsys_mcu51_dbg 0x05c rtcsys_mcu51_dbg

sw_reg0 0x060 sw_reg0
n by
sw_reg1_por 0x064 sw_reg1_por

fab_lp_ctrl 0x068 fab_lp_ctrl
tio lic
fab_option 0x06c fab_option

rtcsys_mcu51_ictrl1 0x07c rtcsys_mcu51_ictrl1
ca ub
rtc_ip_pwr_req 0x080 rtc_ip_pwr_req

rtc_ip_iso_ctrl 0x084 rtc_ip_iso_ctrl
ifi p
rtcsys_spare_reg0 0x088 rtcsys_spare_reg0

od de
rtcsys_spare_reg1 0x08c rtcsys_spare_reg1

rtcsys_spare_ro 0x090 rtcsys_spare_ro
M a
rtcsys_wkup_ctrl1 0x094 rtcsys_wkup_ctrl1

M
rtcsys_sram_ctrl 0x098 rtcsys_sram_ctrl

rtcsys_io_ctrl 0x09c rtcsys_io_ctrl
rtcsys_wdt_ctrl 0x0a0 rtcsys_wdt_ctrl
rtcsys_irrx_clk_ctrl 0x0a4 rtcsys_irrx_clk_ctrl
rtcsys_rtc_wkup_ctrl 0x0a8 rtcsys_rtc_wkup_ctrl
rtcsys_por_rst_ctrl 0x0ac rtcsys_por_rst_ctrl
201
CV1835
3.9.6 RTC register description
3.9.6.1 RTC_CORE_REG
RTC_ANA_CALIB
ed
w
15:0 RTC_ANA_CALIB R/W Adjusting the frequency of the analog 0x100
lo
module's 32K oscillator.
al
17:16 RTC_ANA_ISEL R/W Adjusting the current of the analog 0x3
module's 32K XTAL oscillator.
t
00 = 2uA, 01 = 1.5uA, 11 = 0.5uA
no
30:18 Reserved
31 RTC_ANA_SEL_FTUNE R/W Select 32K OSC calibration value source: 0x1
e
0 = controlled by RTC_ANA_CALIB
ar
register
1 = controlled by hardware circuitry
n
RTC_SEC_PULSE_GEN
tio

u

ib
7:0 RTC_SEC_PULSE_GEN_FRAC R/W the fractional part of the second pulse 0x0
r
generator
di V
st
23:8 RTC_SEC_PULSE_GEN_INT R/W the integer part of the second pulse 0x8000
re k-
generator
d il
When the counter increment value is

an M
greater than the integer part value, a

second pulse signal is generated to
increment the second counter.
n by
30:24 Reserved
31 RTC_SEL_SEC_PULSE R/W Select the source of second pulse signal: 0x1
tio lic
0 = Second pulse signal is generated

ca ub
internally.
1 = Second pulse signal is generated by
ifi p
external hardware circuit.

When set to 1, the registers
od de
RTC_SEL_PULSE_GEN_FRAC and
RTC_SEL_PULSE_GEN_INT have no
M a
effect.
M
RTC_ALARM_TIME
31:0 RTC_ALARM_TIME R/W Set the time for timed alarm. 0xffffffff
RTC_ALARM_ENABLE
0 RTC_ALARM_ENABLE R/W Alarm Enable 0x0
Set to 1 to enable the alarm, set to 0 to
202
CV1835

disable or clear the alarm interrupt
status.
31:1 Reserved
RTC_SET_SEC_CNTR_VALUE
31:0 RTC_SET_SEC_CNTR_VALUE R/W Set the value of the second counter. 0x0
ed
RTC_SET_SEC_CNTR_TRIG
w
lo
al
0 RTC_SET_SEC_CNTR_TRIG W1C Load seconds counter value.
Set to 1 to enable
t
RTC_SET_SEC_CNTR_VALUE to take
no
effect. The register will automatically
clear to 0 after being written to 1.
31:1 Reserved
e
RTC_SEC_CNTR_VALUE
ar
n
tio

31:0 RTC_SEC_CNTR_VALUE RO Read current value of the second
u
counter.
ib
RTC_INFO0
r
di V
st

re k-

d il
31:0 RTC_INFO0 R/W Information register 0 0xABCD

an M
1234
n by
RTC_INFO1
tio lic

31:0 RTC_INFO1 R/W Information register 1 0xDEAD
ca ub
BEEF
ifi p
RTC_INFO2
od de

M a
M
31:0 RTC_INFO2 R/W Information register 2 0xABCD

1234
RTC_INFO3
31:0 RTC_INFO3 R/W Information register 3 0xDEAD
BEEF
RTC_NOPOR_INFO0
203
CV1835

31:0 RTC_NOPOR_INFO0 R/W No reset information register 0 Random
RTC_NOPOR_INFO1
RTC_NOPOR_INFO2
ed
w
lo
RTC_NOPOR_INFO3
al
t
no
RTC_APB_BUSY_SEL
e
ar
n
3:0 Reserved R/W
tio
4 rtc_apb_32k_busy_sel R/W Select the source of the RTC PCLK busy 0x0
signal (keep PCLK at full speed when
u
busy):
ib
0 = The PCLK busy signal is generated by

r
the hardware circuit.

di V
st
1 = The PCLK busy signal is controlled by

re k-
the register rtc_apb_32k_force_busy.

d il
7:5 Reserved
an M
8 rtc_apb_32k_force_busy R/W 1 = PCLK runs at full speed always. 0x0

0 = PCLK only returns to full speed when
n by
PSel is asserted.
31:9 Reserved
tio lic
RTC_DB_PWR_VBAT_DET
ca ub

ifi p
15:0 RTC_DB_PWR_VBAT_DET R/W PWR_VBAT_DET debounce time (unit: 0x2

od de
32K clocks)
31:16 Reserved
M a
M
RTC_DB_BUTTON1
15:0 RTC_DB_BUTTON1 R/W PWR_BUTTON1 debounce time (unit: 0x100
32K clocks)
The default value 0x100 is about 8ms.
31:16 Reserved
RTC_DB_PWR_ON
204
CV1835

15:0 RTC_DB_PWR_ON R/W PWR_ON debounce time (unit: 32K 0x100
clocks)
31:16 Reserved
RTC_7SEC_RESET
7:0 RTC_7SEC_RESET R/W Long press PWR_BUTTON1 reset 0x7
ed
debounce time (unit: seconds).
This register will only be cleared by POR.
w
15:8 Reserved
lo
31:16 RTC_7SEC_UNLOCK_KEY WO Writing 0xDC78 at the same time can 0x0
remove the write protection of
al
RTC_7SEC_RESET.
t
no
RTC_THM_SHDN_AUTO_REBOOT
e
ar
0 RTC_THM_SHDN_AUTO_REBOOT R/W Select the behavior when receiving 0x0
REQ_THM_SHDN:
n
0 = start power-off process
tio
1 = start power-cycle process (power off
and then power on again)
31:1 Reserved
u
ib
RTC_POR_DB_MAGIC_KEY
r
di V
st

re k-

d il
15:0 RTC_POR_DB_MAGIC_KEY R/W Writing 0x5AF0 will cause a POR Random

an M
debounce (approximately 1ms).

31:16 Reserved
n by
RTC_DB_SEL_PWR
tio lic

ca ub
0 Reserved
ifi p
1 DB_SEL_PWR_BUTTON1 R/W Select the debounce mode for 0x1

PWR_BUTTON1:
od de
0 = The state machine uses the falling

edge of the PWR_BUTTON1 debounce
M a
M
signal as trigger.
1 = The state machine uses the low level
of the PWR_BUTTON1 debounce signal
as trigger.
2 DB_SEL_PWR_ON R/W Select PWR_ON debounce mode: 0x1
0 = The state machine is triggered by
the rising edge of the PWR_ON
debounce signal.
1 = The state machine is triggered by
the high level of the PWR_ON debounce
signal.
3 DB_SEL_PWR_WAKEUP0 R/W Select PWR_WAKEUP0 debounce mode 0x1
0 = The state machine triggers on the
205
CV1835

rising edge of PWR_WAKEUP0
debounce signal
1 = The state machine triggers on the
high level of PWR_WAKEUP0 debounce
signal.
4 DB_SEL_PWR_WAKEUP1 R/W Select PWR_WAKEUP1 debounce mode: 0x1
0 = State machine triggers on rising
edge of PWR_WAKEUP1 debounce
signal.
ed
31:5 Reserved
w
RTC_UP_SEQ0
lo
al
15:0 RTC_UP_SEQ0 R/W Power-on sequence PWR_SEQ0 rising 0x0
t
time from 0 to 1 (unit: 32K clocks)
no
31:16 Reserved
e
RTC_UP_SEQ1
ar
n
tio

31:16 Reserved
u
ib
RTC_UP_SEQ2
r
di V
st

re k-

d il

an M

31:16 Reserved
n by
RTC_UP_SEQ3
tio lic

ca ub
15:0 RTC_UP_SEQ3 R/W Power-on sequence PWR_SEQ3 rising 0xc0

ifi p

31:16 Reserved
od de
RTC_UP_IF_EN
M a
M

15:0 RTC_UP_IF_EN R/W Time for releasing the isolation of the 0x100
power-off area during the power-on
sequence (unit: 32K clock).
31:16 Reserved
RTC_UP_RSTN
15:0 RTC_UP_RSTN R/W Power-up process system reset release 0x140
time (unit: 32K clock)
206
CV1835

31:16 Reserved
RTC_UP_MAX
15:0 RTC_UP_MAX R/W Complete power-up sequence 0x180
completion time (unit: 32K clocks).
RTC_UP_SEQ0~RTC_UP_MAX are the
ed
absolute timing of each stage of the
power-up sequence. It is recommended
w
to use the default values.
31:16 Reserved
lo
al
RTC_DN_SEQ0
t
no
15:0 RTC_DN_SEQ0 R/W The time for PWR_SEQ0 output to 0x140
e
transition from 1 to 0 during the power-
ar
down process (in units of 32K clock).
31:16 Reserved n
tio
RTC_DN_SEQ1
u

ib

r

di V
st

re k-
31:16 Reserved
d il
an M
RTC_DN_SEQ2
n by

15:0 RTC_DN_SEQ2 R/W The time for PWR_SEQ2 output to 0xc0
tio lic

ca ub
31:16 Reserved
ifi p
RTC_DN_SEQ3
od de

M a

M

31:16 Reserved
RTC_DN_IF_EN
15:0 RTC_DN_IF_EN R/W The duration for opening the isolation 0x40
signal of the power-down area during
the power-down process (unit: 32K
clock).
207
CV1835

31:16 Reserved
RTC_DN_RSTN
15:0 RTC_DN_RSTN R/W Time for the power-down process to 0x0
issue a system reset (unit: 32K clock).
31:16 Reserved
ed
RTC_DN_MAX
w
lo
al
15:0 RTC_DN_MAX R/W Complete shutdown or sleep process 0x180
completion time (unit: 32K clock cycles).
t
RTC_DN_SEQ0~RTC_DN_MAX are the
no
absolute timing of each stage of the
shutdown process, and it is
e
recommended to use the default values.
ar
31:16 Reserved
n
RTC_PWR_CYC_MAX
tio

u
15:0 RTC_PWR_CYC_MAX R/W Complete Power-cycle process 0x4000

ib
completion time (Unit: 32K clock)

r
The Power-cycle time includes the

di V
st
complete down sequence process and

re k-
up sequence process.
d il
31:16 Reserved
an M
RTC_WARM_RST_MAX
n by

tio lic
15:0 RTC_WARM_RST_MAX R/W Complete WARM_RESET process 0x40

completion time (unit: 32K clocks)
ca ub
Equivalent to the low-level time of

ifi p
system reset.
31:16 Reserved
od de
RTC_EN_7SEC_RST
M a
M

0 RTC_EN_7SEC_RST R/W Enable long-pressing PWR_BUTTON1 0x0
for 7 seconds to trigger RTC forced
reset.
1 RTC_7SEC_RST_MODE R/W 7-second forced reset mode 0x0
0 = Low-level mode, 1 = Short-pulse
mode
When a 7-second forced reset occurs,
select whether to generate a short pulse
reset signal or keep the reset until the
PWR_BUTTON1 button is released.
2 DB_SEL_PWR_BUTTON1_7SEC R/W 0 = Reset 7-second reset counter if 0x0
208
CV1835

PWR_BUTTON1 is pressed after power-
up sequence is triggered.
1 = NOP.
3 SEL_7SEC_RST_RTCSYS R/W 0 = The 7-second forced reset signal will 0x1
reset the RTC subsystem (sec reset will
reset rtcsys).
1 = The RTC subsystem will not be reset.
15:4 Reserved
31:16 RTC_EN_7SEC_UNLOCK_KEY WO Simultaneously writing 0xDC78 can 0x0
ed
remove the write protection for [3:0].
w
RTC_EN_PWR_WAKEUP
lo
al
6:0 RTC_EN_PWR_WAKEUP R/W Set the source that can trigger wake-up 0x0
t
from self-sleep mode:
no
0 = Cannot trigger wake-up
1 = Can trigger wake-up.
e
[0] = PWR_WAKEUP0
ar
[1] = PWR_WAKEUP1
[2] = PWR_ON
n
[3] = REQ_POWERUP
tio
[4] = PWR_BUTTON1
[5] = Alarm
[6] = REQ_WAKEUP
u
ib
7 Reserved
14:8 RTC_EN_PWR_UP R/W Set the sources that can trigger power- 0x14
r
di V
on.
st
re k-
0 = Cannot trigger power-on.

1 = Can trigger power-on.
d il
[8] = PWR_WAKEUP0
an M
[9] = PWR_WAKEUP1
[10] = PWR_ON
n by
[11] = REQ_POWERUP
[12] = PWR_BUTTON1
tio lic
[13] = Alarm
[14] = REQ_WAKEUP
ca ub
31:15 Reserved
ifi p
RTC_EN_SHDN_REQ
od de

M a

M
0 RTC_EN_SHDN_REQ R/W Enable software to request power 0x0

down. (REQ_SHDN)
0 = disable, 1 = enable
31:1 Reserved
RTC_EN_THM_SHDN
0 RTC_EN_THM_SHDN R/W Enable request for thermal shutdown or 0x0
reboot.(REQ_THM_SHDN)
31:1 Reserved
209
CV1835
RTC_EN_PWR_CYC_REQ
0 RTC_EN_PWR_CYC_REQ R/W Enable request for Power-cycle 0x0
(REQ_PWR_CYC)
31:1 Reserved
RTC_EN_WARM_RST_REQ
ed
Offset Address: 0x0cc
w
0 RTC_EN_WARM_RST_REQ R/W Enable request for a system soft restart. 0x0
lo
(REQ_WARM_RST)
al
31:1 Reserved
t
no
RTC_EN_PWR_VBAT_DET
e
ar
0 RTC_EN_PWR_VBAT_DET_UP R/W Enable State Machine to Reference 0x1
Battery Low Voltage Detection State
n
(PWR_VBAT_DET)
tio
If this value is set to 1, when any button
u
attempts to trigger power-on or wake-

ib
up, the state machine will check the low

voltage detection output value. If the
r
di V
st
low voltage detection output is low

re k-
(indicating low battery voltage or no

power supply), the RTC state machine
d il
will maintain the current state without

an M
changing.
1 RTC_EN_PWR_VBAT_DET_DN R/W Enable power off on battery low voltage 0x1
n by
status:
tio lic
If this value is set to 1, when the chip is

powered on or in sleep mode, the RTC
ca ub
state machine will check the low voltage

detection output. If the low voltage
ifi p
detection output transitions from high

to low (indicating low battery voltage or
od de
power loss), the state machine will

M a
trigger the power-off process.

M
2 RTC_EN_AUTO_POWER_UP R/W Enable RTC state machine to 0x1

automatically enter power-up state:
1 = Automatically power-up when
entering Power-down and
PWR_VBAT_DET is at high level.
0 = Stay in this state when entering
Power-down, until any power-up source
is triggered.
31:3 Reserved
FSM_STATE
210
CV1835

3:0 FSM_STATE RO RTC state machine values:
4’h0 = ST_OFF (Power-off completed)
4’h1 = ST_UP (Power-up process in
progress)
4’h2 = ST_DN (Power-down process in
progress)
4’h3 = ST_ON (Power-on completed)
4’h4 = ST_PWR_CYC2 (Power-cycle
power-down completed)
ed
4’h6 = ST_PWR_CYC (Power-cycle
power-down in progress)
w
4’h7 = ST_WARM_RESET (System reset
in progress)
lo
4’h9 = ST_SUSP (System suspended)
al
4’hB = ST_PRE_SUSP (Suspend power-
down process in progress)
t
31:4 Reserved
no
RTC_EN_WDG_RST_REQ
e
ar
n Reset
0 RTC_EN_WDG_RST_REQ R/W Enable Watchdog to request reset of 0x0
tio
system(REQ_WDG_RST)
1 RTC_EN_SUS_WDG_RST_REQ R/W Enable Watchdog to request system 0x1
u
reset when in Sleep Mode.

ib
r
di V
31:2 Reserved
st
re k-
RTC_EN_SUSPEND_REQ
d il
an M

n by
0 RTC_EN_SUSPEND_REQ R/W Enable request for 0x0

sleep(REQ_SUSPEND)
tio lic
31:1 Reserved
ca ub
RTC_PG_REG
ifi p

od de

3:0 RTC_PG_REG R/W Chip Power Good Status 0xF
M a
1 = Chip powered on (Power Good), IO

M
signals can pass through

0 = Chip powered off, IO signals are in
retentive state
[0] = Controls DDR IO
[3:1] = Reserved
This register signal is used to control
whether the chip and DDR IO interface
are normally passed through or in
retentive state. Before the system
enters sleep, the software must first set
the value of this register to 0 to keep
the DDR IO in a fixed state. After the
system is awakened from sleep, the
211
CV1835

value of this register must be set to 1 to
restore normal operation of the DDR.
When entering power-down state, the
value of this register will be
automatically cleared to all 1.
31:4 Reserved
RTC_ST_ON_REASON
ed
w
3:0 ST_ON_REASON_LAST_STATE RO RTC state machine returns to power-on
completion (ST_ON) state from the
lo
following states:
al
4'h0 = Return from power-off (ST_OFF)
to power-on state
t
4'h3 = Return from Power-cycle or
no
Warm-reset to power-on state
4'h9 = Return from sleep to power-on
e
state
ar
After system reboot, software can read
this register to determine the cause of
n
the chip's power-on.
tio
15:4 Reserved
31:16 ST_ON_REASON_LAST_INPUT RO Trigger reasons for the state machine to
u
return to the power-on state (record the

ib
status value of each signal):

[0] = PWR_VBAT_DET (0: power-off
r
di V
st
triggered)
re k-
[1] = PWR_ON (1: power-on triggered

by button)
d il
an M
[2] = RTC_EN_AUTO_POWER_UP
[3] = PWR_BUTTON1 (0: power-on
triggered by button)
n by
[4] = PWR_BUTTON1_7SEC
[5] = PWR_WAKEUP0 (1: wakeup
tio lic
[6] = PWR_WAKEUP1 (1: wakeup
ca ub
[7] = Alarm (1: timed alarm occurred)
ifi p
[8] = REQ_PWR_CYC (1: software-

od de
triggered Power-cycle)
[9] = REQ_THM_SHDN (1: software-
M a
triggered power-off/power-cycle)
M
[10] = REQ_WARM_RST (1: software-

triggered reset)
[11] = REQ_WDG_RST (1: Watchdog-
triggerd reset)
[12] = REQ_SHDN (1: software-triggered
power-off)
[13] = REQ_SUSPEND (1: software-
triggered suspend)
[14] = REQ_WAKEUP (1: event-triggered
wakeup)
[15] = REQ_POWERUP
RTC_ST_OFF_REASON
212
CV1835

3:0 ST_OFF_REASON_LAST_STATE RO RTC state machine has previously
entered power-down (ST_OFF) from the
following states:
4'h3 = Entered power-down from
power-on (ST_ON)
4'h9 = Entered power-down from
suspend (ST_SUSP)
Others = 7-second forced reset occurred
ed
After system restart, software can
determine the reason for the previous
w
power-down by reading this register.
lo
15:4 Reserved
al
31:16 ST_OFF_REASON_LAST_INPUT RO Reasons for the state machine entering
power-down (record signal state value):
t
[14:0] same as
no
ST_ON_REASON_LAST_INPUT
[15] = 0: Forced reset occurred in 7
seconds.
e
ar
RTC_EN_WAKEUP_REQ
n
tio
0 RTC_EN_WAKEUP_REQ R/W Enable event request to wake up from 0x0

suspend state:
u
ib
1 RTC_EN_POWERUP_REQ R/W Enabled event request power-on: 0x0

r
di V
st
re k-
31:2 Reserved
d il
an M
RTC_PWR_WAKEUP_POLARITY
n by

0 PWR_WAKEUP0_POLARITY R/W Select PWR_WAKEUP0 active polarity: 0x1
1 = High level active
tio lic
0 = Low level active

ca ub
1 PWR_WAKEUP1_POLARITY R/W Select PWR_WAKEUP1 active polarity: 0x1

1 = High level active
ifi p
0 = Low level active

31:2 Reserved
od de
M a
RTC_DB_SEL_REQ
M

0 DB_SEL_REQ_SHDN R/W Select debounce mode for software 0x1
signal REQ_SHDN:
0 = Triggered by rising edge of register
value
1 = Triggered by pulse signal of register
1 DB_SEL_REQ_THM_SHDN R/W Select debounce mode for signal 0x1
REQ_THM_SHDN:
0 = triggered by high level of signal
1 = triggered by rising edge of signal
2 DB_SEL_REQ_PWR_CYC R/W Select debounce mode for software 0x1
213
CV1835

signal REQ_PWR_CYC:
value
3 DB_SEL_REQ_WARM_RST R/W Select debounce mode for software 0x1
signal REQ_WARM_RST:
value
ed
4 DB_SEL_REQ_WDG_RST R/W Select debounce mode for signal 0x1
REQ_WDG_RST:
w
0 = Triggered by signal high level
1 = Triggered by rising edge of signal.
lo
5 DB_SEL_REQ_SUSPEND R/W Select debounce mode for software 0x1
al
signal REQ_SUSPEND:
t
value
no
6 DB_SEL_REQ_WAKEUP R/W Select debounce mode for signal 0x1
e
REQ_WAKEUP:
ar
n
7 DB_SEL_REQ_POWERUP R/W Select debounce mode for signal 0x1
tio
REQ_POWERUP:
u

ib
31:8 Reserved
r
di V
st
RTC_PWR_DET_SEL
re k-

d il

an M
0 pwr_det_o_sel_comp R/W Select the source of the status signal 0x0

output for low-voltage detection:
n by
0 = Directly from IO PWR_VBAT_DET

1 = From the analog low-voltage
tio lic
detection circuit output

The low-voltage detection status value
ca ub
can be read from register

RTC_CTRL_STATUS0[0].
ifi p
1 pwr_det_i_sel_comp R/W Select the source of low-voltage trigger 0x0

power-off signal for the RTC state
od de
machine:
0 = Directly from IO PWR_VBAT_DET
M a
1 = From analog low-voltage detection

M
circuit output
31:2 Reserved
214
CV1835
3.9.6.2 RTC_MACRO_CTRL
RTC_PWR_DET_COMP
ed
0 pwr_det_comp_enable R/W Enable analog module low voltage 0x0
detection:
w
1 = enable
lo
0 = disable
7:1 Reserved
al
12:8 pwr_det_comp_sel R/W Setting low voltage detection voltage 0xf
t
comparison threshold.
no
Threshold = 1.20V +
(pwr_det_comp_sel * 12.5mV)
31:13 Reserved
e
RTC_MACRO_DA_CLEAR_ALL
ar
n
tio

0 DA_CLEAR_ALL R/W 0x0
u
ib
31:1 Reserved
r
di V
st
RTC_MACRO_DA_SET_ALL
re k-
d il

an M

0 DA_SEL_ALL R/W 0x0
n by
31:1 Reserved
tio lic
RTC_MACRO_DA_LATCH_PASS
ca ub

ifi p
0 DA_LATCH_PASS R/W 0x0

od de
31:1 Reserved
M a
M
RTC_MACRO_DA_SOC_READY
0 DA_SOC_READY R/W 0x0
31:1 Reserved
RTC_MACRO_PD_SLDO
0 PD_SLDO R/W 0x0
215
CV1835

31:1 Reserved
RTC_MACRO_RG_DEFD
15:0 RG_DEFD R/W 0x7fff
31:16 Reserved
ed
RTC_MACRO_RG_SET_T
w
lo
al
31:0 RG_SET_T R/W 0x0
t
no
RTC_MACRO_RO_CLK_STOP
e
ar
0 RO_CLK_STOP RO
n
31:1 Reserved
tio
RTC_MACRO_RO_DEFQ
u
ib

r

di V
st
re k-
15:0 RO_DEFQ RO
31:16 Reserved
d il
an M
RTC_MACRO_RO_T
n by

tio lic
31:0 RO_T RO
ca ub
ifi p
od de
3.9.6.3 RTC_CTRL
M a
M
RTC_CTRL0_UNLOCKKEY
15:0 rtc_ctrl0_unlockkey R/W The value 0xab18 must be written to 0x0000
this register to unlock the write
permission of register RTC_CTRL0.
If unlockkey_clear is set to 1, the
register value will be automatically
cleared to 0 after a write operation to
RTC_CTRL0, and RTC_CTRL0 will return
216
CV1835

to write lock.
31:16 Reserved
RTC_CTRL0
0 req_shdn R/W request power down 0x0
ed
0 = no action, 1 = request to RTC
Register RTC_ EN_ SHDN_ REQ must be
w
set to 1.
1 req_sw_thm_shdn R/W Software mode request thermal 0x0
lo
shutdown
al
Register RTC_ EN_ THM_ SHDN must be
t
set to 1.
no
2 hw_thm_shdn_en R/W Enable hardware thermal shutdown 0x0
0 = diable, 1 = enable
e
Register RTC_ EN_ THM_ SHDN must be
ar
set to 1.
3 req_pwr_cyc R/W Request power cycle 0x0
n
Register RTC_ EN_ PWR_ CYC_ REQ
tio
must be set to 1.
4 req_warm_rst R/W Request Warm-reset 0x0
u

ib
Register RTC_EN_WARM_RST_REQ
r
must be set to 1.
di V
st
5 req_sw_wdg_rst R/W Software mode request Watchdog reset 0x0

re k-

d il
Register RTC_EN_WDG_RST_REQmust
an M
be set to 1 to be valid.
6 hw_wdg_rst_en R/W Enable hardware mode Watchdog reset 0x0
n by
0 = diable, 1 = enable
7 req_suspend R/W Request suspend 0x0
tio lic
Register RTC_ EN_ SUSPEND_ REQ must

ca ub
be set to 1.
8 unlockkey_clear R/W Enable auto clear register unlock 0x0
ifi p
9 Reserved
10 reg_rtc_mode R/W The source of 32K clock 0x0
od de
0 = OSC32K, 1 = XTAL32K
11 reg_clk32k_cg_en R/W The switch of 32K clock 0x1
M a
M
0 = close, 1 = open
31:12 Reserved
RTC_CTRL_STATUS0
0 rtc_pwr_vbat_det_o RO Low voltage detection status signal
output
1 rtc_pwr_button0_o RO PWR_BUTTON0 IO signal output
2 rtc_pwr_button1_o RO PWR_BUTTON1 IO signal output
3 Reserved
217
CV1835

4 rtc_pwr_on_o RO PWR_ON IO signal output
5 rtc_pwr_wakeup0_o RO PWR_WAKEUP0 IO signal output
6 rtc_pwr_wakeup1_o RO PWR_WAKEUP1 IO signal output
7 rtc_mode_o RO RTC_MODE IO signal output
20:8 Reserved
21 rtc_alarm_o RO Alarm status
22 hw_thm_shdn_sta_i RO Thermal shutdown status signal
ed
23 hw_wdg_rst_sta_i RO Watchdog reset status signal
24 sys_reset_x_i RO
w
25 cg_en_out_clk_32k RO
lo
29:26 rtc_fsm_st RO Value of the RTC state machine.
31:30 Reserved
al
t
RTC_CTRL_STATUS1
no
e
31:0 rtc_sec_value_o RO RTC second counter value
ar
n
tio
rtc_ctrl_status2gpio
u

ib
7:0 status2gpio_en R/W 0x0

r
di V
31:8 Reserved
st
re k-
rtcsys_rst_ctrl
d il
an M

n by
0 Reserved
1 reg_soft_rstn_mcu R/W 0 : reest MCU 0x0
tio lic
2 reg_soft_rstn_sdio R/W 0 : reset SD1 0x1

3 reg_soft_rstn_uart R/W 0 : reset Uart 0x1
ca ub
4 reg_soft_rstn_spinor R/W 0 : reset spinor1 0x1

5 reg_soft_rstn_ictl R/W 0 : reset dw_ictl 0x1
ifi p
6 reg_soft_rstn_mbox R/W 0 : reset mbox 0x1

od de
7 reg_soft_rstn_fab_hs2rtc R/W 0 : reset hs2rtc 0x1

8 reg_soft_rstn_fab_rtc2ap R/W 0 : reset rtc2ap 0x1
M a
9 reg_soft_rstn_fab_sram R/W 0 : reset ahb sram logic 0x1

M
10 reg_soft_rstn_apb R/W no load 0x1

11 reg_soft_rstn_apb_timer R/W 0 : reset dw timer apb logic 0x1
12 reg_soft_rstn_timer0 R/W 0 : reset dw timer0 0x1
14 reg_soft_rstn_osc R/W 0 : reset osc 0x1
15 reg_soft_rstn_gpio R/W 0 : reset gpio 0x1
16 reg_soft_rstn_i2c R/W 0 : reset i2c 0x1
17 reg_soft_rstn_saradc R/W 0 : reset saradc 0x1
18 reg_soft_rstn_wdt R/W 0 : reset wdt 0x1
19 reg_soft_rstn_irrx R/W 0 : reset irrx 0x1
20 reg_soft_rstn_f32kless R/W 0: reset f32kless 0x1
31:21 Reserved
218
CV1835
rtcsys_clkmux
3:0 reg_sdio_clk_mux R/W clk_sd1_pre 0x0
0 : fpll/4 1: osc_div
7:4 reg_fab_clk_mux R/W clk_fab_pre 0x0
0 : 32K, 1: fpll/5, 2: osc_div
9:8 reg_timer0_clk_mux R/W 0: xtal 0x0
1: 32K
ed
1: 32K
13:12 reg_apb_clk_mux R/W 00 : cgdiv and refer to apbactive 0x1
w
01 : force clk_apb, clk_fab 1:1 (default)
lo
10 : force clk_apb, clk_fab 1:2
al
15:14 Reserved
t
17:16 reg_i2c_clk_mux R/W 0: xtal 0x0
no
1: osc div
19:18 reg_sd_mclk_clk_mux R/W 0: 100Khz from OSC, 1: 32K 0x0
e
20 reg_saradc_clk_mux R/W 0 : XTAL, 1: OSC DIV 0x0
ar
21 reg_irrx_clk_mux R/W 0 : XTAL, 1: OSC DIV 0x0
31:22 Reserved
n
tio
rtcsys_mcu51_ctrl0
u

ib
4:0 reg_51_rom_addr_size R/W Determines how many of the sixteen 0xc

r
di V
internal ROM address bits (irom_addr)

st
re k-
are used (0 = no internal ROM present);

5 reg_51_mem_ea_n R/W 0 : external rom exist, 1: external rom 0x0
d il
not exist
an M
6 reg_51_xdata_mode R/W 0 : fetch xdata with clock gating 0x0

1 : fetch xdata wo clock gating (to
n by
support 51 timer and 51 uart)

7 reg_51_rom_addr_def R/W 0: mercury define , max internal rom = 0x0
tio lic
2^reg_51_rom_addr_size -1
internal rom offset =
ca ub
4K*reg_51irom_ioffset
1: mars define , max internal rom =
ifi p
2K*reg_51_rom_addr_size -1
od de
10:8 Reserved
M a
M
31:11 reg_51xdata_ioffset0 R/W Set offset address[31:12] to select 0x05200

mcu8051 boot device
rtcsys_mcu51_ctrl1
4:0 reg_51irom_ioffset R/W boot rom offset to rtcsys_sram 0x0
5 Reserved
9:6 reg_51_pf_mode R/W reg_51_pf_mode 0x0
10 Reserved
31:11 reg_51xdata_doffset0 R/W Set offset address[31:12] to select 0x05200
mcu8051 xdata
219
CV1835
rtcsys_pmu
3:0 Reserved
4 reg_dis_pmu_ldo_ctrl R/W disable pmu ldo ctrl 0x0
0: enable pmu to ctrl RTC_LDO sleep
mode
1: disable pmu to ctrl RTC_LDO sleep
mode
ed
5 reg_wdt_clkoff_by_pmu R/W wdt_clk gate by pmu when mcu into 0x0
idle mode
w
1. wdt clock gate by pmu
6 reg_force_osc_off R/W 1 : force osc off 0x0
lo
7 reg_force_osc_on R/W 1 : force osc on 0x0
al
8 reg_pmu_sleep_mode R/W pmu enter light sleep mode when mcu 0x0
idle
t
1 : enable pmu light sleep mode when
no
mcu idle
(pmu control osc_req/ sram slp)
e
0 disable pmu light sleep mode
ar
9 reg_pmu_lowpwr_mode R/W mcu_pmu into sleep state when rtc at 0x0
suspend state & mcu idle &
n
reg_pmu_sleep_mode enable
tio
1 : enable mcu_pmu into sleep mode
(trigger rtc ldo step down power)
0 disable mcu_pmu sleep mode
u
13:10 reg_pmu_stable_cnt R/W Stable timer when mcu_pmu leave 0x3

ib
sleep state,
r
di V
clock unit : 31.25us (32khz), wait for

st
re k-
1~16 tick cycle

14 reg_xtal_off_by_pmu R/W pmu control xtal request 0x0
d il
1: xtal request disable by pmu sleep

an M
mode
15 reg_rtcsys_clk25m_req R/W xtal request1 for rtcsys 0x1
n by
0: disable 25m xtal request1(rtcsys)

1: enable 25m xtal request1 (rtcsys)
tio lic
19:16 reg_rtc_vbat_det_db_cnt R/W vbat det int debounce time (cycle unit : 0x2
32K)
ca ub
20 reg_rtc_vbat_det_db_en R/W 0: disable vbat det int debounce 0x1

1: enable vbat det int debounce
ifi p
21 reg_ahb_sram_auto_slp_en R/W 1: enable ahb sram into slp md when 0x0

bus idle
od de
23:22 reg_ahb_sram_busy_sel R/W 2'd0: cs | cs_d1 0x0

M a
2'd1: cs | cs_d1 | cs_d2

M
2'd2: cs | cs_d1 | cs_d2 | cs_d3

3'd3: cs | cs_d1 | cs_d2 | cs_d3 | cs_d4
24 reg_rtc_stint_clr W1P clear rtc state change interrupt
25 reg_vbat_det_int_clr W1P clear vbet det interrupt
26 reg_rtcsys_clk25m_hw_req R/W xtal request1 for rtcsys from hw ip 0x0
0: disable 25m xtal request1 from hw
ip(rtcsys)
1: enable 25m xtal request1 from hw
ip(rtcsys)
27 Reserved
28 reg_vbat_det_force_clk R/W 1: when vbat det happen, change rtcsys 0x0
bus clock to OSC
220
CV1835

29 reg_mcu_clkoff_by_pmu R/W mcu_clk gate by pmu when into idle 0x1
mode
1. mcu clock gate by pmu
30 reg_xtal_off_by_susp R/W ISO off control xtal request 0x0
1: xtal request disable by ISO_OFF
31 reg_osc_off_by_susp R/W ISO off control osc request 0x0
1: osc request disable by ISO_OFF
rtcsys_status
ed
w
31:0 reg_rtcsys_status RO [0] enable rtc2apb ahb path
lo
0: rtcsys ip can only access
al
0x05000000+16MB
1: rtcsys ip can access full range
t
address
no
[1] flag of vbat_det_force_clk
rtcsys_clkbyp
e
ar
n
31:0 reg_clk_byp R/W [0] : clk_fab , 0: clk_fab_pre, 1: xtal 0xffffffff
tio
(default)
[1] : clk_sdio, 1: clk_sd1_pre, 1: xtal
u
(default)
ib
[31:2]: NA
r
di V
st
rtcsys_clk_en
re k-

d il

an M
31:0 reg_clk_en R/W [0]: NA 0xffffffff

[1]: clk_sd1 (sd1 card clock)
n by
[2]: clk_fab_sd1 (sd1 core clock)

[3]: clk_mcu
[4]: clk_hs2rtc_mst
tio lic
[5]: clk_rtc2ap_slv
ca ub
[6]: clk_spinor1
[7]: clk_fab_sram (AHB sram)
ifi p
[8]: NA
[9]: clk_apb_timer
od de
[10]: clk_timer0
[11]: clk_timer1
M a
[12]: clk_apb_uart
M
[13]: clk_uart
[14]: clk_apb_ictrl
[15]: clk_apb_mbox
[16]: clk_apb_gpio
[17]: clk_apb_osc
[18]: clk_gpio_db
[19]: clk_apb_i2c
[20]: clk_i2c
[21]: NA
[22]: clk_sd1_tmclk
[23]: clk_apb_saradc
[24]: clk_saradc
[25]: clk_apb_wdt
221
CV1835

[26]: clk_wdt
[27]: clk_irrx
[31:28]: NA
rtcsys_wkup_ctrl
ed
w
lo
14:0 reg_rtcsys_wkint_mask R/W mask int to RTC_CORE.REQ_WAKEUP/ 0xff
MCU_PMU
al
[0]: irrrx_intr
[1]: gpio_int
t
[2]: timer0_int
no
[3]: timer1_int
[4]: saradc_int
e
[5]: rtcsys_ictrl_int
ar
[6]: wdt_int
[7]: irrx_wakeup
n
15 reg_vbat_det_wkup_mask R/W 1: mask vbat det int 0x1
tio
16 reg_sw_wkint_req R/W mcu sw wakeup interrupt to RTC_CORE 0x0
1: interrupt active
u
23:17 Reserved
ib
24 reg_wkint2rtc_mask R/W 1: mask wakeup int (rtcsys int) to RTC 0x1

r
core
di V
st
31:25 Reserved
re k-
d il
rtcsys_clkdiv
an M

n by
3:0 reg_div_clk_osc_fab_div_val R/W Clock Divider Factor 0x1

4 reg_div_clk_osc_fab_dis R/W Clock gate 0x0
tio lic
5 reg_div_clk_osc_fab_hwide R/W Select High Wide Control (when Divider 0x0

Factor is odd) 0: Low level of the clock is
ca ub
wider 1: High level of the clock is wider

15:6 Reserved
ifi p
19:16 reg_div_clk_osc_i2c_div_val R/W Clock Divider Factor 0x1

od de
20 reg_div_clk_osc_i2c_dis R/W Clock gate 0x0

21 reg_div_clk_osc_i2c_hwide R/W Select High Wide Control (when Divider 0x0
M a

M

23:22 Reserved
29:24 reg_div_clk_osc_saradc_div_val R/W Clock Divider Factor 0x1
30 reg_div_clk_osc_saradc_dis R/W Clock gate 0x0
31 reg_div_clk_osc_saradc_hwide R/W Select High Wide Control (when Divider 0x0
fc_coarse_en
222
CV1835

0 fc_coarse_en R/W Enable 32K coarse tuning. 0x0
0 = disable
1 = enable
31:1 Reserved
fc_coarse_cal
ed
15:0 fc_coarse_value RO 32K coarse tuning counter value (unit:
25MHz clock). One 32K clock period
w
counts as one unit in a 25MHz clock.
31:16 fc_coarse_time RO 32K coarse adjustment completion
lo
count.
al
fc_fine_en
t
no
0 fc_fine_en R/W Enable 32K fine tuning. 0x0
e
0 = disable,
ar
1 = enable
31:1 Reserved
n
tio
fc_fine_period
u

ib

r
15:0 fc_fine_period R/W 32K fine tuning counting period (unit: 0x0100
di V
st
32K clock) Set how many 32K clock

re k-
cycles to count each time using the

d il
25MHz clock.
an M
31:16 Reserved
n by
fc_fine_cal
tio lic

23:0 fc_fine_value RO 32K Fine-Tuning Counter Value (in units
ca ub
of 25MHz clock) - The 25MHz clock

counts one fc_fine_period period.
ifi p
31:24 fc_fine_time RO 32K fine adjustment completion count.

od de
rtcsys_pmu2
M a

M

0 reg_rtc_sys_wkint_db_en R/W PMU wakeup int debounce enable 0x1
4:1 reg_rtc_sys_wkint_db_cnt R/W PMU wakeup int debounce cycle (32K) 0x2
31:5 Reserved
rtcsys_clkdiv1
15:0 Reserved
21:16 reg_div_clk_osc_irrx_div_val R/W Clock Divider Factor 0x0
223
CV1835

22 Reserved
23 reg_div_clk_osc_irrx_dis R/W Clock gate 0x1
31:24 Reserved
rtcsys_mcu51_dbg
3:0 reg_51_dbg_sel R/W select mcu51 debug bus (check mcu 0x0
ed
design review ppt)
4 reg_51_dbg_snap_shot W1P snap shot mcu51 internal register to
w
dbg register (reg_rtcsys_dbg)
lo
5 reg_51_dbg_step_en R/W 0: disable mcu debug function 0x0
al
1: enable mcu debug function, and mcu
stop at current PC
t
6 reg_51_dbg_step W1P 1: mcu jump to next PC
no
7 reg_51_dbg_jump W1P 1: mcu jump to target pc value
(reg_51_dbg_jump2pc)
e
15:8 Reserved
ar
31:16 reg_51_dbg_jump2pc R/W 16 bit mcu target pc value
n 0x0
sw_reg0
tio

u
7:0 sw_reg0 R/W reg for SW 0x0

ib
31:8 Reserved
r
di V
st
re k-
sw_reg1_por
d il

an M

7:0 sw_reg1_por R/W reg for SW could only be reset by power 0x0
n by
reset
31:8 Reserved
tio lic
fab_lp_ctrl
ca ub

ifi p
7:0 rtcsys_fab_busy_sel R/W select signal to request sys_ctrl to speed 0xDF

od de
up fab clock
9:8 rtcsys_fab_busy_ctrl R/W rtcsys_fab_busy signal is combi or 0x0
M a
register out
M
11:10 apdbg_busy_ctrl R/W apdbg_busy signal is combi or register 0x0

out
13:12 reg_apb_busy_ctrl R/W apb bridge_busy signal is combi or 0x3
register out
15:14 reg_mcu_busy_ctrl R/W mcu_busy signal is combi or register out 0x3
31:16 Reserved
rtcsys_mcu51_ictrl1
224
CV1835

15:0 reg_51_int1_src_mask R/W select rtcsys_int src to mcu int1_n 0xffff
1: mask, 0: un-mask
[0]: vbat_det
[1]: mbox0_int
[2]: NA
[3]: irrx_int
[4]: gpio_int
[5]: uart_int
[6]: spinor1_int
ed
[7]: timer0_int
[8]: timer1_int
w
[9]: irq_ap2rtc[0]
[10]: irq_ap2rtc[1]
lo
[11]: i2c_int
al
[12]: rtc_state_change_int
[13]: hw_thm_shdn
t
[14]: saradc
no
[15]: wdt_int
31:16 reg_51_int1_final_status R0 mcu int1_n status
e
[0]: vbat_det
ar
[1]: mbox0_int
[2]: NA
n
[3]: irrx_int
tio
[4]: gpio_int
[5]: uart_int
u
[6]: spinor1_int
ib
[7]: timer0_int
[8]: timer1_int
r
di V
[9]: irq_ap2rtc[0]
st
re k-
[10]: irq_ap2rtc[1]
[11]: i2c_int
d il
an M
[13]: hw_thm_shdn
[14]: saradc
n by
[15]: wdt_int
rtc_ip_pwr_req
tio lic

ca ub

0 reg_sd1_pwr_req R/W power fence control 0x1
ifi p
1: power on, 0: power off

od de
[0]: sd1
1 reg_sd1_pwr_req_2nd R/W power fence control 0x1
M a

M
[0]: sd1
2 reg_mcu_pwr_req R/W power fence control 0x1
[1]: mcu subsys
3 reg_mcu_pwr_req_2nd R/W power fence control 0x1
[1]: mcu subsys
15:4 Reserved
16 reg_sd1_pwr_ack R0 power fence power status
[0]: sd1
17 reg_sd1_pwr_ack_2nd R0 power fence power status
225
CV1835

[0]: sd1
18 reg_mcu_pwr_ack R0 power fence power status
[1]: mcu subsys
19 reg_mcu_pwr_ack_2nd R0 power fence power status
[1]: mcu subsys
31:20 Reserved
ed
rtc_ip_iso_ctrl
w
lo
al
0 reg_sd1_iso_en R/W sd1 iso enablel 0x0
1: iso enable, 0: iso disable
t
1 reg_mcu_iso_en R/W mcu iso enablel 0x0
no
15:2 Reserved
e
17:16 reg_ip_por_en R/W 1: pwr_island reset assert when power 0x3
ar
ack is 0
31:18 Reserved
n
tio
rtcsys_wkup_ctrl1
u

ib

7:0 reg_rtcsys_wkint_final_status RO wkint final status
r
di V
st
[0]: sd1_wakeup_intr
re k-
[1]: gpio_int
[2]: timer0_int
d il
an M
[3]: timer1_int
[4]: saradc_int
n by
[6]: NA
[7]: NA
tio lic
31:8 Reserved
ca ub
rtcsys_sram_ctrl
ifi p

od de
0 reg_ahb_sram_slp R/W 1 : ahb sram into sleep mode 0x0

M a
1 reg_ahb_sram_sd R/W 1 : ahb sram into shut down mode 0x0

M
2 reg_ahb_sram_ctrl_ov R/W 0 : ahb sram ctrl by PMU FSM and ahb 0x1
sram busy
1: sram ctrol by register
reg_ahb_sram_slp/reg_ahb_sram_sd
3 reg_sdio_sram_slp R/W 1 : sdio sram into sleep mode 0x0
4 reg_sdio_sram_sd R/W 1 : sdio sram into shut down mode 0x0
5 reg_sdio_sram_ctrl_ov R/W 0 : sram's sd pin = 1'b0 0x1
reg_sdio_sram_sd
6 reg_mcu_sram_slp R/W 1 : mcu iram sram into sleep mode 0x0
7 reg_mcu_sram_sd R/W 1 : mcu iram sram into shut down mode 0x0
8 reg_mcu_sram_ctrl_ov R/W 0 : mcu iram sram ctrl by PMU FSM 0x1
226
CV1835

9 reg_rtc_sram_slp R/W 1 : mcu iram sram into sleep mode 0x0
10 reg_rtc_sram_sd R/W 1 : mcu iram sram into shut down mode 0x0
11 reg_rtc_sram_ctrl_ov R/W 0 : mcu iram sram ctrl by PMU FSM 0x1
27:12 Reserved
28 reg_mcu_sram_force_ce R/W 1: force mcu_iram cs = 1 0x1
31:29 Reserved
ed
w
rtcsys_io_ctrl
lo
al
0 reg_i2c_mux_opt0 R/W 0: pwr_gpio6/8 control by dw_gpio 0x0
t
1: pwr_gpio6 is PWR_IIC_SDA
no
pwr_gpio8 is PWR_IIC_SCL
31:1 Reserved
e
ar
rtcsys_wdt_ctrl
n
tio
0 reg_rtc_hw_wdg_rst_en R/W 0: disable rtc wdt trigger warm reset or 0x0

pwrcyc reset
u
1: enable rtc wdt trigger warm reset or

ib
pwrcyc reset
1 reg_rtc_wdt_ctrl_mask_en R/W
r
no load 0x1
di V
st
31:2 Reserved
re k-
d il
rtcsys_irrx_clk_ctrl
an M

n by
0 reg_irrx_clk_sw_force_on R/W force on clk ctrl of irrx 0x1

1 reg_irrx_xtal_req_en R/W enable irrx clk ctrl requet XTAL 0x0
tio lic
2 reg_irrx_osc_req_en R/W enable irrx clk ctrl requet OSC 0x0

3 reg_irrx_ldo_req_en R/W enable irrx clk ctrl requet LDO 0x0
ca ub
7:4 Reserved
ifi p
15:8 reg_irrx_xtal_filter_cyc R/W irrx xtal filter cycle (default 2ms) 0x40
19:16 reg_irrx_clk_ctrl_st RO irrx clock ctrol state
od de
31:20 Reserved
M a
M
rtcsys_rtc_wkup_ctrl
7:0 reg_rtc_wkint_mask R/W wakeup source mask int to RTC_CORE 0xff
[0]: irrrx_intr
[1]: gpio_int
[2]: timer0_int
[3]: timer1_int
[4]: saradc_int
[6]: wdt_int
[7]: irrx_wakeup
227
CV1835

15:8 Reserved
23:16 reg_rtc_puint_mask R/W power-up source mask int to RTC_CORE 0xff
[0]: irrrx_intr
[1]: gpio_int
[2]: timer0_int
[3]: timer1_int
[4]: saradc_int
[6]: wdt_int
ed
[7]: irrx_wakeup
31:24 Reserved
w
lo
rtcsys_por_rst_ctrl
al
t
no
0 reg_rtcsys_reset_en R/W 0: not allow rtcsys reset by pwr cyc/ wdt 0x0
warm reset
1 : allow rtcsys reset by pwr cyc/ wdt
e
warm reset
ar
1 reg_rtcsys_rstn_src_sel R/W select rtcsys rstn src 0x0
0: rtc_core fsm (reset with die
n
domain)
tio
1: por_pwr_rstn
31:2 Reserved
u
r ib
di V
st
re k-
3.10Power management and low power consumption

d il
an M
mode
n by
tio lic
3.10.1 Overview
ca ub
ifi p
The CV180ZB/CV1800B/CV1801B chip supports two main power modes.

od de
a. Active
M a
M
3.10.1.1 Active Mode
Active mode is the state where the chip is fully awake and operational. However, there
are still power-saving techniques such as dynamic frequency scaling or dynamic clock
gating.
228
CV1835
3.10.2 Clock control
3.10.2.1 Turn off unwanted clock dividers
Refer to the clock configuration section, turn off the unused clock divider according to
the clock source required by each module. To achieve the purpose of saving power
ed
consumption.
w
lo
3.10.2.2 Adjust the working frequency of the module
al
According to the required clock specifications of each module, choose a lower clock
t
no
source. The frequency division configuration is more to reduce the working frequency
of the module. It is the first mock exam that the frequency of a single module is not
e
ar
necessarily reduced. n
tio
3.10.2.3 Module level low power control

u
Analog module: Mipi / USB / eth / aud related register settings, will not use the
r ib
module off or into low power consumption mode.

di V
st
re k-
Digital module: according to the hardware and specifications, turn off the clock of
d il
unnecessary digital module

an M
n by
3.10.2.4 Turn off unused PLL

tio lic
Referring to PLL configuration, you can powerdown the PLL you don't need to use to
ca ub
save power.
ifi p
od de
3.10.3 DDR low power consumption control

M a
M
After the bus has not been accessed for a period of time, the DDR controller will
automatically enter the state of self refresh and power down to reduce the system
power consumption.
In some scenarios, due to intermittent access, it is impossible to find enough space to
enter self refresh. In this case, we can also consider building a statistics register of the
amount of data accessed to confirm whether the band is excessive. We can consider
direct frequency reduction.
229
CV1835
DDR controller supports dynamic frequency adjustment. However, since adjusting the
frequency will temporarily stop DDR access for a period of time, in order to reduce the
interruption time, it may cause real-time application buffer underflow / overflow. It is
limited to 50% and 100%.
ed
w
lo
3.10.4 Voltage regulation
al
t
CV180ZB/CV1800B/CV1801B uses PWM0 to control VDDC voltage regulation by
no
default.
e
ar
The following is an example of using PWM to control the output voltage of DCDC
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
230
CV1835
Chart 3- 9 Example of using PWM to control DCDC voltage.
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
231
CV1835
3.11Chip internal temperature detection
Temperature sensor is built in the chip. Please refer to 12.8 for details
High junction temperature may cause thermal run away and cause permanent damage.
So the chip needs to control the temperature
ed
The first stage is software behavior
w
The temperature sensor can automatically detect whether the temperature exceeds a
lo
specific temperature and send out an overheat interrupt. After receiving the overheat
al
interrupt, the software can reduce the power consumption and temperature by limiting
t
no
the frequency or voltage of the high-power module and starting the fan. If the
temperature returns to the safe range, the limit is removed
e
The second stage is hardware behavior ar
n
tio
If the temperature continues to rise after the software is started, the hardware will
u
intervene in the emergency of thermal shut-down. However, this function is turned off
ib
by default. After the software is started, it needs to set the relevant settings and then
r
di V
st
enable
re k-
d il
an M
3.128051 subsystem
n by
tio lic
3.12.1 Overview
ca ub
ifi p
The 8051 subsystem is located in a module that is independently powered by the RTC.
od de
The subsystem is configured with an 8051, an I2C/UART/SPI NOR/SD controller, a

M a
M
Timer/WDT, interrupt management, and a Mailbox IP. The system software can use the
8051 to manage wake-up conditions and wake up the system while it is in sleep mode,
and communicate with external devices through peripheral controllers.
Configuration of the subsystem:
232
CV1835
 The 8051 microprocessor has the following features:

 Supports standard 8051 instruction set
 Frequency range of 25MHz ~ 300 MHz
 Debugging functions: single-step execution / jump2pc / snapshot PSW,
DPTR, PC
 Supports 32-bit data access
ed
 Reset vector can be configured to system AHB SRAM / DRAM / SPINOR
w
 Supports WFI (Clock gating)
lo
 Supports code banking (maximum 64x64 KB)
al
 Provides 8KB of AHB SRAM space, which can be used by 8051 as instruction
t
no
TCM or temporary storage for data
 Provides 2 sets of 32-bit counters for timing and counting functions, which
e
ar
can be used by applications to implement timing and counting, or by the
operating system to implement system clocks.
n
tio
 Provides 1 set of WDT for system interrupt or reset signal after a certain
period of time in case of system exception.
u
ib
 Provides 1 set of external SPINOR control.

r
di V
st
 Provides interrupt controller for managing interrupt sources.

re k-
 Provides 2 sets of Mailbox for communication between ACPU and 8051.

d il
an M
 Provides 1 set of I2C.

n by
 Provides 1 set of UART.

tio lic
ca ub
ifi p
od de
M a
M
233
CV1835
ed
w
lo
al
t
no
e
ar
Figure 3-10 the architecture of 8051 subsystem
n
The subsystem is divided into two power domains: the AO domain and the MCU
tio
domain (green area). The system can use registers to select the power domain of the
u
MCU to achieve power-saving requirements.

r ib
In sleep mode, the system can handle interrupts through the MCU and wake up the
di V
st
re k-
system by configuring registers. It can also communicate with external devices through
d il
I2C/UART.
an M
n by
3.12.4 Working Mode

tio lic
3.12.4.1 Power Domain Control Flow

ca ub
ifi p
The subsystem is divided into three power domains: RTC domain (Always on), MCU
od de
domain. The power on/off process of the MCU domain can be controlled by configuring
M a
the registers, which follow the steps below:

M
MCU power_off>
1. Set the software reset register to 0.
2. Set the isolation enable register reg_mcu_iso_en to 1.
3. Set the power request register reg_mcu_pwr_req to 0.
MCU power_on=>
1. Set the power request register reg_mcu_pwr_req to 1.
2. Poll the power acknowledge register reg_mcu_pwr_ack until it is 1.
234
CV1835
3. Set the isolation enable register reg_mcu_iso_en to 0.

4. Set the software reset register to 1.
3.12.4.2 8051 Initailization
The 8051 is in a reset state at the system initialization, and it can complete the following
ed
software flow through the ACPU using the 8051:
w
lo
al
1. The 8051 is in the reset state (register reg_soft_rstn_mcu = 0).
2. Configure the register reg_mcu_rom_addr_size to determine the instruction TCM
t
no
size.
3. Configure the register reg_51irom_ioffset to determine the location of TCM
e
ar
execution on AHB SRAM. n
4. Release the 8051 reset state by setting the register reg_soft_rstn_mcu = 1.
u tio
ib
3.12.4.3 Interrupt Handling

r
di V
st
re k-
The 8051 can receive external level-triggered interrupts through the int0_n and int1_n
d il
an M
interfaces. int0_n/int1_n can be selected to output interrupt signals to the 8051 from ictl
(interrupt controller) and configuration register reg_51_int1_src_mask, respectively.
n by
Interrupt Interrupt
tio lic
Number Name Interrupt Description

System power-off
ca ub
0 Vbat_det interrupt
ifi p
1 mbox_int0 Mailbox interrupt

od de
2 NA Reserved
M a
Remote control reception

M
3 irrx interrupt
4 gpio_int PWR GPIO interrupt
5 uart_int PWR UART interrupt
6 spinor1_int SPINOR1 interrupt
7 timer_int0 TIMER0 interrupt
8 timer_int1 TIMER1 interrupt
9 Irq_ap2rtc[0] System interrupt
10 Irq_ap2rtc[1] System interrupt
235
CV1835
11 I2c_int PWR I2C interrupt

RTC state change
12 st_change_int interrupt
System overheat
13 hw_thm_shdn interrupt
14 saradc SARADC interrupt
15 wdt_int Watchdog interrupt
ed
Table 3-12 the interrupt list of 8051 subsystem
w
lo
al
3.12.4.4 MAILBOX
t
no
Mailbox provides 2 sets of spinlock fields and 4 sets of 32-bit message fields, which
e
allow ACPU/8051 to transfer information between each other.
ar
n
tio
3.12.5 8051 Subsystem Registers Overview

u
ib
Table 3-12 RTC_CTRL registers overview(base address 0x05025000)

r
di V
st

re k-
Offset
rtc_ctrl_version 0x000 rtc_ctrl_version
d il
an M
rtc_ctrl_unlockkey 0x004 rtc_ctrl_unlockkey

rtc_ctrl0 0x008 rtc_ctrl0
rtc_ctrl_status0
n by
0x00c rtc_ctrl_status0
rtc_ctrl_status1 0x010 rtc_ctrl_status1
rtc_ctrl_status2gpio 0x014 rtc_ctrl_status2gpio
tio lic
rtcsys_rst_ctrl 0x018 rtcsys_rst_ctrl

rtcsys_clkmux 0x01c rtcsys_clkmux
ca ub

ifi p

rtcsys_pmu 0x028 rtcsys_pmu
od de
rtcsys_status 0x02c rtcsys_status

rtcsys_clkbyp 0x030 rtcsys_clkbyp
M a
rtcsys_clk_en 0x034 rtcsys_clk_en

M
rtcsys_wkup_ctrl 0x038 rtcsys_wkup_ctrl

rtcsys_clkdiv 0x03c rtcsys_clkdiv
fc_coarse_en 0x040 fc_coarse_en
fc_coarse_cal 0x044 fc_coarse_cal
fc_fine_en 0x048 fc_fine_en
fc_fine_period 0x04c fc_fine_period
fc_fine_cal 0x050 fc_fine_cal
rtcsys_pmu2 0x054 rtcsys_pmu2
rtcsys_clkdiv1 0x058 rtcsys_clkdiv
rtcsys_mcu51_dbg 0x05c rtcsys_mcu51_dbg
sw_reg0 0x060 sw_reg0
sw_reg1_por 0x064 sw_reg1_por
236
CV1835

Offset
fab_lp_ctrl 0x068 fab_lp_ctrl
fab_option 0x06c fab_option
rtcsys_mcu51_ictrl1 0x07c rtcsys_mcu51_ictrl1
rtc_ip_pwr_req 0x080 rtc_ip_pwr_req
rtc_ip_iso_ctrl 0x084 rtc_ip_iso_ctrl
rtcsys_wkup_ctrl1 0x094 rtcsys_wkup_ctrl1
rtcsys_sram_ctrl 0x098 rtcsys_sram_ctrl
rtcsys_io_ctrl 0x09c rtcsys_io_ctrl
ed
rtcsys_wdt_ctrl 0x0a0 rtcsys_wdt_ctrl
rtcsys_irrx_clk_ctrl 0x0a4 rtcsys_irrx_clk_ctrl
w
rtcsys_rtc_wkup_ctrl 0x0a8 rtcsys_rtc_wkup_ctrl
lo
rtcsys_por_rst_ctrl 0x0ac rtcsys_por_rst_ctrl
al
t
no
3.12.6 8051 Subsystem Registers
e
ar
n
rtc_ctrl_unlockkey
tio

u

ib
15:0 rtc_ctrl_unlockkey R/W "rtc_ctrl0" could be write when 0x0000

r
unlockkey is set to be 0xAB18.

di V
st
"ptest_adc2ram_ctrl" could be write

re k-
when unlockkey is set to be 0x0423.

d il
If unlockkey_clear is set to 1, the

an M
rtc_ctrl0_unlockkey will be clear after a

apb write to rtc_ctrl0 or
n by
ptest_adc2ram_ctrl
31:16 Reserved
tio lic
rtc_ctrl0
ca ub

ifi p
Write Lock: wr_lock_rtc_ctrl0

od de

0 req_shdn W1P
M a
Mask: Enabled
M
1 req_sw_thm_shdn R/W 0x0

Mask: Enabled
2 hw_thm_shdn_en R/W 0x0
Mask: Enabled
3 req_pwr_cyc W1P
Mask: Enabled
4 req_warm_rst W1P
Mask: Enabled
5 req_sw_wdg_rst R/W 0x0
Mask: Enabled
6 hw_wdg_rst_en R/W 0x0
Mask: Enabled
237
CV1835

7 req_suspend W1P
Mask: Enabled
8 unlockkey_clear R/W 0x0
Mask: Enabled
9 Reserved
10 reg_rtc_mode R/W 0x0
Mask: Enabled
11 reg_clk32k_cg_en R/W 0x1
Mask: Enabled
ed
31:12 Reserved
w
rtc_ctrl_status0
lo
al
t
0 rtc_pwr_vbat_det_o RO
no
1 rtc_pwr_button0_o RO
2 rtc_pwr_button1_o RO
e
ar
3 rtc_pwr_button1_7sec_o RO
4 rtc_pwr_on_o RO
n
5 rtc_pwr_wakeup0_o RO
tio
6 rtc_pwr_wakeup1_o RO
7 rtc_mode_o RO
u
ib
19:8 Reserved
r
20 rtc_rstn_o RO
di V
st
21 rtc_alarm_o RO
re k-
22 hw_thm_shdn_sta_i RO
d il
23 hw_wdg_rst_sta_i RO
an M
24 sys_reset_x_i RO
n by
25 cg_en_out_clk_32k RO
29:26 rtc_fsm_st RO
tio lic
31:30 Reserved
ca ub
rtc_ctrl_status1
ifi p

od de

31:0 rtc_sec_value_o RO
M a
M
rtc_ctrl_status2gpio
7:0 status2gpio_en R/W 0x0
31:8 Reserved
rtcsys_rst_ctrl
238
CV1835

0 Reserved
1 reg_soft_rstn_mcu R/W 0 : reest MCU 0x0
2 reg_soft_rstn_sdio R/W 0 : reset SD1 0x1
3 reg_soft_rstn_uart R/W 0 : reset Uart 0x1
4 reg_soft_rstn_spinor R/W 0 : reset spinor1 0x1
5 reg_soft_rstn_ictl R/W 0 : reset dw_ictl 0x1
6 reg_soft_rstn_mbox R/W 0 : reset mbox 0x1
7 reg_soft_rstn_fab_hs2rtc R/W 0 : reset hs2rtc 0x1
8 reg_soft_rstn_fab_rtc2ap R/W 0 : reset rtc2ap 0x1
ed
9 reg_soft_rstn_fab_sram R/W 0 : reset ahb sram logic 0x1
w
10 reg_soft_rstn_apb R/W no load 0x1
11 reg_soft_rstn_apb_timer R/W 0 : reset dw timer apb logic 0x1
lo
al
14 reg_soft_rstn_osc R/W 0 : reset osc 0x1
t
15 reg_soft_rstn_gpio R/W 0 : reset gpio 0x1
no
16 reg_soft_rstn_i2c R/W 0 : reset i2c 0x1
17 reg_soft_rstn_saradc R/W 0 : reset saradc 0x1
e
18 reg_soft_rstn_wdt R/W 0 : reset wdt 0x1
ar
19 reg_soft_rstn_irrx R/W 0 : reset irrx 0x1
20 reg_soft_rstn_f32kless R/W 0 : reset f32kless 0x1
n
31:21 Reserved
tio
rtcsys_clkmux
u
ib

r

di V
st
3:0 reg_sdio_clk_mux R/W clk_sd1_pre 0x0

re k-
0 : fpll/4 1: osc_div
d il
7:4 reg_fab_clk_mux R/W clk_fab_pre 0x0

an M
0 : 32K, 1: fpll/5, 2: osc_div

n by
1: 32K
1: 32K
tio lic
13:12 reg_apb_clk_mux R/W 00 : cgdiv and refer to apbactive 0x1

ca ub
01 : force clk_apb, clk_fab 1:1 (default)

ifi p

15:14 Reserved
od de
17:16 reg_i2c_clk_mux R/W 0: xtal 0x0

M a
1: osc div
M
19:18 reg_sd_mclk_clk_mux R/W 0: 100Khz from OSC, 1: 32K 0x0

20 reg_saradc_clk_mux R/W 0 : XTAL, 1: OSC DIV 0x0
21 reg_irrx_clk_mux R/W 0 : XTAL, 1: OSC DIV 0x0
31:22 Reserved
rtcsys_mcu51_ctrl0
4:0 reg_51_rom_addr_size R/W Determines how many of the sixteen 0xc
internal ROM address bits (irom_addr)
are used (0 = no internal ROM present);
239
CV1835

5 reg_51_mem_ea_n R/W 0 : external rom exist, 1: external rom 0x0
not exist
6 reg_51_xdata_mode R/W 0 : fetch xdata with clock gating 0x0
1 : fetch xdata wo clock gating (to
support 51 timer and 51 uart)
7 reg_51_rom_addr_def R/W 0: mercury define , max internal rom = 0x0
2^reg_51_rom_addr_size -1
ed
1: mars define , max internal rom =
2K*reg_51_rom_addr_size -1
w
lo
10:8 Reserved
al
31:11 reg_51xdata_ioffset0 R/W Set offset address[31:11] to select 0x0A400
t
mcu8051 boot device
no
rtcsys_mcu51_ctrl1
e
ar
4:0 reg_51irom_ioffset R/W boot rom offset to rtcsys_sram 0x0
n
5 Reserved
tio
9:6 reg_51_pf_mode R/W reg_51_pf_mode 0x0

u
10 Reserved
ib
31:11 reg_51xdata_doffset0 R/W Set offset address[31:11] to select 0x0A400

r
mcu8051 xdata
di V
st
re k-
rtcsys_pmu
d il
an M

n by
3:0 Reserved
4 reg_dis_pmu_ldo_ctrl R/W disable pmu ldo ctrl 0x0
tio lic
0: enable pmu to ctrl RTC_LDO sleep

mode
ca ub
1: disable pmu to ctrl RTC_LDO sleep

mode
ifi p
5 reg_wdt_clkoff_by_pmu R/W wdt_clk gate by pmu when mcu into 0x0

idle mode
od de
1. wdt clock gate by pmu

6 reg_force_osc_off R/W 1 : force osc off 0x0
M a
M
7 reg_force_osc_on R/W 1 : force osc on 0x0

8 reg_pmu_sleep_mode R/W pmu enter light sleep mode when mcu 0x0
idle
1 : enable pmu light sleep mode when
mcu idle
(pmu control osc_req/ sram slp)
0 disable pmu light sleep mode
9 reg_pmu_lowpwr_mode R/W mcu_pmu into sleep state when rtc at 0x0
suspend state & mcu idle &
reg_pmu_sleep_mode enable
1 : enable mcu_pmu into sleep mode
(trigger rtc ldo step down power)
0 disable mcu_pmu sleep mode
240
CV1835

13:10 reg_pmu_stable_cnt R/W Stable timer when mcu_pmu leave 0x3
sleep state,
clock unit : 31.25us (32khz), wait for
1~16 tick cycle
14 reg_xtal_off_by_pmu R/W pmu control xtal request 0x0
1: xtal request disable by pmu sleep
mode
15 reg_rtcsys_clk25m_req R/W xtal request1 for rtcsys 0x1
0: disable 25m xtal request1(rtcsys)
ed
1: enable 25m xtal request1 (rtcsys)
19:16 reg_rtc_vbat_det_db_cnt R/W vbat det int debounce time (cycle unit : 0x2
w
32K)
lo
20 reg_rtc_vbat_det_db_en R/W 0: disable vbat det int debounce 0x1
1: enable vbat det int debounce
al
21 reg_ahb_sram_auto_slp_en R/W 1: enable ahb sram into slp md when 0x0
bus idle
t
no
23:22 reg_ahb_sram_busy_sel R/W 2'd0: cs | cs_d1 0x0
2'd1: cs | cs_d1 | cs_d2
2'd2: cs | cs_d1 | cs_d2 | cs_d3
e
3'd3: cs | cs_d1 | cs_d2 | cs_d3 | cs_d4
ar
24 reg_rtc_stint_clr W1P clear rtc state change interrupt
25 reg_vbat_det_int_clr W1P clear vbet det interrupt
n
26 reg_rtcsys_clk25m_hw_req R/W xtal request1 for rtcsys from hw ip 0x0
tio
0: disable 25m xtal request1 from hw

ip(rtcsys)
u
1: enable 25m xtal request1 from hw

ib
ip(rtcsys)
r
di V
27 Reserved
st
re k-
28 reg_vbat_det_force_clk R/W 1: when vbat det happen, change rtcsys 0x0

bus clock to OSC
d il
29 reg_mcu_clkoff_by_pmu R/W mcu_clk gate by pmu when into idle 0x1

an M
mode
1. mcu clock gate by pmu
n by
30 reg_xtal_off_by_susp R/W ISO off control xtal request 0x0

1: xtal request disable by ISO_OFF
tio lic
31 reg_osc_off_by_susp R/W ISO off control osc request 0x0

1: osc request disable by ISO_OFF
ca ub
rtcsys_status
ifi p

od de

M a
31:0 reg_rtcsys_status RO [0] enable rtc2apb ahb path

M
0: rtcsys ip can only access

0x05000000+16MB
1: rtcsys ip can access full range
address
[1] flag of vbat_det_force_clk
rtcsys_clkbyp
31:0 reg_clk_byp R/W [0] : clk_fab , 0: clk_fab_pre, 1: xtal 0xffffffff
(default)
241
CV1835

[1] : clk_sdio, 1: clk_sd1_pre, 1: xtal
(default)
[31:2]: NA
rtcsys_clk_en
31:0 reg_clk_en R/W [0]: NA 0xffffffff
ed
[1]: clk_sd1 (sd1 card clock)
[2]: clk_fab_sd1 (sd1 core clock)
w
[3]: clk_mcu
lo
[4]: clk_hs2rtc_mst
[5]: clk_rtc2ap_slv
al
[6]: clk_spinor1
t
[7]: clk_fab_sram (AHB sram)
no
[8]: NA
[9]: clk_apb_timer
[10]: clk_timer0
e
[11]: clk_timer1
ar
[12]: clk_apb_uart
[13]: clk_uart
n
[14]: clk_apb_ictrl
tio
[15]: clk_apb_mbox
[16]: clk_apb_gpio
u
[17]: clk_apb_osc
ib
[18]: clk_gpio_db
[19]: clk_apb_i2c
r
di V
st
[20]: clk_i2c
re k-
[21]: NA
[22]: clk_sd1_tmclk
d il
an M
[23]: clk_apb_saradc
[24]: clk_saradc
[25]: clk_apb_wdt
n by
[26]: clk_wdt
[27]: clk_irrx
tio lic
[31:28]: NA
ca ub
rtcsys_wkup_ctrl
ifi p

od de

14:0 reg_rtcsys_wkint_mask R/W mask int to RTC_CORE.REQ_WAKEUP/ 0xff
M a
MCU_PMU
M
[0]: irrrx_intr
[1]: gpio_int
[2]: timer0_int
[3]: timer1_int
[4]: saradc_int
[6]: wdt_int
[7]: irrx_wakeup
15 reg_vbat_det_wkup_mask R/W 1: mask vbat det int 0x1
16 reg_sw_wkint_req R/W mcu sw wakeup interrupt to RTC_CORE 0x0
1: interrupt active
23:17 Reserved
242
CV1835

24 reg_wkint2rtc_mask R/W 1: mask wakeup int (rtcsys int) to RTC 0x1
core
31:25 Reserved
rtcsys_clkdiv
ed
3:0 reg_div_clk_osc_fab_div_val R/W Clock Divider Factor 0x1
4 reg_div_clk_osc_fab_dis R/W Clock gate 0x0
w
5 reg_div_clk_osc_fab_hwide R/W Select High Wide Control (when Divider 0x0
lo
al
15:6 Reserved
19:16 reg_div_clk_osc_i2c_div_val R/W Clock Divider Factor 0x1
t
20 reg_div_clk_osc_i2c_dis R/W Clock gate 0x0
no
21 reg_div_clk_osc_i2c_hwide R/W Select High Wide Control (when Divider 0x0
e
ar
23:22 Reserved
29:24 reg_div_clk_osc_saradc_div_val R/W Clock Divider Factor 0x1
n
30 reg_div_clk_osc_saradc_dis R/W Clock gate 0x0
tio
31 reg_div_clk_osc_saradc_hwide R/W Select High Wide Control (when Divider 0x0

u

r ib
fc_coarse_en
di V
st
re k-

d il

an M
0 fc_coarse_en R/W Enable 32K course tuning: 0x0

0 = disable,
n by
1 = enable
31:1 Reserved
tio lic
fc_coarse_cal
ca ub

ifi p

od de
15:0 fc_coarse_value RO 32K coarse counter value (unit: 25MHz

clock) 25MHz clock counts one 32K
M a
clock cycle.
M
31:16 fc_coarse_time RO 32K coarse tune completion count.
fc_fine_en
0 fc_fine_en R/W Enable 32K fine tuning: 0x0
0 = disable,
1 = enable
31:1 Reserved
243
CV1835
fc_fine_period
15:0 fc_fine_period R/W 32K fine adjustment counting period 0x0100
(unit: 32K clock) Set how many 32K
clock periods are counted each time
using the 25MHz clock.
31:16 Reserved
ed
fc_fine_cal
w
lo
al
23:0 fc_fine_value RO 32K fine adjustment counter value (unit:
25MHz clock) One 25MHz clock counts
t
one fc_fine_period cycle.
no
31:24 fc_fine_time RO 32K fine tune completion count.
e
rtcsys_pmu2
ar
Offset Address: 0x054 n
tio
0 reg_rtc_sys_wkint_db_en R/W PMU wakeup int debounce enable 0x1

4:1 reg_rtc_sys_wkint_db_cnt R/W PMU wakeup int debounce cycle (32K) 0x2
u
31:5 Reserved
r ib
di V
rtcsys_clkdiv1
st
re k-

d il

an M
15:0 Reserved
21:16 reg_div_clk_osc_irrx_div_val R/W Clock Divider Factor 0x0
n by
22 Reserved
23 reg_div_clk_osc_irrx_dis R/W Clock gate 0x1
tio lic
31:24 Reserved
ca ub
rtcsys_mcu51_dbg
ifi p

od de

M a
3:0 reg_51_dbg_sel R/W select mcu51 debug bus (check mcu 0x0
M
design review ppt)

4 reg_51_dbg_snap_shot W1P snap shot mcu51 internal register to
dbg register (reg_rtcsys_dbg)
5 reg_51_dbg_step_en R/W 0: disable mcu debug function 0x0
1: enable mcu debug function, and mcu
stop at current PC
6 reg_51_dbg_step W1P 1: mcu jump to next PC
7 reg_51_dbg_jump W1P 1: mcu jump to target pc value
(reg_51_dbg_jump2pc)
15:8 Reserved
31:16 reg_51_dbg_jump2pc R/W 16 bit mcu target pc value 0x0
244
CV1835
sw_reg0
7:0 sw_reg0 R/W reg for SW 0x0
31:8 Reserved
sw_reg1_por
G
ed
w
lo
7:0 sw_reg1_por R/W reg for SW could only be reset by power 0x0
reset
al
31:8 Reserved
t
no
fab_lp_ctrl
e
ar
7:0 rtcsys_fab_busy_sel R/W select signal to request sys_ctrl to speed 0xDF
up fab clock
n
tio
9:8 rtcsys_fab_busy_ctrl R/W rtcsys_fab_busy signal is combi or 0x0
register out
11:10 apdbg_busy_ctrl R/W apdbg_busy signal is combi or register 0x0
u
out
ib
13:12 reg_apb_busy_ctrl R/W apb bridge_busy signal is combi or 0x3

r
di V
register out
st
re k-
15:14 reg_mcu_busy_ctrl R/W mcu_busy signal is combi or register out 0x3

31:16 Reserved
d il
an M
fab_option
n by

tio lic
1:0 rtcsys_fab_option R/W the ahb_h2h2 design option 0x0

31:2 Reserved
ca ub
ifi p
rtcsys_mcu51_ictrl1
od de

M a
M
15:0 reg_51_int1_src_mask R/W select rtcsys_int src to mcu int1_n 0xffff

1: mask, 0: un-mask
[0]: vbat_det
[1]: mbox0_int
[2]: NA
[3]: irrx_int
[4]: gpio_int
[5]: uart_int
[6]: spinor1_int
[7]: timer0_int
[8]: timer1_int
[9]: irq_ap2rtc[0]
[10]: irq_ap2rtc[1]
245
CV1835

[11]: i2c_int
[13]: hw_thm_shdn
[14]: saradc
[15]: wdt_int
31:16 reg_51_int1_final_status RO mcu int1_n status
[0]: vbat_det
[1]: mbox0_int
[2]: NA
ed
[3]: irrx_int
[4]: gpio_int
w
[5]: uart_int
lo
[6]: spinor1_int
[7]: timer0_int
al
[8]: timer1_int
[9]: irq_ap2rtc[0]
t
[10]: irq_ap2rtc[1]
no
[11]: i2c_int
e
[13]: hw_thm_shdn
ar
[14]: saradc
[15]: wdt_int
n
tio
rtc_ip_pwr_req
u
ib

r
0 reg_sd1_pwr_req R/W power fence control 0x1

di V
st

re k-
[0]: sd1
1
d il
reg_sd1_pwr_req_2nd R/W power fence control 0x1

an M

[0]: sd1
n by
2 reg_mcu_pwr_req R/W power fence control 0x1

[1]: mcu subsys
tio lic
3 reg_mcu_pwr_req_2nd R/W power fence control 0x1

ca ub
[1]: mcu subsys

15:4 Reserved
ifi p
16 reg_sd1_pwr_ack RO power fence power status

od de

[0]: sd1
M a
17 reg_sd1_pwr_ack_2nd RO power fence power status

M

[0]: sd1
18 reg_mcu_pwr_ack RO power fence power status
[1]: mcu subsys
19 reg_mcu_pwr_ack_2nd RO power fence power status
[1]: mcu subsys
31:20 Reserved
rtc_ip_iso_ctrl
246
CV1835

0 reg_sd1_iso_en R/W sd1 iso enablel 0x0
1 reg_mcu_iso_en R/W mcu iso enablel 0x0
15:2 Reserved
17:16 reg_ip_por_en R/W 1: pwr_island reset assert when power 0x3
ack is 0
ed
31:18 Reserved
w
rtcsys_wkup_ctrl1
lo
al
t
7:0 reg_rtcsys_wkint_final_status RO wkint final status
no
[0]: sd1_wakeup_intr
[1]: gpio_int
[2]: timer0_int
e
[3]: timer1_int
ar
[4]: saradc_int
n
[6]: NA
tio
[7]: NA
31:8 Reserved
u
ib
rtcsys_sram_ctrl
r
di V
st

re k-

d il
0 reg_ahb_sram_slp R/W 1 : ahb sram into sleep mode 0x0

an M
1 reg_ahb_sram_sd R/W 1 : ahb sram into shut down mode 0x0

2 reg_ahb_sram_ctrl_ov R/W 0 : ahb sram ctrl by PMU FSM and ahb 0x1
n by
sram busy
tio lic
3 reg_sdio_sram_slp R/W 1 : sdio sram into sleep mode 0x0
ca ub
4 reg_sdio_sram_sd R/W 1 : sdio sram into shut down mode 0x0

5 reg_sdio_sram_ctrl_ov R/W 0 : sram's sd pin = 1'b0 0x1
ifi p

od de
reg_sdio_sram_sd
6 reg_mcu_sram_slp R/W 1 : mcu iram sram into sleep mode 0x0
M a
7 reg_mcu_sram_sd R/W 1 : mcu iram sram into shut down mode 0x0
M
8 reg_mcu_sram_ctrl_ov R/W 0 : mcu iram sram ctrl by PMU FSM 0x1

9 reg_rtc_sram_slp R/W 1 : mcu iram sram into sleep mode 0x0
10 reg_rtc_sram_sd R/W 1 : mcu iram sram into shut down mode 0x0
11 reg_rtc_sram_ctrl_ov R/W 0 : mcu iram sram ctrl by PMU FSM 0x1
12 reg_ahb_sram_1_slp R/W 1 : ahb sram into sleep mode 0x0
13 reg_ahb_sram_1_sd R/W 1 : ahb sram into shut down mode 0x0
14 reg_ahb_sram_1_ctrl_ov R/W 0 : ahb sram ctrl by PMU FSM and ahb 0x1
sram busy
247
CV1835

15 reg_ahb_sram_2_slp R/W 1 : ahb sram into sleep mode 0x0
16 reg_ahb_sram_2_sd R/W 1 : ahb sram into shut down mode 0x0
17 reg_ahb_sram_2_ctrl_ov R/W 0 : ahb sram ctrl by PMU FSM and ahb 0x1
sram busy
27:18 Reserved
28 reg_mcu_sram_force_ce R/W 1: force mcu_iram cs = 1 0x1
ed
31:29 Reserved
w
rtcsys_io_ctrl
lo
al
t
0 reg_i2c_mux_opt0 R/W 0: pwr_gpio6/8 control by dw_gpio 0x0
no
1: pwr_gpio6 is PWR_IIC_SDA
pwr_gpio8 is PWR_IIC_SCL
e
31:1 Reserved
rtcsys_wdt_ctrl
ar
n
tio

u
0 reg_rtc_hw_wdg_rst_en R/W 0: disable rtc wdt trigger warm reset or 0x0

ib
pwrcyc reset
r
1: enable rtc wdt trigger warm reset or

di V
st
pwrcyc reset
re k-
1 reg_rtc_wdt_ctrl_mask_en R/W no load 0x1

d il
31:2 Reserved
an M
rtcsys_irrx_clk_ctrl
n by

tio lic

0 reg_irrx_clk_sw_force_on R/W force on clk ctrl of irrx 0x1
ca ub
1 reg_irrx_xtal_req_en R/W enable irrx clk ctrl requet XTAL 0x0

2 reg_irrx_osc_req_en R/W enable irrx clk ctrl requet OSC 0x0
ifi p
3 reg_irrx_ldo_req_en R/W enable irrx clk ctrl requet LDO 0x0

od de
7:4 Reserved
15:8 reg_irrx_xtal_filter_cyc R/W irrx xtal filter cycle (default 2ms) 0x40
M a
19:16 reg_irrx_clk_ctrl_st RO irrx clock ctrol state

M
31:20 Reserved
rtcsys_rtc_wkup_ctrl
7:0 reg_rtc_wkint_mask R/W wakeup source mask int to RTC_CORE 0xff
[0]: irrrx_intr
[1]: gpio_int
[2]: timer0_int
[3]: timer1_int
[4]: saradc_int
248
CV1835

[6]: wdt_int
[7]: irrx_wakeup
15:8 Reserved
23:16 reg_rtc_puint_mask R/W power-up source mask int to RTC_CORE 0xff
[0]: irrrx_intr
[1]: gpio_int
[2]: timer0_int
[3]: timer1_int
ed
[4]: saradc_int
w
[6]: wdt_int
lo
[7]: irrx_wakeup
31:24 Reserved
al
t
rtcsys_por_rst_ctrl
no
e
ar
0 reg_rtcsys_reset_en R/W 0: not allow rtcsys reset by pwr cyc/ wdt 0x0
warm resetn
1 : allow rtcsys reset by pwr cyc/ wdt
tio
warm reset
1 reg_rtcsys_rstn_src_sel R/W select rtcsys rstn src 0x0
0: rtc_core fsm (reset with die
u
domain)
ib
1: por_pwr_rstn
r
di V
31:2 Reserved
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
249
CV1835
Memory Interface
4.1 DDR Controller
ed
4.1.1 Overview
w
lo
DDR controller realizes the data access of dynamic random access memory (DRAM). It
al
converts the data access command of each main device in SoC into the DRAM
t
no
command conforming to JEDEC standard and schedules it properly, so as to improve
the efficiency of dynamic memory.
e
4.1.2 Characteristics ar
n
tio
• Features:
u
ib
• Supports:
r
DDR2 with maximum data rate of 1333 Mbps.

di V
st
re k-
DDR3 with maximum data rate of 1866 Mbps.

d il
an M
• Supports interface data width of 16-bit.

• Supports single channel, single rank.
n by
• Supports automatic refresh control.

tio lic
• Supports priority control.

ca ub
• Supports data flow statistics.

ifi p
• Supports low power mode.

od de
• Supports address mapping.

M a
• Supports pin multiplexing.

M
250
CV1835
4.1.3.1 Application Block Diagram
The DRAM interface supports a 16-bit data width. Figure 4-1 shows a schematic
diagram of the interconnection between the main chip and a single DRAM device.
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
Figure 4- 1 SoC/DRAM Interconnection Diagram

d il
an M
n by
Command consists of several signals, which vary according to DRAM type. Table 4‑1
compares the DDR2 / DDR3 command signals.
tio lic
Table 4‑1 DDR2/DDR3 Command Difference Comparison

ca ub
ifi p
Function DDR2 DDR3

DDR CKE D2x_CKE D3x_CKE
od de
DDR CLKN D2x_CK_N D3x_CK_N

DDR CLKP D2x_CK_P D3x_CK_P
M a
DDR CSB D2x_CS_N D3x_CS_N

M
DDR RESETN D2x_RESET_N D3x_RESET_N

DDR RASN D2x_RAS_N D3x_RAS_N
DDR CASN D2x_CAS_N D3x_CAS_N
DDR WEN D2x_WE_N D3x_WE_N
DDR ACTN N/A N/A
DDR BA D2x_BAn D3x_BAn
DDR BG N/A N/A
DDR MA D2x_An (n = 0 – 15) D3x_An (n = 0 – 15)
DDR ODT D2x_ODT D3x_ODT
Explanation:
The pin names may have slight differences depending on the package.
251
CV1835
4.1.3.2 Function Principle
Based on the storage characteristics of DRAM, JEDEC formulates a set of standards,

which regulate the command and sequence needed to access DRAM data and control
DRAM status. With proper configuration of DDR register, DDR controller can send out
ed
the commands that meets JEDEC standard and complete the actions of reading, writing
w
and power consumption control.
lo
al
4.1.3.2.1 Command Truth Table
t
no
DDR interface meets JDEDC standard, which is shown in Table 4-1 and Table 4-2. They
e
are the support commands truth tables of DDR2, DDR3 respectively for users' reference.
ar
Other information can refer to JEDEC standard. n
tio
Table 4- 1 DDR2 Command Truth Table
u
Function CKE CKE CS RA CA W BA0 A11 A1 A0

ib
Pre Cur # S# S# E# - - 0 -
BA2 A15 / A9
r
di V
st
re k-
AP
d il
an M
Mode Register Set H H L L L L BA OP

Refresh H H L L L H V V V V
n by
Self Refresh Entry H L L L L H V V V V

Self Refresh Exit L H H X X X X X X X
tio lic
L H H H V V V V
Single Bank Precharge H H L L H L BA V L V
ca ub
Precharge all Banks H H L L H L V V H V

Bank Activate H H L L H H BA RA
ifi p
Write H H L H L L BA RFU L CA
Write with Auto Precharge H H L H L L BA RFU H CA
od de
Read H H L H L H BA RFU L CA
M a
Read with Auto Precharge H H L H L H BA RFU H CA

M
Read with Auto Precharge H H L H L H BA RFU H CA

No Operation H H L H H H V V V V
Device Deselected H H H X X X X X X X
Power Down Entry H L L H H H V V V V
H X X X X X X X
Power Down Exit L H L H H H V V V V
H X X X X X X X
H：High level；L：Low level；V：Effective；X：Does not matter
RFU：reserve for future using.
252
CV1835
Table 4- 2 DDR3 Command Truth Table

Function CKE CKE CS RA CA W BA0 A13 A1 A1 A0
Pre Cur # S# S# E# - - 2 0 -
BA2 A15 / / A9,
11
BC AP
#
ed
Mode Register Set H H L L L L BA OP
w
Refresh H H L L L H V V V V V
lo
Self Refresh Entry H L L L L H V V V V V
Self Refresh Exit L H H X X X X X X X X
al
L H H H V V V V V
t
Single Bank Precharge H H L L H L BA V V L V
no
Precharge all Banks H H L L H L V V V H V
Bank Activate H H L L H H BA RA
Write H H L H L L BA RFU V L CA
e
(Fixed BL8 or BC4)
ar
Write H H L H L L BA RFU L L CA
(BC4, on the Fly)
n
Write H H L H L L BA RFU H L CA
tio
(BL8, on the Fly)

Write with Auto Precharge H H L H L L BA RFU V H CA
u
(Fixed BL8 or BC4)

ib
Write with Auto Precharge H H L H L L BA RFU L H CA

r
(BC4, on the Fly)

di V
st
Write with Auto Precharge H H L H L L BA RFU H H CA

re k-
(BL8, on the Fly)

d il
Read H H L H L H BA RFU V L CA
an M
(Fixed BL8 or BC4)

Read H H L H L H BA RFU L L CA
n by
(BC4, on the Fly)

Read H H L H L H BA RFU H L CA
(BL8, on the Fly)
tio lic
Read with Auto Precharge H H L H L H BA RFU V H CA

ca ub
(Fixed BL8 or BC4)

Read with Auto Precharge H H L H L H BA RFU L H CA
ifi p
(BC4, on the Fly)

Read with Auto Precharge H H L H L H BA RFU H H CA
od de
(BL8, on the Fly)

No Operation H H L H H H V V V V V
M a
M
Device Deselected H H H X X X X X X X X
Power Down Entry H L L H H H V V V V V
H X X X X X X X X
Power Down Exit L H L H H H V V V V V
H X X X X X X X X
ZQ Calibration Long H H L H H L X X X H X
ZQ Calibration Short H H L H H L X X X L X
H：High level；L：Low level；V：Effective；X：Does not matter
RFU：reserve for future using.
253
CV1835
4.1.3.2.2 Automatic Refresh
The DDR controller has the ability to refresh the DRAM content automatically. The
purpose of controlling the automatic refresh is to reduce the delay of accessing data or
the impact of refresh command on the DRAM bandwidth by trying to send refresh
command when the DRAM is idle. The specific available means are as follows：
ed
Equal Interval Refresh: issue refresh command ever tREFI time.
Smart Refresh: The internal DDR controller will count the number of expired tREFI,
w
lo
and then use the idle time to send data continuously.
al
4.1.3.2.3 Low Power Consumption Management
t
no
DDR controller supports low power consumption mode:
e
Normal Low Power Consumption Mode: Set an idle timer through register. When
ar
the normal low power consumption mode is enabled and the DDR controller was
n
tio
idle for a shorter period, the DRAM will be automatically put to the normal low
power consumption mode until there is any access.
u
ib
Self Refresh Mode: It is a mode that consumes much lower power. When the self
r
di V
refresh mode is enabled and the DDR controller was idle for a longer period, the
st
re k-
DRAM will be automatically put to the self refresh mode until there is any access.
d il
an M
4.1.3.2.4 Arbitration mechanism

n by
DDR controller optimizes the bandwidth utilization of the system based on the control
tio lic
timing of DRAM, and schedules the commands through priority scheduling algorithm.
ca ub
In addition, DDRC also implements two scheduling auxiliary means and real-time
ifi p
control (enabling these two control means according to business needs, which can be
od de
enabled at the same time or separately), to control command requests

M a
Continuous Address Access Restrictions:

M
The limitation is 0 ~ 15 DRAM read / write instructions, and the configuration of each
AXI port is independent. DDR controller has high priority for continuous address by
default to optimize DRAM utilization. This mechanism limits the maximum length of
continuous access DRAM for each AXI port.
Timeout Control
For each read/write transfer on the AXI port, a timeout register can be configured to
avoid waiting for an excessively long time. Once the waiting time is reached, the AXI
254
CV1835
port that has not yet reached the waiting time or has not been configured with timeout
properties will be forcibly masked.
Priority Scheduling:
The priority level is 0-15. The higher the value is, the higher the priority is. The read /
write priority configuration of each AXI port is independent.
Real-time Control:
ed
For real-time function, the hardware buffer threshold can be configured. If the buffer is
w
insufficient, the priority will be raised to the highest automatically, and other AXI ports
lo
can be restricted to generate new transmissions
al
t
4.1.3.2.5 Flow Statistics and Command Latency Statistics Function
no
DDR controller supports traffic statistics function: it can count the read and write traffic
e
ar
of each AXI port to collect the current traffic information and decide whether to control
n
the traffic. It can be used to count the total read / write traffic of DRAM.
tio
DDR controller supports AXI latency statistics function, which supports cumulative
u
latency statistics for specified/unscheduled transfers.

r ib
di V
st
4.1.3.2.6 Address Mapping Method

re k-
d il
DDR controller converts the access address of system to that of DRAM. It realizes RBC
an M
(row_bank_column) , BRC and bank interleave in row / column bit.

n by
4.1.4 Working Method

tio lic
ca ub
4.1.4.1 Soft Reset

ifi p
od de
Soft reset is not supported.

M a
M
4.1.4.2 DDR Initialization Configuration Process
The initialization process of the controller is provided in the form of software package.
255
CV1835
4.1.5 AXI Register
4.1.5.1 AXI RegisterOverview
Base Address: 0x0800_4000
ed
Offset
w
AXI_CTRL0_1 0x4b4 AXI1 read timeout control
lo
AXI_CTRL1_1 0x4b8 AXI1 write timeout control
AXI_CTRL0_2 0x564 AXI2 read timeout control
al
AXI_CTRL1_2 0x568 AXI2 write timeout control
t
AXI_CTRL0_3 0x614 AXI3 read timeout control
no
AXI_CTRL1_3 0x618 AXI3 write timeout control
e
ar
n
Offset
tio
AXI_MON0_CTRL 0x000 AXI monitor 0 control

AXI_MON0_INPUT 0x004 AXI monitor 0 input selection
u
AXI_MON0_FILTER0 0x010 AXI monitor 0 filter settings

ib

AXI_MON0_FILTER2
r
0x018 AXI monitor 0 filter settings

di V
st
AXI_MON0_FILTER3 0x01c AXI monitor 0 filter settings

re k-

d il

an M

n by

AXI_MON0_RPT0 0x040 AXI monitor 0 cycle count
AXI_MON0_RPT1 0x044 AXI monitor 0 hit count
tio lic
AXI_MON0_RPT2 0x048 AXI monitor 0 byte count

ca ub
AXI_MON0_RPT3 0x04c AXI monitor 0 latency count

ifi p

od de

M a
M

AXI_MON1_FILTER4 0x0a0 AXI monitor 1 filter settings
AXI_MON1_FILTER7 0x0ac AXI monitor 1 filter settings
AXI_MON1_FILTER8 0x0b0 AXI monitor 1 filter settings
AXI_MON1_RPT0 0x0c0 AXI monitor 1 cycle count
AXI_MON1_RPT1 0x0c4 AXI monitor 1 hit count
AXI_MON1_RPT2 0x0c8 AXI monitor 1 byte count
AXI_MON1_RPT3 0x0cc AXI monitor 1 latency count
256
CV1835

Offset
ed
w
lo
al
t
no
e
ar
n
tio
u

ib

r
di V
st

re k-

d il
an M

n by

tio lic

ca ub

ifi p

od de

M a

M

257
CV1835

Offset
ed
w
lo
al
t
no
e
ar
n
tio
u

ib

r
di V
st

re k-

d il
an M

n by

tio lic

ca ub

ifi p

od de

M a

M

258
CV1835

Offset
ed
w
lo
al
t
no
e
ar
n
tio
u

ib

r
di V
st

re k-

d il
an M

n by

tio lic

ca ub

ifi p

od de
M a
M
4.1.5.2 AXI Register Description
AXI_CTRL0_1
259
CV1835

9:0 axi1_rd_timeout_val R/W After an AXI read transaction is granted, 0x0
a timeout counter starts to count. When
it counts to axi<n>_rd_timeout_val, the
corresponding channel has the highest
priority.
11:10 Reserved
12 axi1_rd_timeout_en R/W If set to 1, enables the timeout function 0x0
for the read channel of port n.
31:13 Reserved
ed
w
AXI_CTRL1_1
lo
al
9:0 axi1_wr_timeout_val R/W After an AXI write transaction is 0x0
t
granted, a timeout counter starts to
no
count. When it counts to
axi<n>_wr_timeout_val, the
e
ar
priority.
11:10 Reserved n
12 axi1_wr_timeout_en R/W If set to 1, enables the timeout function 0x0
tio
for the write channel of port n.

31:13 Reserved
u
ib
AXI_CTRL0_2
r
di V
st

re k-

d il

an M

n by

priority.
11:10 Reserved
tio lic

ca ub

31:13 Reserved
ifi p
od de
AXI_CTRL1_2
M a

M

priority.
11:10 Reserved
31:13 Reserved
260
CV1835
AXI_CTRL0_3
priority.
11:10 Reserved
ed
w
31:13 Reserved
lo
al
AXI_CTRL1_3
t
no
e
ar
n
tio
priority.
11:10 Reserved
u

ib

r
31:13 Reserved
di V
st
re k-
d il
基址 0x0800_8000
an M
AXI_MON0_CTRL
n by

tio lic

0 axi_mon0_en R/W If set to 1, enables the AXI monitor 0x0
ca ub
function.
1 axi_mon0_clear R/W Clear all the counter. 0x0
ifi p
2 axi_mon0_snapshot R/W Snapshot all the counter. 0x0

od de
3 axi_mon0_snapshot_all R/W Snapshot all the counter of all AXI 0x0

monitors
M a
4 axi_mon0_irq_en R/W If set to 1, enables the AXI monitor 0x0

M
interrupt.
5 axi_mon0_irq_clear R/W If set to 1, clears the axi_mon_irq. 0x0
6 Reserved
7 axi_mon0_irq RO Assert when all axi_mon<n>_hit_sel
suscces.
31:8 Reserved
AXI_MON0_INPUT
5:0 axi_mon0_input_sel R/W Input/clk selection, 0 = No selection. 0x0
261
CV1835

31:6 Reserved
AXI_MON0_FILTER0
9:0 axi_mon0_hit_sel R/W Select which conditions are used to 0x0
judege hit
bit [0]: addr_st/addr_sp
ed
bit [1]: id/id_mask
w
bit [2]: len
bit [3]: size
lo
bit [4]: burst
al
bit [5]: lock
bit [6]: cache
t
bit [7]: prot
no
bit [8]: qos
bit [9]: AXI transaction cross 4KB
boundary
e
31:10
ar
Reserved
n
AXI_MON0_FILTER1
tio

u

ib
31:0 axi_mon0_hit_addr_st_lo R/W Hit start address[31:0] 0x0

hit = (Ax_addr >= hit_addr_st) &&
r
di V
st
(Ax_addr < hit_addr_sp)

re k-
d il
AXI_MON0_FILTER2
an M

n by
7:0 axi_mon0_hit_addr_st_hi R/W Hit start address[39:32] 0x0

tio lic

31:8 Reserved
ca ub
ifi p
AXI_MON0_FILTER3
od de

M a
M
31:0 axi_mon0_hit_addr_sp_lo R/W Hit end address[31:0] 0x0
AXI_MON0_FILTER4
7:0 axi_mon0_hit_addr_sp_hi R/W Hit end address[39:32] 0x0
31:8 Reserved
AXI_MON0_FILTER5
262
CV1835

23:0 axi_mon0_hit_id_mask R/W hit = (hit_id & hit_id_mask) == (Ax_id & 0x0
hit_id_mask)
31:24 Reserved
AXI_MON0_FILTER6
ed
23:0 axi_mon0_hit_id R/W hit = Ax_id == hit_id 0x0
31:24 Reserved
w
lo
AXI_MON0_FILTER7
al
t
no
7:0 axi_mon0_hit_len R/W hit = Ax_len == hit_len 0x0
10:8 axi_mon0_hit_size R/W hit = Ax_size == hit_size 0x0
11 Reserved
e
13:12
ar
axi_mon0_hit_burst R/W hit = Ax_burst == hit_burst 0x0
31:14 Reserved n
tio
AXI_MON0_FILTER8
u
ib

0 axi_mon0_hit_lock R/W hit = Ax_lock == hit_lock 0x0
r
di V
st
3:1 Reserved
re k-
7:4 axi_mon0_hit_cache R/W hit = Ax_cache == hit_cache 0x0

d il
10:8 axi_mon0_hit_prot R/W hit = Ax_prot == hit_prot 0x0

an M
11 Reserved
15:12 axi_mon0_hit_qos R/W hit = Ax_qos == hit_qos 0x0
n by
31:16 Reserved
tio lic
AXI_MON0_RPT0
ca ub

ifi p
31:0 axi_mon0_cycle_count RO AXI monitor 0 cycle count, counting

od de
after func_en assert

M a
AXI_MON0_RPT1
M

31:0 axi_mon0_hit_count RO AXI monitor 0 hit count, counting after
func_en assert
AXI_MON0_RPT2
31:0 axi_mon0_byte_count RO AXI monitor 0 byte count, counting after
func_en assert, (Ax_len + 1) << Ax_size
263
CV1835
AXI_MON0_RPT3
31:0 axi_mon0_latency_count RO AXI monitor 0 latency count, counting
after func_en assert, += oustanding
AXI_MON1_CTRL
ed
w
function.
lo
al
t
monitors
no
interrupt.
e
ar
6 Reserved
n
suscces.
tio
31:8 Reserved
u
AXI_MON1_INPUT
ib

r
di V
st

re k-

d il
31:6 Reserved
an M
AXI_MON1_FILTER0
n by

tio lic

ca ub
judege hit
ifi p
bit [1]: id/id_mask

od de
bit [2]: len

bit [3]: size
M a
bit [4]: burst

M
bit [5]: lock

bit [6]: cache
bit [7]: prot
bit [8]: qos
boundary
31:10 Reserved
AXI_MON1_FILTER1
264
CV1835

AXI_MON1_FILTER2
ed
w
31:8 Reserved
lo
al
AXI_MON1_FILTER3
t
no
e
ar
AXI_MON1_FILTER4 n
tio

u
31:8 Reserved
r ib
di V
AXI_MON1_FILTER5
st
re k-

d il

an M
hit_id_mask)
n by
31:24 Reserved
tio lic
AXI_MON1_FILTER6
ca ub

ifi p

od de
31:24 Reserved
M a
M
AXI_MON1_FILTER7
11 Reserved
13:12 axi_mon1_hit_burst R/W hit = Ax_burst == hit_burst 0x0
31:14 Reserved
AXI_MON1_FILTER8
265
CV1835

3:1 Reserved
11 Reserved
31:16 Reserved
ed
w
AXI_MON1_RPT0
lo
al
t
no
AXI_MON1_RPT1
e
ar
n Reset
tio
func_en assert
u
AXI_MON1_RPT2
ib

r
di V
st

re k-

d il

an M
AXI_MON1_RPT3
n by

tio lic

ca ub

ifi p
AXI_MON2_CTRL
od de

M a
M

function.
monitors
interrupt.
6 Reserved
suscces.
266
CV1835

31:8 Reserved
AXI_MON2_INPUT
31:6 Reserved
ed
AXI_MON2_FILTER0
w
lo
al
judege hit
t
no
bit [1]: id/id_mask
bit [2]: len
e
bit [3]: size
ar
bit [4]: burst
bit [5]: lock
n
bit [6]: cache
tio
bit [7]: prot

bit [8]: qos
u

ib
boundary
31:10 Reserved
r
di V
st
re k-
AXI_MON2_FILTER1
d il
an M

n by

tio lic
ca ub
AXI_MON2_FILTER2
ifi p

od de

M a

M

31:8 Reserved
AXI_MON2_FILTER3
AXI_MON2_FILTER4
267
CV1835

31:8 Reserved
AXI_MON2_FILTER5
ed
hit_id_mask)
31:24 Reserved
w
lo
AXI_MON2_FILTER6
al
t
no
31:24 Reserved
e
ar
AXI_MON2_FILTER7
n
tio

u
11 Reserved
ib

r
di V
st
31:14 Reserved
re k-
d il
AXI_MON2_FILTER8
an M

n by

3:1 Reserved
tio lic

ca ub

11 Reserved
ifi p

od de
31:16 Reserved
M a
M
AXI_MON2_RPT0
AXI_MON2_RPT1
func_en assert
268
CV1835
AXI_MON2_RPT2
AXI_MON2_RPT3
ed
w
lo
al
AXI_MON3_CTRL
t
no
e
function.
ar
2 axi_mon3_snapshot R/W Snapshot all the counter.
n 0x0
tio
monitors
u
interrupt.
ib

6 Reserved
r
di V
st

re k-
suscces.
d il
31:8 Reserved
an M
AXI_MON3_INPUT
n by

tio lic

ca ub
31:6 Reserved
ifi p
AXI_MON3_FILTER0
od de

M a

M

judege hit
bit [1]: id/id_mask
bit [2]: len
bit [3]: size
bit [4]: burst
bit [5]: lock
bit [6]: cache
bit [7]: prot
bit [8]: qos
boundary
269
CV1835

31:10 Reserved
AXI_MON3_FILTER1
ed
w
AXI_MON3_FILTER2
lo
al
t
no
31:8 Reserved
e
ar
AXI_MON3_FILTER3 n
tio

u
ib
AXI_MON3_FILTER4
r
di V
st

re k-

d il

an M
31:8 Reserved
n by
AXI_MON3_FILTER5
tio lic

ca ub
hit_id_mask)
ifi p
31:24 Reserved
od de
M a
AXI_MON3_FILTER6
M

31:24 Reserved
AXI_MON3_FILTER7
270
CV1835

11 Reserved
31:14 Reserved
AXI_MON3_FILTER8
ed
3:1 Reserved
w
lo
11 Reserved
al
t
31:16 Reserved
no
AXI_MON3_RPT0
e
ar
n
tio

u
AXI_MON3_RPT1
ib

r
di V
st

re k-

d il
func_en assert
an M
AXI_MON3_RPT2
n by

tio lic

ca ub

ifi p
AXI_MON3_RPT3
od de

M a

M

AXI_MON4_CTRL
function.
monitors
271
CV1835

interrupt.
6 Reserved
suscces.
31:8 Reserved
ed
AXI_MON4_INPUT
w
lo
al
31:6 Reserved
t
no
AXI_MON4_FILTER0
e
ar
judege hit
n
tio
bit [1]: id/id_mask

bit [2]: len
u
bit [3]: size

ib
bit [4]: burst

r
bit [5]: lock

di V
st
bit [6]: cache

re k-
bit [7]: prot

d il
bit [8]: qos

an M

boundary
n by
31:10 Reserved
tio lic
AXI_MON4_FILTER1
ca ub

ifi p

od de

M a
M
AXI_MON4_FILTER2
31:8 Reserved
AXI_MON4_FILTER3
272
CV1835

AXI_MON4_FILTER4
31:8 Reserved
ed
AXI_MON4_FILTER5
w
lo
al
hit_id_mask)
t
31:24 Reserved
no
AXI_MON4_FILTER6
e
ar
n
tio
31:24 Reserved
u
ib
AXI_MON4_FILTER7
r
di V

st
re k-

d il
an M

11 Reserved
n by

31:14 Reserved
tio lic
AXI_MON4_FILTER8
ca ub

ifi p

od de

3:1 Reserved
M a

M

11 Reserved
31:16 Reserved
AXI_MON4_RPT0
273
CV1835
AXI_MON4_RPT1
func_en assert
AXI_MON4_RPT2
ed
w
lo
al
AXI_MON4_RPT3
t
no
e
AXI_MON5_CTRL
ar
n
tio

u

ib
function.
r
di V
st

re k-

monitors
d il
an M

interrupt.
5
n by
axi_mon5_irq_clear R/W If set to 1, clears the axi_mon_irq. 0x0

6 Reserved
tio lic
suscces.
ca ub
31:8 Reserved
ifi p
AXI_MON5_INPUT
od de

M a

M

31:6 Reserved
AXI_MON5_FILTER0
judege hit
bit [1]: id/id_mask
bit [2]: len
274
CV1835

bit [3]: size
bit [4]: burst
bit [5]: lock
bit [6]: cache
bit [7]: prot
bit [8]: qos
boundary
31:10 Reserved
ed
w
AXI_MON5_FILTER1
lo
al
t
no
e
AXI_MON5_FILTER2
ar
n
tio
u
ib
31:8 Reserved
r
di V
st
AXI_MON5_FILTER3
re k-

d il
an M

n by
AXI_MON5_FILTER4
tio lic

ca ub

ifi p
31:8 Reserved
od de
AXI_MON5_FILTER5
M a
M

hit_id_mask)
31:24 Reserved
AXI_MON5_FILTER6
31:24 Reserved
275
CV1835
AXI_MON5_FILTER7
11 Reserved
31:14 Reserved
ed
AXI_MON5_FILTER8
w
lo
al
3:1 Reserved
t
no
11 Reserved
e
ar
31:16 Reserved n
tio
AXI_MON5_RPT0
u

ib

r

di V
st

re k-
d il
AXI_MON5_RPT1
an M

n by

func_en assert
tio lic
ca ub
AXI_MON5_RPT2
ifi p

od de

M a

M
AXI_MON5_RPT3
AXI_MON6_CTRL
276
CV1835

function.
monitors
interrupt.
ed
6 Reserved
7
w
axi_mon6_irq RO Assert when all axi_mon<n>_hit_sel
suscces.
lo
31:8 Reserved
al
AXI_MON6_INPUT
t
no
e
ar
31:6 Reserved n
AXI_MON6_FILTER0
tio

u

ib

r
judege hit
di V
st

re k-
bit [1]: id/id_mask

d il
bit [2]: len

an M
bit [3]: size

bit [4]: burst
n by
bit [5]: lock

bit [6]: cache
bit [7]: prot
tio lic
bit [8]: qos

ca ub

boundary
ifi p
31:10 Reserved
od de
AXI_MON6_FILTER1
M a

M

AXI_MON6_FILTER2
277
CV1835

31:8 Reserved
AXI_MON6_FILTER3
ed
AXI_MON6_FILTER4
w
lo
al
31:8 Reserved
t
no
AXI_MON6_FILTER5
e
ar
hit_id_mask)
n
31:24 Reserved
u tio
AXI_MON6_FILTER6
ib

r
di V
st

re k-

31:24 Reserved
d il
an M
AXI_MON6_FILTER7
n by

tio lic

ca ub

11 Reserved
ifi p

od de
31:14 Reserved
M a
AXI_MON6_FILTER8
M

3:1 Reserved
11 Reserved
31:16 Reserved
278
CV1835
AXI_MON6_RPT0
AXI_MON6_RPT1
ed
w
func_en assert
lo
al
AXI_MON6_RPT2
t
no
e
AXI_MON6_RPT3
ar
n
tio

u

ib

r
di V
st
AXI_MON7_CTRL
re k-

d il
an M

n by
function.
tio lic

ca ub
monitors
ifi p
interrupt.
od de
6 Reserved
M a
M
suscces.
31:8 Reserved
AXI_MON7_INPUT
31:6 Reserved
AXI_MON7_FILTER0
279
CV1835

judege hit
bit [1]: id/id_mask
bit [2]: len
bit [3]: size
bit [4]: burst
bit [5]: lock
ed
bit [6]: cache
bit [7]: prot
w
bit [8]: qos
lo
al
boundary
31:10 Reserved
t
no
AXI_MON7_FILTER1
e
ar
n
tio
u
AXI_MON7_FILTER2
ib

r
di V
st

re k-

d il
an M

31:8 Reserved
n by
AXI_MON7_FILTER3
tio lic

ca ub

ifi p
od de
AXI_MON7_FILTER4
M a
M

31:8 Reserved
AXI_MON7_FILTER5
hit_id_mask)
31:24 Reserved
280
CV1835
AXI_MON7_FILTER6
31:24 Reserved
AXI_MON7_FILTER7
ed
w
lo
11 Reserved
al
31:14 Reserved
t
no
AXI_MON7_FILTER8
e
ar
n
3:1 Reserved
tio

u

ib
11 Reserved
r

di V
st
31:16 Reserved
re k-
d il
AXI_MON7_RPT0
an M

n by

tio lic

ca ub
AXI_MON7_RPT1
ifi p

od de

M a
func_en assert
M
AXI_MON7_RPT2
AXI_MON7_RPT3
281
CV1835

AXI_MON8_CTRL
function.
ed
w
lo
monitors
al
interrupt.
t
no
6 Reserved
e
suscces.
ar
31:8 Reserved
n
AXI_MON8_INPUT
tio

u

ib

r
31:6 Reserved
di V
st
re k-
AXI_MON8_FILTER0
d il
an M

n by

judege hit
tio lic

bit [1]: id/id_mask
ca ub
bit [2]: len

bit [3]: size
ifi p
bit [4]: burst

bit [5]: lock
od de
bit [6]: cache

M a
bit [7]: prot

M
bit [8]: qos

boundary
31:10 Reserved
AXI_MON8_FILTER1
282
CV1835
AXI_MON8_FILTER2
31:8 Reserved
ed
AXI_MON8_FILTER3
w
lo
al
AXI_MON8_FILTER4
t
no
e
ar
31:8 Reserved
n
AXI_MON8_FILTER5
tio

u

ib
r
hit_id_mask)
di V
st
31:24 Reserved
re k-
d il
an M
AXI_MON8_FILTER6
n by

tio lic
31:24 Reserved
ca ub
AXI_MON8_FILTER7
ifi p

od de

M a
M

11 Reserved
31:14 Reserved
AXI_MON8_FILTER8
3:1 Reserved
283
CV1835

11 Reserved
31:16 Reserved
AXI_MON8_RPT0
ed
w
lo
AXI_MON8_RPT1
al
t
no
func_en assert
e
ar
AXI_MON8_RPT2 n
tio

u

r ib
di V
AXI_MON8_RPT3
st
re k-

d il

an M

n by
AXI_MON9_CTRL
tio lic

ca ub

ifi p
function.
od de

M a

M
monitors
interrupt.
6 Reserved
suscces.
31:8 Reserved
AXI_MON9_INPUT
284
CV1835

31:6 Reserved
AXI_MON9_FILTER0
ed
judege hit
w
bit [1]: id/id_mask
bit [2]: len
lo
bit [3]: size
al
bit [4]: burst
bit [5]: lock
t
bit [6]: cache
no
bit [7]: prot
bit [8]: qos
e
ar
boundary
31:10 Reserved n
tio
AXI_MON9_FILTER1
u
ib

r
di V
st

re k-

d il
an M
AXI_MON9_FILTER2
n by

tio lic

ca ub
31:8 Reserved
ifi p
AXI_MON9_FILTER3
od de

M a
M

AXI_MON9_FILTER4
31:8 Reserved
AXI_MON9_FILTER5
285
CV1835

hit_id_mask)
31:24 Reserved
AXI_MON9_FILTER6
ed
w
31:24 Reserved
lo
al
AXI_MON9_FILTER7
t
no
e
ar
11 Reserved
n
31:14 Reserved
tio
AXI_MON9_FILTER8
u
ib

r

di V
st

re k-
3:1 Reserved
d il

an M

11 Reserved
n by

31:16 Reserved
tio lic
ca ub
AXI_MON9_RPT0
ifi p

od de

M a
M
AXI_MON9_RPT1
func_en assert
AXI_MON9_RPT2
286
CV1835

AXI_MON9_RPT3
ed
w
AXI_MON10_CTRL
lo
al
t
function.
no
e
ar
monitors
4 axi_mon10_irq_en R/W If set to 1, enables the AXI monitor
n 0x0
interrupt.
tio
6 Reserved
u

ib
suscces.
31:8 Reserved
r
di V
st
re k-
AXI_MON10_INPUT
d il
an M

n by

31:6 Reserved
tio lic
AXI_MON10_FILTER0
ca ub

ifi p

od de

judege hit
M a

M
bit [1]: id/id_mask

bit [2]: len
bit [3]: size
bit [4]: burst
bit [5]: lock
bit [6]: cache
bit [7]: prot
bit [8]: qos
boundary
31:10 Reserved
287
CV1835
AXI_MON10_FILTER1
AXI_MON10_FILTER2
ed
w
lo
al
31:8 Reserved
t
no
AXI_MON10_FILTER3
e
ar
n
tio
AXI_MON10_FILTER4
u

ib

r

di V
st
31:8 Reserved
re k-
d il
AXI_MON10_FILTER5
an M

n by

tio lic
hit_id_mask)
31:24 Reserved
ca ub
ifi p
AXI_MON10_FILTER6
od de

M a

M
31:24 Reserved
AXI_MON10_FILTER7
11 Reserved
31:14 Reserved
288
CV1835
AXI_MON10_FILTER8
3:1 Reserved
11 Reserved
ed
31:16 Reserved
w
lo
AXI_MON10_RPT0
al
t
no
e
ar
AXI_MON10_RPT1
n
tio

func_en assert
u
ib
AXI_MON10_RPT2
r
di V
st

re k-

d il
31:0 axi_mon10_byte_count RO AXI monitor 10 byte count, counting

an M
after func_en assert, (Ax_len + 1) <<

Ax_size
n by
AXI_MON10_RPT3
tio lic

ca ub

ifi p

od de
AXI_MON11_CTRL
M a
M

function.
monitors
interrupt.
6 Reserved
289
CV1835

suscces.
31:8 Reserved
AXI_MON11_INPUT
ed
31:6 Reserved
w
lo
AXI_MON11_FILTER0
al
t
no
judege hit
e
bit [1]: id/id_mask
ar
bit [2]: len
bit [3]: size
n
bit [4]: burst
tio
bit [5]: lock

bit [6]: cache
u
bit [7]: prot

ib
bit [8]: qos

r
di V
st
boundary
re k-
31:10 Reserved
d il
an M
AXI_MON11_FILTER1
n by

tio lic

ca ub

ifi p
AXI_MON11_FILTER2
od de

M a
M

31:8 Reserved
AXI_MON11_FILTER3
AXI_MON11_FILTER4
290
CV1835

31:8 Reserved
AXI_MON11_FILTER5
ed
hit_id_mask)
w
31:24 Reserved
lo
al
AXI_MON11_FILTER6
t
no
e
31:24 Reserved
AXI_MON11_FILTER7
ar
n
tio
u

ib

r
11 Reserved
di V
st

re k-
31:14 Reserved
d il
an M
AXI_MON11_FILTER8
n by

tio lic

3:1 Reserved
ca ub

ifi p

11 Reserved
od de

31:16 Reserved
M a
M
AXI_MON11_RPT0
AXI_MON11_RPT1
291
CV1835

func_en assert
AXI_MON11_RPT2
31:0 axi_mon11_byte_count RO AXI monitor 11 byte count, counting
after func_en assert, (Ax_len + 1) <<
ed
Ax_size
w
AXI_MON11_RPT3
lo
al
t
no
e
4.1.6 DDRC Register
ar
n
tio
4.1.6.1 DDRC Register Overview

u
r ib
di V
st
re k-

d il

an M
Offset
DRAM_REF_CTRL 0x064 DRAM refresh parameter
n by
DRAM_MRD0 0x0dc DRAM MR value

DRAM_MRD1 0x0e0 DRAM MR value
tio lic
ca ub
4.1.6.2 DDRC Register Description

ifi p
od de
M a

M
DRAM_REF_CTRL
9:0 t_rfc R/W Specify tRFC 0x8c
Unit: ddr core clock cycles
15:10 Reserved
27:16 t_refi R/W Specify tREFI 0x62
Unit: 32 ddr core clocks
31:28 Reserved
292
CV1835
DRAM_MRD0
15:0 ddr_mr1 R/W DDR3: Write value for MR1 register 0x510
DRAM_MRD1
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
293
CV1835
4.2 SPI NOR Flash Controller
4.2.1 Overview
Support external SPI NOR flash data access.
ed
4.2.2 Characteristic
w
lo
 Support one SPI NOR chip select.
al
 Support Dual/Qual read/write operation.
t
no
 Support various specifications of devices.
 Support 3 Byte address device and 4 Byte address device.
e
ar
 Suppport up to 256MB capacity.
 SPI NOR is one of boot devices.
n
u tio

r ib
di V
st
re k-
4.2.3.1 Interface Description

d il
an M
SPI NOR Flash controller can support three SPI NOR interface types: Standard SPI, Dual
n by
SPI and Qual SPI interface mode.

tio lic
ca ub
 Standard SPI Interface Mode:

Standard SPI interface mode has 1 bit data input line and 1 bit data output line. The
ifi p
od de
figure below shows the write and write operation sequence diagrams of standard SPI
interface mode.
M a
M
294
CV1835
ed
w
lo
Figure 4- 2 Standard SPI Interface Mode Write Operation Sequence
al
t
Sequence description:
no
 command/address/dummy cycles are output on DO line in single bit serial
e
mode.
ar
 Data is output on DO line in single bit serial mode.
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
Figure 4- 3 Standard SPI Interface Mode Read Operation Sequence

ifi p
Sequence description:
od de
 Command/Address/Dummy Cycles are output on DO line in single bit serial

M a
M
mode.
 Data is output on DI line in single bit serial mode.
 Dual-Input SPI Interface Mode:

In Dual Input SPI interface mode, two bit data lines are paralleled in data input phase.
The figure below shows the Dual Input SPI interface mode operation sequence diagram.
295
CV1835
ed
w
lo
Figure 4- 4 Dual-Input SPI Interface Sequence
al
Sequence description：
t
no
mode.
e
ar
 Data is input (read) on the DO / DI line in 2 bits mode.
n
tio
 Dual-IO SPI Interface Mode:

u
In Dual IO SPI interface mode, two bit data lines are paralleled in address output and
ib
data input stages. The figure below shows the Dual IO SPI interface mode operation
r
di V
st
sequence.
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
Figure 4- 5 Dual-IO SPI Interface Sequence

M
 Command is output on DO line in single bit serial mode.
 Address/Dummy Cycles/Data output (write) or input (read) on DO / DI line in 2
bits mode.
 Quad-Input SPI Interface Mode:
In Quad Input SPI interface mode, 4 bit data line are paralleled in data input phase. The
figure below shows the Quad Input SPI interface mode operation sequence.
296
CV1835
ed
w
lo
al
t
no
Figure 4- 6 Quad-Input SPI Interface Sequence
e
ar
Sequence description： n
tio
mode.
u
 Data is input (read) in DO / DI / WPN / HOLDN in 4 bits mode.

r ib
di V
st
Quad-IO SPI Interface Mode:

re k-

d il
In Quad IO SPI interface mode, two bit data lines are paralleled in address output and
an M
data input stages. The figure below shows the Quad IO SPI interface mode operation
n by
sequence.
tio lic
ca ub
ifi p
od de
M a
M
Figure 4- 7 Quad-IO SPI Interface Sequence
297
CV1835
 Command is output on DO line in single bit serial mode.

 Address/Dummy Cycles/Data is input (read) in DO / DI / WPN / HOLDN in 4
bits mode.
4.2.3.2 Boot Function
SPI NOR Boot data is located at chip address 0x1000_0000~0x1FFF_FFFF, directly
ed
mapped to SPI NOR flash continuous address space 0x0000_0000~0x0FFF_FFFF. The
w
controller can support flashs up to 256MB, 4 bytes address mode is required if you need
lo
al
to use flashs larger than 16MB. The reset state of the controller is in 3 bytes address
mode, and 4 bytes address mode could be enabled after configuration, so SPI_ NOR
t
no
flash needs to support 3bytes / 4bytes address mode.
e
ar
4.2.3.3 Register Operation
n
The user configures the controller register, such as operation command, address, etc.,
tio
and finally configures reg_go_busy register to issue spi transition . The controller issues
u
ib
commands to the device according to registers configuration.

r
di V
st
re k-
4.2.3.4 DMA Operation

d il
an M
 DMMR Reading Mode:

n by
When SPI_NOR controller operating in dmmr mode, the content in flash is directly
mapped to chip address space 0x1000_0000~0x1FFF_FFFF. The system DMA can use
tio lic
memory-to-memory mode to copy SPI_NOR data to DDR.

ca ub
 Non-DMMR Read and Write Mode:

ifi p
Instructions, addresses and data must be transmitted through FF_ PORT. Read
od de
instruction, write instruction, instruction length and data length should be configured
M a
first, and then write data to FF_PORT by CPU or DMA to issue instructions and
M
addresses.
298
CV1835
4.2.4 Workflow
4.2.4.1 Initialization Process
Step 1. Configure SPI clock divider according to the flash device and issued command.
Step 2. Configure the interrupt control register.
ed
w
lo
4.2.4.2 Device Status Register Operation
al
Step 1. Configure transmission data length.
t
no
Step 2. Configure transmission mode.
Step 3. Configure reg_go_busy.
e
ar
Step 4. Write the transfer content to the cache. n
Step 5. Check INT_STS and wait for the operation to be finished.
u tio
ib
4.2.4.3 SPI NOR Flash Address Mode Switching Process

r
di V
st
re k-
For SPI_NOR flash device, it supports 3-Byte and 4-Byte Flash address modes, and the
d il
mode can be dynamically switched when system is working. Please follow these steps
an M
to switch the flash address mode:

n by
tio lic
Step 1. Complete all operation on SPI_NOR flash device.

ca ub
Step 2. According to the device requirements, configure the device's register in register
ifi p
operation mode to enable 4-byte mode.

od de
Step 3. Configure the register [reg_byte4en] in SPI_NOR flash controller to 4-byte mode
M a
and complete the switch from 3 bytes address mode to 4 bytes address mode.
M
4.2.4.4 DMA Read Operation Flow
Step.1 Disable DMMR mode and DMA_EN mode.

Step.2 Write FF_PT as 1 to clear FIFO and reset read / write index.
Step.3 Enable DMMR mode
299
CV1835
Step.4 Configure the system DMA as mem-to-mem transfer mode. DST_TR_WIDTH =

0x2 (transaction width is 32bit)、DST_MSIZE = 0x0 (burst transaction length =1)、
BLOCK_TS = TRAN_NUM/4 -1 . Block_TS/ DST_TR_WIDTH/ DST_MSIZE should be
configured according to the actual transmission length.
Step. 5 Enable system DMA channel and start memory moving
Step. 6 When the corresponding channel is interrupted, the DMA read is completed.
ed
w
4.2.4.5 DMA Write Operation Flow
lo
al
Step. 1 Disable DMMR mode and DMA_EN mode.
Step.2 Write FF_PT as 1 to clear FIFO and reset read / write index
t
no
Step.3 Configure the system DMA channel mapping and map the selected DMA
channel to 39: dma_req_spi_nor.
e
ar
Step.4 Configure the system DMA as mem-to-mem transfer mode. DST_TR_WIDTH =
n
0x2 (transaction width is 32bit)、DST_MSIZE = 0x0 (burst transaction length =1)、
tio
BLOCK_TS = TRAN_NUM/4 -1 . Block_TS/ DST_TR_WIDTH/ DST_MSIZE should be

u
configured according to the actual transmission length.

ib
Step. 5 Enable system DMA channel

r
di V
st
re k-
Step. 6 Configure SPI_NOR Register TRAN_NUM, excluding instruction and address.

d il
Step.7 Configure SPI_NOR Register TRAN_CSR，tran_mode = 0x2 (tx only), fast_mode,

an M
bus_width, addr_bn, dma_en=0 and reg_go_busy. Ex: TRAN_CSR = 0x0000BC2A

n by
Step.8 Write to command address to SPI_NOR Register FF_Port.

Step.9 Query SPI_NOR Register rdat_ff_PT = 0, ensure that the command and address
tio lic
are sent.
ca ub
Step.10 Configure SPI_NOR Register TRAN_CSR and enable dma_en.

ifi p
Step.11 Detect SPI_NOR Register INT_STS and wait for the operation to complete. This
od de
indicates that the buffer content has been written to the device.
M a
M
4.2.4.6 Other Reminders
Before the device operation is completed, do not change the relevant register
configuration, otherwise the operation may be abnormal.
300
CV1835
4.2.5 Register overview
Base Address 0x10000000

Offset
SPI_CTRL 0x000 SPI_NOR operation control
ed
CE_CTRL 0x004 CE operation control
w
lo
DLY_CTRL 0x008 Delay control
al
DMMR_CTRL 0x00c DMMR mode contro
t
TRAN_CSR 0x010 Transmission control
no
TRAN_NUM 0x014 Transfer frame count
e
ar
FF_PORT 0x018 FIFO write/read port
FF_PT 0x020 FIFO pointer status
n
tio
INT_STS 0x028 Interrupt status

u
INT_EN 0x02c Interrupt enable

r ib
di V
st
re k-
4.2.6 Register Discription

d il
an M
n by
SPI_CTRL
tio lic

ca ub
10:0 sck_div R/W SPI Clock Divider 0x9

SCK frequency = HCLK frequency /
ifi p
(2(SckDiv+ 1))
11 Reserved
od de
12 cpha R/W Clock Phase 0x0

M a
0：When the chip selection is valid, the

M
first clock edge of SCK starts to sample

data.
1：When the chip selection is valid, the
second clock edge of SCK starts to
sample data.
13 cpol R/W Clock Polarity 0x0
0：Low level when SCK is idle
1：High level when SCK is idle
14 hold_o R/W HOLD pin output level 0x1
15 wp_o R/W WP pin output level 0x1
19:16 frame_len R/W Frame length for sending and receiving 0x8
301
CV1835

20 lsb_first R/W LSBF: Least Significant Bit First 0x0
0: Frame MSB first
1: Frame LSB first
21 srst R/W Write 1 to reset all state machines and 0x0
interrupt flag bits
31:22 Reserved
CE_CTRL
ed
w
0 ce_manual R/W CEManual controls the level of CE pin. 0x0
lo
1 ce_manual_en R/W CE Manual Enable 0x0
al
0：The level of CE pin is controlled by
hardware state machine
t
no
1：The level of CE pin is controlled by
CEManual register.
31:2 Reserved
e
DLY_CTRL
ar
n
tio

u
3:0 frame_interval R/W Control the frame interval between two 0x0
ib
adjacent frames of data: T = TSCK *

FmIntvl (no SCK pulse in the frame
r
di V
st
interval). If the frame interval between

re k-
two adjacent frames of data is 0, there

is no frame interval.
d il
7:4 Reserved
an M
11:8 cet R/W CET controls the time that CE is effective 0x3
n by
in advance of the first clock edge of SCK

before the beginning of a transmission
and the time that CE remains effective
tio lic
relative to the last clock edge of SCK

after the end of transmission. This time
ca ub
is calculated as t = tsck * (CET + 1)

13:12 smp_en_dly R/W Receive Sampling Delay Option. Delay 0x0
ifi p
the sample cycle (in IP working clock)

od de
after the rising edge of SCK for

sampling.
M a
15:14 rx_pipe_ctrl R/W Receiving sampling clock edge options. 0x0

M
0: Normal sampling
1: Sampling at the negative edge of SCK
for high-speed transmission
31:16 Reserved
DMMR_CTRL
0 dmmr_mode R/W When the bit is 1, the read address on 0x1
AHB will be directly mapped to SPI flash,
and the controller will automatically
302
CV1835

read data from the corresponding
address of SPI flash
SPI flash can be used as Rom. when

dmmr is 1, register in IP can be written
but not read.
31:1 Reserved
TRAN_CSR
ed
w
lo
1:0 tran_mode R/W Transfer Mode 0x0
al
00: No Tx, No Rx
01: Rx only
t
10: Tx only
no
11: Tx and Rx
TranMode indicates the sending and
receiving mode of transmission data
e
ar
except command and address
2 Reserved n
3 fast_mode R/W FastMode: 0x0
tio
0: Normal Mode
1: Fast Mode
5:4 bus_width R/W Bus Width 0x0
u
00: 1 bit bus

ib
01: 2 bit bus

r
di V
10: 4 bit bus

st
re k-
11: Reserved
6 dma_en R/W 0: DMA Disable 0x0
d il
1: DMA Enable
an M
When tranmode is 11 (sending and

receiving simultaneously), DMA
n by
transmission is not supported

7 miso_cked R/W Level value of miso_i pin 0x0
tio lic
10:8 addr_bn R/W Address Byte Number represents the 0x3

number of bytes of the current flash
ca ub
transfer address field, and 0 represents

no address field.
ifi p
11 with_cmd R/W With Command 0x1

0: Current transmission without
od de
command
1: Current transmission with command
M a
M
13:12 ff_trg_lvl R/W FFTrgLvl controls under what conditions 0x3

FIFO generates interrupts and DMA
requests.
00：1 Byte
01：2 Bytes
10：4 Bytes
11：8 Bytes
For transmit, when the number of free
bytes in FIFO is greater than or equal to
the number of bytes defined by fftrglvl,
interrupt and DMA request are
generated;
303
CV1835
For receive, interrupt and DMA request

are generated when the number of
effective bytes in FIFO is greater than or
equal to the number of bytes defined by
FFtrglvl.
14 Reserved
15 go_busy R/W Writing 0 to this bit doesn't work. 0x0
Writing 1 to this position 1 will start a
ed
transmission. After the transmission,
this bit will be cleared automatically.
w
Before initiating a new transmission, the
lo
software should query the register, and
only when the register is 0 can a new
al
transmission be initiated.
19:16 dummy_cyc R/W dummy cycle count 0x0
t
no
20 byte4en R/W 4 bytes address cycle enable in 0x0
dmmr_mode
21 byte4cmd R/W 4 bytes address cmd enable in 0x0
e
dmmr_mode
ar
31:22 Reserved n
tio
TRAN_NUM
u

ib
15:0 rdat_tran_num R/W When not under dmmr_mode, 0x0

r
di V
TRAN_NUM is the number of frames

st
re k-
sent and received in a transmission

31:16 Reserved
d il
an M
FF_PORT
n by

tio lic
31:0 rdat_ff_port R/W FIFO write read address 0x0

ca ub
FF_PT
ifi p

od de

3:0 rdat_ff_pt R/W Read as the number of effective data 0x0
M a
bytes in FIFO, write as FIFO clear

M
7:4 Reserved
9:8 wrcnt R/W Current FIFO, write byte offset indicator 0x0
status
12:10 rdpt R/W Current FIFO, read byte offset indicator 0x0
status
31:13 Reserved
INT_STS
304
CV1835

0 tran_done_int R/W The interrupt is generated once every 0x0
successful transmission of a frame of
data
1 Reserved
2 rdff_int R/W The interrupt is generated once for each 0x0
successful received frame.
3 wrff_int R/W After receiving the interrupt, CPU writes 0x0
frame data to FIFO.
4 rx_frame_int R/W The CPU reads frame data from FIFO 0x0
ed
after receiving the interrupt .
5 tx_frame_int R/W This interrupt marks the completion of a 0x0
w
transmission.
lo
31:6 Reserved
al
INT_EN
t
no
e
0 tran_done_int_en R/W Enable interrupt tran_done_int 0x0
ar
1 Reserved
2 rdff_int_en R/W Enable interrupt rdff_int 0x0
n
3 wrff_int_en R/W Enable interrupt wrff_int 0x0
tio
4 rx_frame_int_en R/W Enable interrupt rx_frame_int 0x0

5 tx_frame_int_en R/W Enable interrupt tx_frame_int 0x0
u
31:6 Reserved
r ib
di V
st
re k-
4.3 SPI NAND Flash Controller

d il
an M
n by
4.3.1 Overview
tio lic
Support external SPI NAND flash data access.

ca ub
ifi p
od de
M a
One chip selection pin.

M
Support SPI NAND Flash X1 / x2 / X4 read / write operation.

Support multiple specifications of SPI NAND flash device.
2KB and 4KB page size.
64 pages/block and 128 pages/block devices.
Support the BOOT function of SPI NAND.
305
CV1835
4.3.3.1 Interface Description
SPI NAND flash controller supports three SPI NAND interface types, Standard SPI, X2
interface mode and X4 interface mode.
ed
w
Standard SPI Interface Mode:
lo
Standard SPI interface mode has 1 bit data input and 1 bit data output. Write operation
al
timing sequence of standard SPI interface mode is shown in Figure 4- 8 Standard SPI
t
no
Write Operation Timing
. Read operation timing sequence of standard SPI interface mode is shown in Figure
e
4- 9 Standard SPI Read Operation Timing
ar
n
tio
mode.
u
ib
 Data is inptut from DI in single bit serial mode.

r
di V
st
.
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 4- 8 Standard SPI Write Operation Timing
 command/address/dummy cycles are output on DO in single bit serial mode.
 Data is output on DO in single bit serial mode.
306
CV1835
ed
w
lo
Figure 4- 9 Standard SPI Read Operation Timing
al
t
no
e
mode.
ar
 Data is inptut from DI in single bit serial mode.
n
tio
X2 Interface Mode:
u
Data input and output use two common I/O pins in X2 interface mode. The operation
r ib
timing sequence is shown in Figure 4- 10.

di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
Figure 4- 10 SPI Nand x2 Interface Mode Operation Sequence

M
 Data output (write) or input (read) on DO / DI line in 2 bits mode.
X4 Interface Mode:
Data input and output use four common I/O pins in X4 interface mode. The operation
timing sequence is shown in Figure 4- 11.
307
CV1835
ed
w
lo
al
t
no
Figure 4- 11 SPI Nand x4 Interface Mode Operation Sequence
e
ar
Sequence description： n
tio
 Data output (write) or input (read) on DO / DI / WPN / HOLDN in 4 bits mode.

u
r ib
di V
st
re k-
4.3.3.2 SPI NAND FLASH Address Description

d il
an M
When issuing the read-write operation of SPI NAND flash, the column address is issued
n by
according to the specific operation.

tio lic
Write operation: configure column address in PROGRAM LOAD operation

ca ub
and row address in PROGRAM EXCUTE operation.

ifi p
Read operation: configure row address in PAGE READ TO CACHE operation

od de
and column address in PAGE READ operation.

M a
The address distribution is completed by the controller. The software needs

M
to configure reg_ trx_ cmd_ idx according to the operation instructions, and
address configures reg_ trx_ cmd_ cnt0 and reg_ trx_ cmd_ cnt1.
4.3.3.3 Boot Function
Because the SPI NAND flash address space is discontinuous and there is the possibility
of bad blocks, boot data can not be directly mapped to flash.
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CV1835
It supports adaptive boot function, and can automatically update the adapter
information according to the data of block0. For controller boot operation requirement
that physical Block0 must be a good block, and other blocks can be automatically
skipped if they are bad blocks.
4.3.3.4 Register Opreation
ed
The software configures the operation related register, such as operation command,
w
address, etc., and set reg_ trx_start register to issue the operation. The controller sends
lo
al
the operation to the device according to the software configuration value. If there are
data content to transfer to the device, the internal DMA will be used.
t
no
e
ar
4.3.3.5 Built-in DMA Operation Method
n
Support built-in system DMA mode to improve read/write operations speed. In this way,
tio
access internal or external memory space by dma bus directly.

u
ib
Step 1. Configure DMA channel.

r
Step 2. Configure the source and destination address.

di V
st
re k-
Step 3. Configure the transmission format and data length.

d il
an M
n by
4.3.3.6 TIMEOUT Function

tio lic
The maximum one second timeout could be set by software. The timout mechanism
ca ub
used to protect system if device does not respond normally.

ifi p
od de
4.3.4 Operation Flow

M a
M
4.3.4.1 Initialization Process
Step 1. (if the timing parameter needs to be adjusted) Based on device timing to
configure time sequence register reg_trx_sck_h and reg_ trx_ sck_ l.
Step 2. Configure the interrupt control register reg_ trx_ done_ int_ en.
309
CV1835
4.3.4.2 Device Register Operation Process
Step 1. Configure the transmission content length reg_ trx_ cmd_ cont_ size and reg_
trx_ data_ size.
Step 2. Configure the device instruction and its related contents reg_ trx_ cmd_ id, reg_
trx_ cmd_ cont0 and reg_ trx_ cmd_ cont1.
ed
Step 3. Set reg_ trx_ start register to issue operation.
w
Step 4. When reg _ trx_ done_ int is asserted, it indicates that the operation is
lo
completed.
al
t
no
4.3.4.3 Erase Operation Process
e
ar
Flash must be erased before programming, and WREN should be set before erase
operation.
n
tio
Step 1. Configure the transmission content length reg_ trx_ cmd_ cont_ size.
Step 2. Configure the device instruction and its related contents reg_ trx_ cmd_ id and
u
ib
reg_ trx_ cmd_ cont0.

r
di V
st

re k-
Step 4. When reg _ trx_ done_ int is asserted , it indicates that the operation is
d il
an M
completed.
n by
4.3.4.4 Built-in DMA Read Operation Process

tio lic
Step 1. Configure the system DMA register, and refer to 错误!未找到引用源。.

ca ub
ifi p
trx_ data_ size.

od de
M a
M

Step 4. Configure reg_ trx_ start register to issue operation.
Step 5. . When reg _ trx_ done_ int is asserted, it indicates that the operation is
completed and data is written to memory buffer.
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4.3.4.5 Built-in DMA Write Operation Process
Step 1. Configure the system dmaregister, and refer to 错误!未找到引用源。.

trx_ data_ size.
ed
w
lo
Step 5. When reg _ trx_ done_ int is asserted, the buffer content has been written to the
al
device cache.
t
no
4.3.4.6 Other Reminders
e
ar
RESET command is required before normal access or after abnormal reset in some
n
tio
SPI NAND device. Therefore, for better device compatibility, the first transmission
instruction after device power up or abnormal reset should be RESET command.
u
ib
Before the device operation is completed, do not change the relevant register
r
di V
st
configuration, otherwise the operation may be abnormal.

re k-
d il
an M
4.3.5 Data Structure (NAND Flash/SPI NAND Flash)

n by
tio lic
4.3.5.1 2KB page_size

ca ub
ifi p
For common 2KB page_size device, the available spare area for software is 64 Bytes. The
od de
actual size of the spare area is depended on the device page structure. Data structure of
M a
buffer and flash page is shown as follow.

M
User Data Data(2048) OOB(64)
4.3.5.2 4KB page_size
For common 4KB page_size device, the available spare area for software is 256 Bytes.
The actual size of the spare area is depended on the device page structure. Data
structure of buffer and flash page is shown as follow.
User Data Data(4096) OOB(256)
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4.3.6 Register Overview

Offset
reg_ctrl 0x000 transmission control
reg_timing_ctrl 0x004 timing control
ed
reg_trx_size 0x008 number of content size
reg_int_en 0x010 interrupt enable
w
reg_int_clr 0x014 interrupt clear
lo
reg_int_sts 0x01c interrupt status
reg_cont0
al
0x030 content 0
reg_cont1 0x034 content 1
t
reg_cmplt_cnt 0x058 number of transferred bytes
no
reg_tx_data 0x060 tx data
reg_rx_data 0x064 rx data
e
ar
4.3.7 Register description n
u tio
reg_ctrl
r ib

di V
st
re k-

0 reg_trx_start W1T trigger spi transmission start
d il
an M
31:1 Reserved
n by
reg_timing_ctrl
tio lic

ca ub
1:0 reg_trx_time_start R/W time for cs assert to 1st command bit 0x0
unit: sck period
ifi p
3:2 Reserved
7:4 reg_trx_time_end R/W time for last data bit to cs de-assert 0x0
od de
unit: sck period

M a
15:8 Reserved
M
19:16 reg_trx_sck_h R/W time for sck high 0x0

unit: source clock period
23:20 reg_trx_sck_l R/W time for sck low 0x1
unit: source clock period
31:24 Reserved
reg_trx_size
2:0 reg_trx_cmd_cont_size R/W numbers of command content byte 0x0
3 Reserved
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5:4 reg_trx_dummy_size R/W numbers of dummy byte 0x0
15:6 Reserved
28:16 reg_trx_data_size R/W numbers of data byte 0x0
31:29 Reserved
reg_int_en
ed
0 reg_trx_done_int_en R/W trx_done interrupt enable 0x1
w
31:1 Reserved
lo
al
reg_int_clr
t
no
0 reg_trx_done_int_clr W1T trx_done interrupt clear
e
31:1 Reserved
reg_int_sts
ar
n
tio
u
0 reg_trx_done_int RO trx_done interrpt

ib
31:1 Reserved
r
di V
st
re k-
reg_cont0
d il

an M

7:0 reg_trx_cmd_idx R/W spi flash command value 0x0
n by
31:8 reg_trx_cmd_cont0 R/W spi flash address, or other contents 0x0

tio lic
reg_cont1
ca ub

ifi p
31:0 reg_trx_cmd_cont1 R/W spi flash address, or other contents 0x0

od de
reg_cmplt_cnt
M a
M

12:0 reg_cmplt_cnt RO number of transferred bytes
31:13 Reserved
reg_tx_data
31:0 reg_tx_data RO spi tx data
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reg_rx_data
31:0 reg_rx_data RO spi rx data
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
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Network interface
5.1 Ethernet MAC
ed
5.1.1 Overview
w
lo
The core chip supports two Ethernet Macs to receive and transmit network data.
al
An Ethernet MAC with built-in 10 / 100Mbps Fast Ethernet transmitter can work in 10 /
t
no
100Mbps full duplex or half duplex mode..
.
e
5.1.2 Function description ar
n
tio
The Ethernet module has the following features:

u
r ib
1. Ethernet MAC0 is paired with a built-in 10/100Mbps Fast Ethernet Transceiver

di V
st
re k-
and a built-in Ethernet PHY to support 10/100Mbit/s rates.

d il
an M
2. Supports full-duplex or half-duplex operation modes.

• Supports CRC verification of input frames.
n by
• Supports adding CRC verification to output frames.

tio lic
• Supports short frame padding.

ca ub
• Supports internal loopback in full-duplex mode.

ifi p
• Supports counting of received and transmitted frames.

od de
• Supports receive and transmit packet buffer.

M a
• Supports COE (Checksum Offload Engine) checksum offload engine functionality.

M
5.1.3 Data flow overview
The conceptual data stream of Ethernet switching interface is shown in Figure 51.
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ed
w
Chart 5- 1 GMAC conceptual data stream
lo
al
t
5.1.4 Single port function configuration description
no
e
ar
5.1.5 Ethernet transceiver frame management function n
tio
CPU first configures Ethernet MAC receive and transmit descriptor list buffer and
content composition of descriptor list, for example, setting of frame address and packet
u
ib
type size parameters

r
di V
st
During receiving, Ethernet MAC receives all kinds of packets, and according to the CPU
re k-
configuration, it receives descriptor list messages, such as packet cache information,

d il
an M
including packet cache starting address, packet cache depth, etc., and stores the
n by
received packets in DDR. And then inform the CPU to do the follow-up processing.
During transmitting, according to the packet cache information of sending descriptor
tio lic
list configured by CPU, such as packet cache starting address, packet length and other
ca ub
packet information, Ethernet MAC carries the packets stored in DDR, assembles them
ifi p
into packets, and then sends them to the network interface. Then inform the CPU that
od de
the packet has been sent.

M a
M
5.1.6 Ethernet packet receiving interrupt management function
5.1.6.1.1 Interrupt generation
Set the receive direction interrupt and configure Re_Int_Enable bit[6] = 1, CPU queries receive
interrupt status Reg_Int_Status bit[6].
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5.1.6.1.2 Interrupt clearing
CPU query receive interrupt status Reg_Int_Status bit[6], write 1 to clear the interrupt status.
5.1.7 Configure the working state of PHY chip
ed
Ethernet MAC provides MDIO interface to config PHY chip. MDIO interface is divided
w
into read operation and write operation. The main register controlling MDIO interface is
lo
Reg_MdioAddr and Reg_MdioData.
al
The configuration steps of read operation are as follows：
t
no
Configure the MDIO control register with the following settings:
Reg_MdioAddr bit [15:11] config the PHY chip address. Please config based on plan
e
ar
according to PHY chip or version n
Reg_MdioAddr bit [10:6] sets the PHY internal register address to read and write.
tio
Reg_MdioAddr bit [1] writes 0 (read action command).

u
Finally, Set Reg_MdioAddr bit [0] = 1 to start reading.

ib
The MDIO interface will receive the read back data to Reg_MdioData bit [15:0], and
r
di V
st
change Reg_MdioData to 0.
re k-
d il
an M
The configuration steps of write operation are as follows：

n by
Configure the MDIO control register with the following settings:

Reg_MdioData bit [15:11] sets the PHY chip address of clause45 mode
tio lic
Reg_MdioData bit [10:6] sets the value written to PHY chip

ca ub
Reg_MdioAddr bit [1] writes 1 (write action command).

ifi p
Finally, Set Reg_MdioAddr bit [0] = 1 to start writing:

od de
The MDIO interface will Reg_Mdi0Addr bit [0] will change to 0 after writing.
M a
M
5.1.8 Working mode switching
Working mode of Ethernet MAC：

Ethernet MAC0 supports the use of built-in ephy function. Its working mode is
RMII (10 / 100M)
The speed and mode switch register is set as follows:
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Configure ETH0 Reg_MacConfig bit[14] = (100M:1, 10M:0)；
Note: this configuration is not allowed when the chip is working normally. It is
recommended to configure it during initialization.
ed
5.1.9 Typical applications
w
lo
5.1.10 Register offset address description
al
t
Ethernet MAC 0/1 Register offset address space:
no
ETH0_MAC : 0x0451_000~0x0451_FFFF
e
ar
n
5.1.11 GMAC register overview
u tio
Table 5- 1 GMAC register overview

r ib
di V
st

re k-
Offset
d il
an M
Reg_MacConfig 0x000 Native MAC operational status register

Reg_MdioAddr 0x010 MDIO operation register
n by
Reg_MdioData 0x014 MDIO data read/write register

Reg_MacAddr0_High 0x040 Native MAC address register #0 high 16 bits
tio lic
Reg_MacAddr0_Low 0x044 Native MAC address register #0 low 32 bits

ca ub
Reg_MacAddr1_High 0x048 Native MAC address register #1 high 16 bits

ifi p
Reg_MacAddr1_Low 0x04c Native MAC address register #1 low 32 bits

od de
Reg_Tx_Packet_Num_Good_Ba 0x118 Transmit good frame and bad frame count

d register
M a
M
Reg_Tx_Bcast_Packets_Good 0x11c Transmit good broadcast frame count register

Reg_Tx_Mcast_Packets_Good 0x120 Transmit good multicast frame count register
Reg_Tx_Ucast_Packets_Good_ 0x13c Transmit good unicast frame and bad frame count
Bad register
Reg_Tx_Mcast_Packets_Good_ 0x140 Transmit good multicast frame and bad frame
Bad count register
Reg_Tx_Bcast_Packets_Good_ 0x144 Transmit good broadcast frame and bad frame
Bad count register
Reg_Rx_Packets_Num_Good_B 0x180 Receive good frame and bad frame count register
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Offset
ad
Reg_Rx_Bcast_Packets_Good 0x18c Receiver successful good broadcast frames count
register
Reg_Rx_Mcast_Packets_Good 0x190 Receiver successful good multicast frames count
register
ed
Reg_Rx_CRC_Error_Packets 0x194 Receiver CRC error frames count register
w
Reg_Rx_Ucast_Packets_Good 0x1c4 Receiver successful good unicast frames count
lo
register
al
Reg_Int_Enable 0x101c Interrupt enable register
Reg_Int_Status 0x1014 Interrupt status register
t
no
e
5.1.12 GMAC register description
ar
n
tio
Reg_MacConfig
u

ib
1:0 Reserved
r
di V
st
2 RX_EN R/W MAC Receive Enable RegisterMAC 0x0

re k-
3 TX_EN R/W MAC Transmit Enable RegisterMAC 0x0

d il
6:4 Reserved
an M
7 APCS_EN R/W Automatic Pad or CRC Stripping Control 0x0

Enable Register
n by
9:8 Reserved
10 CHKS_EN R/W IP Checksum Offload Enable Register 0x0
tio lic
11 DUPLEX_MODE R/W Full/Half Duplex Mode Register, 1 0x0

(Enables Full Duplex Mode)
ca ub
12 LPBK_MODE R/W Loopback Mode Control Register 0x0

13 Reserved
ifi p
14 SPEED_MODE R/W Speed Mode Register 0x0

od de
1'b1: 100M, 1'b0: 10M

16:15 Reserved
M a
M
19:17 IPG_VAL R/W Transmit Packet Spacing Control 0x0

Register
22:20 Reserved
23 WD_DISABLE R/W Watchdog Disable Register 0x0
24 Reserved
25 CRC_STRIP_EN R/W CRC Stripping Type Packet Control 0x0
Enable Register
31:26 Reserved
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CV1835
Reg_MdioAddr
0 GO R/W MDIO operation completion indication 0x0
1: Start operation 0: operation
completed
1 CMD R/W MDIO operation command type 0x0
Write (1'b1), Read (1'b0)
5:2 Reserved
ed
10:6 RegAddr R/W External PHY address configuration 0x0
register
w
15:11 PhyAddr R/W PHY device internal register address 0x0
lo
register
al
31:16 Reserved
t
Reg_MdioData
no
e
ar
15:0 MdioData R/W MDIO writes or reads back the data 0x0
register from PHY
n
31:16 RegAddrC45 R/W 0x0
tio
Reg_MacAddr0_High
u
ib

r

di V
st
15:0 Addr_High R/W MAC address register #0 bit[47:32] 0x0

re k-
30:16 Reserved
d il
31 AddrEN R/W Address Enable 0x0

an M
Reg_MacAddr0_Low
n by

tio lic

31:0 Addr_Low R/W MAC address register #0 bit[31:0] 0x0
ca ub
ifi p
od de
Reg_MacAddr1_High
M a
M

15:0 Addr1_High R/W MAC address register #1 bit[47:32] 0x0
23:16 Reserved
29:24 Addr1_MASK R/W Addr1 Mask Byte 0x0
30 Addr1_TYPE R/W 1'b1: compare SA 0x0
1'b0: compare DA
31 Addr1_EN R/W Addr1 Enable 0x0
Reg_MacAddr1_Low
31:0 Addr1_Low R/W MAC address register #1 bit[31:0] 0x0
320
CV1835
Reg_Tx_Byte_Num_Good_Bad
31:0 TxByteNumGB RO Successfully sent good packet and bad
packet byte count register
ed
Reg_Tx_Bcast_Packets_Good
w
lo
31:0 TxBcG RO Successfully sent broadcast frame count
al
register of good packets
t
no
Reg_Tx_Mcast_Packets_Good
e
ar
31:0 TxMcG RO Successfully sent multicast frame count
register of good packets
n
tio
Reg_Tx_Ucast_Packets_Good_Bad
u

ib

r
di V
31:0 TxUcGB RO Successfully sent unicast frame count

st
re k-
register of good packets and wrong

packets
d il
an M
Reg_Tx_Mcast_Packets_Good_Bad
n by

tio lic
31:0 TxMcGB RO Successfully sent multicast frame count

register for good packets and bad
ca ub
packets.
ifi p
Reg_Tx_Bcast_Packets_Good_Bad
od de

M a

M
31:0 TxBcGB RO Successfully sent statistics register of

the number of broadcast frames of
good packets and wrong packets
Reg_Rx_Packets_Num_Good_Bad
31:0 RxPktGB RO Successfullly received statistics register
of frame number of good packets and
wrong packets.
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Reg_Rx_Bcast_Packets_Good
31:0 RxBcG RO Receive successful good packet
broadcast frame count register.
Reg_Rx_Mcast_Packets_Good
ed
w
31:0 RxMcG RO Received good packets' multicast frame
lo
count statistics register.
al
Reg_Rx_CRC_Error_Packets
t
no
31:0 RxCrcERR RO Receiver CRC error frame count register.
e
ar
Reg_Rx_Ucast_Packets_Good
n
tio
31:0 RxUcG RO Counter register for the number of

successfully received unicast frames.
u
ib
Reg_Int_Enable
r

di V
st
re k-

0 TxInt_EN0 R/W Send interrupt enable register 0x0
d il
5:1 Reserved
an M
6 RxInt_EN0 R/W Receive interrupt enable register 0x0

n by
31:7 Reserved
Reg_Int_Status
tio lic

ca ub

0 TxInt_ST0 RO Send interrupt state register
ifi p
5:1 Reserved
od de
6 RxInt_ST0 RO Receive interrupt state register

M a
31:7 Reserved
M
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CV1835
5.2 Ethernet PHY
5.2.1 Overview
The chip provides a set of built-in Ethernet 10/100 Base-TX compliant PHY interfaces.
ed
w
lo
Support IEEE 802.3 10/100 Base-TX compliant.
al
Support full duplex and half duplex and auto-negotiation function.
t
no
Support Auto-MDIX function to auto detect crossover cable or straight-through
cable and flip the TX and RX accordingly.
e
ar
Support WOL (Wake on LAN) over Ethernet.
n
tio
5.2.3 Functional block diagram

u
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
Chart 5- 2 built-in 10/100 Ethernet PHY chart

ifi p
The 10 / 100Mbps transmission and receiving is on the standard category 5(CAT5)

od de
twisted pair table. The transmission and receiving signals are connected to the RJ45
M a
M
standard interface through a transformer.
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Video and image codec
6.1 Overalll overview
ed
The video and image codec hardware unit integrates video codec unit (VCU)
w
and JPEG codec unit (JCU). VCU supports H.265/HEVC, H.264/AVC
lo
international standards, while JCU supports JPEG and Motion-JPEG. VCU/JPU
al
provides real-time, high performance, low delay, low power consumption,
t
no
small bus bandwidth and CPU utilization.
e
6.2 VCU (Video Codec Unit)
ar
n
u tio
6.2.1 Overview
r ib
di V
st
VCU (Video Codec Unit) includes two functions: video encoding (VENC) and
re k-
d il
video decoding (VDEC). With software control, it can encode and decode
an M
simultaneously according to application requirements.

n by
6.2.2 Features
tio lic
ca ub
VENC module supports the following features:

ifi p
Support ITU-T H.265/HEVC Main Profile @Level 4 Main Tier coding

od de
Support I and P frames

M a
Support 1/2、1/4 pixel precision motion compensation

M
Support CTU 64 coding unit

Inter prediction supports 32x32, 16X16, 8x8 and other PU types
Inter prediction supports Merge/Skip mode
Intra prediction supports 32x32, 16X16, 8x8 and other PU types
Support TU types such as 32x32, 16X16, 8x8 and 4X4
Support CABAC entropy coding
Support De-blocking filter
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Support QPMap
Support H.265 HSVC time domain layering (HSVC-T)
Support ITU-T H.264/AVC High Profile/Main Profile/Constrained
Baseline Profile@Level 4.2 coding
Support I and P frames
Support 1/2、1/4 pixel precision motion compensation
ed
Inter frame prediction supports PU types such as 16x16, 16x8, 8x16
w
and 8x8
lo
Intra prediction supports 16x16, 8x8, 4x4 and other PU types
al
Support TU types such as 8x8 and 4X4
t
no
Support CABAC、CAVLC entropy coding
Support De-blocking filter
e
ar
Support QPMap
Support H.264 SVC time domain layering (SVC-T)
n
tio
The following input image formats are supported

Planar YCbCr4:2:0
u
ib
H.265/H.264 multi-stream encoding performance：

r
di V
st
2880x1620@20ps+720x576@20ps encoding
re k-
It supports configurable image resolution

d il
an M
Minimum image resolution：256x256

n by
Maximum image resolution：2880x1620

Support Region Of Interest coding (ROI)
tio lic
Region of interest coding for up to 8 regions is supported

ca ub
Support CBR/VBR/FIXQP/QPMAP rate control mode

ifi p
Support slice output interrupt

od de
Output code rate H.265 up to 25Mbps

M a
Output bit rate H.264 up to 50Mbps

M
325
CV1835
ed
w
lo
al
t
no
e
ar
n
Figure 6- 1 VENC function block diagram
u tio
ib
The functional block diagram of VENC is shown in Figure 6-1. The function of
r
di V
st
VENC module is divided into two groups: V-CPU and V-CORE. The main V-CORE
re k-
group implements motion estimation (ME) / Inter-prediction, Intra-prediction,

d il
an M
Transform / Quantizer, Inv-Quant/Inv-Transform, Mode Decision, Motion

n by
Compensation, entropy coding and stream generation, deblocking filtering and

SAO (only supporting h.265) And so on. The V-CPU group is mainly built with a
tio lic
MCU (micro control unit) and its required on-chip memory, which receives
ca ub
commands from the upper ARM software and controls the generation of
ifi p
bitstream in V-CORE. ARM CPU software completes coding control processing

od de
such as rate control and interrupt processing.

M a
M
As shown in the figure, before starting VENC for video encoding, CPU software
needs to allocate the following three types of buffers in external SDRAM.
Picture Input buffer
Before encoding, the original image to be encoded is usually written into
the buffer by the video input unit or the video processing unit. During the
encoding process, VENC will read the image from this image input buffer
and start encoding.
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CV1835
Reference/Reconstruction Picture buffer

In the process of encoding, VENC will write the reconstructed image to
this buffer as the reference image of the original image to be encoded.
When P-frame encoding, the reference image will be read from this
buffer and compared with the original image to construct the best
motion vector.
ed
Bitstream Output buffer
w
During the encoding process, VENC will write the encoded bistream to
lo
this buffer. This buffer is usually read by the software and packaged in the
al
next stage
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
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CV1835
6.3 JCU (JPEG Codec Unit)
6.3.1 Overview
JCU (JPEG Codec Unit) contains JPEG image or Motion-JPEG video encoding
ed
(JPE) and decoding (JPD) two major functions. As same as VCU, through
w
lo
software control, according to the application requirements, JPU can
al
simultaneously do encoding and decoding.
t
no
6.3.2 Features
e
JPE module supports the following features: ar
n
tio
Support ISO/IEC 10918-1 Baseline Profile JPEG coding

u
− Support image coding with YCbCr4:0:0, YCbCr4:2:0, YCbCr4:2:2,

ib
YCbCr4:4:4 chroma sampling format

r
di V
st
− Support up to 3 quantization tables

re k-
Support 8-bit sampling accuracy.

d il
−
an M
Encoding performance
n by
− minimum image resolution : 16x16

− maximum image resolution : 2880x1620
tio lic
− Motion-JPEG encoding up to 5M(2880x1620, YCbCr4:2:0)@20fps

ca ub
− Motion-JPEG output rate range：20Kbps～200Mbps

ifi p
od de
JPD module supports the following features:

M a
M
Support ISO/IEC 10918-1 Baseline Profile JPEG decoding：

− Support image decoding of YCbCr4:0:0, YCbCr4:2:0, YCbCr4:2:2,
YCbCr4:4:4 chroma sampling formats
− Support up to 3 quantization tables
− Support 8-bit sampling accuracy
Decoding performance
− minimum image resolution：16x16
− maximum image resolution：2880x1620
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CV1835
− Motion-JPEG decoding up to 5M(2880x1620, YCbCr4:2:0)@20fps
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
Figure 6- 2 JPE function block diagram

re k-
d il
an M
The functional block diagram of JPE is shown in Figure 6-2. JPE hardware
n by
implements the processing of image input DMA, level shift, DCT (Discrete
tio lic
Cosine Transform), Quantization, Reorder, VLC coding and bitstream output

ca ub
DMA, while CPU software completes the coding control processing of

quantization table configuration and interrupt processing.
ifi p
od de
As shown in the figure, before starting JPE for encoding, CPU software needs
M a
M
to allocate the following two types of buffers in external SDRAM：

Picture Input buffer
Before encoding, the original image to be encoded is usually written into
the buffer by the video input unit or the video processing unit. During the
encoding process, JPE will read the image from this image input buffer,
and then start encoding.
Bitstream output buffer
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CV1835
During the encoding process, JPE will write the encoded bitstream to
this buffer. This buffer is usually read by the software and packaged in
the next stage.
。
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
330
CV1835
ed
w
lo
al
t
no
e
ar
n
tio
Figure 6- 3 JPD function block diagram

u
r ib
di V
st
re k-
As shown in the figure, JPD function block diagram is shown in Figure 6-3.
d il
JPD hardware implements the processing with large amount of computation,

an M
such as bitstream input DMA, VLD decoding, Reorder, Inverse Quantization,

n by
IDCT, post processor, level shift and image output DMA, while ARM CPU
software completes decoding control processing, such as package header
tio lic
decoding and interrupt processing.

ca ub
ifi p
As shown in the figure, before starting JPD for decoding, the ARM CPU
od de
software needs to allocate the following two types of buffers in the External
M a
M
SDRAM：
Bitstream input buffer
Usually, the bitstream to be decoded is written into this buffer by
software before decoding, and then read by JPD during decoding.
Picture output buffer
JPD will write the decoded image into this buffer during decoding.
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CV1835
Video and graphics processing
7.1 VPSS (sc_top)
ed
7.1.1 Overview
w
lo
The Video Processing Subsystem (VPSS) implements video processing functions and
al
supports both online modes (ISP-VPSS online and ISP-VPSS-VC fully online) and offline
t
no
modes. It includes video masking, privacy masking, video cropping, scaling, mirror, flip,
180-degree rotation, LBA amplitude ratio conversion, circular masking, OSD overlay,
e
ar
and multi-area stitching. n
tio

u
ib
The characteristics of VPSs are as follows:

r
When the output width is less than 2880, the video source with maximum input
di V
st
re k-
width of 4096 is supported

d il
an M
Support video source with maximum input width of 2880 when the output width
is above 2880
n by
Support up to 3 channels of video output

tio lic
3-channel video output can be configured independently

ca ub
The input data is 420/422/single component/RGB planer/ Packet

ifi p
RGB/NV12/NV21/422-packet/420 semi-planar
od de
The output data is 420/422/ component /RGB planer/ Packet RGB/

M a
NV12/NV21/422-packet/420 semi-planar/HSV/BF16
M
Support video clipping

Support mirror / flip / 180 degree rotation
Support low delay mode of output channel
LBA format ratio conversion: adjust the image format ratio by adding a fixed
background color border to the upper and lower edges or left and right edges of
the image
Support circular occlusion function
332
CV1835
Supports OSD and video overlay in 8 regions, and uses this feature to achieve
video masking.
Provides privacy masking function (pixel-based, grid 8x8, RGB332 format).
OSD input format: ARGB8888/ARGB4444/ARGB1555/8-bit LUT/4-bit LUT/bit-
font.
OSD font supports color inversion with background brightness.
ed
Supports OSD compression/decompression to save memory space.
w
Scaling factor supports 1/32-32 times.
lo
al
7.2 LDC (Lens Distortion Correction)
t
no
7.2.1 Overview
e
ar
Lens Distortion Correction (LDC) corrects lens distortion and rotates (90/270) a frame of
n
tio
image. It mainly consists of two functions: geometric distortion correction and affine
transformation.
u
r ib

di V
st
re k-
d il
 LDC features are as follows:

an M
 Lens Distortion Correction

n by
• Supports video sources with a maximum input width of 4096 and a

tio lic
maximum output width of 4096.

ca ub
• Supports output to Dynamic Random-Access Memory (DRAM).

ifi p
• When outputting to DRAM, supports NV12/NV21 and 8-bit input/output.

od de
• When outputting to DRAM, supports single Y 1-plane and 8-bit

M a
input/output.
M
• Supports 90/270-degree rotation.

• Supports correction of barrel and pincushion distortion.
 Supports up to 20% correction of barrel distortion.
 Supports up to 20% correction of pincushion distortion.
 Supports barrel expansion function.
• Maximum output performance of 240 megapixels per second.
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CV1835
 Affine Transformation
• Supports video sources with a maximum input width of 4096 and a maximum
output width of 4096.
• Affine transformation only supports output to DRAM.
• Supports single Y-plane, N21/NV12, and 8-bit input/output.
• Maximum output performance of 240 megapixels per second.
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
334
CV1835
AI engine
8.1 TPU (Tensor Processing Unit)
ed
w
lo
8.1.1 Overview
al
t
TPU is an AI acceleration engine for deep learning neural network, which can be used to
no
accelerate image classification, object detection, face detection and recognition,
e
segmenataion, and LSTM, etc.. Figure 8-1 shows the block diagram between TPU and
ar
CPU on the chip. The main function of TPU is to offload CPU work and to accelerate
n
Computer Vision and Speech related operations. The two blocks communicate through
tio
interruption.
u
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 8- 1 TPU working mode diagram
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CV1835
The main features of TPU are as following:
ed
 Support a wide range of AI models, such as Resnet、Vgg16、GoogleNet、Yolo、
w
lo
MobileNet, LSTM etc.
al
 Support dynamic voltage and frequency scaling
t
 Support high-performance and low-power CNN convolution
no
 Support high-performance, low-power fully connected layer matrix
e
multiplication and addition
ar
 Support various activation functions (such as: ReLU、tanh、Sigmoid, etc.)
n
 Support Elementwise tensor operations (including AND、OR、XOR、ADD、SUB、
tio
MIN、MAX、SHIFT、MUL、MAC)
u
 Support pooling operation (AVG and MAX)

r ib
 Support strided copy

di V
st
re k-
 Support strided convolution

d il
 Support Zero-Padding and Zero-Insertion

an M
 support deconvolution and dilated convolution

n by
 support depthwise separable convolution

tio lic
 Support lossless compression

ca ub
 Support LUT function

ifi p
 Support Inverse Sqrt Root、Exponential、Sqrt Root、Division and other

od de
nonlinear operations
M a
 Support 8-bit and 16-bit operation modes

M
 Support image batch and tiling processing

 Support high-performance multi-dimensional tensor movement and transpose
 Support high performance matrix movement and transpose
 Support performance monitoring unit (PMU)
336
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
337
CV1835
Video interface
9.1 VI
ed
9.1.1 Overview
w
lo
Video input unit VI (Video Input) is a camera video data receiving camera module,
al
which can support receiving video data through MIPI Rx interface or BT.656, BT.601,
t
no
interface and DC (Digital Camera) signal, and then send it to the next level of image
processing module (ISP). The functional block diagram of VI is shown in Figure 9.1.
e
ar
VI is divided into two physical sub modules, which are MIPI RX and VI Proc. MIPI RX
module receives and processes different video data, while VI Proc module will integrate
n
tio
different video signals into a single video signal required by ISP module.
u
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 9- 1 VI function block diagram
MIPI Rx supports up to two sensor data inputs simultaneously.
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CV1835
• Single sensor supports linear input of up to 5M (2688x1944, 2880x1620) @

20fps.
• MIPI Rx input supports a maximum data width of 12 bits.
• Supports MIPI Rx multi-channel fusion input (1, 2, 4 channels).
• Supports BT.656, BT.601 (only supports progressive mode).
ed
DC interface
w
• Supports MIPI CSI-2 interface.
lo
• Supports YUV422 format input via MIPI interface.
al
t
no
9.1.3 Mode function description
e
9.1.3.1 Typical applications
ar
n
tio
VI can support a variety of timing input and different interfaces, and do video input
u
acquisition for different encoding methods. The system can use the register to
r ib
configure different function modes to adapt to different video interfaces.

di V
st
re k-
The VI module can support up to two input channels. The typical inputs are as follows:
d il
an M
• 1 channel 5M(2688x1944, 2880x1620) linear @20fps input

n by
9.1.3.2 BT.656 interface timing

tio lic
ca ub
VI also supports BT.656 interface timing of Y / C combined input. During transmission,

ifi p
SAV and EAV are also used to indicate the beginning and end of valid line data, but only
od de
8bit is used to transmit video signal, and brightness and chroma are transmitted in
M a
time-sharing mode, as shown in Figure 9-2

M
Figure 9- 2 BT.656horizontal interface timing
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CV1835
The difference between BT.656 and BT.1120 is only 16 bit (BT.1120) and 8 bit (BT.656) for
image transmission, and other vertical timing and synchronous code formats are the
same.
9.1.3.3 BT.601 interface timing
ed
In addition to using synchronization codes bt.1120 and BT.656, VI supports BT.601
w
interface timing using a variety of different synchronization signals. The actual video
lo
al
data can be set to 16bit mode of Y / C separate input or 8bit mode of Y / C combined
time-sharing input by register, while the synchronization mode can be set to vhs, vde or
t
no
vsde mode by register. The detailed sequence is shown in the figure below.
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
Figure 9- 3 BT.601 vhs Synchronization mode

ca ub
ifi p
The input synchronization signal of VHS mode is frame synchronization signal (VS) and
od de
line synchronization signal (HS). The system must set the number of hidden lines after
M a
M
frame (vs_back_porch), image height (img_ht), pixel number after line (hs_back_porch)
and image width (img_wd)
340
CV1835
Figure 9- 4 BT.601 vde Synchronization mode
ed
vde mode synchronization signals are frame valid signal (vde) and row valid signal (hde).
w
lo
In this mode, the system does not need to set the parameters related to time sequence
al
and phase sequence. VI module will receive data according to hde / vde signal to
t
update the frame according to vde signal.。
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
figure 9- 5 BT.601 vsde Synchronization mode

n by
The synchronization signals of vsde mode are frame synchronization signal (vs) and
tio lic
effective pixel flag (de). In this mode, the system does not need to set the parameters
ca ub
related to time sequence and phase sequence. The VI module will receive data
ifi p
according to the de signal to update the frame according to the vs signal.

od de
M a
M
Figure 9- 6 BT.601 Y/C separate 16bit mode
341
CV1835
Figure 9- 7 BT.601 Y/C merge 8bit mode
ed
w
lo
9.1.3.4 Digital camera (DC) interface timing
al
VI supports the transmission of RAW format analog BT digital camera (DC) interface
t
no
timing. In DC interface, it can support 8bit, 10bit, and 12bit three different modes. It can
also use register settings to receive video signals by using receive synchronization code
e
ar
or three different synchronization modes similar to BT.601
n
tio
Figure 9- 8 DC Synchronization code mode

u
r ib
di V
st
re k-
d il
an M
Figure 9- 2 DC Synchronous signal mode -vhs mode

n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 9- 10 DC Synchronous signal mode -VDE mode
342
CV1835
ed
Figure9- 11 DC Synchronous signal mode -VSDE mode
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
343
CV1835
9.1.4 Image storage mode
The images stored in DRAM are divided into Bayer 12bit and YCbCr 8 bit formats. Y / Cb
/ Cr is stored separately in three different DRAM positions. The arrangement of images
ed
in two formats (12bit / 8bit) in DRAM is shown in the figure below.
w
Figure 9-xx Bayer 12 bit Image storage mode
lo
al
t
no
e
ar
n
u tio
r ib
Figure 9-xx YCbCr 8bit Image storage mode

di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
9.1.5 VI register overview

M a
M
CV1835 chip has two sets of the same VI module, the internal register offset address is
the same, and the base address is 0x0A0C2000 and 0x0A0C4000。
Figure 9- 3 VI register overview

Offset
REG_00 0x000 MODE
REG_10 0x010 TTL_MODE_0
344
CV1835

Offset
REG_1C 0x01c TTL_MODE_3
REG_40 0x040 HDR_MODE_0
ed
w
REG_50 0x050 BLC_MODE
lo
REG_54 0x054 BLC_MODE_0
al
REG_58 0x058 BLC_MODE_1
REG_60 0x060 VI_PINMUX_0
t
no
REG_6C 0x06c VI_PINMUX_3
e
ar
REG_80 0x080 BT_PATH_0 n
REG_88 0x088 BT_PATH_2
tio
REG_8C 0x08c BT_PATH_3
u

ib

REG_9C 0x09c BT_PATH_7
r
di V
st
REG_A0 0x0a0 BT_PATH_8

re k-
REG_A4 0x0a4 BT_PATH_A

REG_B0 0x0b0 CROP_0
d il
an M
REG_B4 0x0b4 CROP_1

REG_D0 0x0d0 MODE_CTRL
REG_D4 0x0d4 SYNC_CODE_0
n by
REG_D8 0x0d8 SYNC_CODE_1

REG_DC 0x0dc SYNC_CODE_2
tio lic
REG_E0 0x0e0 SYNC_CODE_3

ca ub

REG_EC 0x0ec SYNC_CODE_6
ifi p
REG_F0 0x0f0 SYNC_CODE_7

od de

M a
REG_FC 0x0fc VS_GEN

M
REG_100 0x100 SYNC_CODE_A

REG_104 0x104 SYNC_CODE_B
REG_108 0x108 HDR_PATTEN_2
REG_110 0x110 HISPI_MODE_CTRL_0
REG_11C 0x11c HISPI_MODE_CTRL_3
345
CV1835
9.1.6 VI register overview
REG_00
ed
2:0 reg_sensor_mac_mode R/W Sensor mode 0x0
3'b000: Disable
w
3'b001: CSI
lo
3'b010: Sub-LVDS
al
3'b011: TTL
3 reg_bt_demux_enable R/W BT Demux enable 0x0
t
4 reg_csi_ctrl_enable R/W CSI controller enable 0x0
no
5 reg_csi_vs_inv R/W CSI VS inverse 0x1
6 reg_csi_hs_inv R/W CSI HS inverse 0x1
e
7 Reserved
ar
8 reg_sublvds_ctrl_enable R/W Sub-LVDS controller enable 0x0
9 reg_sublvds_vs_inv R/W Sub-LVDS VS inverse 0x1
n
10 reg_sublvds_hs_inv R/W Sub-LVDS HS inverse 0x1
tio
11 reg_sublvds_hdr_inv R/W Sub-LVDS HDR inverse 0x1

31:12 Reserved
u
ib
REG_10
r

di V
st
re k-

0 reg_ttl_ip_en R/W TTL enable 0x0
d il
2:1 reg_ttl_sensor_bit R/W TTL bit mode 0x0

an M
2'b00: 8-bit
2'b01: 10-bit
n by
2'b10: 12-bit
2'b11: 16-bit
tio lic
3 Reserved
5:4 reg_ttl_bt_fmt_out R/W TTL BT output format 0x2
ca ub
2'b00: {Cb,Y},{Cr,Y}
2'b01: {Cr,Y},{Cb,Y}
ifi p
2'b10: {Y,Cb},{Y,Cr}
od de
2'b11: {Y,Cr},{Y,Cb}
7:6 Reserved
M a
11:8 reg_ttl_fmt_in R/W TTL input format 0x0

M
4'b0000: bt_2x with sync pattern, 9-bit

BT656
4'b0001: bt_1x with sync pattern, 17-bit
BT1120
4'b0010: bt_2x without sync pattern,
11-bit BT601 (vhs mode)
19-bit BT601 (vhs mode)
11-bit BT601 (vde mode)
19-bit BT601 (vde mode)
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CV1835

11-bit BT601 (vsde mode)
19-bit BT601 (vsde mode)
4'b100x: sensor with sync pattern
4'b101x: sensor without sync pattern,
use vs + hs (vhs mode)
use vde + hde (vde mode)
ed
use vs + hde (vsde mode)
w
13:12 reg_ttl_bt_data_seq R/W TTL bt data sequence 0x0
2'b00: Cb0-Y0-Cr0-Y1
lo
2'b01: Cr0-Y0-Cb0-Y1
al
2'b10: Y0-Cb0-Y1-Cr0
2'b11: Y0-Cr0-Y1-Cb0
t
14 reg_ttl_vs_inv R/W TTL vs inverse 0x0
no
15 reg_ttl_hs_inv R/W TTL hs inverse 0x0
31:16 Reserved
e
ar
REG_14
n
tio
11:0 reg_ttl_vs_bp R/W TTL vsync back porch setting 0x0

15:12 Reserved
u
ib
27:16 reg_ttl_hs_bp R/W TTL hsync back porch setting 0x0

31:28 Reserved
r
di V
st
re k-
REG_18
d il

an M

11:0 reg_ttl_img_wd R/W TTL image width setting 0x0
n by
15:12 Reserved
27:16 reg_ttl_img_ht R/W TTL image height setting 0x0
tio lic
31:28 Reserved
ca ub
REG_1C
ifi p

od de
15:0 reg_ttl_sync_0 R/W TTL sync code 0 0x0

M a

M
REG_20
31:16 Reserved
REG_24
15:0 reg_ttl_sav_vld R/W TTL valid line SAV 0x0
31:16 reg_ttl_sav_blk R/W TTL blanking line SAV 0x0
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CV1835
REG_28
15:0 reg_ttl_eav_vld R/W TTL valid line EAV 0x0
31:16 reg_ttl_eav_blk R/W TTL blanking line EAV 0x0
REG_30
ed
2:0 reg_vi_sel R/W VI input mode select 0x0
3'h1: RAW
w
3'h2: BT601
3'h3: BT656
lo
3'h4: BT1120
al
else: reserved
3 reg_vi_from R/W VI input from VI0 or VI1 0x0
t
1'b0: from VI0
no
1'b1: from VI1
4 reg_vi_clk_inv R/W VI clock inverse 0x0
e
5 reg_vi_v_sel_vs R/W 1'b1: vs_in signal as vs 0x1
ar
1'b0: vs_in signal as vde
6 reg_vi_vs_dbg R/W vsync source select
n 0x0
7 Reserved
tio
8 reg_pad_vi0_clk_inv R/W vi0 clk inverse 0x0

u

ib
31:11 Reserved
r
di V
st
REG_40
re k-

d il

an M
0 reg_sensor_mac_hdr_en R/W Sensor mac hdr manual mode enable 0x0

Shadow: Yes
n by
Shadow Ctrl: up_1t

Shadow Read Select: shrd_sel
tio lic
1 reg_sensor_mac_hdr_vsinv R/W Sensor mac vsync output inverse 0x0

Shadow: Yes
ca ub
Shadow Ctrl: up_1t

ifi p
2 reg_sensor_mac_hdr_hsinv R/W Sensor mac hsync output inverse 0x0

od de
Shadow: Yes
Shadow Ctrl: up_1t
M a

M
3 reg_sensor_mac_hdr_deinv R/W Sensor mac de output inverse 0x0

Shadow: Yes
Shadow Ctrl: up_1t
4 reg_sensor_mac_hdr_hdr0inv R/W Sensor mac hdr[0] output inverse 0x0
Shadow: Yes
Shadow Ctrl: up_1t
5 reg_sensor_mac_hdr_hdr1inv R/W Sensor mac hdr[1] output inverse 0x0
Shadow: Yes
Shadow Ctrl: up_1t
6 reg_sensor_mac_hdr_blcinv R/W Sensor mac blc output inverse 0x0
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CV1835

Shadow: Yes
Shadow Ctrl: up_1t
7 Reserved
8 reg_sensor_mac_hdr_mode R/W Sensor mac hdr mode 0x0
1'b1 stands for HiSPi S-SP HDR mode,
remove HDR blanking line
Shadow: Yes
Shadow Ctrl: up_1t
ed
31:9 Reserved
w
lo
REG_44
al
t
no
12:0 reg_sensor_mac_hdr_shift R/W Sensor mac hdr long exposure shift 0x0
(long exposure lines before 1st short
exposure line)
e
Shadow: Yes
ar
Shadow Ctrl: up_1t
n
15:13 Reserved
tio
28:16 reg_sensor_mac_hdr_vsize R/W Sensor mac hdr vsize 0x0

Shadow: Yes
u
Shadow Ctrl: up_1t

ib

r
31:29 Reserved
di V
st
re k-
REG_48
d il

an M

12:0 reg_sensor_mac_info_line_num R/W Info line number 0x1
n by
Shadow: Yes
Shadow Ctrl: up_1t
tio lic

15:13 Reserved
ca ub
16 reg_sensor_mac_rm_info_line R/W Remove info line 0x0

ifi p
Shadow: Yes
Shadow Ctrl: up_1t
od de

31:17 Reserved
M a
M
REG_50
0 reg_sensor_mac_blc0_en R/W BLC0 mode enable 0x0
1 reg_sensor_mac_blc1_en R/W BLC1 mode enable 0x0
31:2 Reserved
REG_54
12:0 reg_sensor_mac_blc0_start R/W BLC0 start line number 0x0
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CV1835

15:13 Reserved
28:16 reg_sensor_mac_blc0_size R/W BLC0 line size 0x4
31:29 Reserved
REG_58
12:0 reg_sensor_mac_blc1_start R/W BLC1 start line number 0x0
ed
15:13 Reserved
w
28:16 reg_sensor_mac_blc1_size R/W BLC1 line size 0x4
31:29 Reserved
lo
al
REG_60
t
no
5:0 reg_vi_vs_sel R/W vi pin select 0x0
[5]: from VI1 or VI0
e
[4:0]: from which VI pad count
ar
7:6 Reserved
13:8 reg_vi_hs_sel R/W vi pin select 0x0
n
tio
15:14 Reserved
u
ib
21:16 reg_vi_vde_sel R/W vi pin select 0x0

r
di V
st

re k-
23:22 Reserved
d il
29:24 reg_vi_hde_sel R/W vi pin select 0x0

an M

n by
31:30 Reserved
tio lic
REG_64
ca ub

5:0 reg_vi_d0_sel R/W vi pin select 0x0
ifi p

od de

7:6 Reserved
M a

M

15:14 Reserved
23:22 Reserved
31:30 Reserved
350
CV1835
REG_68
7:6 Reserved
ed
15:14 Reserved
w
lo
al
23:22 Reserved
t
no
31:30 Reserved
e
ar
REG_6C n
tio

u

ib

7:6 Reserved
r
di V
st

re k-

d il

an M
15:14 Reserved
n by

tio lic
23:22 Reserved
ca ub

ifi p
31:30 Reserved
od de
REG_70
M a
M

7:6 Reserved
15:14 Reserved
351
CV1835

23:22 Reserved
31:30 Reserved
REG_74
ed
w
2:0 reg_vi_bt_d0_sel R/W vi bt pin select from which VI2 pad 0x0
lo
count
3 Reserved
al
t
count
no
7 Reserved
e
count
ar
11 Reserved
n
count
tio
15 Reserved
u
count
ib
19 Reserved
r
di V
st
re k-
count
23 Reserved
d il
an M
count
n by
27 Reserved
tio lic
count
31 Reserved
ca ub
REG_80
ifi p

od de

0 reg_bt_clr_sync_lost_1t R/W Clear sync_lost signal 0x0
M a
1 reg_bt_ip_en R/W BT path enable 0x0

M
2 reg_bt_ddr_mode R/W BT DDR mode 0x0

3 reg_bt_hs_gate_by_vde R/W HS gating by VDE 0x0
4 reg_bt_vs_inv R/W vsync inverse 0x0
5 reg_bt_hs_inv R/W hsync inverse 0x0
6 reg_bt_vs_as_vde R/W input vsync as vde 0x0
7 reg_bt_hs_as_hde R/W input hsync as hde 0x0
14:8 reg_bt_sw_en_clk R/W Clock gating software enable 0x0
[0]: delay control clock enable
[1]: timing demultiplexer clock enable
[2]: timing gen clock enable
[3]: rx decode 0 clock enable
352
CV1835

15 Reserved
17:16 reg_bt_demux_ch R/W Demux setting 0x0
2'h0: No demux
2'h1: Demux 2
2'h2: Demux 3
2'h3: Demux 4
19:18 Reserved
ed
22:20 reg_bt_fmt_sel R/W 3'b000 : bt_2x with sync pattern, 9-bit 0x0
w
BT656 (clock + 8-bit data )
3'b001 : bt_1x with sync pattern, 17-bit
lo
BT1120 (clock + 16-bit data )
al
3'b010 : bt_2x without sync pattern, 11-
bit BT601 (clock + 8-bit data + vs + hs)
t
(vhs_mode )
no
bit BT601 (clock + 16-bit data + vs + hs)
e
(vhs_mode )
ar
bit BT601 (clock + 8-bit data + vde +
hde) (vde_mode )
n
tio
bit BT601 (clock + 16-bit data + vde +

hde) (vde_mode )
u

ib
bit BT601 (clock + 8-bit data + vs + hde)

r
(vsde_mode)
di V
st

re k-
bit BT601 (clock + 16-bit data + vs +

d il
hde) (vsde_mode)
an M
31:23 Reserved
n by
REG_88
tio lic

11:0 reg_bt_img_wd_m1 R/W BT image width 0x0
ca ub
15:12 Reserved
ifi p
27:16 reg_bt_img_ht_m1 R/W BT image height 0x0

31:28 Reserved
od de
M a
REG_8C
M

11:0 reg_bt_vs_bp_m1 R/W BT vsync back porch 0x0
15:12 Reserved
27:16 reg_bt_hs_bp_m1 R/W BT hsync back porch 0x0
31:28 Reserved
REG_90
7:0 reg_bt_vs_fp_m1 R/W BT vsync front porch 0x0
353
CV1835

15:8 reg_bt_hs_fp_m1 R/W BT hsync front porch 0x0
31:16 Reserved
REG_94
7:0 reg_bt_sync_0 R/W BT sync code byte 0 0x0
ed
31:24 Reserved
w
lo
REG_98
al
t
7:0 reg_bt_sav_vld_0 R/W BT valid SAV sync code for demux 0 0x0
no
15:8 reg_bt_sav_blk_0 R/W BT blank SAV sync code for demux 0 0x0
23:16 reg_bt_eav_vld_0 R/W BT valid EAV sync code for demux 0 0x0
e
31:24 reg_bt_eav_blk_0 R/W BT blank EAV sync code for demux 0 0x0
ar
REG_9C n
tio

u
ib
r
di V
st
re k-
REG_A0
d il

an M

n by
tio lic
ca ub
REG_A4
ifi p

od de
M a
M
REG_B0
12:0 reg_sensor_mac_crop_start_x R/W Pixels before 0xFFF
reg_sensor_mac_crop_start_x will be
cropped in each line if enable
reg_sensor_mac_crop_en.
15:13 Reserved
28:16 reg_sensor_mac_crop_end_x R/W Pixels after 0xFFF
reg_sensor_mac_crop_end_x will be
354
CV1835

cropped in each line if enable
30:29 Reserved
31 reg_sensor_mac_crop_en R/W enable crop function 0x0
REG_B4
ed
12:0 reg_sensor_mac_crop_start_y R/W Lines before 0xFFF
reg_sensor_mac_crop_start_y will be
w
cropped in each frame if enable
lo
15:13 Reserved
al
28:16 reg_sensor_mac_crop_end_y R/W Lines after 0xFFF
reg_sensor_mac_crop_end_y will be
t
no
cropped in each frame if enable
31:29 Reserved
e
ar
REG_D0
n
tio
0 reg_ttl_as_slvds_enable R/W Sub-LVDS lane enable for each lane 0x0
u
7:1 Reserved
ib
9:8 reg_ttl_as_slvds_bit_mode R/W Sub-LVDS bit mode 0x2

r
2'b00: 8-bit
di V
st
2'b01: 10-bit
re k-
2'b10: 12-bit
d il
10 reg_ttl_as_slvds_data_reverse R/W Sub-LVDS data packet bit inverse 0x0

an M
11 Reserved
12 reg_ttl_as_slvds_hdr_mode R/W Sub-LVDS HDR mode enable 0x0
n by
13 reg_ttl_as_slvds_hdr_pattern R/W Sub-LVDS HDR pattern mode 0x0

1'b0: pattern 1
1'b1: pattern 2
tio lic
31:14 Reserved
ca ub
REG_D4
ifi p

od de

11:0 reg_ttl_as_slvds_sync_1st R/W Sub-LVDS SYNC code 1st word 0xFFF
M a
15:12 Reserved
M
27:16 reg_ttl_as_slvds_sync_2nd R/W Sub-LVDS SYNC code 2nd word 0x000

31:28 Reserved
REG_D8
11:0 reg_ttl_as_slvds_sync_3rd R/W Sub-LVDS SYNC code 3rd word 0x000
15:12 Reserved
27:16 reg_ttl_as_slvds_norm_bk_sav R/W Normal mode blanking SAV 0xAB0
31:28 Reserved
355
CV1835
REG_DC
11:0 reg_ttl_as_slvds_norm_bk_eav R/W Normal mode blanking EAV 0xB60
15:12 Reserved
27:16 reg_ttl_as_slvds_norm_sav R/W Normal mode active SAV 0x800
31:28 Reserved
REG_E0
ed
w
11:0 reg_ttl_as_slvds_norm_eav R/W Normal mode active EAV 0x9D0
lo
15:12 Reserved
al
27:16 reg_ttl_as_slvds_n0_bk_sav R/W HDR mode n0 blanking SAV 0x2B0
31:28 Reserved
t
no
REG_E4
e
ar
11:0 reg_ttl_as_slvds_n0_bk_eav R/W HDR mode n0 blanking EAV 0x360
15:12 Reserved
n
tio
27:16 reg_ttl_as_slvds_n1_bk_sav R/W HDR mode n1 blanking SAV 0x6B0
31:28 Reserved
u
ib
REG_E8
r

di V
st

re k-
11:0 reg_ttl_as_slvds_n1_bk_eav R/W HDR mode n1 blanking EAV 0x760

d il
15:12 Reserved
an M
27:16 reg_ttl_as_slvds_n0_lef_sav R/W Sub-LVDS mode: n0 long exposure sav 0x801

Sub-LVDS 12-bit LEF SAV n0 (801)
n by

HiSPi P-SP mode: SOL T1 (800)
tio lic
31:28 Reserved
ca ub
REG_EC
ifi p

od de
11:0 reg_ttl_as_slvds_n0_lef_eav R/W Sub-LVDS mode: n0 long exposure eav 0x9D1

M a
Sub-LVDS 12-bit LEF EAV n0 (9D1)

M

HiSPi P-SP mode: EOL T1 (A00)
15:12 Reserved
27:16 reg_ttl_as_slvds_n0_sef_sav R/W Sub-LVDS mode: n0 short exposure sav 0x802
Sub-LVDS 12-bit SEF SAV n0 (802)
31:28 Reserved
REG_F0
356
CV1835

11:0 reg_ttl_as_slvds_n0_sef_eav R/W Sub-LVDS mode: n0 short exposure eav 0x9D2
Sub-LVDS 12-bit SEF EAV n0 (9D2)
Sub-LVDS 10-bit SEF EAV n0 (1d8)
15:12 Reserved
27:16 reg_ttl_as_slvds_n1_lef_sav R/W Sub-LVDS mode: n1 long exposure sav 0xC01
Sub-LVDS 12-bit LEF SAV n1 (C01)
HiSPi P-SP mode: SOF T1 (C00)
ed
31:28 Reserved
w
REG_F4
lo
al
11:0 reg_ttl_as_slvds_n1_lef_eav R/W Sub-LVDS mode: n1 long exposure eav 0xDD1
t
no
Sub-LVDS 12-bit LEF EAV n1 (DD1)
HiSPi P-SP mode: EOF T1 (E00)
e
15:12 Reserved
ar
27:16 reg_ttl_as_slvds_n1_sef_sav R/W Sub-LVDS mode: n1 short exposure sav 0xC02
Sub-LVDS 12-bit SEF SAV n1 (C02)
n
tio

31:28 Reserved
u
ib
REG_F8
r
di V
st

re k-

d il
11:0 reg_ttl_as_slvds_n1_sef_eav R/W Sub-LVDS mode: n1 short exposure eav 0xDD2

an M
Sub-LVDS 12-bit SEF EAV n1 (DD2)

n by

31:12 Reserved
tio lic
REG_FC
ca ub

ifi p
11:0 reg_ttl_as_slvds_vs_gen_sync_code R/W vs generate sync code value 0xC00

od de
using scenario: HiSPi P-SP HDR

12 reg_ttl_as_slvds_vs_gen_by_sync_c R/W vs generate by identical sync code 0x0
M a
ode using scenario: HiSPi P-SP HDR

M
31:13 Reserved
REG_100
11:0 reg_ttl_as_slvds_n0_lsef_sav R/W SAV for n0 long & short exposure both 0x803
exist line
only used for pattern 2
15:12 Reserved
27:16 reg_ttl_as_slvds_n0_lsef_eav R/W EAV for n0 long & short exposure both 0x9D3
exist line
357
CV1835

31:28 Reserved
REG_104
11:0 reg_ttl_as_slvds_n1_lsef_sav R/W SAV for n1 long & short exposure both 0xC03
exist line
ed
15:12 Reserved
27:16 reg_ttl_as_slvds_n1_lsef_eav R/W EAV for n1 long & short exposure both 0xDD3
w
exist line
lo
31:28 Reserved
al
t
REG_108
no
e
13:0 reg_ttl_as_slvds_hdr_p2_hsize R/W Hsize for pattern 2 0xF0
ar
15:14 Reserved
29:16 reg_ttl_as_slvds_hdr_p2_hblank R/W Hblank size for pattern 2 0x14
n
31:30 Reserved
tio
REG_110
u

ib

r
di V
st
0 reg_ttl_as_hispi_mode R/W HiSPi mode enable 0x0

re k-
1'b0: Sub-LVDS
1'b1: HiSPi
d il
an M
1 reg_ttl_as_hispi_use_hsize R/W HiSPi DE de-assert by register count 0x0

3:2 Reserved
n by
4 reg_ttl_as_hispi_hdr_psp_mode R/W HiSPi P-SP HDR mode enable 0x0

31:5 Reserved
tio lic
REG_114
ca ub

ifi p
11:0 reg_ttl_as_hispi_norm_sof R/W HiSPi SOF sync code 0xC00

od de
15:12 Reserved
27:16 reg_ttl_as_hispi_norm_eof R/W HiSPi EOF sync code 0xE00
M a
31:28 Reserved
M
REG_118
11:0 reg_ttl_as_hispi_hdr_t1_sof R/W HiSPi HDR T1 SOF 0xC00
15:12 Reserved
27:16 reg_ttl_as_hispi_hdr_t1_eof R/W HiSPi HDR T1 EOF 0xE00
31:28 Reserved
REG_11C
358
CV1835

11:0 reg_ttl_as_hispi_hdr_t1_sol R/W HiSPi HDR T1 SOL 0x800
15:12 Reserved
27:16 reg_ttl_as_hispi_hdr_t1_eol R/W HiSPi HDR T1 EOL 0xA00
31:28 Reserved
REG_120
ed
11:0 reg_ttl_as_hispi_hdr_t2_sof R/W HiSPi HDR T2 SOF 0xC20
15:12 Reserved
w
27:16 reg_ttl_as_hispi_hdr_t2_eof R/W HiSPi HDR T2 EOF 0xE20
lo
31:28 Reserved
al
REG_124
t
no
11:0 reg_ttl_as_hispi_hdr_t2_sol R/W HiSPi HDR T2 SOL 0x820
e
15:12 Reserved
ar
27:16 reg_ttl_as_hispi_hdr_t2_eol R/W HiSPi HDR T2 EOL
n 0xA20
31:28 Reserved
u tio
r ib
di V
9.2 MIPI Rx
st
re k-
d il
an M
9.2.1 Overview
n by
The main function of MIPI Rx (Mobile Industry Processor Interface Receiver) module is
tio lic
to receive the video data transmitted by CMOS sensor. It supports different serial video
ca ub
signal input such as MIPI D-PHY, sub LVDS (Low-Voltage Differential Signal) and HiSPi
ifi p
(High-Speed Serial Pixel Interface), and then the processing is transformed into internal
od de
video timing, which is transmitted to the next level of video processing module (ISP).
M a
M
MIPI Rx module can be divided into PHY and Controller. PHY module integrates analog
and digital parts, mainly converting serial signals into parallel signals, while Controller
module is responsible for decoding different video data formats and transmitting them
to the back-end video processing module (ISP). The functional block diagram and its
position in the system are shown in Figure 9-13.
359
CV1835
ed
w
lo
al
Figure 9- 4 MIPI Rx Functional Block Diagrams and Position
t
no
e
ar
9.2.2 Charateristics n
tio
• Supported MIPI DPHY-ver2.1

• Maximum support for single sensor linear input is 5M (2688x1944, 2880x1620)
u
ib
@20fps
r
di V
st
• Up to 4-Lane MIPI D-PHY interface is supported for a single input, with a maximum
re k-
of 1.5Gbps/Lane
d il
an M
• Support for parsing RAW8/ RAW10/ RAW12/RAW16 data types

• Support for parsing YUV422 8-bit/ YUV422 10-bit data types
n by
• Support for configurable number of lanes and lane order.

tio lic
ca ub
ifi p

od de
M a
9.2.3.1 Typical Application

M
In applications that use image sensors, the MIPI Rx module registers are set, and the
MIPI Rx also supports the transmission of different speeds and resolutions, and is
compatible with multiple image sensor formats.
The MIPI Rx is only responsible for interface timing conversion and decoding, and does
not handle the image processing part. Therefore, it can support any resolution and
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CV1835
frame rate as long as the bandwidth is satisfied. The MIPI Rx bandwidth has two
limitations: the interface data rate of the PHY and the internal processing speed. The
input interface supports a maximum of 1.5Gbps/Lane, and the maximum internal
processing speed is 600M*1pixels/s.
Common mode Differential Maximum clock Maximum data
voltage mode voltage frequency rate per lane
MIPI DPHY 200mV 200mV 750MHz 1.5Gbps
ed
w
lo
Figure 9- 5 Interface Types Supported by MIPI Rx
al
t
9.2.3.2 MIPI Interface Data Formats
no
MIPI specification is developed and maintained by different working groups,
e
ar
corresponding to different applications. MIPI Rx supports D-PHY and CSI-2 (Camera
Serial Interface). D-PHY specifies the transmission specification of physical layer, while
n
tio
CSI-2 specifies the format and protocol of Camera output packet.

u
ib
• D-PHY
r
di V
st
D-PHY is a high-speed physical layer standard issued by MIPI Alliance, which

re k-
specifies the physical characteristics and transmission protocol of interface layer. D-

d il
an M
PHY adopts the low-voltage differential signal technology of 200mV source

n by
synchronization, and the data green rate range of each Lane supports up to
2500Mbps. D-PHY can work in two modes: low power (LP) and high speed (HS).
tio lic
ca ub
• CSI-2
ifi p
CSI-2 is a data protocol for camera, which specifies the data packet format of
od de
communication between host and peripheral.

M a
M
CSI-2 can support image applications with different pixel formats, and the minimum
granularity of data transmission is byte. In order to enhance the performance of CSI-2,
the number of data lanes can be selected. CSI-2 protocol specifies the mechanism for
the sender to package pixel data into bytes, and it indicates the way to allocate and
manage multiple data lanes. Byte data is organized in the form of packets, which are
transmitted between SOT and EOT. The receiver parses the corresponding packets
according to the protocol and recovers the original pixel data.
361
CV1835
MIPI Rx supports the parsing of RAW8/ RAW10/ RAW12/ YUV422-8bit/ YUV422-10bit

data types.
CSI-2 data packet is divided into long packet and short packet, including check code,
which can correct and detect errors.
ed
w
Both long packets and short packets are transmitted between SOT and EOT. In the
lo
gap of data transmission, D-PHY is in LP mode. The transmission mechanism of CSI-2
al
packet is shown in the figure. PH and PF represent Packet Header and Packet Footer
t
no
respectively.
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
Figure 9- 6 Transmission Mechanism of Data Packet

n by
tio lic
The long packet is used to transmit effective pixel data, which is divided into five parts:
ca ub
Data ID, Word Count, ECC, PAYLOAD and CHECKSUM.

ifi p
od de
The Data ID contains Virtual Channel and Data Type. Virtual Channel controls the
M a
channel used for transmission, and different channels can be used to transmit different
M
data. Data Type specifies the type of data to be transmitted.
Word Count represents the amount of data that the receiver needs to receive.
ECC is an error correcting code, which can correct or detect the error of Data Type and
Word Count.
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CV1835
PAYLOAD is the pixel data to be transmitted.
CHECKSUM is the check sum generated by the linear feedback shift register, which is
used to check the PAYLOAD data.
The structure of the long package is shown in Figure 9-16.
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
Figure 9- 7 CSI-2 Long Packet Format

tio lic
ca ub
ifi p
The short packet is used to transmit information synchronously, including Data ID, Data
od de
Field and ECC. Its format is shown in Figure 9-17.

M a
M
363
CV1835
ed
w
lo
al
t
no
Figure 9- 8 CSI-2 Short Packet Format
e
ar
MIPI Rx supports six video formats, including YUV422-8bit, YUV422-10bit, RAW8,
n
tio
RAW10, RAW12, and RAW16. Different data formats are transmitted as follows.
u
ib
The transmission mode of YUV422-8bit is in the form of UYVY, as shown in Figure 9-23.
r
di V
st
re k-
d il
an M
n by
Figure 9- 18 YUV422 8-bit Data Transmission Sequence

tio lic
ca ub
The correspondence of packets to video signals is shown in Figure 9-19.

ifi p
od de
M a
M
364
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
Figure 9- 19 YUV422-8bit Data Packet Transmission Correspondence

tio lic
ca ub
ifi p
The transmission format of the whole frame is shown in Figure 9-20.

od de
M a
M
365
CV1835
ed
w
lo
al
t
no
Figure 9- 9 YUV422 8-bit Frame Format
e
ar
The transmission mode of YUV422-10bit is also UYVY, and the transmission sequence is
n
tio
shown in Figure 9-21.

u
r ib
di V
st
re k-
d il
an M
n by
Figure 9- 10 YUV422-10bit Data Transmission Sequence

tio lic
ca ub
ifi p
The correspondence of packets to video signals is shown in Figure 9-22.

od de
M a
M
366
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
Figure 9- 11 YUV422-10bit Data Packet Transmission Correspondence

re k-
d il
an M
n by

tio lic
ca ub
ifi p
od de
M a
M
Figure 9- 12 YUV422-10bit Frame Format
367
CV1835
The transmission sequence of RAW8 is shown in Figure 9-24.
Figure 9- 13 RAW8 Data Transmission Sequence
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
Figure 9- 14 RAW8 Frame Format

tio lic
ca ub
ifi p

od de
M a
M
Figure 9- 15 RAW10 Data Transmission Sequence
368
CV1835
ed
w
lo
al
t
no
e
ar
n
tio

u
r ib
di V
st
re k-
d il
an M
n by
tio lic
Figure 9- 17 RAW12Data Transmission Sequenc

ca ub
ifi p

od de
M a
M
369
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
ib
图表 9‑18 RAW16Data Transmission Sequenc

r
di V
st
re k-

d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
图表 9‑19 RAW16 Frame Format
370
CV1835
9.2.3.3 MIPI Interface Linear Mode
The linear mode transmission format of MIPI interface is shown in Figure 9-32. The
transmission of each graph starts with Frame Start (FS) and ends with Frame End (FE).
The video content in the middle is based on the behavior unit, and each long packet
transmits a complete video line. The long packet format is regulated by MIPI standard.
ed
Each row has 32bit Packet Header (PH), which contains the Virtual Channel and Data
w
Type information of the current row.
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
371
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 9- 20 MIPI Interface Image Format
9.2.3.4 MIPI Interface Wide Dynamic Mode
MIPI Rx supports four kinds of Wide Dynamic (WDR) modes of MIPI interface.
1. Use Data Type (DT) to distinguish long and short exposure data
2. Use the Identification Code (ID) to distinguish the long and short exposure data
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CV1835
3. Use the register to set the delay interval of long and short exposure data
The WDR transmission mode using DT is shown in Figure 9-33. Different exposure
lengths share a group of FS / FE short packets, and the packet header of the long packet
contains DT information. Different DT can be used to distinguish the long and short
exposure data. The real data format DT and the two groups of DT representing the long
ed
and short exposure data can be set by registers. MIPI Rx can then analyze the correct
w
wide dynamic timing and send it to the rear video processing module.
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
Figure 9- 21 MIPI Interface Wide Dynamic Data Transfer (using DT)

tio lic
ca ub
ifi p
The WDR transmission mode using ID is shown in Figure 9-34. Different exposure
od de
lengths share a group of FS / FE short packets. The first four pixels of each long packet
M a
in the transmission data are used to transmit the Identification Code (ID) representing
M
different exposure lengths. The ID representing long and short exposures can be set by
the register. MIPI Rx will use ID to expose different video signals, remove the first four
pixels and then send them to the video processing module.
373
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
Figure 9- 22 MIPI Interface Wide Dynamic Data Transfer (using ID)

an M
n by
tio lic
The last kind of transmission mode supported WDR is that there is no DT or ID to

ca ub
indicate the transmitted long packet is the content of long exposure or short exposure.
ifi p
Users must set their own registers to indicate the difference in the number of exposure
od de
lines between long exposure and short exposure. MIPI Rx will analyze the
M a
corresponding timing to the video processing module. The actual transmission timing is
M
shown in Figure 9-35.
374
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ed
w
lo
al
t
no
e
ar
n
tio
Figure 9- 23 MIPI Interface Wide Dynamic Data Transfer (register setting)

u
r ib
di V
st
9.2.4 MIPI Rx Register Overview

re k-
d il
an M
Up to one set of MIPI Rx modules can be used simultaneously in the chip, which is
mainly divided into three sets of registers. The first part is the register that controls the
n by
PHY module, with a base address of 0x0A0D0000. The second part is the register that
tio lic
controls the CSI module, with base addresses of 0x0A0C2400 and 0x0A0C4400. The
ca ub
third part is the register that controls the Sub-LVDS and HiSPi modules, with base
ifi p
addresses of 0x0A0C2200 and 0x0A0C4200.

od de
Figure 9- 24 MIPI Rx PHY Register Overview

M a
M

Offset
REG_00 0x000 PD_CTRL
REG_04 0x004 ANALOG_CTRL
REG_30 0x030 SENSOR_MODE_CTRL
REG_34 0x034 ANALOG_CAL_0
REG_3C 0x03c ANALOG_CAL_2
REG_80 0x080 CLOCK_INVERCE_CTL
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CV1835

Offset
REG_A0 0x0a0
REG_A4 0x0a4
REG_A8 0x0a8
REG_AC 0x0ac
Offset = 0x0A0D0300
ed
Offset
w
lo
REG_04 0x004 LANE_SWAP_0
al
REG_0C 0x00c CSI_GLB_CTL_0
t
REG_20 0x020 SLVDS_CTRL_0
no
REG_D0_0 0x100 D0_REG_CTRL_CALIB_0
e
ar
REG_D0_3 0x10c D0_CALIB_RESULT_0
REG_D0_4 0x110 D0_CALIB_RESULT_1
n
tio
u

ib

REG_D0_A 0x128 D0_CALIB_RESULT_7
r
di V
st

re k-

d il
an M

n by

tio lic

ca ub

ifi p

od de

M a

M

REG_D2_8 0x1a0 D2_CALIB_RESULT_5
REG_D2_9 0x1a4 D2_CALIB_RESULT_6
REG_D2_A 0x1a8 D2_CALIB_RESULT_7
REG_D3_0 0x1c0 D3_REG_CTRL_CALIB_0
REG_D3_1 0x1c4 D3_REG_CTRL_CALIB_1
REG_D3_3 0x1cc D3_CALIB_RESULT_0
REG_D3_4 0x1d0 D3_CALIB_RESULT_1
REG_D3_7 0x1dc D3_CALIB_RESULT_4
REG_D3_8 0x1e0 D3_CALIB_RESULT_5
376
CV1835

Offset
REG_D3_9 0x1e4 D3_CALIB_RESULT_6
REG_D3_A 0x1e8 D3_CALIB_RESULT_7
Offset = 0x0A0D0600
Offset
ed
w
REG_0C 0x00c CSI_GLB_CTL_0
lo
al
REG_D0_3
t
0x10c D0_CALIB_RESULT_0
no
e
ar
n
tio

u

ib

r
REG_D1_5
di V
0x154 D1_CALIB_RESULT_2
st
re k-

d il

an M

n by
tio lic
Table 9‑25 MIPI Rx CSI control registers overview

ca ub

Offset
ifi p
REG_00 0x000 MODE_CTRL

od de
REG_04 0x004 INTR_CTRL

REG_08 0x008 HDR_CTRL_0
M a
REG_0C 0x00c HDR_CTRL_1

M

REG_14 0x014 BLC_CTRL
REG_1C 0x01c HDR_CTRL_4
REG_40 0x040 CSI_STATUS
REG_60 0x060
REG_70 0x070 CSI_VS_GEN
REG_74 0x074 HDR_DT_CTRL
377
CV1835
Table 9‑26 MIPI Rx Sub-LVDS control registers overview

Offset
REG_00 0x000 MODE_CTRL
REG_04 0x004 SYNC_CODE_0
REG_0C 0x00c SYNC_CODE_2
ed
REG_1C 0x01c SYNC_CODE_6
w
lo
al
REG_2C 0x02c VS_GEN
t
REG_30 0x030 LANE_MODE
no
REG_50 0x050 SYNC_CODE_A
REG_54 0x054 SYNC_CODE_B
REG_58 0x058 HDR_PATTEN_2
e
ar
n
REG_6C 0x06c HISPI_MODE_CTRL_3
tio

u
REG_80 0x080 DBG_SEL

r ib
di V
st
re k-
d il
an M
9.2.5 MIPI RxRegister Overview

n by
The first part is the description of MIPI Rx PHY register.

tio lic
ca ub
REG_00
ifi p

od de
13:0 Reserved
M a
14 reg_mipirx_pd_ibias R/W Power down analog ibias 0x1

M
15 Reserved
21:16 reg_mipirx_pd_rxlp R/W Power down analog RXLP 0x3f
31:22 Reserved
REG_04
15:0 Reserved
21:16 reg_mipirx_sel_clk_channel R/W Analog macro clock lane select 0x0
30:22 Reserved
31 reg_mipimpll_clk_csi_en R/W Gating test clock from mipimpll 0x0
378
CV1835
REG_30
2:0 reg_sensor_phy_mode R/W Sensor PHY mode enable select 0x0
0: 1C4D
1: 1C2D + 1C2D
else: reserved
31:3 Reserved
ed
REG_34
w
lo
31:0 reg_mipirx_ro_cal0 RO Analog lane 0 calibration result
al
REG_38
t
no
e
ar
REG_3C
n
tio
u
ib
REG_40
r

di V
st

re k-

d il
an M
REG_44
n by

tio lic
ca ub
REG_48
ifi p

od de

M a
REG_80
M

0 reg_ad_d0_clk_inv R/W AD clock lane0 inverse 0x0
31:6 Reserved
REG_A0
379
CV1835

13:0 reg_cam0_vtt R/W 0x0
15:14 Reserved
29:16 reg_cam0_vs_str R/W 0x0
31:30 Reserved
REG_A4
ed
w
13:0 reg_cam0_vs_stp R/W 0x0
lo
15:14 Reserved
al
29:16 reg_cam0_htt R/W 0x0
31:30 Reserved
t
no
REG_A8
e
ar
13:0 reg_cam0_hs_str R/W 0x0
n
15:14 Reserved
tio
29:16 reg_cam0_hs_stp R/W 0x0

u
31:30 Reserved
r ib
REG_AC
di V
st

re k-

d il
0 reg_cam0_vs_pol R/W 0x0

an M
1 reg_cam0_hs_pol R/W 0x0

n by
2 reg_cam0_tgen_en R/W 0x0

31:3 Reserved
tio lic
ca ub
Offset = 0x0A0D0300
ifi p
REG_00
od de

M a
1:0 reg_sensor_mode R/W Sensor mode select 0x0

M
2'b00: CSI
2'b01: Sub-LVDS & HiSPi
2'b10: SLVSEC
31:2 Reserved
REG_04
2:0 reg_csi_lane_d0_sel R/W Data lane 0 select 0x1
3 Reserved
380
CV1835

7 Reserved
11 Reserved
31:15 Reserved
REG_08
ed
w
2:0 reg_csi_lane_ck_sel R/W Clock lane select 0x0
3 Reserved
lo
4 reg_csi_lane_ck_pnswap R/W Clock lane pn swap 0x0
al
7:5 Reserved
t
8 reg_csi_lane_d0_pnswap R/W Data lane 0 pn swap 0x0
no
e
ar
15:12 Reserved
23:16 reg_csi_ck_phase R/W Clock lane phase 0x0
n
31:24 Reserved
tio
REG_0C
u

ib

r
3:0 reg_deskew_lane_en R/W Deskew lane enable 0x0

di V
st
4'h0: No lane
re k-
4'h1: 1-lane
d il
4'h3: 2-lane
an M
8'hf: 4-lane
31:4 Reserved
n by
REG_20
tio lic

ca ub
0 reg_slvds_inv_en R/W Sub-LVDS bit reverse 0x1

ifi p
1'b0: LSB first

1'b1: MSB first
od de
1 Reserved
3:2 reg_slvds_bit_mode R/W Sub-LVDS bit mode 0x2
M a
M
2'b00: 8-bit
2'b01: 10-bit
2'b10: 12-bit
7:4 reg_slvds_lane_en R/W Sub-LVDS lane enable 0x0
Set this register to start finding sync
code
15:8 Reserved
27:16 reg_slvds_sav_1st R/W Sub-LVDS sync code 1st symbol 0xfff
31:28 Reserved
REG_24
381
CV1835

11:0 reg_slvds_sav_2nd R/W Sub-LVDS sync code 2nd symbol 0x0
15:12 Reserved
27:16 reg_slvds_sav_3rd R/W Sub-LVDS sync code 3rd symbol 0x0
31:28 Reserved
REG_D0_0
ed
0 reg_d0_prbs9_en R/W Manual PRBS9 enable 0x0
1 reg_d0_prbs9_clr_err R/W PRBS9 clear error 0x0
w
2 reg_d0_prbs9_source R/W PRBS9 source select 0x0
lo
1'b0: after sync code shift
1'b1: direct from input
al
3 reg_d0_prbs9_stop_when_done R/W PRBS9 error count accumalation 0x0
t
1'b0: still count after test time done
no
1'b1: do not count after test time done
7:4 Reserved
e
15:8 reg_d0_calib_max R/W Calibration max step 0x1f
ar
23:16 reg_d0_calib_step R/W Calibration one step value 0x1
31:24 reg_d0_calib_pattern R/W Calibration golden pattern
n 0xaa
REG_D0_1
tio

u

ib
0 reg_d0_calib_en R/W Calibration software enable 0x0

1 reg_d0_calib_source R/W
r
Calibration source 0x0

di V
st
1'b0: normal position

re k-
1'b1: direct from analog

2 reg_d0_calib_mode R/W Calibration software mode 0x0
d il
an M
1'b0: use identical calibration pattern

1'b1: use PRBS9 pattern
3 reg_d0_calib_ignore R/W Ignore calibration command 0x0
n by
31:4 Reserved
tio lic
REG_D0_3
ca ub

ifi p
31:0 reg_d0_skew_calib_result_0 RO Calibration result phase 0~31

od de
REG_D0_4
M a

M

REG_D0_5
REG_D0_6
382
CV1835

REG_D0_7
REG_D0_8
ed
w
lo
al
REG_D0_9
t
no
e
REG_D0_A
ar
tio
u
REG_D1_0
ib

r

di V
st
re k-

d il

an M

n by

tio lic

7:4 Reserved
ca ub

ifi p
31:24 reg_d1_calib_pattern R/W Calibration golden pattern 0xaa

od de
REG_D1_1
M a

M

1 reg_d1_calib_source R/W Calibration source 0x0
31:4 Reserved
REG_D1_3
383
CV1835

REG_D1_4
ed
REG_D1_5
w
lo
al
REG_D1_6
t
no
e
ar
REG_D1_7
n
tio
u
ib
REG_D1_8
r

di V
st

re k-

d il
an M
REG_D1_9
n by

tio lic
ca ub
REG_D1_A
ifi p

od de

M a
REG_D2_0
M

7:4 Reserved
384
CV1835

REG_D2_1
ed
w
lo
al
31:4 Reserved
t
no
REG_D2_3
e
ar
n
REG_D2_4
tio

u

ib

r
di V
st
REG_D2_5
re k-

d il

an M

n by
REG_D2_6
tio lic

ca ub

ifi p
REG_D2_7
od de

M a

M
REG_D2_8
REG_D2_9
385
CV1835
REG_D2_A
REG_D3_0
ed
w
lo
al
t
no
7:4 Reserved
e
ar
REG_D3_1
n
tio

u

ib

r
di V
st

re k-

d il

an M

31:4 Reserved
n by
REG_D3_3
tio lic

ca ub

ifi p
od de
REG_D3_4
M a

M
REG_D3_5
REG_D3_6
386
CV1835
REG_D3_7
REG_D3_8
ed
REG_D3_9
w
lo
al
t
REG_D3_A
no
e
ar
n
Offset = 0x0A0D0600
tio
REG_00
u

ib

r
di V
1:0 reg_sensor_mode R/W Sensor mode select 0x0

st
re k-
2'b00: CSI
2'b01: Sub-LVDS & HiSPi
d il
2'b10: SLVSEC
an M
31:2 Reserved
n by
REG_04
tio lic

ca ub

3:2 Reserved
ifi p

od de
31:6 Reserved
M a
REG_08
M

1:0 reg_csi_lane_ck_sel R/W Clock lane select 0x0
3:2 Reserved
4 reg_csi_lane_ck_pnswap R/W Clock lane pn swap 0x0
7:5 Reserved
15:10 Reserved
23:16 reg_csi_ck_phase R/W Clock lane phase 0x0
31:24 Reserved
387
CV1835
REG_0C
1:0 reg_deskew_lane_en R/W Deskew lane enable 0x0
2'h0: No lane
2'h1: 1-lane
2'h3: 2-lane
31:2 Reserved
REG_20
ed
w
lo
0 reg_slvds_inv_en R/W Sub-LVDS bit reverse 0x1
1'b0: LSB first
al
1'b1: MSB first
1 Reserved
t
no
2'b00: 8-bit
2'b01: 10-bit
e
2'b10: 12-bit
ar
5:4 reg_slvds_lane_en R/W Sub-LVDS lane enable 0x0
Set this register to start finding sync
n
code
tio
31:6 Reserved
u
REG_D0_0
ib

r
di V
st

re k-

d il
an M

n by

tio lic

7:4 Reserved
ca ub

ifi p

od de
REG_D0_1
M a
M

31:4 Reserved
388
CV1835
REG_D0_3
REG_D0_4
ed
REG_D0_5
w
lo
al
t
REG_D0_6
no
e
REG_D0_7 ar
n
tio
u

r ib
REG_D0_8
di V
st

re k-

d il

an M
REG_D0_9
n by

tio lic

ca ub
REG_D0_A
ifi p

od de

M a
M
REG_D1_0
389
CV1835

7:4 Reserved
REG_D1_1
ed
w
lo
al
t
no
31:4 Reserved
e
REG_D1_3
ar
n
tio
u
REG_D1_4
ib

r

di V
st

re k-
d il
REG_D1_5
an M

n by

tio lic
REG_D1_6
ca ub

ifi p

od de
REG_D1_7
M a

M

REG_D1_8
REG_D1_9
390
CV1835

REG_D1_A
ed
w
The second part is MIPI Rx CSI controller register.
lo
al
REG_00
t
no
2:0 reg_csi_lane_mode R/W Lane mode 0x0
3'b000: 1-lane
e
ar
3'b001: 2-lane
3'b011: 4-lane
3'b111: 8-lane
n
3 reg_csi_ignore_ecc R/W Ignore ecc result 0x0
tio
1'b0: normal
1'b1: still processing even ecc error
u
4 reg_csi_vc_check R/W VC check enable 0x0

ib
1'b0: do not check VC

r
1'b1: only process packets that meet

di V
st
vc_set[3:0]
re k-
7:5 Reserved
d il
11:8 reg_csi_vc_set R/W VC set 0x0

an M
only use when reg_csi_vc_check assert

12 reg_csi_line_start_sent R/W LS and LE packet sent 0x0
n by
1'b0: create hsync signal by controller

1'b1: use LS and LE to create hsync
tio lic
signal
31:13 Reserved
ca ub
REG_04
ifi p

od de

7:0 reg_csi_intr_mask R/W Interrupt mask control 0x0
M a
M
15:8 reg_csi_intr_clr W1T Interrupt clear

16 reg_csi_hdr_en R/W HDR mode enable 0x0
17 reg_csi_hdr_mode R/W HDR mode selection 0x0
1'b0: HDR VC mode
1'b1: HDR ID mode
18 reg_csi_id_rm_else R/W Remove non reconized ID line 0x1
1'b0: dont remove
1'b1: remove
19 reg_csi_id_rm_ob R/W Remove ob line 0x1
1'b0: don’t remove
1'b1: remove
31:20 Reserved
391
CV1835
REG_08
15:0 reg_csi_n0_ob_lef R/W ID for LEF ob n0 0x221
31:16 reg_csi_n0_ob_sef R/W ID for SEF ob n0 0x222
REG_0C
ed
15:0 reg_csi_n0_lef R/W ID for LEF active n0 0x241
31:16 reg_csi_n1_ob_lef R/W ID for LEF ob n1 0x231
w
REG_10
lo
al
15:0 reg_csi_n1_ob_sef R/W ID for SEF ob n1 0x232
t
no
31:16 reg_csi_n1_lef R/W ID for LEF active n1 0x251
REG_14
e
ar
5:0 reg_csi_blc_dt R/W Data type for optical black line 0x37
n
7:6 Reserved
tio
8 reg_csi_blc_en R/W Optical black line mode enable 0x0

u
11:9 Reserved
ib
14:12 reg_csi_blc_format_set R/W Optical black line data format set 0x2
r
3'd0: YUV422 8bit

di V
st
3'd1: YUV422 10bit

re k-
3'd2: RAW8
d il
3'd3: RAW10
an M
3'd4: RAW12
3'd5: RAW16
n by
else: reserved
31:15 Reserved
tio lic
REG_18
ca ub

ifi p
3:0 reg_csi_vc_map_ch00 R/W VC mapping to ISP channel 00 0x0

od de

M a

M
31:16 Reserved
REG_1C
15:0 reg_csi_n0_sef R/W ID for SEF active n0 0x242
31:16 reg_csi_n1_sef R/W ID for SEF active n1 0x252
REG_20
15:0 reg_csi_n0_sef2 R/W ID for SEF2 active n0 0x244
392
CV1835

31:16 reg_csi_n1_sef2 R/W ID for SEF2 active n1 0x254
REG_24
15:0 reg_csi_n0_ob_sef2 R/W ID for SEF2 ob n0 0x224
31:16 reg_csi_n1_ob_sef2 R/W ID for SEF2 ob n1 0x234
REG_40
ed
w
0 reg_csi_ecc_no_error RO ECC no error
lo
1 reg_csi_ecc_corrected_error RO ECC corrected error
al
2 reg_csi_ecc_error RO ECC error
t
3 Reserved
no
4 reg_csi_crc_error RO CRC error
e
5 reg_csi_wc_error RO WC error
ar
7:6 Reserved
8 reg_csi_fifo_full RO CSI FIFO full
n
tio
15:9 Reserved
21:16 reg_csi_decode_format RO CSI decode format from header
u
bit[0]: YUV422 8bit

ib
bit[1]: YUV422 10bit

bit[2]: RAW8
r
di V
st
bit[3]: RAW10
re k-
bit[4]: RAW12
bit[5]: RAW16
d il
an M
31:22 Reserved
n by
REG_60
tio lic

7:0 reg_csi_intr_status RO Interrupt status
ca ub
bit[0]: ecc error

bit[1]: crc error
ifi p
bit[2]: hdr id error

bit[3]: word count error
od de
bit[4]: fifo full

M a
31:8 Reserved
M
REG_70
1:0 reg_csi_vs_gen_mode R/W 2'b00: vs gen by FS 0x2
2'b01: vs gen by FE
else: vs gen by FS & FE
3:2 Reserved
4 reg_csi_vs_gen_by_vcset R/W Vsync generation setting 0x0
1'b0: generated by all vc short packet
1'b1: only generated by indicated vc
short packet
393
CV1835

31:5 Reserved
REG_74
0 reg_csi_hdr_dt_mode R/W CSI HDR DT mode enable 0x0
3:1 Reserved
9:4 reg_csi_hdr_dt_format R/W CSI HDR DT mode video format data 0x0
ed
type
11:10 Reserved
w
17:12 reg_csi_hdr_dt_lef R/W CSI HDR DT mode LEF data type 0x0
lo
19:18 Reserved
al
25:20 reg_csi_hdr_dt_sef R/W CSI HDR DT mode SEF data type 0x0
31:26 Reserved
t
no
The third part is MIPI Rx Sub-LVDS control registers
e
REG_00 ar
n
tio
u
7:0 reg_slvds_enable R/W Sub-LVDS lane enable for each lane 0x0
ib

2'b00: 8-bit
r
di V
st
2'b01: 10-bit
re k-
2'b10: 12-bit
10 reg_slvds_data_reverse R/W Sub-LVDS data packet bit inverse 0x0
d il
an M
11 Reserved
12 reg_slvds_hdr_mode R/W Sub-LVDS HDR mode enable 0x0
n by
13 reg_slvds_hdr_pattern R/W Sub-LVDS HDR pattern mode 0x0

1'b0: pattern 1
1'b1: pattern 2
tio lic
31:14 Reserved
ca ub
REG_04
ifi p

od de

11:0 reg_slvds_sync_1st R/W Sub-LVDS SYNC code 1st word 0xFFF
M a
15:12 Reserved
M
27:16 reg_slvds_sync_2nd R/W Sub-LVDS SYNC code 2nd word 0x000

31:28 Reserved
REG_08
11:0 reg_slvds_sync_3rd R/W Sub-LVDS SYNC code 3rd word 0x000
15:12 Reserved
27:16 reg_slvds_norm_bk_sav R/W Normal mode blanking SAV 0xAB0
31:28 Reserved
394
CV1835
REG_0C
11:0 reg_slvds_norm_bk_eav R/W Normal mode blanking EAV 0xB60
15:12 Reserved
27:16 reg_slvds_norm_sav R/W Normal mode active SAV 0x800
31:28 Reserved
REG_10
ed
w
11:0 reg_slvds_norm_eav R/W Normal mode active EAV 0x9D0
lo
15:12 Reserved
al
27:16 reg_slvds_n0_bk_sav R/W HDR mode n0 blanking SAV 0x2B0
31:28 Reserved
t
no
REG_14
e
ar
11:0 reg_slvds_n0_bk_eav R/W HDR mode n0 blanking EAV 0x360
15:12 Reserved
n
tio
27:16 reg_slvds_n1_bk_sav R/W HDR mode n1 blanking SAV 0x6B0
31:28 Reserved
u
ib
REG_18
r

di V
st

re k-
11:0 reg_slvds_n1_bk_eav R/W HDR mode n1 blanking EAV 0x760

d il
15:12 Reserved
an M
27:16 reg_slvds_n0_lef_sav R/W Sub-LVDS mode: n0 long exposure sav 0x801

n by

tio lic
31:28 Reserved
ca ub
REG_1C
ifi p

od de
11:0 reg_slvds_n0_lef_eav R/W Sub-LVDS mode: n0 long exposure eav 0x9D1

M a

M

15:12 Reserved
27:16 reg_slvds_n0_sef_sav R/W Sub-LVDS mode: n0 short exposure sav 0x802
31:28 Reserved
REG_20
395
CV1835

11:0 reg_slvds_n0_sef_eav R/W Sub-LVDS mode: n0 short exposure eav 0x9D2
Sub-LVDS 10-bit SEF EAV n0 (1d8)
15:12 Reserved
27:16 reg_slvds_n1_lef_sav R/W Sub-LVDS mode: n1 long exposure sav 0xC01
Sub-LVDS 12-bit LEF SAV n1 (C01)
ed
31:28 Reserved
w
REG_24
lo
al
11:0 reg_slvds_n1_lef_eav R/W Sub-LVDS mode: n1 long exposure eav 0xDD1
t
no
Sub-LVDS 12-bit LEF EAV n1 (DD1)
e
15:12 Reserved
ar
27:16 reg_slvds_n1_sef_sav R/W Sub-LVDS mode: n1 short exposure sav 0xC02
Sub-LVDS 12-bit SEF SAV n1 (C02)
n
tio

31:28 Reserved
u
ib
REG_28
r
di V
st

re k-

d il
11:0 reg_slvds_n1_sef_eav R/W Sub-LVDS mode: n1 short exposure eav 0xDD2

an M
Sub-LVDS 12-bit SEF EAV n1 (DD2)

n by

31:12 Reserved
tio lic
REG_2C
ca ub

ifi p
11:0 reg_vs_gen_sync_code R/W vs generate sync code value 0xC00

od de

12 reg_vs_gen_by_sync_code R/W vs generate by identical sync code 0x0
M a

M
31:13 Reserved
REG_30
2:0 reg_slvds_lane_mode R/W Sub-LVDS lane mode 0x3
2'b0: 1-lane
2'b1: 2-lane
2'b3: 4-lane
2'b7: 8-lane
3 Reserved
11:4 reg_slvds_sync_source R/W Sub-LVDS output sync source select 0x1
396
CV1835

31:12 Reserved
REG_50
11:0 reg_slvds_n0_lsef_sav R/W SAV for n0 long & short exposure both 0x803
exist line
ed
15:12 Reserved
27:16 reg_slvds_n0_lsef_eav R/W EAV for n0 long & short exposure both 0x9D3
w
exist line
lo
31:28 Reserved
al
t
REG_54
no
e
11:0 reg_slvds_n1_lsef_sav R/W SAV for n1 long & short exposure both 0xC03
ar
exist line
n
15:12 Reserved
tio
27:16 reg_slvds_n1_lsef_eav R/W EAV for n1 long & short exposure both 0xDD3
exist line
u

ib
31:28 Reserved
r
di V
st
REG_58
re k-

d il

an M
13:0 reg_slvds_hdr_p2_hsize R/W Hsize for pattern 2 0xF0

15:14 Reserved
n by
29:16 reg_slvds_hdr_p2_hblank R/W Hblank size for pattern 2 0x14

31:30 Reserved
tio lic
ca ub
REG_60
ifi p

od de
0 reg_hispi_mode R/W HiSPi mode enable 0x0

1'b0: Sub-LVDS
M a
1'b1: HiSPi
M
1 reg_hispi_use_hsize R/W HiSPi DE de-assert by register count 0x0

3:2 Reserved
4 reg_hispi_hdr_psp_mode R/W HiSPi P-SP HDR mode enable 0x0
31:5 Reserved
REG_64
11:0 reg_hispi_norm_sof R/W HiSPi SOF sync code 0xC00
15:12 Reserved
27:16 reg_hispi_norm_eof R/W HiSPi EOF sync code 0xE00
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31:28 Reserved
REG_68
11:0 reg_hispi_hdr_t1_sof R/W HiSPi HDR T1 SOF 0xC00
15:12 Reserved
27:16 reg_hispi_hdr_t1_eof R/W HiSPi HDR T1 EOF 0xE00
ed
31:28 Reserved
w
REG_6C
lo
al
11:0 reg_hispi_hdr_t1_sol R/W HiSPi HDR T1 SOL 0x800
t
15:12 Reserved
no
27:16 reg_hispi_hdr_t1_eol R/W HiSPi HDR T1 EOL 0xA00
31:28 Reserved
e
ar
REG_70 n
tio
11:0 reg_hispi_hdr_t2_sof R/W HiSPi HDR T2 SOF 0xC20
u
15:12 Reserved
ib
27:16 reg_hispi_hdr_t2_eof R/W HiSPi HDR T2 EOF 0xE20

r
31:28 Reserved
di V
st
re k-
REG_74
d il
an M

n by
11:0 reg_hispi_hdr_t2_sol R/W HiSPi HDR T2 SOL 0x820

15:12 Reserved
27:16 reg_hispi_hdr_t2_eol R/W HiSPi HDR T2 EOL 0xA20
tio lic
31:28 Reserved
ca ub
REG_80
ifi p

od de

7:0 reg_dbg_sel R/W Debug signal select 0x0
M a
31:8 Reserved
M
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ISP
10.1Function Overview
ed
Image signal processor (ISP) optimizes the image captured by sensor, including 3A
w
(automatic exposure (AE), automatic white balance (AWB), automatic focus (AF)), black
lo
level correction (BLC), defect pixel correction (DPC), fix pattern noise(FPN), high
al
dynamic range image processing (HDR), Bayer domain noise reduction (BNR), and de
t
no
mosaic (CFA), gamma correction, Dehaze, color space convert (CSC), image sharpen,
time domain noise reduction(3DNR), brightness noise reduction(YNR), color noise
e
reduction(CNR), hsv space conversion(HSV), etc. The specifications it supports are as
follows.
ar
n
tio
Support black level noise reduction

Support defect pixel correction
u
ib
Support Bayer noise reduction

r
di V
st
Support demosaic processing

re k-
Support purple edge correction

d il
an M
Support gamma correction

Support automatic white balance
n by
Support auto exposure

tio lic
Support auto focus

ca ub
Support lens shading correction

ifi p
Support automatic dehaze

od de
Support image sharpen

M a
Support time domain noise reduction

M
Support 8 / 10 / 12 bits of Bayer input data (maximum 12 bits)

The maximum image resolution is 2880x1620@20fps linear input
The maximum image resolution is 2880x1620@20fps output
The minimum horizontal blanking area is 72 pixels
The minimum vertical blanking area is 48 rows
Support IR sensor input
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10.2Overview
10.2.1 Function Block Diagram
As shown in Figure 10-1, ISP can be roughly divided into pre_raw_fe_top、

pre_raw_be_top、raw_top、rgb_top, and yuv_ top according to the format of data
ed
processing. The pre_raw_fe_top has two sets that support dual-camera input, while the
w
pre_raw_be_top is used to process statistical data of pre_raw_fe_top dual-camera input
lo
al
separately. The three main modules, raw_top, rgb_top, and yuv_top, can also be
collectively referred to as post_raw. Figures 10-2, 10-3, 10-4, and 10-5 are detailed block
t
no
diagrams of the four main modules. As the ISP supports dual-camera input, two sets of
e
modules in pre_raw_fe_top are responsible for receiving dual-camera data. The image
ar
data from the two sensors are then processed separately in pre_raw_be_top and
n
post_raw.
u tio
r ib
di V
st
re k-
d il
Figure 10- 1 ISP Overall Structure Diagram

an M
n by
The following figure shows the basic module diagram of pre_raw_fe and pre_raw_be.
tio lic
The CSI_BRG of pre_raw_fe receives signals from the sensor side, and the data stream is
ca ub
divided into two paths. One path is directly stored in DRAM or transmitted to
ifi p
pre_raw_be, while the other path is cropped to the desired processing size, and then
od de
RGBMAP statistics and WBG correction are performed, and the data is stored in DRAM.
M a
M
The input data of pre_raw_be is the raw data sent by pre_raw_fe through DRAM or
direct transmission. After being processed by crop, BLC, and DPC, one path is directly
sent to post_raw for processing of RGB Bayer data, or it is first stored in DRAM and then
extracted by post_raw from DRAM. The AF statistics data is directly written to DRAM.
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ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
Figure 10- 2 Pre_raw_fe and Pre_raw_be Module Diagram
The following is the basic block diagram of the raw_top module. The long and short
tio lic
exposure data are processed by modules such as CROP, BNR, LSC, CFA, RGBCAC, and
ca ub
LCAC to generate RGB data, which is then sent to rgb_top. The parallel statistical
ifi p
processing is divided into two paths: one is processed by AE and GMS after LSC module
od de
processing and the data is stored in DRAM, and the other is processed by WBG and
M a
M
then processed by LMAP and stored in DRAM for reference in subsequent WDR
processing.
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ed
w
lo
al
Figure 10- 3 raw_top Module Diagram
t
no
The following is the basic module diagram of rgb_top. Its input is the processed RGB
e
data from raw_top. The data is processed through modules such as CCM, HDR
ar
(Fusion+LTM), User gamma, Gamma, Dehaze, and CLUT, and then converted to the YUV
n
domain by the RGB2YUV (CSC) module. The YUV data is then transferred to YUV_TOP.
tio
The other path is the statistical data path, which is processed by Hist_v after CCM
u
processing and then stored in the DRAM.

r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
Figure 10- 4 rgb_top Module Diagram

ifi p
The first module in yuv_top is PRE_EE which does the first round of edge enhancement.
od de
3DNR then works on temporal domain for noise reduction. The brightness and color
M a
M
information are then separately processed in spatial domain using YUV422 format for
noise reduction (YNR, CNR). After brightness noise reduction, it will go through
SHARPPEN(EE) and then the brightness and chroma information will be combined for
DCI, LDCI, and CA processing. The brightness and chroma information will then be split
again. The brightness goes through the Ycurve module while the chroma information
goes through the CA2 module. After passing through the image size cropping module
(Crop) once more, the entire ISP image processing process is complete.
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Figure 10- 5 yuv_top Module Diagram
ed
w
10.2.2 Working Mode
lo
al
- The maximum 12 bit Bayer input is supported. When the input is less than 12 bit, the
t
lower bit will be 0
no
Raw 8 = {data_in[7:0],4’b0}
e
Raw 10 = {data_in[9:0], 2’b0}
ar
- Support any RG, GB order interchange n
- Support IR sensor
tio
- Support two in one WDR

u
- Support single brightness component mode (abandon UV data, output in pure

r ib
brightness mode))
di V
st
re k-
d il
10.3ISP Interruption System

an M
n by

tio lic
ca ub
Hardware interrupt events of ISP are detailed in Table 10-1.

ifi p
od de
Table 10- 1 Interrupt Indication Register

M a
M
地址状态位清除位描述
1 : 有中断 (写 1 清成 0)
0 : 无中断
0x0A07_0000 bit[29] bit[29] post_raw register update completed
(shadow update done) interrupt
bit[24] bit[24] pre_raw_be channel 0 update
completed (shadow update
done)intertupt
bit[19] bit[19] pre_raw_fe0 channel 3 update
completed (shadow update
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地址状态位清除位描述
1 : 有中断 (写 1 清成 0)
0 : 无中断
done)interrupt
bit[18] bit[18] pre_raw_fe0 channel 2 register update
completed (shadow update done)
interrupt
ed
w
interrupt
lo
al
interrupt
t
no
bit[10] bit[10] post_raw frame done interrupt
bit[8] bit[8] pre_raw_be channel 0 frame done
e
interrupt
ar
bit[3] bit[3] pre_raw_fe0 channel 3 frame done
n
interrupt
tio

interrupt
u
ib

r
interrupt
di V
st

re k-
interrupt
d il
an M
0x0A07_0008 bit[16] bit[16] dma error interrupt

bit[14] bit[14] post_raw transmission specified line
n by
completed interrupt
bit[11] bit[11] pre_raw_fe0 transmission specified
tio lic
line completed interrupt

ca ub
bit[10] bit[10] command queue completed interrupt

ifi p
bit[8] bit[8] pre_raw_fe frame error interrupt

bit[3] bit[3] pre_raw_fe0 channel 3 frame start
od de
interrupt
M a

M
interrupt
interrupt
interrupt
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10.3.2 Interrupt Timing
Interruption is mainly divided into several parts.
a. pre_raw_fe0/pre_raw_be/post_raw frame completion interrupt: indicates

that the last pixel of a frame has been transmitted.
ed
b. pre_raw_fe0/pre_raw_be/post_raw register completion interrupt:
w
indicates that the register has updated the working register from the
lo
shadow register, and the user can continue to write the register settings
al
of the next frame into the shadow register.
t
no
c. p re_raw_fe0 frame error interrupt: when an error condition (ex. drop
frame or csi bridge fifo overflow) occurs in the transmission process, ISP
e
ar
will send this interrupt to inform the user that the error detection is in
pre_raw_fe0, so post_ raw will not have this interrupt.
n
tio
d. Instruction queue interrupt: in the instruction queue mode, when the last
u
instruction is completed, this interrupt will be sent to inform the user.

ib
e. p re_raw_fe0 frame start interrupt: this interrupt will be sent at the

r
di V
st
beginning of each frame, which makes it convenient for users to calculate

re k-
the number of frames currently transmitted. Only pre_raw_fe0 detects the

d il
an M
start of the frame, so post_ raw will not have this interrupt.
n by
f. pre_raw_fe0/post_raw completes the specified line interrupt: in some

special applications, the user can specify that the interrupt will be sent
tio lic
when the transmission reach a certain line, rather than when the last
ca ub
frame is completed.
ifi p
od de
Figure 10-6 is the timing diagram of ISP interrupt under normal transmission condition.
M a
Frame start -- > shadow update done -- > frame done will occur in sequence
M
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ed
w
lo
al
Figure 10- 6 ISP Timing Diagram when Interrupt occurs
t
no
e
10.4Module Function
ar
n
tio
10.4.1 Color_bar (patgen)

u
ib
The graphics generator provides three modes of images.

r
di V
a. Solid color map

st
re k-
b. Horizontal color block

d il
an M
c. Vertical color block

All modes support gradient color, and the gradient degree automatically matches
n by
the image size.

tio lic
ca ub
10.4.2 Crop
ifi p
The module can cut the input image, as shown in Figure 10-7.
od de
M a
M
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ed
w
lo
al
t
no
Figure 10- 7 Image Cutting Diagram
e
10.4.3 AE (Auto Exposure) ar
n
tio
Auto exposure collects image data in Bayer domain, and then uses software
u
ib
algorithm to realize auto focus (AF).

r
di V
st
Automatic exposure (AE) statistical information cuts the image into 32x30 blocks,
re k-
accumulates the values of the pixels in each block according to the (R, G, b) three
d il
an M
fields, counts the number of points in the R/G/B three fields at the same time,
and finally outputs them to the memory (DRAM), and then uses the software
n by
algorithm in order to make further AE decision.

tio lic
The AE module also includes AWB statistics. The AWB statistics information uses
ca ub
a 34x30 block to accumulate the values of pixels in the R/G/B three domains that
ifi p
fall within the specified upper and lower threshold values, and counts the
od de
number of pixels that meet the threshold values. Finally, the information is
M a
output to DRAM and further AWB decisions are made using algorithms.
M
10.4.4 AF (Auto Focus)
AF (auto focus) collects image data in Bayer domain, and then uses software
algorithm to realize the function of AF.
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AF statistics engine cuts the image into 17x15 blocks, makes a series of vertical
and horizontal high-pass filters and low-pass filters for the pixels in each block
with a 17x5 moving window, counts the number of highlight points in each block,
and finally outputs them to DRAM, and then uses software algorithm to make
further AF decision.
ed
10.4.5 DIS (Digital image stabilization)
w
lo
DIS (Digital image stabilization) realizes the function of anti-shaking for images
al
in Bayer domain.
t
no
DIS will collect the histogram of cumulative number of green pixels in X and Y
e
directions in 3x3 blocks of the image, and then output it to DRAM for further DIS
ar
decision. n
u tio
10.4.6 BLC (Black level correction)

r ib
di V
st
BLC (black level correction) provides the function of adding and subtracting
re k-
color difference or multiplying digital gain in Bayer domain. R / Gr / Gb / B has

d il
an M
corresponding registers.
n by
10.4.7 DG (Digital Gain)

tio lic
ca ub
DG (Digital gain) provides the function of multiplying the image in Bayer domain
ifi p
by digital gain. R / Gr / Gb / B has corresponding registers.

od de
10.4.8 DPC
M a
M
DPC aims to detect and compensate the bad points, which is divided into two
parts: static bad points and dynamic bad points. Static bad points can be filled in
the internal SRAM by software in advance, while dynamic bad points are
detected dynamically in the process of image moving to compensate for single
bad point and bad point aggregation.
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10.4.9 GE
GE aims to correct the phenomenon that the pixel values of Gr and Gb are not
equal when the sensor leaves the factory, the phenomenon that will lead to
irregular noise in the image. After GE compensates the pixels of Gr and Gb, the
gap between them is narrowed and the crosstalk phenomenon is removed.
ed
w
lo
10.4.10 LSC (Lens shading correction)
al
t
LSC (lens shading correction) is used to correct the dark area of lens. Due to the
no
optical properties of the lens, the image in the corner area may be darker than
e
that in the central area, so we need to use gain compensation. LSC provides
ar
37x37 gain matrix of four components (R, Gr, Gb, B) for correction. The 37x37
n
gain matrix is evenly distributed to the input image and uniformly compensated
tio
on each phase element by interpolation.

u
ib
10.4.11 DRC (LTM)

r
di V
st
re k-
DRC (Dynamic Range Control) adjusts the color intensity by dynamically

d il
an M
converting the values with a larger value range to a smaller value range. It
n by
selectively enhances the image contrast in different regions while preserving the
details of the edges, making the image more suitable for display and human
tio lic
observation.
ca ub
ifi p
10.4.12 WBG (White Balance Gain)

od de
M a
WBG (white balance gain) provides the function of multiplying the image in
M
Bayer domain by digital gain. R / Gr / Gb / B has corresponding registers.
10.4.13 BNR (Bayer Noise Reduction)
BNR module in Bayer domain pixel data achieves image denoising. The purpose
is to remove the noise, while retaining the details. The module can eliminate the
sensor noise according to the noise model provided by users.
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10.4.14 DEMOSAIC (CFA)
The purpose of demosaicing is to reconstruct the original pixels into complete R,

G, B three-color pixels. Through the image orientation characteristics and edge
detection, interpolation is performed on the surrounding pixels to produce
accurate and high-resolution pixels. The RGBCAC module is introduced to
ed
eliminate the chromatic aberration (purple fringing) distortion commonly
w
caused by lenses in chroma.
lo
al
10.4.15 CCM
t
no
It is to convert the R, G, B obtained by the sensor into the standard R, G, B format
e
through linear transformation. Using 3x3 array, the parameter is s3.10. Using the
ar
array CCM parameters corrected in advance under different color temperatures,
n
Firmware dynamically calculates the CCM parameters according to the current
tio
image color temperature or image brightness.

u
r ib
di V
st
re k-
d il
an M
n by
10.4.16 Gamma
tio lic
ca ub
Gamma is an exponential function to adjust the pixel value according to the

ifi p
brightness of the scene. Here we use a 257-point table, where each element is
od de
12bit and is used for adjustment and interpolation. R, G and B can support the
M a
dynamic adjustment of different curves.

M
10.4.17 Dehaze
Dehaze aims at the function of demisting. By analyzing the image scene and
calculating the ambient light source, the contrast difference between the fog
area and the surrounding area can be obtained. Based on the contrast difference,
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the pixels in the fog area can be enhanced to achieve the effect of fog area
removal.
10.4.18 CSC
CSC transforms R, G, B to Y, U, V through 3x3 matrix.
ed
10.4.19 3DNR (3-Dimensional Noise Reduction)
w
lo
Combining the noise suppression function of time domain (adjacent frame) and
al
space domain (surrounding pixel) calculus, the picture is smoother.
t
no
10.4.20 YNR
e
ar
In the luminance Y domain, the noise suppression in the spatial domain is
n
implemented with reference to the information of the surrounding pixels and the
tio
motion of the object.

u
ib
10.4.21 LDCI (DCI)

r
di V
st
re k-
d il
LDCI is based on the equalization of the region histogram, using enhanced

an M
region saturation to improve the details of the dark region and the performance
n by
of high-frequency parts.
tio lic
10.4.22 Sharpen
ca ub
ifi p
Sharpen the middle frequency and high frequency edges of the image to
od de
highlight the details of the image. The image details can be divided into material area,
M a
texture and directional edge. The texture area or edge area can be adjusted separately
M
according to the needs to enhance part of the image details, avoiding noise
enhancement caused by single sharpening method and achieving better visual effect.
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10.4.23 CNR
CNR implements noise suppression in spatial domain in terms of chroma

information, peripheral pixel information and object motion in chroma UV
domain.
ed
10.4.24 CAC (PFC inside CNR)
w
CNR acts on YUV domain and can be used to reduce the noise of chroma. PFC
lo
al
acts at the end of CNR, and its function is to further eliminate the phenomenon
t
of purple fringes, which is common in chroma.
no
10.4.25 CLUT (HSV_3D_LUT)
e
ar
CLUT (Color Look-Up Table) uses a 3D LUT (Lookup Table) with a size of 17x17x17
n
tio
in the RGB color space to perform three-dimensional color adjustment

operations, and the adjustment direction of each color in each region can be
u
ib
independently controlled.
r
di V
st
re k-
10.4.26 RGBCAC
d il
an M
RGBCAC corrects purple fringing in the RGB data field after CFA processing.
n by
10.4.27 PREYEE
tio lic
ca ub
The module functions the same as sharpen, but is located in front of NR.
ifi p
od de
10.4.28 Hist_V
M a
M
Hist_V is used to calculate the histogram of brightness as the basis for adjusting
brightness weights.
10.4.29 CACP
The CA mode provides the ability to multiply the chroma by different gain values
determined by the luminance (Luma) and sensitivity luminance (ISO), while the CP
mode provides different color results directly corresponding to different brightness.
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10.4.30 CA2
CA_LITE provides the ability to multiply the chroma by gain values determined by
different saturation levels.
10.4.31 LCAC
ed
Also known as Local Chromatic Aberration Cancellation, its function is to eliminate
w
regional purple fringing. Purple fringing is easy to occur at the junction of high and low
lo
al
brightness, and this function can be turned on for purple fringing removal.
t
no
10.4.32 User Gamma
e
ar
Brightness value gamma correction performed before gamma correction in the RGB
domain.
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
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Audio interface
11.1AIAO
ed
11.1.1 Overview
w
lo
The Audio Input/Audio Output interface is used for connecting with the built-in Audio
al
Codec or external Audio Codec and the digital microphone to complete the
t
no
transmitting and receiving of audio data and realize the functions of recording, playing
and intercom. The AIAO related modules are integrated into a subsystem. The built-in
e
ar
Audio Codec ADC/DAC can support stereo input and output. The AIAO integrates four
sets of I2S TX/RX modules and supports two sets of I2S IO interfaces for connecting
n
tio
with external device. The AIAO can transmit and receive the audio data simultaneously
u
and support multi-channel data. The AIAO block diagram is shown as below figure:
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 11-1 AIAO block diagram
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11.1.2 Features
AIAO interface supports both Master-mode and Slave-mode of I2S, PCM, multi-channel
TDM modes. The received audio data or audio data to be transmitted are transferred
ed
using System DMA. The specific features are as follows:
w
lo
High flexible and configurable timing parameters, including frame period,
al
channel period, frame sync signal active period and polarity
t
Configurable clock sampling edge for input and output signals
no
Support transmitting and receiving stereo audio data in I2S master and slave
e
modes
ar
Support transmitting and receiving stereo and mono audio data in PCM master
n
and slave modes
tio
Support transmitting and receiving multi-channel audio data in TDM master and
u
slave modes
r ib
Transmitting and receiving operations can be enabled individually or

di V
st
re k-
simultaneously
d il
an M
n by
11.1.2.1 PCM interface

tio lic
Support 16-bit data

ca ub
Frame sync signal supports short pulse (one bit clock cycle) and long pulse
ifi p
(configurable number of bit clock cycles)

od de
Supports standard mode and left-justified mode

M a
M
11.1.2.2 I2S interface
Support 16-bit/24-bit data

Support 8kHz ~ 192kHz sampling rate
Configurable LRCK polarity
Supports standard mode and left-justified mode
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AIAO subsystem connects with chip built-in audio codec, I2S IO pins and
transmitter/receiver modules through internal pinmux. It needs to be properly
configured to achieve different connection modes.
ed
11.1.3.1 Typical applications
w
lo
The typical application and connection are described as follows:
al
t
no
Support I2S slave mode to connect with internal Audio Codec ADC, or
I2S/PCM/TDM master or slave mode to connect with external ADC for audio
e
ar
recording n
Support I2S master mode to connect with internal Audio Codec DAC, or
tio
I2S/PCM/TDM master or slave mode to connect with external DAC for audio
u
playback
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 11-2 Example connection of I2S TX/RX module with internal Audio Codec
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ed
w
lo
al
t
no
e
ar
n
u tio
Figure 11-3 Example connection of I2S TX/RX module with external Audio Codec
ib
using slave mode

r
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
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Figure 11-4 Example connection of I2S TX/RX module with external Audio Codec
using master mode
11.1.3.2 Interface timing
ed
The audio source is converted into digital data sample by internal or external Audio
Codec ADC. The data sample is received by RX module through I2S or PCM interface,
w
lo
and stored into the circular buffer within DRAM through DMA. The data sample can be
al
further processed and transfered to storage device to complete the recording function.
t
The TX module reads the digital data sample from the circular buffer through DMA and
no
transmits to internal or external Audio Codec DAC through I2S or PCM interface to
e
complete the audio playback function.
ar
n
The typical I2S interface timing is shown in Figure 11-5.
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
Figure 11-5 I2S interface timing

M a
M
Figure 11-5 takes 24-bit data sample as an example. The data sample is transmitted in
MSB first mode. The MSB delays one BCLK cycle relative to LRCK. The signals are issued
at the falling edge of BCLK and latched at the rising edge of BCLK (tx_sample_edge = 0,
rx_sample_edge = 1). However, it can be configured to use rising edge of BCLK issue
signals and falling edge of BCLK latch signals (tx_sample_edge = 1, rx_sample_edge =0).
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The typical PCM interface standard mode timing is shown in Figure 11-6, and the left-
justified mode timing is shown in Figure 11-7.
ed
w
lo
al
t
no
e
ar
n
Figure 11-6 PCM interface standard mode timing
u tio
ib
Figure 11-6 takes 16-bit data sample as an example. The data sample is transmitted in
r
di V
st
MSB first mode. The MSB delays one BCLK cycle relative to LRCK. The signals are issued
re k-
at the falling edge of BCLK and latched at the rising edge of BCLK (tx_sample_edge = 0,
d il
an M
rx_sample_edge = 1).
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 11-7 PCM interface left-justified mode timing
419
CV1835
In left-justified mode, the MSB of data sample and LRCK signals are issued at the same
BCLK clock cycle.
11.1.4 Operation control
ed
The AIAO subsystem control registers including i2s_tdm_sclk_in_sel, i2s_tdm_fs_in_sel,
i2s_tdm_sdi_in_sel, and i2s_tdm_sdo_out_sel, should be properly configured depending
w
lo
on the audio interface connection prior to enable data transmission.
al
t
no
11.1.4.1 Clock control
e
If AIAO operates at master mode, the register bit master_mode should be set to 1. The
ar
clock division registers I2S_CLK_CTRL1 (mclk_div, bclk_div) should be properly
n
tio
configured depending on data sampling rate, and then set the register aud_en to 1 to
turn-on audio clock source.
u
r ib
di V
st
re k-
11.1.4.2 Soft reset

d il
an M
The four TX/RX modules integrated in AIAO all have individual software reset. Each
n by
module must be applied FIFO_RESET and I2S_RESET before triggering operation.

tio lic
ca ub
11.1.5 AIAO register overview

ifi p
od de
An overview fo the AIAO subsystem registers is shown in Table 11-1.

M a
M
Table 11- 1 AIAO subsystem register overview (base address: 0x0410_8000)

Offset
i2s_tdm_sclk_in_sel 0x000 Select the source of TX/RX module’ SCLK in slave mode.
i2s_tdm_fs_in_sel 0x004 Select the source of TX/RX module’s frame synchronizing
signal in slave mode.
i2s_tdm_sdi_in_sel 0x008 Select the source of RX module’s SDI signal.
i2s_tdm_sdo_out_sel 0x00c Select the source of subsystem’s SDO output.
i2s_bclk_oen_sel 0x030 The output control of BCLK IO.
audio_pdm_ctrl 0x040 Enable PDM mode.
420
CV1835

Offset
i2s_sys_int_en 0x060 Enable the interrupt signal of I2S subsystem.
i2s_sys_ints 0x064 The status of I2S subsystem’s interrupt signal.
I2S_ TDM_ 0~I2S_ TDM_ 3 module registers overview is shown in Table 11-2.
ed
w
Table 11- 2 I2S_TDM_0/1/2/3 register overview (address 0x0410_0000 + n*0x10000)
lo
al
Offset
BLK_MODE_SETTING 0x000 TX/RX module operation control
t
no
FRAME_SETTING 0x004 Audio frame timing control
SLOT_SETTING1 0x008 Channel and data control
SLOT_SETTING2 0x00c Channel enable
e
ar
DATA_FORMAT 0x010 Specify storage data format
BLK_CFG 0x014 TX/RX block config
n
I2S_ENABLE 0x018 TX/RX block enable
tio
I2S_RESET 0x01c TX/RX block reset

I2S_INT_EN 0x020 Interrupt enable
u
ib
I2S_INT 0x024 Interrupt status

r
FIFO_THRESHOLD 0x028 FIFO threshold

di V
st
I2S_LRCK_MASTER 0x02c BCLK/LRCK master generator mode

re k-
FIFO_RESET 0x030 FIFO reset

d il
an M
RX_STATUS 0x040 RX block internal status

TX_STATUS 0x048 TX block internal status
n by
I2S_CLK_CTRL0 0x060 Clock control

I2S_CLK_CTRL1 0x064 Clock divider
tio lic
I2S_PCM_SYNTH 0x068 PCM FS synthesis mode

RX_RD_PORT 0x080 RX FIFO read port
ca ub
TX_WR_PORT 0x0c0 TX FIFO write port

ifi p
od de
M a
M
11.1.6 AIAO register description
11.1.6.1 AIAO subsystem register description
421
CV1835
i2s_tdm_sclk_in_sel
Select sclk source
2:0 i2s_tdm_0_sclk_in_sel R/W Select SCLK input source for i2s_tdm_0 0x4
when operates at slave mode
000 = reserved
001 = From i2s_tdm_1 bclk_out
ed
w
100 = From IO bclk_in_i2s0 (internal
AADC)
lo
101 = From IO bclk_in_i2s1
al
t
3 Reserved
no
e
ar
001 = From internal audio_pdm i2s_sck
n
tio
AADC)
u

ib

r
di V
7 Reserved
st
re k-
d il

an M

010 = reserved
n by

tio lic
AADC)
ca ub

ifi p
11 Reserved
od de
M a

M

011 = reserved
AADC)
31:15 Reserved
i2s_tdm_fs_in_sel
422
CV1835

2:0 i2s_tdm_0_fs_in_sel R/W Select FS input source for i2s_tdm_0 0x4
000 = reserved
001 = From i2s_tdm_1 ws_lrck_fs_out
100 = From IO ws_lrck_fs_in_i2s0
(internal AADC)
ed
w
3 Reserved
lo
al
001 = From internal audio_pdm i2s_lrck
t
no
e
(internal AADC)
ar
n
tio
7 Reserved
u

ib

r

di V
st
010 = reserved
re k-

d il

an M
(internal AADC)
n by

11 Reserved
tio lic

ca ub

ifi p

od de
011 = reserved
M a
(internal AADC)
M

31:15 Reserved
i2s_tdm_sdi_in_sel
2:0 i2s_tdm_0_sdi_in_sel R/W Select SDI input source for i2s_tdm_0 0x4
000 = reserved
001 = From i2s_tdm_1 sdo
423
CV1835

100 = From IO sdi_i2s0 (internal AADC)
101 = From IO sdi_i2s1
3 Reserved
ed
001 = From internal audio_pdm
i2s_sdata
w
lo
al
t
no
7 Reserved
e
ar
010 = reserved
n
tio

u

ib

r
11 Reserved
di V
st
re k-
d il

an M

011 = reserved
n by

tio lic

ca ub
31:15 Reserved
ifi p
i2s_tdm_sdo_out_sel
od de

M a

M
2:0 i2s_tdm_0_sdo_out_sel R/W Only 0x4 is allowed. 0x4

3 Reserved
6:4 i2s_tdm_1_sdo_out_sel R/W Select sdo_i2s1 output from which 0x5
i2s_tdm
100 = select i2s_tdm_0 sdo to IO
sdo_i2s1
sdo_i2s1
sdo_i2s1
sdo_i2s1
others = reserved
424
CV1835

7 Reserved
10:8 i2s_tdm_2_sdo_out_sel R/W Select sdo_i2s2 output from which 0x6
i2s_tdm
sdo_i2s2
sdo_i2s2
sdo_i2s2
ed
sdo_i2s2
w
others = reserved
lo
11 Reserved
al
14:12 i2s_tdm_3_sdo_out_sel R/W Only 0x7 is allowed. 0x7
31:15 Reserved
t
no
i2s_bclk_oen_sel
e
ar
0 i2s0_bclk_oen_sel R/W Reserved 0x0
n
1 i2s1_bclk_oen_sel R/W Select bclk_out_i2s1 IO oen control 0x0
tio
0 = bclk_oen from I2S1 internal

1 = bclk_oen controlled by
u
i2s1_bclk_oen_ext
ib
2 i2s2_bclk_oen_sel R/W Select bclk_out_i2s2 IO oen control 0x0

0 = bclk_oen from I2S2 internal
r
di V
st
1 = bclk_oen controlled by
re k-
i2s2_bclk_oen_ext
3 i2s3_bclk_oen_sel R/W Only 0x0 is allowed. 0x0
d il
an M
7:4 Reserved
8 i2s0_bclk_oen_ext R/W External control bclk_out_i2s0 IO oen 0x0
n by
0 = output disable
1 = output enable
tio lic
0 = output disable
1 = output enable
ca ub

ifi p
0 = output disable
1 = output enable
od de
11 i2s3_bclk_oen_ext R/W Only 0x0 is allowed. 0x0

15:12 Reserved
M a
16
M
i2s_bclk_oen_no_delay R/W Only 0x0 is allowed. 0x0

31:17 Reserved
audio_pdm_ctrl
1:0 audio_pdm_sel_i2s_io R/W Enable PDM mode: 0x0
00 = General operating mode
01 = I2S1 IO operates in PDM mode
10 = I2S2 IO operates in PDM mode
The i2s_tdm_1 RX module is used
to receive data. When this value
425
CV1835

is set to 01, the oen of
I2S1_BCLK IO is fixedly
controlled by the
i2s1_bclk_oen_ext register. When
this value is set to 10, the oen
of I2S2_BCLK IO is fixedly
controlled by the
i2s2_bclk_oen_ext register.
31:2 Reserved
ed
w
lo
i2s_sys_int_en
al
t
no
0 i2s0_int_en R/W Enable I2S0 interrupt 0x1
e
ar
7:4 Reserved n
8 i2s_subsys_int_en R/W Enable I2S_SUBSYS interrupt 0x1
tio
31:9 Reserved
u
i2s_sys_ints
ib

r

di V
st
0 i2s0_int RO I2S0 interrupt status

re k-
When an I2S0 interrupt occurs, the

d il
I2S_INT value in the I2S0 register can be

an M
further read to determine the interrupt

status.
n by

tio lic

ca ub
status.
ifi p

od de

status.
M a

M

status.
31:4 Reserved
426
CV1835
11.1.6.2 I2S_TDM module register description
BLK_MODE_SETTING
ed
0 tx_mode R/W Transmission mode 0x0
0 = RX mode, 1 = TX mode
w
1 master_mode R/W I2S master/slave operation mode 0x0
0 = slave mode, 1 = master mode
lo
2 rx_sample_edge R/W Select sampling clock edge for SDI & 0x0
al
LRCK
0 = negative edge, 1 = positive edge
t
3 tx_sample_edge R/W Select sampling clock edge for SDO in TX 0x0
no
mode
0 = negative edge, 1 = positive edge
e
6:4 Reserved
ar
7 dma_mode R/W DMA transfer mode 0x1
0 = SW mode, 1 = HW DMA mode
n
8 Reserved R/W Multiple I2S synchronous operation 0x0
tio
mode
0 = standalone operation
u
1 = support multi-bit I2S

ib
9 Reserved
r
10 slave_tx_fs_direct_in R/W WS(FS/LRCK) directly input for slave 0x0

di V
st
mode TX
re k-
0 = internally generate WS
d il
1 = select external WS from master

an M
11 Reserved
12 pcm_synth_mode R/W PCM FS use synthesis mode 0x0
n by
0 = PCM FS period controlled by

frame_length
1 = PCM FS period controlled by
tio lic
ck_coef_n & ck_coef_m

ca ub
Only valid for Master mode.

15:13 Reserved
ifi p
31:16 reg_dummy R/W Reserved 0xff00

od de
FRAME_SETTING
M a
M

8:0 frame_length R/W Audio frame length bits 0x1F
0~511 = 1~512 bits
11:9 Reserved
12 fs_polarity R/W Frame sync polarity 0x0
0 = active low, 1 = active high
For I2S mode, set this bit to 0 means left
channel first (LRCK low). For PCM mode,
set this bit to 1 means active high FS
pulse.
13 fs_offset R/W Frame offset, first bit starts: 0x1
0 = the same edge with FS transition
427
CV1835

1 = 1 bit after FS transition
Set this bit to 0 for Left-justified mode.
14 fs_idef R/W Frame sync signal role 0x1
0 = as start of frame (FS, usually 1 bit
clk)
1 = as channel side identification
(WS/LRCK)
Notes: If fs_offset = 1 & fs_idef = 0, one
bit offset will be inserted before MSB of
ed
first data sample for each frame. If
fs_offset = 1 & fs_idef = 1, one bit offset
w
will be inserted before MSB of every
sample whenever WS/LRCK toggle.
lo
15 Reserved
al
23:16 fs_active_length R/W Frame sync (FS/WS/LRCK) active length 0x0F
0~255 = 1~256 bits. The value of
t
no
fs_active_length must less than
frame_length. It is usually half of frame
length in I2S mode, and is 1-bit for
e
PCM/TDM mode.
ar
31:24 Reserved n
SLOT_SETTING1
tio

u

ib
3:0 slot_num R/W Number of slot (channel) per audio 0x1

r
di V
frame
st
re k-
0~15 = 1~16 slots

Set to 1 for two (left/right) channels
d il
I2S/PCM mode.
an M
7:4 Reserved
13:8 slot_size R/W Slot size 0x0F
n by
0~63 = 1~64 bits

15:14 Reserved
tio lic
20:16 data_size R/W data size inside the slot (channel) 0x0F
0~31 = 1~32 bits
ca ub
Set same value for slot_size and

data_size in I2S/PCM mode.
ifi p
23:21 Reserved
od de
28:24 fb_offset R/W data offset inside the Slot 0x0

0 = no offset, 1~31 = 1~31 bits
M a
Set the first valid data bit within each

M
slot.
31:29 Reserved
SLOT_SETTING2
15:0 slot_en R/W Active slot (channel) 0x0003
slot_en[n] = 1 means slot-n is active.
Otherwise, slot-n is inactive.
31:16 Reserved
428
CV1835
DATA_FORMAT
0 data_format R/W Storage data format 0x0
0 = packet mode
1 = reserved
2:1 word_length R/W Word length selection for each data 0x1
sample storage
00 = 8-bit, 01 = 16-bit, 10 = 32-bit, 11 =
ed
reserved
Right align each data sample if size
w
smaller than setting.
lo
3 pad_slot_no R/W Pad slot number to data sample (RX 0x0
only)
al
0 = no
1 = pad 4-bit slot/channel number to
t
no
MSB of each data sample.
For example, if data sample size is 24-bit
and register word_length set to 2'b10,
e
each data will be padded to 32-bit word
ar
as {slot[3:0], 4'h0, data[23:0]}. This
function is no used when data size is
n
equal to word_length.
tio
4 skip_rx_inactive_slot R/W Skip inactive Slot data for receive mode 0x0
0 = store zero instead of received data
u
into FIFO during inactive slot state

ib
1= skip received data during inactive

slot state without store into FIFO
r
di V
st
5 skip_tx_inactive_slot R/W Skip inactive Slot data for transmit 0x0

re k-
mode
0 = Read data from FIFO but transmit
d il
an M
zero to receiver during inactive slot

state
1= directly transmit zero to receiver
n by
without reading FIFO during inactive

slot state
tio lic
6 tx_source_left_align R/W Select left-aligned word data for 0x0

transmit
ca ub
0 = select right-aligned
1 = select left-aligned
ifi p
When word_length is larger than

od de
data_size in TX mode, for example

source data is 32-bit (word_length =
M a
2'b10) and data sample to be

M
transmitted is 24-bit, bits [23:0] of

source data will be selected if set this
bit to 0, and bits [31:8] of source data
will be selected if set this bit to 1.
31:7 Reserved
BLK_CFG
0 force_complete R/W force complete mode 0x0
0 = stop operation until an audio frame
429
CV1835

is received or transmitted complete
after i2s_enable set from 1 to 0
1 = force stop TX or RX operation
immediately after i2s_enable set from 1
to 0
1 dma_req_force_stop R/W dma_req force stop mode 0x1
0 = dma_req keep high until receive
dma_ack after i2s_enable set from 1 to
0
ed
1 = dma_req forced to low after
i2s_enable set from 1 to 0 in dma mode
w
3:2 Reserved
lo
4 auto_disable_with_ch_en R/W I2S FIFO control auto disable 0x0
0 = normal operation
al
1 = FIFO control will automatically stop
operation after DMA channel is disabled
t
no
before I2S is disabled (i2s_enable set to
0). No further RX data will be received
and TX zero bit will be transmitted.
e
5 Reserved
ar
6 rx_start_wait_dma_en R/W I2S receiver block wait DMA enable 0x0
0 = I2S receiver block start operation
n
after i2s_enable set from 0 to 1
tio
1 = I2S receiver block will pend

operation until DMA is enabled
u
7 Reserved
ib
8 rx_blk_clk_force_en R/W I2S receiver block sclk force on 0x0

r
0 = enable clock auto gating

di V
st
1 = always on
re k-
9 rx_fifo_dma_clk_force_en R/W RX FIFO/DMA control block pclk force 0x1

d il
on
an M

1 = always on
n by
15:10 Reserved
16 tx_blk_clk_force_en R/W I2S transmitter block sclk force on 0x0
tio lic

1 = always on
ca ub
17 tx_fifo_dma_clk_force_en R/W TX FIFO/DMA control block pclk force 0x1

on
ifi p

1 = always on
od de
31:18 Reserved
M a
M
I2S_ENABLE
block enable
0 i2s_enable R/W i2s_tdm engine enable 0x0
Must set i2s_reset_tx or i2s_reset_rx to
1 then to 0 firstly before setting
i2s_enable
31:1 Reserved
430
CV1835
I2S_RESET
sw reset
0 i2s_reset_rx R/W Reset receiver block 0x0
0 = nop, 1 = reset
Set to 1 then set to 0 to reset receiver
block. Must add some delay before set
this bit back to 0 due to the signal needs
ed
to be synced from pclk domain to sclk
w
domain.
1 i2s_reset_tx R/W Reset transmitter block 0x0
lo
0 = nop, 1 = reset
al
Set to 1 then set to 0 to reset transmit
block. Must add some delay before set
t
this bit back to 0 due to the signal needs
no
to be synced from pclk domain to sclk
domain.
31:2 Reserved
e
I2S_INT_EN
ar
n
interrupt enable
tio

u

ib
0 rx_fifo_avail_int_en R/W Enable RX FIFO data available interrupt 0x0

r
1 rx_fifo_overflow_int_en R/W Enable RX FIFO overflow interrupt 0x1

di V
st
2 rx_fifo_underflow_int_en R/W Enable RX FIFO underflow interrupt 0x1

re k-
3 Reserved
d il
4 tx_fifo_avail_int_en R/W Enable TX FIFO data available interrupt 0x0

an M
5 tx_fifo_overflow_int_en R/W Enable TX FIFO overflow interrupt 0x1

6 tx_fifo_underflow_int_en R/W Enable TX FIFO underflow interrupt 0x1
n by
7 Reserved
8 i2s_int_en R/W Enable I2S IP interrupt 0x1
tio lic
All I2S interrupt signals are merged into

a 1-bit signal and reflected in the I2S
ca ub
subsystem register i2s_sys_ints.

31:9 Reserved
ifi p
od de
M a
I2S_INT
M
interrupt status
0 rx_fifo_avail_int RO RX FIFO data available interrupt status
This bit will be set to 1 whenever RX
FIFO fullness is larger than
rx_fifo_threshold and
rx_fifo_avail_int_en is 1. Write 1 to
clear.
1 rx_fifo_overflow_int RO RX FIFO overflow interrupt status
Write 1 to clear.
431
CV1835

2 rx_fifo_underflow_int RO RX FIFO underflow interrupt status
Write 1 to clear.
3 Reserved
4 tx_fifo_avail_int RO TX FIFO data available interrupt status
This bit will be set to 1 whenever TX
FIFO emptyness is larger than
tx_fifo_threshold and
tx_fifo_avail_int_en is 1. Write 1 to
clear.
ed
5 tx_fifo_overflow_int RO TX FIFO overflow interrupt status
Write 1 to clear.
w
6 tx_fifo_underflow_int RO TX FIFO underflow interrupt status
lo
Write 1 to clear.
al
7 Reserved
8 rx_fifo_avail_int_raw RO RX FIFO data available interrupt raw
t
status
no
This bit will be set to 1 whenever RX
FIFO fullness is larger than
e
rx_fifo_threshold no matter
ar
rx_fifo_avail_int_en is 1 or 0. Write 1 to
clear.
9 rx_fifo_overflow_int_raw RO RX FIFO overflow interrupt raw status
n
Write 1 to clear.
tio
10 rx_fifo_underflow_int_raw RO RX FIFO underflow interrupt raw status

Write 1 to clear.
u
11 Reserved
ib
12 tx_fifo_avail_int_raw RO TX FIFO data available interrupt raw

r
di V
st
status
re k-
This bit will be set to 1 whenever TX

FIFO emptyness is larger than
d il
tx_fifo_threshold no matter
an M
tx_fifo_avail_int_en is 1 or 0. Write 1 to
clear.
n by
13 tx_fifo_overflow_int_raw RO TX FIFO overflow interrupt raw status

Write 1 to clear.
tio lic
14 tx_fifo_underflow_int_raw RO TX FIFO underflow interrupt raw status

Write 1 to clear.
ca ub
31:15 Reserved
ifi p
FIFO_THRESHOLD
od de

M a

M
4:0 rx_fifo_threshold R/W RX FIFO threshold level 0x7

Issue rx_fifo_avail_int when FIFO
fullness larger than this value
15:5 Reserved
20:16 tx_fifo_threshold R/W TX FIFO threshold level 0x7
Issue tx_fifo_avail_int when FIFO
emptyness larger than this value
23:21 Reserved
28:24 tx_fifo_high_threshold R/W TX FIFO high threshold level 0x1F
Transmit block start when FIFO fullness
larger than this value
31:29 Reserved
432
CV1835
I2S_LRCK_MASTER
block enable
0 i2s_lrck_master_enable R/W Enable i2s_tdm use as bclk/lrck master 0x0
generator
If the i2s_tdm IP need to operate as a
BCLK & LRCK generator master only
without TX or RX data transfer, set
ed
master_mode to 1 and BCLK will start to
w
output after aud_en set to 1. Then LRCK
will start to output after this bit set to 1.
lo
No need to set i2s_enable in this
al
condition. In addition, apply
i2s_reset_rx or i2s_reset_tx before set
t
this bit to 1.
no
31:1 Reserved
e
FIFO_RESET
ar
tio
0 rx_fifo_reset R/W Receive Channel FIFO Reset 0x0

Write 1 then write 0 to reset RX FIFO
u
15:1 Reserved
ib
16 tx_fifo_reset R/W Transmit Channel FIFO Reset 0x0

r
Write 1 then write 0 to reset TX FIFO

di V
st
31:17 Reserved
re k-
d il
RX_STATUS
an M

n by

8:0 rx_frame_size_cnt RO Receive blk internal counter status
tio lic
9 rx_i2s_disable_req RO Internal signal

10 i2s_rx_start_wait RO Internal signal
ca ub
16:11 rx_data_size_cnt RO Receive blk internal counter status

ifi p
22:17 rx_slot_size_cnt RO Receive blk internal counter status

od de
23 i2s_reset_rx_sclk RO i2s_reset_rx in sclk domain

28:24 rx_slot_num_cnt RO Receive blk internal counter status
M a
29 receive_start_sclk RO Receive blk start in sclk domain

M
30 rx_blk_active RO Receive blk active

31 rx_dma_req RO Receive DMA request
TX_STATUS
8:0 tx_frame_size_cnt RO Transmit blk internal counter status
9 tx_i2s_disable_req RO Internal signal
10 i2s_tx_start_wait RO Internal signal
433
CV1835

16:11 tx_data_size_cnt RO Transmit blk internal counter status
22:17 tx_slot_size_cnt RO Transmit blk internal counter status
23 i2s_reset_tx_sclk RO i2s_reset_tx in sclk domain
28:24 tx_slot_num_cnt RO Transmit blk internal counter status
29 transmit_start_sclk RO Transmit blk start in sclk domain
30 tx_blk_active RO Transmit blk active
31 tx_dma_req RO Transmit DMA request
ed
I2S_CLK_CTRL0
w
lo
al
0 aud_clk_sel R/W I2S audio clock (aud_clk) source select 0x0
0 = from audio PLL
t
no
1 = from external mclk_in
2:1 Reserved reserved
3 bclk_out_inv R/W bclk_out clock inverse 0x0
e
0 = bclk_out without inverse
ar
1 = bclk_out inverted
4 bclk_in_inv R/W bclk_in clock inverse 0x0
n
0 = bclk_in without inverse
tio
1 = bclk_in inverted
5 Reserved bclk_in clock inverse
u
0 = bclk_in without inverse

ib
1 = bclk_in inverted
r
6 bclk_out_clk_force_en R/W bclk_out clock force enable 0x1

di V
st
1 = always output
re k-
0 = bclk_out output after transmission

d il
start
an M
7 mclk_out_en R/W mclk_out IO output enable 0x0

0 = disable
n by
1 = enable
8 aud_en R/W I2S clock gen and master signal out 0x0
enable
tio lic
0 = disable clock generator and bclk_out

ca ub
IO
1 = enable clock generator and bclk_out
ifi p
IO
Always set this bit to 0 when I2S
od de
operate at slave mode. When set this

bit to 0, bclk generated from internal
M a
clock generator will be gated and clock

M
dividor of bclk and mclk will be reset.

Specify mclk_div or bclk_div before set
aud_en to 1.
31:9 Reserved
I2S_CLK_CTRL1
15:0 mclk_div R/W mclk clock divider from audio clock 0x2
1 = div 1, 2 = div 2, …
31:16 bclk_div R/W bclk clock divider from audio clock (for 0x2
434
CV1835

master mode only)
1 = div 1, 2 = div 2, …
I2S_PCM_SYNTH
11:0 ck_coef_n R/W PCM FS period synthesis timing 0x1
coefficient N
ed
The frequency of FS for PCM mode =
BCLK * (N/M) when pcm_synth_mode
w
set to 1.
lo
The value of ck_coef_n must smaller
than ck_coef_m.
al
15:12 Reserved
t
31:16 ck_coef_m R/W PCM FS period synthesis timing 0x40
no
coefficient M
The frequency of FS for PCM mode =
BCLK * (N/M) when pcm_synth_mode
e
set to 1.
RX_RD_PORT ar
n
tio

u
31:0 rx_rd_port RO Receive data FIFO Read Port

r ib
di V
st
TX_WR_PORT
re k-

d il
an M

31:0 tx_wr_port WO Transmit data FIFO Write Port 0x0
n by
tio lic
ca ub
11.2Audio Codec
ifi p
od de
11.2.1 Overview
M a
M
The chip integrates high-performance Audio Codec, including stereo playback DAC
(90dB DR A-Weighted), supporting two single-end lineout; stereo recording ADC (90dB
DR A-Weighted), supporting stereo single-end input.
90dB DR A-Weighted stereo DAC
435
CV1835
Stereo single-end Lineout

Digital volume control range of DAC: - 24dB ~ 0dB;
The DAC supports 8kHz ~ 48kHz sampling rate
90dB DR A-Weighted stereo ADC
The gain range of ADC PGA is 0dB ~ 48dB
The ADC supports 8kHz~48kHz sampling rate
ed
The ADC supports Mic in stereo single-end input or line in stereo single-end input
w
lo
11.2.3 Audio Codec register overview
al
t
no
11.2.3.1 Audio DAC/ADC register overview
e
ar
Offset
txdac_ctrl0 0x000 n
txdac_ctrl1 0x004
tio
txdac_status 0x008
u
txdac_afe0 0x00c
ib
txdac_afe1 0x010
r
txdac_ana0 0x020
di V
st
re k-
txdac_ana1 0x024
d il
rxadc_ctrl0 0x100
an M
rxadcc_ctrl1 0x104
rxadc_status 0x108
n by
rxadc_ana0 0x110
tio lic
rxadc_ana1 0x114
rxadc_ana2 0x118
ca ub
rxadc_ana3 0x11c
ifi p
rxadc_ana4 0x120
od de
M a
M
11.2.3.2 Audio ADC Register Description
rxadc_ctrl0
0 reg_rxadc_en R/W 0x0
1 reg_i2s_tx_en R/W 0x0
436
CV1835

31:2 Reserved
rxadcc_ctrl1
1:0 reg_rxadc_cic_opt R/W CIC decimation filter option 0x0
ed
0: downsample ratio 64
w
lo
al
t
no
2 reg_rxadc_chn_swap R/W L/R input data channel swap 0x0
3 reg_rxadc_single R/W Only single channel supported, 0x0
e
used when ANALOG in differential
ar
input mode
n
tio
6:4 reg_rxadc_dcb_opt R/W DC blocking filter option 0x5
3'b000: bypass
u
ib
3'b001: 1-2^(-8)
r
3'b010: 1-2^(-9)
di V
st
re k-
3'b011: 1-2^(-10)
d il
3'b100: 1-2^(-11)
an M
3'b101: 1-2^(-12)
n by
other: bypass
tio lic
7 Reserved
ca ub
8 reg_rxadc_igr_init R/W i2s keep silence when filter 0x0

with initial value
ifi p
9 reg_rxadc_clk_force_en R/W force clock enable 0x0

od de
10 reg_rxadc_fsm_src_sel R/W FSM trigger source 0x0

M a
M
0: adc0_vld
1: adc1_vld
31:11 Reserved
rxadc_status
0 reg_rxadc_cic0_init_done RO cic_d_0 init done
1 reg_rxadc_fir1_0_init_done RO fir1_0 init done
437
CV1835

3 Reserved
4 reg_rxadc_cic1_init_done RO cic_d_1 init done
7 Reserved
10:8 reg_rxadc_fsm RO ADC FSM state
31:11 Reserved
ed
rxadc_ana0
w
lo
al
12:0 reg_gstepl_rxpga R/W PGA feedback resistance selection 0x0001
2dB/step default:20Kohm
t
no
13 reg_g6dbl_rxpga R/W PGA input resistance selection 0x0
0:20Kohm 1:10Kohm
15:14 reg_gainl_rxadc R/W PGA input resistance selection 0x0
e
0:20Kohm(0dB)
ar
1:10Kohm(6dB)
2: 5Kohm(12dB)
n
3: 2.5Kohm(18dB)
tio
28:16 reg_gstepr_rxpga R/W PGA feedback resistance selection 0x0001

2dB/step default:20Kohm
u
29 reg_g6dbr_rxpga R/W PGA input resistance selection 0x0

ib
0:20Kohm 1:10Kohm
r
31:30 reg_gainr_rxadc R/W PGA input resistance selection 0x0

di V
st
0:20Kohm(0dB)
re k-
1:10Kohm(6dB)
2: 5Kohm(12dB)
d il
an M
3: 2.5Kohm(18dB)
n by
rxadc_ana1
tio lic

ca ub
15:0 reg_gainl_status RO [12:0]: gstep1

[13]: g6dbl
ifi p
[15:14]: gainl
31:16 reg_gainr_status RO [28:16]: gstepr
od de
[29]: g6dbr
[31:30]: gainr
M a
M
rxadc_ana2
0 reg_mutel_rxpga R/W Enable pin of mute left channel, active 0x0
high
1 reg_muter_rxpga R/W Enable pin of mute right channel, active 0x0
high
15:2 Reserved
16 reg_diff_en_rxpga R/W Enable pin of differential mode(Left 0x0
channel only,
VIN/VINB=PAD_VINL/PAD_VINR
438
CV1835

17 reg_tristate_rxpga R/W ? 0x0
31:18 Reserved
rxadc_ana3
0 reg_addi_rxadc R/W ADC opamp current +50%, active High 0x0
ed
1 reg_cksel_rxadc R/W PGA enable control input, active High 0x0
2 reg_en_asar_i_rxadc R/W Enable pin of L channel quantizer 0x1
w
3 reg_en_asar_q_rxadc R/W Enable pin of Q channel quantizer 0x1
5:4 reg_dem_type_rxadc R/W DEM TYPE 0x1
lo
0:rotation
al
1: min cell switching
2/3: NA
t
7:6 Reserved
no
11:8 reg_ctune_rxadc R/W RXADC integrator CFB selection 0xc
12*135fF + (8/4/2/1)*135fF
e
12 reg_en_dither_rxadc R/W Enable pin of dithering 0x1
ar
13 reg_rstsdm_rxadc R/W Enable pin of resetting integrator 0x0
14 reg_en_vcmt_rxadc R/W ? 0x0
n
15 Reserved
tio
17:16 reg_vldo0p9_rxadc R/W 0.9V LDO output selection 0x1

00:0.85V
u
01:0.9V
ib
10:0.95V
r
11:1.0V
di V
st
19:18 reg_vldo12_rxadc R/W 1.2V LDO output selection 0x1

re k-
00:1.1V
d il
01:1.15V
an M
10:1.2V
11:1.25V
n by
21:20 reg_rnlvl_rxadc R/W Dither option 0x0

31:22 Reserved
tio lic
rxadc_ana4
ca ub

ifi p

od de
0 reg_da_en_rxpga_status RO DA_EN_RXPGA status

1 reg_da_end2us_rxpga_status RO DA_END2US_RXPGA status
M a
2 reg_da_en_rxadc_status RO DA_EN_RXADC status

M
3 reg_da_en_audbias_status RO DA_EN_AUDBIAS status

15:4 Reserved
18:16 reg_ad_dol_rxadc RO Left channel 3-bits output
19 Reserved
22:20 reg_ad_dor_rxadc RO Right channel 3-bits output
31:23 Reserved
439
CV1835
11.2.3.3 Audio DAC Register Description
txdac_ctrl0
ed
0 reg_txdac_en R/W audio dac enable 0x0
1 reg_i2s_rx_en R/W audio dac i2s output enable 0x0
w
31:2 Reserved
lo
txdac_ctrl1
al
t
no
1:0 reg_txdac_cic_opt R/W CIC decimation filter option 0x0
e
ar
0: upsample ratio 64
n
tio

u

ib
3:2 Reserved
r
di V
st
5:4 reg_txdac_dem_type R/W DEM TYPE 0x1

re k-
0:rotation
d il
an M
1: min cell switching

n by
2/3: thermal code
7:6 Reserved
tio lic
8 reg_txdac_dsm_opt R/W DSM order option 0x0

ca ub
0: order2
ifi p
1: order1
od de
9 reg_txdac_zcd_en R/W enable zero corssing function 0x0

M a
move from reg_spare0

M
10 reg_txdac_fsm_src_sel R/W FSM trigger source 0x1

0: i2s1_vld
1: i2s0_vld
11 Reserved
14:12 reg_txdac_dither_opt R/W Dither option 0x0
0: disable
others: weight = LSB/(2^(n-1))
440
CV1835
31:15 Reserved
txdac_status
ed
2:0 reg_txdac_fsm RO DAC main fsm state
3 Reserved
w
6:4 reg_txdac_afe_fsm RO DAC AFE fsm state
lo
7 Reserved
al
16:8 reg_txdac_gain0 RO DAC L-channel gain
t
19:17 Reserved
no
28:20 reg_txdac_gain1 RO DAC R-channel gain
31:29 Reserved
e
ar
txdac_afe0 n
tio

u
5:0 reg_txdac_init_dly_cnt R/W DAC AFE initialize delay, min>2us 0x28

ib
7:6 Reserved
r
di V
st
re k-
15:8 reg_txdac_value_tick R/W DAC AFE tick value for 0x0

d il
initialize/stop value ramp

an M
27:16 reg_txdac_gain_tick R/W DAC AFE tick value for gain ramp 0x800
n by
31:28 Reserved
tio lic
txdac_afe1
ca ub

ifi p
8:0 reg_txdac_gain_ub_0 R/W channel 0, L-channel, DAC gain upper 0xff

od de
bound
0x00: gain=0
M a
0xff: gain=1-2^(-8), default value to

M
prevent DSM overflow

0x100: gain=1
15:9 Reserved
24:16 reg_txdac_gain_ub_1 R/W channel 1, R-channel, DAC gain upper 0xff
bound
0x00: gain=0
0xff: gain=1-2^(-8), default value to
prevent DSM overflow
0x100: gain=1
27:25 Reserved
28 reg_txdac_ramp_bp R/W bypass initial ramp procedure 0x0
31:29 Reserved
441
CV1835
txdac_ana0
0 reg_addi_txdac R/W na 0x0
3:1 Reserved
5:4 reg_tsel_txdac R/W 2'b00: NA 0x0
2'b01: VCM
2'b10: VDD15A
2'b11: undefined
ed
7:6 Reserved
w
9:8 reg_vsel_txdac R/W 1.5V LDO output selection 0x3
2'b00:1.35V
lo
2'b01:1.4V
al
2'b10:1.45V
2'b11:1.5V
t
31:10 Reserved
no
txdac_ana1
e
ar
n
0 reg_da_en_txdac_ow_val R/W DA_EN_TXDAC overwrite value 0x0
tio
1 reg_da_end2us_txdac_ow_val R/W DA_END2US_TXDAC overwrite value 0x0

15:2 Reserved
u
16 reg_da_en_txdac_ow_en R/W DA_EN_TXDAC overwrite enable 0x0

ib
17 reg_da_end2us_txdac_ow_en R/W DA_END2US_TXDAC overwrite enable 0x0

r
31:18 Reserved
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
442
CV1835
Peripherals equipment
12.1I2C
ed
12.1.1 Overview
w
lo
There are five I2C controllers in the chip. Each I2C controller can be individually
al
configured as Master / Slave. For IO configuration, please refer to chapter 2.2 pin
t
no
information description.
e
ar
n
I2C controller has the following features:
tio
 Support standard address (7bit) and extended address (10bit).

u
ib
 The transmission rate supports standard mode (100kbit/S) and fast mode
r
(400kbits/S).
di V
st
re k-
 Support the functions of general call and start byte.

d il
an M
 It does not support CBUS devices.

 Support DMA operation.
n by
 Support 64X8bits TX FIFO and 64X8bits RX FIFO.

tio lic
ca ub
12.1.3 Function block diagram

ifi p
od de
Figure 12-1 shows the functional block diagram of I2C module. IIC_CLK is the module
M a
M
clock, and could be 25MHz or 100MHz. CPU configures registers through APB bus to
select I2C modes and timing, writes TXFIFO, reads RXFIFO, and triggers FSM to send and
receive SDA / SCL related IO signals. System DMA can also be used with I2C DMA_IF,
and write TXFIFO and read RXFIFO through APB bus to send and receive I2C signal.
443
CV1835
ed
w
lo
al
t
no
Figure 12-1 I2C function block diagram
e
12.1.4 I2C Agreement timing
ar
n
The I2C protocol timing of chip I2C supporting general standards is shown in Figure 12-
tio
2.
u
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 12-2 I2C protocol timing
444
CV1835
12.1.5 Working mode
12.1.5.1 Configure I2C clock and timing parameters
1. Refer to the register chapter of CLK_DIV CRG , configure clk_byp_0_31 to select

25MHz or 100MHz to be clock source of IIC_CLK.
ed
2. Setting related timing configuration should be in controller disable state. The
w
IC_ENABLE needs to be set 0 and query IC_ENABLE_Status [0] confirmed to be 0.
lo
3. Refer to table 12-1, according to the frequency of IIC_CLK to config controller
al
registers.
t
no
e
Table 12-1 Relationship between I2C clock selection and related register
ar
configuration n
tio
Register 25M IIC_CLK 100M IIC_CLK Description
IC_SS_SCL_HCNT 115 460 SCL high level time counting in standard
u
speed mode
ib
IC_SS_SCL_LCNT 135 540 SCL low level time counting in standard

r
di V
speed mode
st
re k-
IC_FS_SCL_HCNT 21 90 SCL high level time counting in fast speed

mode
d il
an M
IC_FS_SCL_LCNT 42 160 SCL low level time counting in fast speed

mode
n by
IC_SDA_HOLD 1 1 SDA holding time count, relative to the

negative edge of SCL
tio lic
IC_SDA_SETUP 6 25 SDA set time count, relative to positive

ca ub
edge of SCL
IC_FS_SPKLEN 2 5 I2C burr suppression time count
ifi p
od de
M a
M
445
CV1835
12.1.5.2 Data transmission in non DMA mode
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
Figure 12-3 data transmission software flow in I2C non DMA mode
M a
M
446
CV1835
12.1.5.3 Data transmission in DMA mode
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 12-4 data transmission software flow under I2C DMA mode
12.1.6 I2C register overview
Base addresses of the 6 group I2C modules on the chip.
447
CV1835
GPIO Module Base Address

I2C0 0x04000000
I2C1 0x04010000
I2C2 0x04020000
I2C3 0x04030000
I2C4 0x04040000
RTCSYS_I2C 0x0502B000
ed
I2C register overview of chip
w
Offset
lo
IC_CON 0x000 I2C Control
al
IC_TAR 0x004 I2C Target Address
IC_SAR 0x008 I2C Slave Address
t
IC_DATA_CMD 0x010 I2C Rx/Tx Data Buffer and Command
no
IC_SS_SCL_HCNT 0x014 Standard speed I2C Clock SCL High Count
IC_SS_SCL_LCNT 0x018 Standard speed I2C Clock SCL Low Count
e
IC_FS_SCL_HCNT 0x01c Fast speed I2C Clock SCL High Count
ar
IC_FS_SCL_LCNT 0x020 Fast speed I2C Clock SCL Low Count
IC_INTR_STAT 0x02c I2C Interrupt Status
n
IC_INTR_MASK 0x030 I2C Interrupt Mask
tio
IC_RAW_INTR_STAT 0x034 I2C Raw Interrupt Status

IC_RX_TL 0x038 I2C Receive FIFO Threshold
u
IC_TX_TL 0x03c I2C Transmit FIFO Threshold

ib
IC_CLR_INTR 0x040 Clear Combined and Individual Interrupts

r
IC_CLR_RX_UNDER 0x044 Clear RX_UNDER Interrupt

di V
st
IC_CLR_RX_OVER 0x048 Clear RX_OVER Interrupt

re k-
IC_CLR_TX_OVER 0x04c Clear TX_OVER Interrupt

d il
IC_CLR_RD_REQ 0x050 Clear RD_REQ Interrupt

an M
IC_CLR_TX_ABRT 0x054 Clear TX_ABRT Interrupt

IC_CLR_RX_DONE 0x058 Clear RX_DONE Interrupt
n by
IC_CLR_ACTIVITY 0x05c Clear ACTIVITY Interrupt

IC_CLR_STOP_DET 0x060 Clear STOP_DET Interrupt
IC_CLR_START_DET 0x064 Clear START_DET Interrupt
tio lic
IC_CLR_GEN_CALL 0x068 Clear GEN_CALL Interrupt

ca ub
IC_ENABLE 0x06c I2C Enable

IC_STATUS 0x070 I2C Status register
ifi p
IC_TXFLR 0x074 Transmit FIFO Level Register

IC_RXFLR 0x078 Receive FIFO Level Register
od de
IC_SDA_HOLD 0x07c SDA hold time length register

M a
IC_TX_ABRT_SOURCE 0x080 I2C Transmit Abort Status Register

M
IC_SLV_DATA_NACK_ONLY 0x084 Generate SLV_DATA_NACK Register

IC_DMA_CR 0x088 DMA Control Register for transmit and receive
handshaking interface
IC_DMA_TDLR 0x08c DMA Transmit Data Level
IC_DMA_RDLR 0x090 DMA Receive Data Level
IC_SDA_SETUP 0x094 I2C SDA Setup Register
IC_ACK_GENERAL_CALL 0x098 I2C ACK General Call Register
IC_ENABLE_STATUS 0x09c I2C Enable Status Register
IC_FS_SPKLEN 0x0a0 ISS and FS spike suppression limit
IC_HS_SPKLEN 0x0a4 HS spike suppression limit
448
CV1835
12.1.7 I2C register description
IC_CON
ed
0 MASTER_MODE R/W enable master mode 0x1
2:1 SPEED R/W 1: standard mode (~100 kbit/s) 0x3
w
2: fast mode (~400 kbit/s)
lo
3 IC_10BITADDR_SLAVE R/W enable 10bit slave address mode 0x1
4 IC_10BITADDR_MASTER R/W enable 10bit master address mode 0x1
al
5 IC_RESTART_EN R/W enable I2C master to be able generate 0x1
restart
t
no
6 IC_SLAVE_DISABLE R/W 0: slave is enabled 0x1
1: slave is disabled
31:7 Reserved
e
ar
IC_TAR n
tio

9:0 IC_TAR R/W I2C Target Address Register 0x55
u
10 GC_OR_START R/W If bit SPECIAL is set to 1, then this bit 0x0

ib
indicates whether a General Call or

r
di V
START byte command

st
re k-
0: general call
1: start byte
d il
11 SPECIAL R/W Used to issue General Call or START 0x0

an M
BYTE
31:12 Reserved
n by
IC_SAR
tio lic

ca ub

9:0
ifi p
IC_SAR R/W I2C Slave Address Register 0x55

31:10 Reserved
od de
M a
IC_DATA_CMD
M

7:0 DAT R/W transmitted or received data port 0x0
8 CMD R/W 0: Write 0x0
1: Read
9 STOP R/W issue stop 0x0
10 RESTART R/W issue restart 0x0
31:11 Reserved
IC_SS_SCL_HCNT
449
CV1835

15:0 IC_SS_SCL_HCNT R/W Standard Speed I2C Clock SCL High 0x0190
Count Register
31:16 Reserved
IC_SS_SCL_LCNT
ed
15:0 IC_SS_SCL_LCNT R/W Standard Speed I2C Clock SCL Low 0x01d6
Count Register
w
31:16 Reserved
lo
IC_FS_SCL_HCNT
al
t
no
15:0 IC_FS_SCL_HCNT R/W Fast Speed I2C Clock SCL High Count 0x003C
Register
e
31:16 Reserved
IC_FS_SCL_LCNT ar
n
tio

u
15:0 IC_FS_SCL_LCNT R/W Fast Speed I2C Clock SCL Low Count 0x0082
ib
Register
r
di V
31:16 Reserved
st
re k-
d il
IC_INTR_STAT
an M

n by
0 R_RX_UNDER RO corresponding masked interrupt staus,

please reference I2C Raw Interrupt
tio lic
Status
1 R_RX_OVER RO corresponding masked interrupt staus,
ca ub

Status
ifi p
2 R_RX_FULL RO corresponding masked interrupt staus,

od de

Status
M a
3 R_TX_OVER RO corresponding masked interrupt staus,

M

Status
4 R_TX_EMPTY RO corresponding masked interrupt staus,
Status
5 R_RD_REQ RO corresponding masked interrupt staus,
Status
6 R_TX_ABRT RO corresponding masked interrupt staus,
Status
7 R_RX_DONE RO corresponding masked interrupt staus,
450
CV1835

Status
8 R_ACTIVITY RO corresponding masked interrupt staus,
Status
9 R_STOP_DET RO corresponding masked interrupt staus,
Status
10 R_START_DET RO corresponding masked interrupt staus,
ed
Status
11 R_GEN_CALL RO corresponding masked interrupt staus,
w
lo
Status
31:12 Reserved
al
t
IC_INTR_MASK
no
e
ar
0 M_RX_UNDER R/W corresponding interrupt staus mask, 0x1
Status
n
1 M_RX_OVER R/W corresponding interrupt staus mask, 0x1
tio

Status
u
2 M_RX_FULL R/W corresponding interrupt staus mask, 0x1

ib

r
Status
di V
st
3 M_TX_OVER R/W corresponding interrupt staus mask, 0x1

re k-

d il
Status
an M
4 M_TX_EMPTY R/W corresponding interrupt staus mask, 0x1

n by
Status
5 M_RD_REQ R/W corresponding interrupt staus mask, 0x1
tio lic
Status
ca ub
6 M_TX_ABRT R/W corresponding interrupt staus mask, 0x1

ifi p
Status
7 M_RX_DONE R/W corresponding interrupt staus mask, 0x1
od de

Status
M a
8 M_ACTIVITY R/W corresponding interrupt staus mask, 0x0

M

Status
9 M_STOP_DET R/W corresponding interrupt staus mask, 0x0
Status
10 M_START_DET R/W corresponding interrupt staus mask, 0x0
Status
11 M_GEN_CALL R/W corresponding interrupt staus mask, 0x1
Status
31:12 Reserved
451
CV1835
IC_RAW_INTR_STAT
0 IST_RX_UNDER RO when receive buffer is empty by reading
from the IC_DATA_CMD register
1 IST_RX_OVER RO receive buffer is oveflow (64Bytes)
2 IST_RX_FULL RO receive buffer reaches or goes above
the RX_TL threshold
3 IST_TX_OVER RO transmit buffer is oveflow (64Bytes)
ed
4 IST_TX_EMPTY RO transmit buffer is at or below the TX_TL
w
threshold
5 IST_RD_REQ RO In slave mode, I2C hold SCL and wait for
lo
the response from processor
al
6 IST_TX_ABRT RO In master or slave mode, when
transmitter is unable to complete the
t
action
no
7 IST_RX_DONE RO In slave-transmitter mode, a NACK is
received
e
8 IST_ACTIVITY RO I2C activity is detected
ar
9 IST_STOP_DET RO STOP occurred
10 IST_START_DET RO START or RESTART occurred
n
11 IST_GEN_CALL RO General Call address is received
tio
31:12 Reserved
u
ib
IC_RX_TL
r
di V
st

re k-

d il
7:0 RX_TL R/W Receive FIFO Threshold Level 0x0

an M
31:8 Reserved
n by
IC_TX_TL
tio lic

ca ub
7:0 TX_TL R/W Transmit FIFO Threshold Level 0x0

31:8 Reserved
ifi p
od de
IC_CLR_INTR
M a

M

0 CLR_INTR RO read to clear corresponding all raw
staus
31:1 Reserved
IC_CLR_RX_UNDER
0 CLR_RX_UNDER RO read to clear corresponding interupt
raw staus, please reference I2C Raw
Interrupt Status
452
CV1835

31:1 Reserved
IC_CLR_RX_OVER
0 CLR_RX_OVER RO read to clear corresponding interupt
Interrupt Status
ed
31:1 Reserved
w
lo
IC_CLR_TX_OVER
al
t
no
0 CLR_TX_OVER RO read to clear corresponding interupt
Interrupt Status
e
31:1 Reserved
IC_CLR_RD_REQ ar
n
tio

u
0 CLR_RD_REQ RO read to clear corresponding interupt

ib

r
di V
Interrupt Status
st
re k-
31:1 Reserved
d il
an M
IC_CLR_TX_ABRT
n by

0 CLR_TX_ABRT RO read to clear corresponding interupt
tio lic

Interrupt Status
ca ub
31:1 Reserved
ifi p
IC_CLR_RX_DONE
od de

M a

M
0 CLR_RX_DONE RO read to clear corresponding interupt

Interrupt Status
31:1 Reserved
IC_CLR_ACTIVITY
0 CLR_ACTIVITY RO read to clear corresponding interupt
Interrupt Status
453
CV1835

31:1 Reserved
IC_CLR_STOP_DET
0 CLR_STOP_DET RO read to clear corresponding interupt
Interrupt Status
ed
31:1 Reserved
w
lo
IC_CLR_START_DET
al
t
no
0 CLR_START_DET RO read to clear corresponding interupt
Interrupt Status
e
31:1 Reserved
IC_CLR_GEN_CALL ar
n
tio

u
0 CLR_GEN_CALL RO read to clear corresponding interupt

ib

r
di V
Interrupt Status
st
re k-
31:1 Reserved
d il
an M
IC_ENABLE
n by

0 ENABLE R/W Enables I2C controller 0x0
tio lic
31:1 Reserved
ca ub
IC_STATUS
ifi p

od de

0 ST_ACTIVITY RO I2C Activity Status.
M a
M
1 ST_TFNF RO Transmit FIFO Not Full

2 ST_TFE RO Transmit FIFO Completely Empty
3 ST_RFNE RO Receive FIFO Not Empty
4 ST_RFF RO Receive FIFO Completely Full
5 ST_MST_ACTIVITY RO Master FSM Activity Status
6 ST_SLV_ACTIVITY RO Slave FSM Activity Status
31:7 Reserved
IC_TXFLR
454
CV1835

6:0 TXFLR RO I2C Transmit FIFO Level
31:7 Reserved
IC_RXFLR
6:0 RXFLR RO I2C Receive FIFO Level Register
ed
31:7 Reserved
w
IC_SDA_HOLD
lo
al
t
15:0 IC_SDA_HOLD R/W Sets the required SDA hold time in units 0x1
no
of IP clock.
31:16 Reserved
e
ar
IC_TX_ABRT_SOURCE n
tio

15:0 TX_ABRT_SOURCE RO I2C Transmit Abort Source Register
u
31:16 Reserved
r ib
di V
st
IC_SLV_DATA_NACK_ONLY
re k-

d il

an M
0 NACK R/W generate a NACK in slave-receiver mode 0x0

31:1 Reserved
n by
IC_DMA_CR
tio lic

ca ub

ifi p
0 RDMAE R/W Receive DMA Enable 0x0

1 TDMAE R/W Transmit DMA Enable 0x0
od de
31:2 Reserved
M a
M
IC_DMA_TDLR
5:0 DMATDL R/W the dma_tx_req signal is generated 0x0
when the number of
valid data entries in the transmit FIFO is
equal to or below this field
value
31:6 Reserved
IC_DMA_RDLR
455
CV1835

5:0 DMARDL R/W dma_rx_req is generated when the 0x0
number of valid data entries in
the receive FIFO is equal to or more
than this field value + 1
31:6 Reserved
IC_SDA_SETUP
ed
w
lo
0 SDA_SETUP R/W SDA Setup time config register 0x64
31:1 Reserved
al
t
IC_ACK_GENERAL_CALL
no
e
ar
0 ACK_GEN_CALL R/W When set to 1, DW_apb_i2c responds 0x1
with a ACK when it receives a General
Call. When set to 0, the IP does not
n
generate General Call interrupts
tio
31:1 Reserved
u
ib
IC_ENABLE_STATUS
r
di V

st
re k-

0 IC_EN RO I2C Enable Status Register
d il
an M
1 SLV_DISABLED_WHILE_BUSY RO Slave Disabled While Busy (Transmit,

Receive)
n by
2 SLV_RX_DATA_LOST RO Slave Received Data Lost.

31:3 Reserved
tio lic
IC_FS_SPKLEN
ca ub

ifi p

od de
7:0 IC_FS_SPKLEN R/W I2C SS and FS Spike Suppression Limit 0x5

Register
M a
31:8 Reserved
M
IC_HS_SPKLEN
7:0 IC_HS_SPKLEN R/W I2C HS Spike Suppression Limit Register 0x1
31:8 Reserved
456
CV1835
12.2UART
12.2.1 Overview
UART (Universal Asynchronous Receiver Transmitter) is an asynchronous serial

communication interface. Its main function is to transfer data from peripheral devices
ed
into internal bus after serial parallel conversion, and output data to external devices
w
after parallel serial conversion. The main function of UART is to connect with UART of
lo
al
external chip, so as to realize the communication between two chips.
This chip provides 5 UART controllers. The relevant overview is shown in the table below.
t
no
For IO configuration, please refer to chapter 2.2 pin information description.
e
ar
Controller Support mode IO pin n
UART0 Two line UART UART0_TX/UART0_RX
tio
UART1 two/four line UART1_TX/UART1_RX/UART1_CTS/UART1_RTS

u
UART
ib
XGPIOA[20]/ XGPIOA[21]/ XGPIOA[22]/ XGPIOA[26]

r
di V
UART2 two/four line UART2_TX/UART2_RX/UART2_CTS/UART2_RTS

st
re k-
UART
XGPIOA[20]/ XGPIOA[21]/ XGPIOA[22]/ XGPIOA[26]
d il
an M
IIC2_SDA/IIC2_SCL
n by
UART3 two/four line SPI0_CS_X/SPI0_SCK/SPI0_SDI/SPI0_SDO

UART
VI_DATA22/VI_DATA21/VI_DATA24/VI_DATA23
tio lic
PWM3/PWM2
ca ub
UART4 Two UART XGPIOA[22]/ XGPIOA[26]

ifi p
od de
UART1_RTS/UART1_CTS
M a
M
UART module has the following characteristics:

 UART module has the following characteristics:
 Support 32 x 8bit transmit FIFO and 32 x 8bit receive FIFO.
457
CV1835
 Support the programmable bit width of data bit and stop bit. Data bits can be
programmed to 5 / 6 / 7 / 8 bits;
 The stop bit can be set to 1 bit, 1.5 bit or 2 bit by programming.
 Support odd, even or no check.
 Support the programmable transmission rate.
 Support receiving FIFO interrupt, sending FIFO interrupt and error interrupt.
ed
 Support initial interrupt status query and post mask interrupt status query.
w
 Support DMA operation.
lo
al
t
no
12.2.3.1 Application diagram
e
ar
UART is a general point-to-point physical layer transport protocol, which can be used to
n
connect various systems, including PC and various peripheral chips, and can be used as
tio
the communication interface between chips.

u
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 12-5 UART application block diagram
12.2.3.2 Function principle
 Baud rate
Since UART interface has no reference clock and belongs to asynchronous transmission
mode, both sides need to use the same transmission speed, that is, the baud rate, to
communicate. If there is any error, the error rate should be small enough to avoid
458
CV1835
misinformation. The rate of one bit is called the baud rate. Typical baud rates are 300,
1200, 2400, 9600, 19200, 38400, 115200 bps, etc.
 Frame structure
The data structure of UART transmission is in frame. The frame structure includes start
signal, data signal, check bit and end signal.
ed
w
lo
al
t
no
Figure 12-6 UART transmission data structure
Start bit
e

ar
The start signal is the mark of the beginning of a frame. The beginning of starting a
n
frame transmission is to send a low level signal bit on the TXD. In RXD, if a low level
tio
signal bit is received in idle state, it is judged as the beginning of receiving a detection
u
transmission
ib
 Data bit
r
di V
st
re k-
The data bit width can be adjusted according to different application requirements,
d il
which can be 5 / 6 / 7 / 8 bit data bit width. The typical data width is 8 bits
an M
 Parity bit
n by
The check bit is a 1-bit error correction signal. The check bit of UART includes odd parity
check, even parity check and fixed check bit. At the same time, it supports the enable
tio lic
and disable of check bit. Please refer to LCR register for detailed description
ca ub
 Stop bit
ifi p
The end signal is the stop bit of the frame. It supports 1 bit, 1.5 bit and 2 bit stop bits.
od de
Sending the end signal of a frame is to send the TXD to high level to complete the
M a
M
transmission and enter the idle state. After counting the check bits of a received frame,
the end signal needs to be received.
459
CV1835
12.2.4 Working mode
12.2.4.1 Baud rate configuration
 UART working clock (UART_SCLK) configuration

Please refer to the CLK_DIV CRG register description to configure clk_sel_0_9~
ed
clk_sel_0_13 and select the working clock of uart0~uart4. The default setting is 1:XTAL
w
25MHz , and could be configurated to 0:187.5mhz, if necessary, frequency division
lo
register div_clk_187p5m can be configured, adjust the clock to 1500/N MHz, up to
al
187.5 MHz.
t
no
 UART baud rate configuration
DLL and DLH are the baud rate frequency division control registers in UART controller.
e
ar
DLH is the high 8 bits and DLL is the low 8 bits. Before configuring DLH and DLL, LCR [7]
must be set to 1. The RBR_THR_DLL(DLL) register and IER_DLH(DLH)register can be
n
tio
configured.
After configuration, baud rate is set. The formula is：
u
ib
�� = ��_�� 16 ∗ (256 ∗ �� + ��)

r
di V
st
 Take UART SCLK 25MHz as an example, 115200 baud rate is configured, and the
re k-
formula is：
d il
an M
256 ∗ �� + �� = 25� 16 ∗ 115200 = 13.5

n by
If DLL is 14 and DLH is 0, the actual baud rate is ：

�� = 25� 16 ∗ 14 = 111607
tio lic
One bit time error is：

ca ub
(115200 − 114286)
�� = 115200 = 3.12%
ifi p
The accumulated time error of one frame is：

od de
�� = 3.12%*10 = 31.2%

M a
M
 Take UART SCLK 187.5MHz as an example, 115200 baud rate is configured, and the
formula is：
256 ∗ �� + �� = 187.5� 16 ∗ 115200 = 101.7
If DLL is 102 and DLH is 0, the actual baud rate is ：
�� = 187.5� 16 ∗ 102 = 114890
One bit time error is：
(115200 − 114890)
�� = 115200 = 0.27%
460
CV1835
The accumulated time error of one frame is：

�� = 3.12%*10 = 2.7%
12.2.4.2 Data transmission flow chart
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 12-7 UART data transmission flow chart
461
CV1835
12.2.4.3 Data receiving flow chart
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 12 8 UART data receiving flow chart
462
CV1835
12.2.4.4 Data transmission in interrupt or query mode
12.2.4.4.1 Initialization steps
1. Write 1 to LCR [7]. Enable and configure division latch access
2. Write the corresponding configuration value to RBR_THR_DLL、IER_DLH
ed
register, configure the baud rate of transmission.
w
3. Write 0 to LCR [7].
lo
al
4. Configure LCR and set corresponding UART working mode.
t
5. Configure FCR and set corresponding transmit and receive FIFO threshold.
no
6. If interrupt mode is used, IER should be set to enable corresponding interrupt
e
ar
signal. n
tio
12.2.4.4.2 Data transmission

u
ib
1. When LCR [7] is 0, the transmitted data could be written into RBR_THR_DLL
r
di V
st
(transmit holding register) to start data transmission.

re k-
d il
2. If query mode is used, TX is detected by reading USR [1] (transmit FIFO not
an M
full) and TFL (transmit FIFO level) to detect the status of TX_FIFO, according to
n by
the status of TX_FIFO determines whether to continue to write data to

tio lic
RBR_THR_DLL.
ca ub
3. If interrupt mode is used, detect according to corresponding interrupt status

ifi p
od de
bit, and decide whether to continue to write data to RBR_THR_DLL.

M a
4. By detecting USR [2] (Transmit FIFO Empty), judge whether UART completes
M
all data transmission.
12.2.4.4.3 Data reception
1. If query mode is used, the status of RX_FIFO is detected by reading USR [3]
(receive FIFO not empty) and RFL (receive FIFO level), according to the status
463
CV1835
of RX_FIFO to determine whether to read RBR_THR_DLL (receive buffer
register) to obtain data.
2. If the interrupt mode is used, whether to read RBR_THR_DLL(Receive Buffer
Register) is determined according to the corresponding interrupt status bit
detection to obtain data.
ed
w
lo
al
12.2.4.5.1 Initialization steps
t
no
1. Write 1 to LCR [7]. Enable and configure Divisor Latch Access
e
2. Write the corresponding configuration value to RBR_THR_DLL、IER_DLH
ar
register, configure the baud rate of transmission.
n
tio
3. Write 0 to LCR [7].

u
4. Configure LCR and set corresponding UART working mode

r ib
di V
5. Configure FCR and set corresponding transmit and receive FIFO threshold.
st
re k-
6. Turn off ETBEI/ERBFI in IER

d il
an M
12.2.4.5.2 Data transmission

n by
tio lic
1. Configure system DMA channel mapping. Refer to 3.5.2.4 system DMA

ca ub
channel mapping, configure the selected UART controller TX / RX request line

ifi p
number to the corresponding system DMA channel. For example, If we want

od de
mapping UART0 TX to DMA channel 3, we should configurate

M a
M
sdma_dma_ch_remap0[29:24] to 9 and write 1 to update_dma_remp_0_3 to
make the configuration effective.
2. Configure DMA data channel, including data transmission source and
destination address, number of data transmission, transmission type and
other parameters. Please refer to chapter 3.6 DMA controller for specific
configuration.
464
CV1835
3. Judge whether the data is sent through DMA interrupt report.
12.2.4.5.3 Data reception
1. Configure system DMA channel mapping. Refer to 3.5.2.4 system DMA
channel mapping, configure the selected UART controller TX / RX request line
ed
number to the corresponding system DMA channel. For example, If we want
w
mapping UART0 RX to DMA channel 1, we should configurate
lo
al
sdma_dma_ch_remap0[13:8] to 8 and write 1 to update_dma_remp_0_3 to
t
make the configuration effective.
no
2. Configure DMA data channel, including data transmission source and
e
ar
destination address, data receiving area address, data transmission number,
n
transmission type and other parameters. Please refer to chapter 3.6 DMA
tio
controller for specific configuration.

u
ib
3. Judge whether the data is received through DMA interrupt report.

r
di V
st
re k-
12.2.5 UART register overview

d il
an M
n by
Base addresses of the 6 group UART modules on the chip

tio lic
GPIO module Base Address

ca ub
UART0 0x04140000
ifi p
UART1 0x04150000
od de
UART2 0x04160000
UART3 0x04170000
M a
UART4 0x041C0000
M
RTCSYS_UART 0x05022000
UART register overview of the chip

Offset
RBR_THR_DLL 0x000 Receive Buffer,Transmit Holding or Divisor Latch Low byte
Register
IER_DLH 0x004 Interrupt Enable or Divisor Latch high byte Register
FCR_IIR 0x008 FIFO Control or Interrupt Identification Register
LCR 0x00c Line Control Register
MCR 0x010 Modem Control Register
465
CV1835

Offset
LSR 0x014 Line Status Register
MSR 0x018 Modem Status Register
LPDLL 0x020 Low Power Divisor Latch (Low) Register
LPDLH 0x024 Low Power Divisor Latch (High) Register
SRBR_STHR 0x030 Shadow Receive/Trasnmit Buffer Register
FAR 0x070 FIFO Access Register
TFR 0x074 Transmit FIFO Read
RFW 0x078 Receive FIFO Write
ed
USR 0x07c UART Status Register
TFL 0x080 Transmit FIFO Level
w
RFL 0x084 Receive FIFO Level
lo
SRR 0x088 Software Reset Register
al
SRTS 0x08c Shadow Request to Send
SBCR 0x090 Shadow Break Control Register
t
SDMAM 0x094 Shadow DMA Mode
no
SFE 0x098 Shadow FIFO Enable
SRT 0x09c Shadow RCVR Trigger
e
STET 0x0a0 Shadow TX Empty Trigger
ar
HTX 0x0a4 Halt TX
DMASA 0x0a8 DMA Software Acknowledge
n
u tio
12.2.6 UART register description

r ib
di V
st
re k-
d il
RBR_THR_DLL
an M

n by

7:0 RBR_THR_DLL R/W LCR[7] bit = 0 : (R) Receive Buffer 0x0
tio lic
Register ,Data byte received on the

serial input port
ca ub
(W)Transmit Holding
Register,Data to be transmitted on the
ifi p
serial output port

LCR[7] bit = 1 : Lower 8 bits of a 16-bit
od de
Divisor Latch register that contains the

baud rate
M a
divisor for the UART

M
31:8 Reserved
IER_DLH
7:0 IER_DLH R/W LCR[7] bit = 0 : 0x0
IER[0] : Enable Received Data
Available Interrupt.
IER[1] : Enable Transmit
Holding Register Empty Interrupt.
IER[2] : Enable Receiver Line
466
CV1835

Status Interrupt.
IER[3] : Enable Modem Status
Interrupt.
IER[7] : Programmable THRE
Interrupt Mode Enable
LCR[7] bit = 1 : Upper 8-bits of a 16-bit
Divisor Latch register that contains the
baud rate
divisor for the UART.
ed
31:8 Reserved
w
FCR_IIR
lo
al
t
7:0 FCR_IIR R/W (R) interrupt Identification Register 0x1
no
[3:0] Interrupt ID
0000 : modem status
0001 : no interrupt pending
e
ar
0010 : THR empty
0100 : received data available
0110 : receiver line status
n
0111 : busy detect
tio
1100 : character timeout

[7:6] FIFOs Enabled
u
00 – disabled
ib
11 – enable
r
(W) FIFO Control Register

di V
st
[0] FIFO Enable

re k-
[1] RCVR FIFO Reset

d il
[2] XMIT FIFO Reset

an M
[3] DMA Mode

0 – mode 0, single DMA data
n by
transfers at a time
1 – mode 1, multi DMA data
transfers are made continuously
tio lic
[5:4] TX Empty
00 – FIFO empty
ca ub
01 – 2 characters in the FIFO

10 – FIFO ¼ full
ifi p
11 – FIFO ½ full
od de
[7:6] RCVR Trigger

00 – 1 character in the FIFO
M a
01 – FIFO ¼ full
M
10 – FIFO ½ full
11 – FIFO 2 less than full
31:8 Reserved
LCR
7:0 LCR R/W Line Control Register 0x0
[1:0] Data Length Select. (00:5
bits,01:6 bits,10:7 bits,11:8 bits)
[2] Number of stop bits. (0:1 stop
467
CV1835

bit,1:1.5 stop bits when Data Length
Select is 0, else 2 stop bits)
[3] Parity Enable
[4] Even Parity Select
[5] Stick Parity
[6] Break Control Bit
[7] Divisor Latch Access Bit
31:8 Reserved
ed
MCR
w
lo
al
7:0 MCR R/W Modem Control Register 0x0
[0] reserved
t
[1] Request to Send. This is used to
no
directly control the Request to Send
(rts_n) output
[2] reserved
e
ar
[3] reserved
[4] reserved
[5] Auto Flow Control Enable.
n
[6] reserved
tio
31:8 Reserved
u
ib
LSR
r

di V
st
re k-

7:0 LSR RO Line Status Register
d il
an M
[0] Data Ready bit. there is at least

one character in the RBR or the receiver
FIFO.
n by
[1] Overrun error bit. This is used to

indicate the occurrence of an overrun
tio lic
error.
[2] Parity Error bit.
ca ub
[3] Framing Error bit..

[4] Break Interrupt bit.
ifi p
[5] Transmit Holding Register Empty

bit.
od de
[6] Transmitter Empty bit.

M a
[7] Receiver FIFO Error bit.

M
31:8 Reserved
MSR
7:0 MSR RO Modem Status Register
[0] Delta Clear to Send.
[1] reserved
[2] reserved
[3] reserved
[4] CTS
468
CV1835

[5] reserved
[6] reserved
[7] reserved
31:8 Reserved
LPDLL
ed
7:0 LPDLL R/W LCR[7] bit = 1 : Low Power Divisor Latch 0x0
w
(Low) Register
31:8 Reserved
lo
al
LPDLH
t
no
7:0 LPDLH R/W LCR[7] bit = 1 : Low Power Divisor Latch 0x0
e
(High) Register
ar
31:8 Reserved n
SRBR_STHR
tio

u

ib
7:0 SRBR_STHR R/W LCR[7] bit = 0 : (R) Shadow Receive 0x0

r
di V
Buffer Register
st
re k-
(W) Shadow Transmit

Holding Register
d il
31:8 Reserved
an M
FAR
n by

tio lic

0 FAR R/W FIFO Access Register,This register is 0x0
ca ub
use to enable a FIFO access mode for

testing
ifi p
31:1 Reserved
od de
TFR
M a
M

7:0 TFR R/W Transmit FIFO Read. These bits are only 0x0
valid when FIFO access mode is enabled
31:8 Reserved
RFW
9:0 RFW R/W Receive FIFO Write. These bits are only 0x0
valid when FIFO access mode is enabled
469
CV1835

[7:0] Receive FIFO Write Data.
[8] Receive FIFO Parity Error.
[9] Receive FIFO Framing Error.
31:10 Reserved
USR
ed
4:0 USR RO UART Status Register
w
[0] UART Busy.
[1] Transmit FIFO Not Full.
lo
[2] Transmit FIFO Empty.
al
[3] Receive FIFO Not Empty.
[4] Receive FIFO Full.
t
31:5 Reserved
no
TFL
e
ar
n
5:0 TFL RO Transmit FIFO Level. This is indicates the
tio
number of
data entries in the transmit FIFO.
u
31:6 Reserved
r ib
RFL
di V
st
re k-

d il

an M
5:0 RFL RO Receive FIFO Level. This is indicates the

number of data
n by
entries in the receive FIFO.

31:6 Reserved
tio lic
SRR
ca ub

ifi p

od de
2:0 SRR R/W Software Reset Register 0x0

[0] UART Reset.
M a
[1] RCVR FIFO Reset.

M
[2] XMIT FIFO Reset.

31:3 Reserved
SRTS
0 SRTS R/W Shadow Request to Send. This is a 0x0
shadow register for the RTS bit (MCR[1])
31:1 Reserved
470
CV1835
SBCR
0 SBCR R/W Shadow Break Control Bit. This is a 0x0
shadow register for the Break bit
(LCR[6]).
31:1 Reserved
ed
SDMAM
w
lo
0 SDMAM R/W Shadow DMA Mode. This is a shadow 0x0
al
register for the DMA mode bit (FCR[3]).
31:1 Reserved
t
no
SFE
e
ar
0 SFE R/W Shadow FIFO Enable. This is a shadow 0x0
n
register for the FIFO enable bit (FCR[0]).
tio
31:1 Reserved
u
SRT
r ib

di V
st
re k-

1:0 SRT R/W Shadow RCVR Trigger. This is a shadow 0x0
d il
register for the RCVR trigger bits

an M
(FCR[7:6]).
31:2 Reserved
n by
STET
tio lic

ca ub

ifi p
1:0 STET R/W Shadow TX Empty Trigger. This is a 0x0

shadow register for the TX empty
od de
trigger bits
(FCR[5:4]).
M a
31:2 Reserved
M
HTX
0 HTX R/W This register is use to halt transmissions 0x0
for testing,
31:1 Reserved
DMASA
471
CV1835

0 DMASA R/W This register is use to perform a DMA 0x0
software acknowledge if a transfer
needs to be terminated due to an error
condition.
31:1 Reserved
ed
12.3SPI
w
lo
al
12.3.1 Overview
t
no
The system is equipped with four SPI controller modules, which can be used as a Master
e
for synchronous serial communication with external devices to realize serial/parallel
conversion of data.
ar
n
u tio
r ib
di V
st
re k-
The characteristics of SPI controller module are as follows:

d il
 Support Motorola SPI (full duplex), TI SSP (full duplex) and NS MicroWire (half
an M
duplex) serial peripheral interface protocols.

n by
 Independent receive / transmit FIFO

Programmable data frame length: 4-16 bits
tio lic

The clock frequency of SPI interface is programmable
ca ub

 Support DMA operation mode
ifi p
 Support internal loopback test mode

od de
 Working reference clock can be set to 187.5MHz or 100MHz, output SPI_SCK

M a
M
supports a maximum of 46.875MHz.
472
CV1835
12.3.3.1 Tpyical application
The application block diagram of SPI master docking with external slave is shown in
Figure 12-9.
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
Figure 12-9 SPI application block diagram

n by
tio lic
ca ub
12.3.4 Working mode

ifi p
od de
12.3.4.1 Work mode

M a
M
SPI's working modes are as follows:

Data transmission in interrupt or query mode
Data transmission in DMA mode
12.3.4.2 Clock
The reference clock of SPI controller module can be set to 187.5MHz or 100MHz.
SPI_SCK output supports a maximum of 46.875MHz.
473
CV1835
The calculation method is as follows:

SPI_SCK output = SPI reference clock / BAUDR
SPI reference clock: 187.5MHz or 100MHz.
BAUDR register: set an even number between 2 and 65534
Calculation example:
SPI reference clock = 187.5MHz and BAUDR = 4
ed
SPI_SCK output = 187.5MHz/4 = 46.875MHz
w
lo
al
12.3.4.3 Interrupt processing
t
no
SPI controller module has six interrupts, the first five of which are level interrupts(active
high) and can be masked independently.
e
ar
RXFINTR
Receive FIFO interrupt request. The interrupt is set when RXFTLR+1 or
n
tio
more valid data are in the receive FIFO

u
RXOINTR
ib
When the receive FIFO is full and new data needs to be written into FIFO,
r
di V
st
FIFO overflow will be caused and the interrupt is set. At this time, the data
re k-
is written to the receive shift register instead of FIFO.

d il
an M
RXUINTR
n by
When the receive FIFO is read empty and no new data is written into the
receive FIFO, a new read request occurs, which will cause FIFO underflow
tio lic
and the interrupt is set. At this time, all the values read are 0. The interrupt
ca ub
can be cleared by reading register RXUICR.

ifi p
TXOINTR
od de
When the transmit FIFO is full and new data needs to be written into FIFO,
M a
M
FIFO overflow will be caused and the interrupt is set.

TXEINTR
Send FIFO interrupt request. This interrupt is set when there are TXFTLR
or less valid data in the transmit FIFO.
SPI_INTR
The combined interrupt is the "OR" operation result of the above five
interrupts.
474
CV1835
To mask this interrupt, register IMR must be set to mask the above five
interrupts.
If any of the above five independent interrupts is set and enabled, the
interrupt is set.
ed
The initialization steps of SPI controller module are as follows:
w
Step 1: set "0" in register SPIENR to stop SPI module.
lo
Step 2: configure the register BAUDR and set the divisor of output clock frequency
al
division. The set value must be even number.
t
no
Step 3: set register CTRLR0, and configure parameters such as bit width and frame
format of transmission data.
e
ar
Step 4: In DMA operation mode, configure register DMACR to enable DMA function of
SPI. When operating in DMA mode, the interrupt related register should be set
n
tio
to prevent the generation of interrupt signal.

u
Step 5: In interrupt operation mode, set register IMR to generate corresponding

ib
interrupt signal
r
di V
st
Step 6: set "1" in register SPIENR to enable SPI module

re k-
d il
an M
12.3.4.5 Data transmission process of SPI

n by
The process of SPI master docking with external SPI / SSP slave is shown in Figure
12-10.
tio lic
ca ub
ifi p
od de
M a
M
475
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 12-10 data transmission process when docking with external SPI / SSP slave
 The process of SPI master docking with external microwire slave is shown in Figure
12-11.
476
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 12-11 data transmission process when connecting to external Microwire slave
477
CV1835
SPI module uses two DMA channels, one for transmitting and one for receiving. The
registers of SPI DMA mode are DMACR, DMATDLR and DMARDLR.
The steps to enable SPI DMA mode are as follows:
Step 1: allocate two DMA channels for SPI.
Step 2: set the register DMACR[1:0] to enable SPI DMA transmission.
ed
Step 3: set "1" in register SPIENR to enable SPI.
w
lo
Step 4: send data
al
1. Configure the control registers related to the transmit DMA channel.
t
2. Start DMA controller to respond to the request of SPI sending FIFO.
no
3. Judge whether the transmission is completed through DMA Controller
e
Interrupt report, and close DMA function of SPI if the transmission is
ar
completed. n
tio
Step 5: receive data

u
1. Configure control registers related to receive DMA channel.

r ib
2. Start DMA controller to respond to the request of SPI receiving FIFO.

di V
st
re k-
3. Through DMA Controller Interrupt report, judge whether the data is

d il
received completely, if it is finished, close the receiving DMA function of

an M
SPI.
n by
Step 6: set "0" to SPIENR register to stop SPI.

tio lic
12.3.5 Three kinds of serial peripheral bus sequence diagram

ca ub
ifi p
12.3.5.1 Motorola SPI interface

od de
M a
The following figures show various data transmission formats of Motorola SPI. SCPH
M
stands for SPI_ SCK phase, SCPOL for SPI_ SCK polarity is set by register CTRLR0[7:6].
(A) SCPH = 0
In this mode, SPI_CS_X is set to high level when it is idle and low level when it
is transmitting. SPI_SCK is different through SCPOL setting, SCPOL = 0, set to
low level when in idle state, capture data by rising edge of clock when
478
CV1835
transmitting, SCPOL = 1, set to high level when in idle state, capture data by
falling edge of clock when transmitting.
The single frame transmission format is shown in Figure 12-12.
ed
w
lo
al
t
no
Figure 12-12Motorola SPI single frame transmission format (SCPH = 0)
e
ar
The format of continuous frame transmission is shown in Figure 12-13.
n
u tio
r ib
di V
st
re k-
d il
an M
n by
Figure 12-13 Motorola SPI continuous frame transmission format (SCPH = 0)

tio lic
ca ub
(B) SCPH = 1
ifi p
od de
In this mode, SPI_CS_X is set to high level when it is idle and low level when it
is transmitting. SPI_SCK is different through scpol setting, SCPOL = 0, set to
M a
M
low level when in idle state, capture data by falling edge of clock when
transmitting, SCPOL = 1, set to high level when in idle state, capture data by
rising edge of clock when transmitting.
479
CV1835
ed
w
Figure 12-14 Motorola SPI single frame transmission format (SCPH = 1)
lo
al
t
The continuous frame transmission format is shown in Figure 12-15.
no
e
ar
n
u tio
r ib
di V
st
re k-
Figure 12-15 Motorola SPI continuous frame transmission

d il
format (SCPH = 1)
an M
n by
12.3.5.2 TI Synchronous Serial Interface

tio lic
In SSP mode, SPI_CS_X is set to high level when in idle state; SPI_CS_X is set to low level
ca ub
when in transmitting state. SPI_ SCK is set to low level when in idle state, and it captures
ifi p
data by falling edge of clock when transmitting.

od de
The following figures show the TI SSP data transmission format.

M a

M
Figure 12- 1 TI SSP Single Frame Transmission Format
480
CV1835
ed
w
lo
al
Figure 12- 2 TI SSP Continuous Frame Transmission Format
t
no
e
12.3.5.3 National Semiconductor Microwire Interface ar
n
tio
In Microwire mode, SPI_CS_X is set to high level when in idle state; SPI_CS_X is set to
u
ib
low level when in transmitting state. SPI_ SCK is set to low level when in idle state, and it
r
captures data by rising edge of clock when transmitting.

di V
st
re k-
In this mode, the control word must be added before data transmission, and then the
d il
an M
external chip responds to the data word required by the Master according to the
control word. The length of the control word can be set through the register
n by
CTRLR0[15:12], and other related parameters can be set through the register MWCR.
tio lic
ca ub
The following figures show the NS Microwire data transmission format.

ifi p

od de
M a
M
Figure 12- 3 NS Microwire Single Frame Transmission Format
481
CV1835
ed
w
lo
al
t
Figure 12- 4 NS Microwire Continuous Frame Transmission Format
no
e
ar
n
tio
The base addresses of four groups of SPI modules are shown in Table 12-2.
u
r ib
Table 12- 2 Four Groups of SPI Module Base Address of the Chip
di V
st
re k-

d il
an M
SPI0 0x04180000
SPI1 0x04190000
n by
SPI2 0x041A0000
SPI3 0x041B0000
tio lic
ca ub
Table 12-3 is the offset address and definition of the first group of SPI module (SPI0)
ifi p
registers. SPI0 to SPI3 have the same register definition.

od de
M a
M
Table 12- 3 SPI Register Overview

Offset
CTRLR0 0x000 Control Register 0
CTRLR1 0x004 Control Register 1
SPIENR 0x008 SPI Enable Register
MWCR 0x00c Microwire Control Register
SER 0x010 Slave Enable Register
BAUDR 0x014 Baud Rate Select
TXFTLR 0x018 Transmit FIFO Threshold Level
RXFTLR 0x01c Receive FIFO Threshold Level
482
CV1835

Offset
TXFLR 0x020 Transmit FIFO Level Register
RXFLR 0x024 Receive FIFO Level Register
SR 0x028 Status Register
IMR 0x02c Interrupt Mask Register
ISR 0x030 Interrupt Status Register
RISR 0x034 Raw Interrupt Status Register
TXOICR 0x038 Transmit FIFO Overflow Interrupt Clear Register
RXOICR 0x03c Receive FIFO Overflow Interrupt Clear Register
ed
RXUICR 0x040 Receive FIFO Underflow Interrupt Clear Register
MSTICR 0x044 Multi-Master Interrupt Clear Register
w
ICR 0x048 Interrupt Clear Register
lo
DMACR 0x04c DMA Control Register
al
DMATDLR 0x050 DMA Transmit Data Level
DMARDLR 0x054 DMA Receive Data Level
t
DR (36 组) 0x060 Data Register
no
RX_SAMPLE_DLY 0x0f0 Rx Sample Delay Register
e
12.3.7 Register Description
ar
n
u tio
ib
CTRLR0
r
di V
st

re k-

d il
15:0 CTRLR0 R/W [15:12] Control Frame Size. 0x7

an M
Selects the length of the control word

for the Microwire frame format.
n by
0000 1-bit control word

tio lic

ca ub

ifi p

od de

M a

M

[11] Shift Register Loop.

Used for testing purposes only. When
internally active, connects the transmit
shift register output to the receive shift
register input. Can be used in both
serialslave and serial-master modes.
483
CV1835

0 – Normal Mode Operation
1 – Test Mode Operation
[10] only for slave mode.
[9:8] Transfer Mode.

Selects the mode of transfer for serial
communication. This field does not
affect the transfer duplicity. Only
ed
indicates whether the receive or
transmit data are valid.
w
In transmit-only mode, data received
lo
from the external device is not valid and
al
is not stored in the receive FIFO
memory; it is overwritten on the next
t
transfer.
no
In receive-only mode, transmitted data
are not valid. After the first write to the
transmit FIFO, the same word is
e
retransmitted for the duration of the
ar
transfer.
In transmit-and-receive mode, both
n
transmit and receive data are valid. The
tio
transfer continues until the transmit

FIFO is empty. Data received from the
u
external device are stored into the

ib
receive FIFO memory, where it can be

r
accessed by the host processor.

di V
st
In eeprom-read mode, receive data is

re k-
not valid while control data is being

transmitted.
d il
an M
When all control data is sent to the

EEPROM, receive data becomes valid
and transmit data becomes invalid. All
n by
data in the transmit FIFO is considered

control data in this mode.
tio lic
00 –- Transmit & Receive

01 –- Transmit Only
ca ub
10 –- Receive Only
11 –- EEPROM Read
ifi p
od de
[7] Serial Clock Polarity.

Valid when the frame format (FRF) is set
M a
to Motorola SPI. Used to select the

M
polarity of the inactive serial clock,

which is held inactive when the SPI
master is not actively transferring data
on the serial bus.
0 – Inactive state of serial clock is low
1 – Inactive state of serial clock is high
[6] Serial Clock Phase.

Valid when the frame format (FRF) is set
to Motorola SPI. The serial clock phase
selects the relationship of the serial
clock with the slave select signal. When
SCPH = 0, data are captured on the first
484
CV1835

edge of the serial clock. When SCPH = 1,
the serial clock starts toggling one cycle
after the slave select line is activated,
and data are captured on the second
edge of the serial clock.
0: Serial clock toggles in middle of first
data bit
1: Serial clock toggles at start of first
data bit
ed
[5:4] Frame Format.
w
Selects which serial protocol transfers
lo
the data.
00 –- Motorola SPI
al
01 –- Texas Instruments SSP
10 –- National Semiconductors
t
no
Microwire
11 –- Reserved
e
[3:0] Data Frame Size.
ar
Selects the data frame length. When the
data frame size is programmed to be
n
less than 16 bits, the receive data are
tio
automatically right-justified by the

receive logic, with the upper bits of the
u
receive FIFO zero-padded. You must

ib
right-justify transmit data before writing

r
into the transmit FIFO. The transmit

di V
st
logic ignores the upper unused bits

re k-
when transmitting the data.

0000 Reserved – undefined operation
d il
an M

0011 4-bit serial data transfer
n by

tio lic

ca ub

ifi p

od de

M a

M

31:16 Reserved
CTRLR1
15:0 CTRLR1 R/W Number of Data Frames. 0x0
When TMOD = 10 or TMOD = 11, this
register field sets the number of data
frames to be continuously received by
485
CV1835

the SPI. The SPI continues to receive
serial data until the number of data
frames received is equal to this register
value plus 1, which enables you to
receive up to 64 KB of data in a
continuous transfer.
31:16 Reserved
SPIENR
ed
w
lo
0 SPIENR R/W SPI Enable. 0x0
al
Enables and disables all SPI operations.
When disabled, all serial transfers are
t
halted immediately. Transmit and
no
receive FIFO buffers are cleared when
the device is disabled. It is impossible to
program some of the SPI control
e
ar
registers when enabled. When disabled,
the spi_sleep output is set (after delay)
to inform the system that it is safe to
n
remove the spi_clk, thus saving power
tio
consumption in the system.

31:1 Reserved
u
ib
MWCR
r
di V
st

re k-

d il
an M
2:0 MWCR R/W [2] Microwire Handshaking. 0x0

Relevant only when the SPI is
configured as a serial-master device.
n by
When configured as a serial slave, this

bit field has no functionality. Used to
tio lic
enable and disable the “busy/ready”

handshaking interface for the Microwire
ca ub
protocol. When enabled, the SPI checks

for a ready status from the target slave,
ifi p
after the transfer of the last

data/control bit, before clearing the
od de
BUSY status in the SR register.

M a
0: handshaking interface is disabled

M
1: handshaking interface is enabled
[1] Microwire Control.

Defines the direction of the data word
when the Microwire serial protocol is
used. When this bit is set to 0, the data
word is received by the SPI from the
external serial device. When this bit is
set to 1, the data word is transmitted
from the SPI to the external serial
device.
[0] Microwire Transfer Mode.
486
CV1835

Defines whether the Microwire transfer
is sequential or non-sequential. When
sequential mode is used, only one
control word is needed to transmit or
receive a block of data words. When
non-sequential mode is used, there
must be a control word for each data
word that is transmitted or received.
0 – non-sequential transfer
ed
1 – sequential transfer
31:3 Reserved
w
lo
SER
al
t
no
0 SER R/W Slave Select Enable Flag. 0x0
This register corresponds to a slave
select line (ss_x_n]) from the SPI master.
e
ar
When this register is set (1), the slave
select line from the master is activated
when a serial transfer begins. It should
n
be noted that setting or clearing this
tio
register have no effect on the

corresponding slave select outputs until
u
a transfer is started. Before beginning a

ib
transfer, you should enable this register

r
that corresponds to the slave device

di V
st
with which the master wants to

re k-
communicate.
d il
1: Selected
an M
0: Not Selected
31:1 Reserved
n by
BAUDR
tio lic

ca ub

15:0 BAUDR R/W SPI Clock Divider(SCKDV). 0x0
ifi p
The LSB for this field is always set to 0

and is unaffected by a write
od de
operation, which ensures an even value

M a
is held in this register. If the value is 0,

M
the serial output clock (sclk_out) is

disabled. The frequency of the sclk_out
is derived from the following equation:
Fsclk_out/SCKDV = Fssi_clk
where SCKDV is any even value between
2 and 65534. For example:
for Fssi_clk = 3.6864MHz and SCKDV =2
Fsclk_out = 3.6864/2 = 1.8432MHz
31:16 Reserved
TXFTLR
487
CV1835

2:0 TXFTLR R/W Transmit FIFO Threshold. 0x0
Controls the level of entries (or below)
at which the transmit FIFO controller
triggers an interrupt. The FIFO depth is
8; If you attempt to set this value
greater than or equal to the depth of
the FIFO, this field is not written and
retains its current value. When the
number of transmit FIFO entries is less
ed
than or equal to this value, the transmit
FIFO empty interrupt is triggered.
w
31:3 Reserved
lo
al
RXFTLR
t
no
2:0 RXFTLR R/W Receive FIFO Threshold. 0x0
Controls the level of entries (or above)
e
ar
at which the receive FIFO controller
triggers an interrupt. The FIFO depth is
8. If you attempt to set this value
n
greater than the depth of the FIFO, this
tio
field is not written and retains its

current value. When the number of
u
receive FIFO entries is greater than or

ib
equal to this value + 1, the receive FIFO

r
full interrupt is triggered.

di V
st
31:3 Reserved
re k-
d il
TXFLR
an M

n by

3:0 TXFLR RO Transmit FIFO Level.
tio lic
Contains the number of valid data

entries in the transmit FIFO.
ca ub
31:4 Reserved
ifi p
RXFLR
od de

M a

M
3:0 RXFLR RO Receive FIFO Level.

Contains the number of valid data
entries in the receive FIFO.
31:4 Reserved
SR
6:0 SR RO [6] Data Collision Error.
This bit is set if the SPI master is actively
transmitting when another master
488
CV1835

selects this device as a slave. This
informs the processor that the last data
transfer was
halted before completion. This bit is
cleared when read.
0 – No error
1 – Transmit data collision error
[5] Transmission Error.
ed
Set if the transmit FIFO is empty when a
transfer is started. Data from the
w
previous transmission is resent on the
lo
txd line. This bit is cleared when read.
0 – No error
al
1 – Transmission error
t
no
[4] Receive FIFO Full.
When the receive FIFO is completely
full, this bit is set. When the receive
e
FIFO contains one or more empty
ar
location, this bit is cleared.
0 – Receive FIFO is not full
n
1 – Receive FIFO is full
tio
[3] Receive FIFO Not Empty.

u
Set when the receive FIFO contains one

ib
or more entries and is cleared when the

r
receive FIFO is empty. This bit can be

di V
st
polled by software to completely empty

re k-
the receive FIFO.

d il
0 – Receive FIFO is empty

an M
1 – Receive FIFO is not empty

n by
[2] Transmit FIFO Empty.

When the transmit FIFO is completely
empty, this bit is set. When the transmit
tio lic
FIFO contains one or more valid entries,

ca ub
this bit is cleared. This bit field does not

request an interrupt.
ifi p
0 – Transmit FIFO is not empty

1 – Transmit FIFO is empty
od de
[1] Transmit FIFO Not Full.

M a
Set when the transmit FIFO contains

M
one or more empty locations, and is

cleared when the FIFO is full.
0 – Transmit FIFO is full
1 – Transmit FIFO is not full
[0] SPI Busy Flag.

When set, indicates that a serial transfer
is in progress; when cleared indicates
that the SPI is idle or disabled.
0 – SPI is idle or disabled
1 – SPI is actively transferring data
31:7 Reserved
489
CV1835
IMR
5:0 IMR R/W [5] Multi-Master Contention Interrupt 0x3F
Mask.
0 – spi_mst_intr interrupt is masked
1 – spi_mst_intr interrupt is not masked
[4] Receive FIFO Full Interrupt Mask
ed
0 – spi_rxf_intr interrupt is masked
1 – spi_rxf_intr interrupt is not masked
w
lo
[3] Receive FIFO Overflow Interrupt
al
Mask
0 – spi_rxo_intr interrupt is masked
t
1 – spi_rxo_intr interrupt is not masked
no
[2] Receive FIFO Underflow Interrupt
e
Mask
ar
0 – spi_rxu_intr interrupt is masked
1 – spi_rxu_intr interrupt is not masked
n
tio
[1] Transmit FIFO Overflow Interrupt
Mask
0 – spi_txo_intr interrupt is masked
u
ib
1 – spi_txo_intr interrupt is not masked

r
di V
st
[0] Transmit FIFO Empty Interrupt Mask

re k-
0 – spi_txe_intr interrupt is masked

1 – spi_txe_intr interrupt is not masked
d il
an M
31:6 Reserved
n by
ISR
tio lic

ca ub
5:0 ISR RO [5] Multi-Master Contention Interrupt

Status.
ifi p
0 = spi_mst_intr interrupt not active

after masking
od de
1 = spi_mst_intr interrupt is active after

masking
M a
M
[4] Receive FIFO Full Interrupt Status

0 = spi_rxf_intr interrupt is not active
after masking
1 = spi_rxf_intr interrupt is full after
masking
[3] Receive FIFO Overflow Interrupt

Status
0 = spi_rxo_intr interrupt is not active
after masking
1 = spi_rxo_intr interrupt is active after
masking
490
CV1835
[2] Receive FIFO Underflow Interrupt

Status
0 = spi_rxu_intr interrupt is not active
after masking
1 = spi_rxu_intr interrupt is active after
masking
[1] Transmit FIFO Overflow Interrupt
ed
Status
0 = spi_txo_intr interrupt is not active
w
after masking
lo
1 = spi_txo_intr interrupt is active after
al
masking
t
[0] Transmit FIFO Empty Interrupt Status
no
0 = spi_txe_intr interrupt is not active
after masking
1 = spi_txe_intr interrupt is active after
e
ar
masking
31:6 Reserved n
tio
RISR
u
ib

5:0 RISR RO [5] Multi-Master Contention Raw
r
di V
st
Interrupt Status.
re k-
0 = spi_mst_intr interrupt is not active

prior to masking
d il
an M
1 = spi_mst_intr interrupt is active prior

masking
n by
[4] Receive FIFO Full Raw Interrupt

Status
tio lic
0 = spi_rxf_intr interrupt is not active

prior to masking
ca ub
1 = spi_rxf_intr interrupt is active prior

to masking
ifi p
od de
[3] Receive FIFO Overflow Raw Interrupt

Status
M a
0 = spi_rxo_intr interrupt is not active

M
prior to masking
1 = spi_rxo_intr interrupt is active prior
masking
[2] Receive FIFO Underflow Raw

Interrupt Status
0 = spi_rxu_intr interrupt is not active
prior to masking
1 = spi_rxu_intr interrupt is active prior
to masking
[1] Transmit FIFO Overflow Raw
491
CV1835

Interrupt Status
0 = spi_txo_intr interrupt is not active
prior to masking
1 = spi_txo_intr interrupt is active prior
masking
[0] Transmit FIFO Empty Raw Interrupt

Status
0 = spi_txe_intr interrupt is not active
ed
prior to masking
1 = spi_txe_intr interrupt is active prior
w
masking
lo
31:6 Reserved
al
TXOICR
t
no
e
0 TXOICR RO Clear Transmit FIFO Overflow Interrupt.
ar
This register reflects the status of the
interrupt. A read from this register
clears the spi_txo_intr interrupt; writing
n
has no effect.
tio
31:1 Reserved
u
ib
RXOICR
r
di V
st

re k-

d il
0 RXOICR RO Clear Receive FIFO Overflow Interrupt.

an M

interrupt.
n by
A read from this register clears the

spi_rxo_intr interrupt; writing has no
effect.
tio lic
31:1 Reserved
ca ub
RXUICR
ifi p

od de

0 RXUICR RO Clear Receive FIFO Underflow Interrupt.
M a
M

interrupt.
spi_rxu_intr interrupt; writing has no
effect.
31:1 Reserved
MSTICR
0 MSTICR RO Clear Multi-Master Contention
Interrupt.
492
CV1835

interrupt.
spi_mst_intr interrupt; writing has no
effect.
31:1 Reserved
ICR
ed
w
0 ICR RO Clear Interrupts.
lo
This register is set if any of the
al
interrupts below are active. A read
clears the spi_txo_intr, spi_rxu_intr,
t
spi_rxo_intr, and the spi_mst_intr
no
interrupts. Writing to this register has
no effect.
31:1 Reserved
e
DMACR
ar
n
tio
u
1:0 DMACR R/W [1] Transmit DMA Enable. 0x0

ib
This bit enables/disables the transmit

FIFO DMA channel.
r
di V
st
0 = Transmit DMA disabled

re k-
1 = Transmit DMA enabled

d il
an M
[0] Receive DMA Enable.

This bit enables/disables the receive
n by
FIFO DMA channel

0 = Receive DMA disabled
1 = Receive DMA enabled
tio lic
31:2 Reserved
ca ub
DMATDLR
ifi p

od de

2:0 DMATDLR R/W Transmit Data Level. 0x0
M a
M
This bit field controls the level at which

a DMA request is made by the transmit
logic. It is equal to the watermark level;
that is, the dma_tx_req signal is
generated when the number of valid
data entries in the transmit FIFO is
equal to or below this field value, and
TDMAE = 1.
31:3 Reserved
DMARDLR
493
CV1835

2:0 DMARDLR R/W Receive Data Level. 0x0
This bit field controls the level at which
a DMA request is made by the receive
logic. The watermark level =
DMARDL+1; that is, dma_rx_req is
generated when the number of valid
data entries in the receive FIFO is equal
to or above this field value + 1, and
RDMAE=1.
ed
31:3 Reserved
w
DR
lo
al
t
15:0 DR R/W Data Register. 0x0
no
When writing to this register, you must
right-justify the data. Read data are
automatically right-justified.
e
ar
Read = Receive FIFO buffer
Write = Transmit FIFO buffer
n
Note :
tio
The DR register in the SPI occupies

thirty-six 32-bit address locations of the
u
memory map to facilitate AHB burst

ib
transfers. Writing to any of these

r
address locations has the same effect as

di V
st
pushing the data from the pwdata bus

re k-
into the transmit FIFO. Reading from

d il
any of these locations has the same

an M
effect as popping data from the receive

FIFO onto the prdata bus.
n by
31:16 Reserved
tio lic
RX_SAMPLE_DLY
ca ub

ifi p
7:0 RX_SAMPLE_DLY R/W Receive Data (rxd) Sample Delay. 0x0

od de
This register is used to delay the sample

of the rxd input signal. Each value
M a
represents a single ssi_clk delay on the

M
sample of the rxd signal.

NOTE: If this register is programmed
with a value that exceeds the depth of
the internal shift registers (DEPTH = 8), a
zero (0) delay will be applied to the rxd
sample.
31:8 Reserved
494
CV1835
12.4SD/SDIO Controller
12.4.1.1 Functional Block Diagram
ed
SD / SDIO controller (SD controller for short) is used to handle the operation of data
w
reading and writing of SD card, as well as the external devices (such as Bluetooth, WiFi,
lo
al
etc.) supported by SDIO protocol. The chip provides two sets of SD controllers,
including:
t
no
SDIO0 supports devices compliant to the Secure Digital Memory (SD 3.0) protocol.
e
ar
SDIO1 supports devices complian to the Secure Digital I/O(SDIO 3.0) protocol.
n
tio
The function signals and pins corresponding to the SD controllers in the chip are shown
u
in the table below.

r ib
di V
st
re k-
Table 12- 4 Corresponding Function Signal and Pin of SD Controller

d il
an M
SDMMC Controller Function Signal Pin Name

SDIO0 SD_CLK SD0_CLK
n by
SD_CMD SD0_CMD
SD_DATA0 SD0_D0
tio lic
SD_DATA1 SD0_D1
ca ub
SD_DATA2 SD0_D2
ifi p
SD_DATA3 SD0_D3
od de
SD_CARD_DETECT SD0_CD
SD_POWER_EN SD0_PWR_EN
M a
M
SDIO1 SDIO_CLK SD1_CLK

SDIO_CMD SD1_CMD
SDIO_DATA0 SD1_D0
SDIO_DATA1 SD1_D1
SDIO_DATA2 SD1_D2
SDIO_DATA3 SD1_D3
495
CV1835
ed
w
lo
al
Figure 12- 20 SD Controller Function Block Diagram
t
no
Functions of SDMMC:
e
ar
1. Support SD card, SDIO device.
2. Transfer data between SD / SDIO and system memory through internal DMA
n
tio
controller.
u
3. Support CRC generation and check of command and data.

ib
4. The required frequency between different modes can be generated through the
r
di V
st
internal frequency divider.

re k-
d il
5. Provide a mechanism to turn off the internal clock and the clock on the interface
an M
to save power.
n by
6. Provide 1-bit and 4-bit data transmission interface to communicate with the
device.
tio lic
7. Support block_size read and write operations with size equal to 1-2048byte.
ca ub
8. Support SDIO protocol, including interrupt interval, suspend, resume and read
ifi p
wait.
od de
9. Support AXI/AHB interface and access system memory through internal DMA.
M a
M
10. Support AHB interface and access internal registers through CPU.
496
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
Figure 12- 21 Typical Application

r ib
di V
st
re k-
d il
an M
12.4.1.2 Command and Response

n by
The bus packet of SD consists of three parts: commmand, response and data.
tio lic
The commmand and response packets are transmitted through the CMD signal line.
ca ub
Command Packet
ifi p
The command packet is sent to the device by the host to indicate the start of an
od de
operation. The packet format consists of 48 bits including start bit, transmit bit,
M a
M
command index, command argument, CRC verification code and end bit. It is shown
in Figure 12-22.
497
CV1835
ed
w
lo
al
Figure 12- 22 SD/SDIO Command Format
t
no
e
ar
Response Packet
After receiving the command, the device will return the response according to
n
tio
different command types, which is used to show the status or parameters of the
u
device. Its length is 48 bits or 136 bits. It is shown in Figure 12-23.

r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 12- 23 SD/SDIO Response Format
Data Packet
498
CV1835
Data packets are used to exchange data between the host and the device.
According to different requirements, 1-bit (DATA0), 4-bit (DATA 0- DATA 3) or 7-bit
(DATA 0- DATA 7) can be selected. In each clock cycle, each data signal line can
choose to transmit 1-bit (single data rate) or 2-bit (dual data rate). The packet
formats are shown in Figure 12-24 to 12-26.
ed
w
lo
al
Figure 12- 24 SD/SDIO 1-bit Data Packet Format
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic

ca ub
ifi p
od de
M a
M
499
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
ib
According to whether there is data transmission, commands can be further divided into
r
di V
st
the following two types.

re k-
Non data transmission command: through the signal line CMD to complete the
d il
an M
command transmission and receiving response.

n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 12- 27 Non data transmission command: Complete Transmission and

Receiving Responses through CMD
Data transmission command: in addition to the transmission on the signal line

CMD, there is also data transmission on the data lines DAT0~DAT3.
500
CV1835
12.4.1.3 Data Transmission
The data transmission between the host and the device is mainly based on the block. In
addition to the data, CRC check bits are also included to verify the correctness of the
data. Common methods of data reading and writing include single-block and multi-
ed
block. Compared with single block data transmission, multi block data transmission has
w
higher efficiency. Among them, the block size of SD card is 512byte. SDIO is special. It
lo
al
can support 1-2048byte block size. Users can define the block size value according to
different devices.
t
no
(1) Single block and multi block read operations are shown in Figure 12-30. Single
block transmission consists of command, response, data and CRC. Multi block
e
ar
transmission terminates transmission by STOP CMD. n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
Figure 12- 5 Single Block and Multi Block Read Operation

ca ub
ifi p
(2) Single block and multi block write operations are shown in Figure 12-31. In the
od de
transmission process, a BUSY signal will be sent through the DAT0 signal line to
M a
M
inform the host that the write device is in progress.
501
CV1835
ed
w
Figure 12- 29 Single Block and Multi Block Write Operation
lo
al
t
no
12.4.1.4 Speed Mode and Voltage Switching supported by SD3.0
e
Voltage Switching Procedure (1.8V  3.3V)
ar
n
Step 1: Set PWRSW to 3.0V mode
tio
=> sd_pwrsw_ctrl (0x030001F4) = 0x00000009

u
ib
(reg_pwrsw_auto=1, reg_pwrsw_disc=0, reg_pwrsw_vsel=0(3.0v), reg_en_pwrsw=1)

r
di V
st
re k-
Step 2: Wait 1ms to complete the voltage switching

d il
an M
Voltage Switching Procedure (3.3V  1.8V)

n by
tio lic
Step 1: Set PWRSW to 1.8V

ca ub
=> sd_pwrsw_ctrl (0x030001F4) = 0x0000000B

(reg_pwrsw_auto=1, reg_pwrsw_disc=0, reg_pwrsw_vsel=1(1.8v), reg_en_pwrsw=1)
ifi p
od de
Step 2: Wait 1ms to complete the voltage switching

M a
M
Supported speed mode and voltage

The speed mode and voltage supported by SD3.0 are shown in the table below.
Table 12- 1 SD3.0 Supported Speed and Voltage

Supported Mode Supported Speed Voltage
DS (default speed) 25Mhz 1.8V/3.3V
HS (high speed) 50Mhz 1.8V/3.3V
502
CV1835
Supported Mode Supported Speed Voltage

SDR12 25Mhz 1.8V
SDR25 50Mhz 1.8V
DDR50 50Mhz 1.8V
SDR50 100Mhz 1.8V
SDR104 187.5Mhz 1.8V
ed
w
12.4.2 Application Explanation
lo
al
12.4.2.1 Clock off Control
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 12- 30 Clock off Control Procedure
503
CV1835
As shown in Figure 12-30, is a clock off control program. The host must ensure that
there is no transmission on the bus before the clock can be turned off.
(1) Read register PRESENT_STS
(2) Check bit CMD_ INHIBIT and DAT_INHIBIT are both 0
(3) If any bit is not 0, it means that the transmission is still in progress and needs to be
ed
delayed.
w
(4) If all are 0, it can be set_ CTL[SD_ CLK_ EN] = 0 to turn off the clock
lo
al
t
12.4.2.2 Soft Reset
no
When the controller operation is abnormal, reset the configuration register (base
e
ar
address = 0x0300_ 3000) for soft reset. The register addresses used are as follows.
n
6. SDIO0 : SOFT_RSTN_0[reg_soft_reset_x_sd0] (address offset : 0x000, Bit16)
tio
7. SDIO1 : SOFT_RSTN_0[reg_soft_reset_x_sd1] (address offset : 0x000, Bit17)

u
r ib
di V
st
12.4.2.3 Interface Clock Configuration

re k-
d il
an M
Figure 12-31 shows the flow chart of interface clock configuration. SD controller
provides a frequency divider, which allows users to adjust the required clock frequency
n by
according to different protocols and speed modes. The relationship is as follows.

tio lic
FSD_CLK_OUT = FINT_CARD_CLK/ (2 x clk_divisor)

ca ub
When SD changes the frequency, in addition to ensuring that no commands and data
ifi p
are still in transmission, it must also be set according to the steps of the interface clock
od de
configuration flow chart to avoid the clock glitch output to the SD device.
M a
(1) Turn off the interface clock.

M
(2) Calculate the frequency division factor.

(3) Set the frequency division factor. Fill the parameters calculated in (2) into CLK_
CTL[FREQ_ SEL] and start to turn on the internal clock switch
(CLK_CTL[INT_CLK_EN]=1)
(4) Check CLK_CTL[INT_CLK_STABLE] to confirm whether the frequency switching is
completed.
(5) If not completed (CLK_CTL[INT_CLK_STABLE]=0), delay to wait.
504
CV1835
(6) If the clock frequency switching is completed, turn on the interface clock.
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 12- 6 Clock Configuration Flow Chart
12.4.2.4 Non Data Transfer Command
Command transfer sequence
505
CV1835
The command transfer procedure is shown in Figure 12-32.

(1) The register bit PRESENT[CMD_INHIBIT] must be 0 to confirm whether the CMD
line is still in use.
(2) If the CMD line is idle, further confirm whether it is an command with busy. If it
is not a busy command, you do not need to check the status on the DATA Line,
and directly execute step (5). Otherwise, if it is a busy command, you must
ed
execute step (3) to confirm whether it is an Abort command.
w
(3) If it is an Abort command, it means that when the CMD line completes the
lo
transmission, the DATA line is also idle, so you can directly go to step (5);
al
otherwise, if it is not an Abort command, you must go to step (4) to confirm
t
no
whether the busy on the DATA line has been released.
(4) Check if register bit PRESENT[DAT_INHIBIT] is 0 to confirm whether the DATA
e
ar
line is still in use or not. If it is still in use, wait until the end of transmission, and
then perform step (5).
n
tio
(5) Set the value of ARGUMENT register and CMD register according to the
command requirements.
u
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
506
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 12- 32 Command Transfer Sequence

507
CV1835
Command Complete Sequence

The command completion sequence is shown in Figure 12-33.
(1) First wait for Interrupt NORM_INT_STS[CMD_CMPL] completed by Command.
(2) Set NORM_INT_STS[CMD_CMPL]=1 to clear the CMD_ Cmpl interrupt status
after receiving interrupt.
(3) Next read RESP1_0, RESP3_ 2, RESP5_ 4, and RESP7_ 6 to get the response value.
ed
(4) If it is an command containing data transmission, step (5) will be executed;
w
otherwise, skip to step (8).
lo
(5) Wait for data transmission interrupt NORM_INT_STS[XFER_CMPL].
al
(6) Set NORM_INT_STS[XFER_CMPL]=1 to clear XFER_CMPL interrupt status after
t
no
receiving interrupt.
(7) Check RESP1_0, RESP3_ 2, RESP5_ 4, and RESP7_ 6 registers to confirm whether
e
ar
there is an error state. If there is no error status, go to step (8) and return that
there is no error. If there is an error, perform step (9) to report the error.
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
508
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 12- 33 Command Complete Sequence
509
CV1835
12.4.2.5 Abort Data Transfer
Abort Command Sequence

For the SD device, the abort command is performed by CMD12, while for the SDIO
device, it is performed by CMD52. There are two main conditions of the time to use
the abort command.
ed
(1) Stop data transmission of infinite block.
w
(2) Stop multi block data transmission.
lo
al
The procedure of abort command is shown in Figure 12-34, and the detailed steps
t
are as follows.
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
510
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
Figure 12- 347 Abort Command Sequence

M a
M
There are two ways of abort command: synchronous abort command and
asynchronous abort command.
Asynchronous Abort Command Sequence
Figure 12-35 shows the diagram of asynchronous abort command. The detailed
steps are as follows.
511
CV1835
(1) The abort command is executed according to different transmission modes.

(2) Set SW_RST_CMD and SW_RST_DAT in SW_RESET register to reset the signal
lines of CMD and DAT.
(3) Check bit SW_RESET[SW_RST_CMD] and SW_RESET[SW_RST_DAT] to confirm
whether the reset is completed. If both are 0, the procedure ends. If one of
them is 1, return to step (3) to delay waiting.
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
Figure 12- 358 Asynchronous Abort Command Procedure

M
Synchronous Abort Command Sequence

Figure 12-36 shows the diagram of the synchronous abort command. The detailed
(1) Write bit BG_CTL[STOP_BG_REQ] to stop the transmission in the Block Gap.
512
CV1835
(2) Wait for the completion of interrupt NORM_INT_STS[XFER_CMPL] transferred.

(3) Set NORM_INT_STS[XFER_CMPL]=1 to clear XFER_CMPL interrupt status after
(4) The abort command is executed according to different transmission modes.
(5) Set SW_RST_CM and SW_RST_DAT in SW_RESET register to reset the signal
lines of CMD and DAT.
ed
(6) Check bit SW_RESET[SW_RST_CMD] and SW_RESET[SW_RST_DAT] to confirm
w
whether the reset is completed. If both are 0, the procedure ends. If one of
lo
them is 1, return to step (6) to delay waiting.
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 12- 36 Synchronous Abort Command Procedure
513
CV1835
12.4.2.6 Non DMA Data Transfer Mode
The procedure of non DMA data transfer mode is shown in Figure 12-37. The detailed
(1) Write BLK_SIZE register to set the block size.
(2) Write BLK_ CNT register to set the number of blocks.
ed
(3) Write ARGUMENT register to set the command argument.
w
(4) Write XFER_MODE register to set the transmission mode. The host can decide the
lo
setting according to the situation, including Single or Multiple Block Select, DMA
al
Enable, Block Count Enable, Data Transfer Direction, Auto CMD Enable.
t
(5) Write CMD register to set the type of command and response.
no
(6) Wait for the interrupt NORM_INT_STS[CMD_CMPL] completed by Command.
e
(7) Set NORM_INT_STS[CMD_CMPL]=1 to clear the CMD_CMPL interrupt status after
ar
n
tio
(9) Step (14) is executed for a read operation and step (10) is executed for a write
u
ib
operation.
r
di V
(10) Wait for the Buffer Write Ready’s interrupt NORM_INT_STS[BUF_WRDY].

st
re k-
(11) Set NORM_INT_STS[BUFF_WRDY]=1 to clear the BUFF_WRDY interrupt status

d il
an M

(12) Write the data in order to the BUF_DATA register.
n by
(13) If there are more blocks to write, go back to step (10) until the last block is
tio lic
written, and then go to step (18).

ca ub
(14) Wait for the Buffer Write Ready’s interrupt NORM_INT_STS[BUF_RRDY].

ifi p
(15) Set NORM_INT_STS[BUFF_RRDY]=1 to clear the BUFF_RRDY interrupt status

od de

M a
(16) Read the data from BUF_DATA in order, the data that received from the device.
M
(17) If there are more blocks to read, go back to step (14), and then go to step (18)
until the last block is read.
(18) Determine the transmission is single module transmission, multi module
transmission or infinite module transmission. If it is single module or multi module
transmission, skip to step (19). If it is infinite module transmission, skip to step (21)
and execute abort command.
514
CV1835
(19) Wait for the interrupt NORM_INT_STS[XFER_CMPL] after the data transmission is
completed.
(20) Set NORM_INT_STS[CMD_XFER]=1 to clear theXFER_CMPL interrupt status after
(21) Execute the abort command procedure.
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
515
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 12- 37 Non DMA Data Transfer Mode Procedure
516
CV1835
12.4.2.7 SDMA Data Transfer Mode
The procedure of SDMA data transmission mode is shown in Figure 12-38, and the
detailed steps are as follows.
(1) Write SDMA_ SA register to set the starting address of system memory used in data
transmission.
ed
(2) Write BLK_ SIZE register to set the block size.
w
lo
(4) Write the ARGUMENT register to set the command argument.
al
(5) Write to XFER_MODE register to set the transmission mode. The host can decide the
t
setting according to the situation, including Single or Multiple Block Select, DMA
no
Enable, Block Count Enable, Data Transfer Direction, Auto CMD Enable.
e
(6) Write to the CMD register to set the type of command and response.
ar
n
(8) Set NORM_INT_STS[CMD_CMPL]=1 to clear the CMD_ Cmpl interrupt status after
tio
u
ib
r
di V
(10) Waiting for data transfer interrupt and DMA interrupt

st
re k-
(11) Read interrupt state register NORM_INT_STS to determine the type of interrupt.
d il
an M
If it is a DMA interrupt, skip to step (12); if it is a data transmission interrupt, skip to

step (14).
n by
(12) Set nNORM_INT_STS[DMA_INT]=1 to clear DMA_ Int status value.

tio lic
(13) Write to SDMA_SA register to reset the next starting address of the system
ca ub
memory for the DMA, and then skip to step (10).

ifi p
(14) Set NORM_INT_STS[DMA_INT]=1 and [NORM_INT_STS[XFER_CMPL]=1 to clear

od de
DMA_INT and XFER_CMPL status value, and then end the sequence.
M a
M
517
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 12- 38 SDMA Data Transfer Mode Procedure
12.4.2.8 ADMA Data Transfer Mode
518
CV1835
The procedure of ADMA data transmission mode is shown in Figure 12-39, and the
detailed steps are as follows.
(15) Fill ADMA description table into system memory.
(16) Write ADMA_ SA_ L and ADMA_ SA_ H register to set the starting address of the
system memory used by the description table.
(17) Write BLK_ SIZE register to set the block size.
ed
w
(19) Write the ARGUMENT register to set the command argument.
lo
(20) Write to XFER_MODE register to set the transmission mode. The main controller
al
can decide the setting according to the situation, including Single or Multiple Block
t
no
Select, DMA Enable, Block Count Enable, Data Transfer Direction, Auto CMD Enable.
(21) Write to the CMD register to set the type of command and response.
e
ar
(23) Set NORM_INT_STS[CMD_CMPL]=1 to clear the CMD_ Cmpl interrupt status
n
tio

u
ib
(25) Wait for data transmission interrupt or ADMA error interrupt.

r
di V
st
(26) Read interrupt state register NORM_INT_STS and ERR_INT_STS to determine the
re k-
type of interrupt. If it is an ADMA error interrupt, skip to step (13); if it is a data

d il
an M
transmission interrupt, skip to step (15).

n by
(27) Set ERR_INT_STS[ADMA_ERR]=1 to clear ADMA_ERR status value.

(28) Enter ADMA abort transaction and execute abort command to abort the data
tio lic
transmission with the device. If necessary, check the ADMA Error Status register to
ca ub
check the cause of the error.

ifi p
(29) Set NORM_INT_STS[XFER_CMPL]=1 to clear XFER_CMPL status value, and then

od de
end the sequence.

M a
M
519
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 12- 39 ADMA Data Transfer Mode Procedure
520
CV1835
Table 12-6 shows an overview of SD registers (the base address of SDIO0 is

0x0431_0000, while the address of SDIO1 is 0x0500_0000).
Table 12- 2 SD Register Overview

ed
Offset
w
SDMA_SADDR 0x000 SDMA System Memory Address/ Argument2
BLK_SIZE_AND_CNT 0x004 Block Size and Block Count Register
lo
ARGUMENT 0x008 Argument 1 Register
al
XFER_MODE_AND_CMD 0x00c Transfer Mode and Command Register
RESP31_0 0x010 Response Bit 31-0 Regsiter
t
no
RESP127_96 0x01c Response Bit 127-96 Regsiter
e
BUF_DATA 0x020 Buffer Data Port Register
ar
PRESENT_STS 0x024 Present State Register
HOST_CTL1_PWR_BG_WUP 0x028 Host Control 1 , Power, Block Gap and Wakeup Register
n
CLK_CTL_SWRST 0x02c Clock and Reset Control Register
tio
NORM_AND_ERR_INT_STS 0x030 Normal and Error Interrupt Status Register
NORM_AND_ERR_INT_STS_EN 0x034 Normal and Error Interrupt Status Enable Register
u
NORM_AND_ERR_INT_SIG_EN 0x038 Normal and Error Interrupt Signal Enable Register

ib
AUTO_CMD_ERR_AND_HOST_CTL2 0x03c Auto CMD Error Status Register and Host Control 2
register
r
di V
st
CAPABILITIES1 0x040 Capabilities 1 Register

re k-
CAPABILITIES2 0x044 Capabilities 2 Register

FORCE_EVENT_ERR 0x050 Force Event Register for Auto CMD Error Status
d il
an M
ADMA_ERR_STS 0x054 ADMA Error Status Register

ADMA_SADDR_L 0x058 ADMA System Address Register for low 32-bit
n by
ADMA_SADDR_H 0x05c ADMA System Address Register for high 32-bit

PRESENT_VUL_INIT_DS 0x060 Present Value Register for Initialization and Default Speed
PRESENT_VUL_HS_SDR12 0x064 Present Value Register for High-speed and SDR12
tio lic
PRESENT_VUL_SDR25_SDR50 0x068 Present Value Register for SDR25 and SDR50

PRESENT_VUL_SDR104_DDR50 0x06c Present Value Register for SDR104 and DDR50
ca ub
SLOT_INT_AND_HOST_VER 0x0fc Slot Interrupt Status and Host Controller Version Register
ifi p
EMMC_CTRL 0x200 MSHC Control register

CDET_TOUT_CTL 0x208 Card Detect Control Register
od de
MBIU_CTRL 0x20c MBIU Control register

PHY_TX_RX_DLY 0x240 PHY tx and rx delay line register
M a
PHY_DS_DLY 0x244 PHY DS delay line register

M
PHY_DLY_STS 0x248 PHY delay line status register

PHY_CONFIG 0x24c PHY Configuration register
521
CV1835
12.4.4 Register Description
The following is a detailed description of the registers.
SDMA_SADDR
SDMA System Memory Address/ Argument2
ed
w
31:0 SDMA_SA R/W Physical system memory address used 0x0
lo
for DMA transfer and the second
argument for Auto CMD23
al
BLK_SIZE_AND_CNT
t
no
Block Size and Block Count Register
e
ar
11:0 XFER_BLK_SIZE R/W Block Size of data transfer. 0x0
- 0x1 : 1 byte
- 0x2 : 2 bytes
n
...........
tio
- 0x200 : 512 bytes

...........
u
- 0x800 : 2048 bytes

r ib
di V
14:12 SDMA_BUF_BDARY R/W Host SDMA buffer Boundary 0x0

st
re k-
- 0x0 ( 4K bytes)
- 0x1 (8K bytes)
d il
- 0x2 (16K bytes)

an M
- 0x3 (32K bytes)

- 0x4 (64K bytes)
n by
- 0x5 (128K bytes)

- 0x6 (256K bytes)
tio lic
- 0x7 (512K bytes)

15 Reserved
ca ub
31:16 BLK_CNT R/W Blocks Count for Current Transfer 0x0

ifi p
ARGUMENT
od de
Argument 1 Register
M a

M
31:0 ARGUMENT R/W Command Argument 1 0x0
XFER_MODE_AND_CMD
Transfer Mode and Command Register
0 DMA_ENABLE R/W DMA enable 0x0
1 : DMA Data Transfer
0 : No data transfer or Non DMA data
transfer
1 BLK_CNT_ENABLE R/W Block Count Enable. 0x0
This bit is used to enable the block
522
CV1835

count regiser, which is only relevant for
multiple block transfers.
1 : Enable
0 : Disable
3:2 AUTO_CMD_ENABLE R/W Auto CMD enable. 0x0
This field determines use of auto
command funcitons
0x0 : Auto command Disabled
0x1 : Auto CMD12 Enable
ed
0x2 : Auto CMD23 Enable
0x3 : Reserved
w
4 DAT_XFER_DIR R/W Data Transfer Direction Select 0x0
1 : Read ( card to host)
lo
0 : Write ( host to card )
al
5 MULTI_BLK_SEL R/W Multi/single Block Select 0x0
1 : Multiple block transfer
t
0 : Single block transfer
no
6 RESP_TYPE R/W Response Type R1/R5 0x0
0x0 : R1 (Memory)
e
0x1 : R5 (SDIO)
ar
7 RESP_ERR_CHK_ENABLE R/W Response Error Check Enable 0x0
1 : Enable
n
0 : Disable
tio
8 RESP_INT_DISABLE R/W Response Interrupt Disable 0x0

1 : Disable
u
0 : Enable
ib
15:9 Reserved
r
17:16 RESP_TYPE_SEL R/W Response Type Select 0x0

di V
st
0x0 : No Response
re k-
0x1 : Response Length 136

d il
0x2 : Response Length 48

an M
0x3 : Response Length 48 with busy

18 SUB_CMD_FLAG R/W Sub Command Flag 0x0
n by
1 : Sub Command
0 : Main Command
19 CMD_CRC_CHK_ENABLE R/W Command CRC check enable 0x0
tio lic
1 : Enable
0 : Disable
ca ub
20 CMD_IDX_CHK_ENABLE R/W Command Index Check Enable 0x0

ifi p
1 : Enable
0 : Disable
od de
21 DATA_PRESENT_SEL R/W Data Present Select. 0x0

It is set to 0 for following :
M a
(1) Commands using only CMD line

M
(ex. CMD52)
(2) Commands with no data transfer
but using busy signal on DAT0 ( ex. R1b)
(3) Resume command
1 : Data Present
0 : No Data Present
23:22 CMD_TYPE R/W Command Type 0x0
0x0 : Normal
0x1 : Suspend ( CMD52 for writing "Bus
Suspend" in CCCR)
0x2 : CMD52 for writing "Function
Select" in CCCR)
0x3 : Abort ( CMD12, CMD52 for writing
523
CV1835

"I/O Abort" in CCCR)
29:24 CMD_IDX R/W Command Index 0x0
31:30 Reserved
RESP31_0
Response Bit 31-0 Regsiter
ed
31:0 RESP31_0 RO Command Response for RSP[39:8]
w
RESP63_32
lo
al
t
no
RESP95_64
e
ar
n
tio
RESP127_96
u
ib

r
di V
st

re k-

d il
an M
BUF_DATA
Buffer Data Port Register
n by

tio lic
31:0 BUF_DATA R/W Buffer Data 0x0

ca ub
PRESENT_STS
ifi p
Present State Register

od de

0 CMD_INHIBIT RO Command Inhibit (CMD)
M a
1 : Cannot issue command

M
0 : Can issue command using only CMD

line
1 CMD_INHIBIT_DAT RO Command Inhibit (DAT)
1 : Cannot issue command wihich used
the DAT line
0 : Can issue command using only DAT
line
2 DAT_LINE_ACTIVE RO DAT Line Active
This bit indicates whether one of the
DAT line on SD Bus is in use.
1 : DAT Line Active
0 : DAT Line Inactive
524
CV1835

3 RE_TUNE_REQ RO Re-Tuning Request
1 : Sampling clock need re-tuning
0 : Fixed or well tuned sampling clock
7:4 Reserved
8 WR_XFER_ACTIVE RO Write Transfer Active
1 : Transferring data
0 : No valid data
9 RD_XFER_ACTIVE RO Read Transfer Active
1 : Transferring data
ed
0 : No valid data
10 BUF_WR_ENABLE RO Buffer Write Enable
w
1 : Enable
lo
0 : Disable
al
11 BUF_RD_ENABLE RO Buffer Read Enable
1 : Enable
t
0 : Disable
no
15:12 Reserved
16 CARD_INSERTED RO Card Inserted
e
1 : Card Inserted
ar
0 : Reset or Debouncing or No card
17 CARD_STABLE RO Card State Stable
n
1 : No Card or Inserted
tio
0 : Reset or Debouncing
18 CARD_CD_STS RO Card Detect Pin Level
u
1 : Card Present ( SD_CD = 0)

ib
0 : No Card Present (SD_CD = 1)

19 CARD_WP_STS RO Write Protect Switch Pin Level
r
di V
st
1 : Write enabled ( SD_WP =0)

re k-
0 : Write protected (SD_WP = 1)

23:20 DAT_3_0_STS RO DAT[3:0] Line Signal Level
d il
an M
24 CMD_LINE_STS RO CMD Line Signal Level

31:25 Reserved
n by
HOST_CTL1_PWR_BG_WUP
tio lic
Host Control 1 Register

ca ub

ifi p
0 LEC_CTL R/W LED Control 0x0

This bit is used to caution the user not
od de
to remove the card while the SD card is

being accessed.
M a
1 : LED on
M
0 : LED off
1 DAT_XFER_WIDTH R/W Data Transfer Width. 0x0
1 : 4-bit mode
0 : 1-bit mode
2 HS_ENABLE R/W High Speed Enable 0x0
1 : High Speed Enable
0 : Normal Speed Enable
4:3 DMA_SEL R/W DMA Select. 0x0
0x0 : SDMA mode
0x1 : Reserved
0x2 : ADMA2
0x3 : ADMA2 or ADMA3
525
CV1835

5 EXT_DAT_WIDTH R/W Extended Data Transfer Width 0x0
1 : 8-bit mode
0 : Selected by DAT_XFER_WIDTH
6 CRAD_DET_TEST R/W Card Detect Test Level 0x0
1 : Card Inserted
0 : No card
7 CARD_DET_SEL R/W Card Detect Signal Selection 0x0
1 : CARD_DET_TEST is selected ( for test
purpose)
ed
0 : SD_CD Is selected
8 SD_BUS_PWR R/W SD Bus Power. 0x0
w
1 : Power on
lo
0 : Power off
11:9 SD_BUS_VOL_SEL R/W SD Bus Voltage Select 0x0
al
111b : 3.3V
110b : 3.0V
t
no
101b : 1.8V
100b - 000b : Reserved
15:12 Reserved
e
16 STOP_BG_REQ R/W Stop At Block Gap Request. 0x0
ar
This bit is used to stop executing read
and write transaction at the next block
n
gap for non-DMA, SDMA and ADMA
tio
transfers.
1 : Stop
u
0 : Transfer
ib
17 CONTINUE_REQ R/W Continue Request. 0x0

r
This bit is used to restart a transaction,

di V
st
which was stoped using the

re k-
STOP_BG_REQ.
d il
1 : Restart
an M
0 : Not affect
18 READ_WAIT R/W Read Wait Control 0x0
n by
1 : Enable Read Wait Control

0 : Disable Read Wait Control
19 INT_BG R/W Interrupt At Block Gap 0x0
tio lic
1 : Enable
ca ub
0 : Disabel
23:20 Reserved
ifi p
24 WAKEUP_ON_CARD_INT R/W Wakeup Event Enable On Card 0x0

Interrupt.
od de
1 : Enable
0 : Disable
M a
M
25 WAKEUP_ON_CARD_INSERT R/W Wakeup Event Enable On Card Insertion. 0x0

1 : Enable
0 : Disable
26 WAKEUP_ON_CARD_REMV R/W Wakeup Event Enable On Card Removal. 0x0
1 : Enable
0 : Disable
31:27 Reserved
CLK_CTL_SWRST
Clock and Timeout Control Register
526
CV1835

0 INT_CLK_EN R/W Internal Clock Enable 0x0
1 : Oscillate
0 : Stop
1 INT_CLK_STABLE RO Internal Clock Stable.
1 : Ready
0 : Not Ready
2 SD_CLK_EN R/W SD Clock Enable for Card 0x0
1 : Enable
0 : Disable
ed
3 PLL_EN R/W PLL Enable 0x0
1 : Enable
w
0 : Disable
lo
5:4 Reserved
al
7:6 UP_FREQ_SEL R/W Upper Bits of SDCLK Frequency Select 0x0
15:8 FREQ_SEL R/W SDCLK Frequency Select 0x0
t
19:16 TOUT_CNT R/W Data Timeout Counter Value 0x0
no
0x0 : TMCLK x 2^13
0x1 : TMCLK x 2^14
…......
e
ar
0xe : TMCLK x 2^ 27
0xf : Reserved
23:20 Reserved
n
tio
24 SW_RST_ALL R/W Software Reset For All 0x0
25 SW_RST_CMD R/W Software Reset For CMD Line 0x0
u
26 SW_RST_DAT R/W Software Reset For DATA Line 0x0

ib
31:27 Reserved
r
di V
st
NORM_AND_ERR_INT_STS
re k-
Normal and Error Interrupt Status Register

d il

an M

0 CMD_CMPL RWC Command Complete
n by
1 XFER_CMPL RWC Transfer Complete

2 BG_EVENT RWC Block Gap Event
tio lic
3 DMA_INT RWC DMA Interrupt

ca ub
4 BUF_WRDY RWC Buffer Write Ready

ifi p
5 BUF_RRDY RWC Buffer Read Ready

od de
6 CARD_INSERT_INT RWC Card Insertion

7 CARD_REMOV_INT RWC Card Removal
M a
M
8 CARD_INT RO Card Interrupt

9 INT_A RO INT_A.
This status is set if INT_A is enabled and
INT_A pin is in low level
10 INT_B RO INT_B.
This status is set if INT_B is enabled and
INT_B pin is in low level
11 INT_C RO INT_C.
This status is set if INT_C is enabled and
INT_C pin is in low level
12 RE_TUNE_EVENT RO Re-Tuning Event
13 Reserved
527
CV1835

14 CQE_EVENT RO Command Queuing Event
15 ERR_INT RO Error Interrupt
16 CMD_TOUT_ERR RWC Command Timeout Error
17 CMD_CRC_ERR RWC Command CRC Error
18 CMD_ENDBIT_ERR RWC Command End Bit Error
19 CMD_IDX_ERR RWC Command Index Error
20 DAT_TOUT_ERR RWC Data Timeout Error
ed
21 DAT_CRC_ERR RWC Data CRC Error
w
22 DAT_ENDBIT_ERR RWC Data End Bit Error
lo
23 CURR_LIMIT_ERR RWC Current Limit Error
al
24 AUTO_CMD_ERR RWC Auto Command Error
25 ADMA_ERR RWC ADMA Error
t
no
26 TUNE_ERR RWC Tuning Error
27 Reserved
e
28 BOOT_ACK_ERR RWC
ar
31:29 Reserved n
tio
NORM_AND_ERR_INT_STS_EN
Normal and Error Interrupt Status Enable Register
u

ib

r
0 CMD_CMPL_EN R/W Command Complete Status Enable 0x0

di V
st
1 XFER_CMPL_EN R/W Transfer Complete Status Enable 0x0

re k-
2 BG_EVENT_EN R/W Block Gap Event Status Enable 0x0

d il
3 DMA_INT_EN R/W DMA Interrupt Status Enable 0x0

an M
4 BUF_WRDY_EN R/W Buffer Write Ready Status Enable 0x0

5 BUF_RRDY_EN R/W Buffer Read Ready Status Enabel 0x0
n by
6 CARD_INSERT_INT_EN R/W Card Insertion Status Enable 0x0

7 CARD_REMOV_INT_EN R/W Card Removal Status Enable 0x0
8 CARD_INT_EN R/W Card Interrupt Status Enable 0x0
tio lic
9 INT_A_EN R/W INT_A Status Enable. 0x0

ca ub
10 INT_B_EN R/W INT_B Status Enable. 0x0

11 INT_C_EN R/W INT_C Status Enable. 0x0
ifi p
12 RE_TUNE_EVENT_EN R/W Re-Tuning Event Status Enable 0x0

13 Reserved
od de
14 CQE_EVENT_EN R/W Command Queuing Event Status Enable 0x0

M a
15 ERR_INT_EN R/W Error Interrupt Status Enable 0x0

M
16 CMD_TOUT_ERR_EN R/W Command Timeout Error Status Enable 0x0

17 CMD_CRC_ERR_EN R/W Command CRC Error Status Enable 0x0
18 CMD_ENDBIT_ERR_EN R/W Command End Bit Error Status Enable 0x0
19 CMD_IDX_ERR_EN R/W Command Index Error Status Enable 0x0
20 DAT_TOUT_ERR_EN R/W Data Timeout Error Status Enable 0x0
21 DAT_CRC_ERR_EN R/W Data CRC Error Status Enable 0x0
22 DAT_ENDBIT_ERR_EN R/W Data End Bit Error Statue Enable 0x0
23 CURR_LIMIT_ERR_EN R/W Current Limit Error Status Enable 0x0
24 AUTO_CMD_ERR_EN R/W Auto Command Error Status Enable 0x0
25 ADMA_ERR_EN R/W ADMA Error Status Enable 0x0
26 TUNE_ERR_EN R/W Tuning Error Status Enable 0x0
27 Reserved
528
CV1835

28 BOOT_ACK_ERR_EN R/W Boot Ack Error Status Enable 0x0
31:29 Reserved
NORM_AND_ERR_INT_SIG_EN
Normal and Error Interrupt Signal Enable Register
0 CMD_CMPL_SIG_EN R/W Command Complete Signal Enable 0x0
ed
1 XFER_CMPL_SIG_EN R/W Transfer Complete Signal Enable 0x0
2 BG_EVENT_SIG_EN R/W Block Gap Event Signal Enable 0x0
w
3 DMA_INT_SIG_EN R/W DMA Interrupt Signal Enable 0x0
lo
4 BUF_WRDY_SIG_EN R/W Buffer Write Ready Signal Enable 0x0
5 BUF_RRDY_SIG_EN R/W Buffer Read Ready Signal Enabel 0x0
al
6 CARD_INSERT_INT_SIG_EN R/W Card Insertion Signal Enable 0x0
7 CARD_REMOV_INT_SIG_EN R/W Card Removal Signal Enable 0x0
t
no
8 CARD_INT_SIG_EN R/W Card Interrupt Signal Enable 0x0
9 INT_A_SIG_EN R/W INT_A Signal Enable. 0x0
10 INT_B_SIG_EN R/W INT_B Signal Enable. 0x0
e
11 INT_C_SIG_EN R/W INT_C Signal Enable. 0x0
ar
12 RE_TUNE_EVENT_SIG_EN R/W Re-Tuning EventSignal Enable 0x0
13 Reserved
n
tio
14 CQE_EVENT_SIG_EN R/W CQE EventSignal Enable 0x0
15 Reserved
u
16 CMD_TOUT_ERR_SIG_EN R/W Command Timeout Error Signal Enable 0x0

ib
17 CMD_CRC_ERR_SIG_EN R/W Command CRC Error Signal Enable 0x0

r
18 CMD_ENDBIT_ERR_SIG_EN R/W Command End Bit Error Signal Enable 0x0

di V
st
19 CMD_IDX_ERR_SIG_EN R/W Command Index Error Signal Enable 0x0

re k-
20 DAT_TOUT_ERR_SIG_EN R/W Data Timeout Error Signal Enable 0x0

d il
21 DAT_CRC_ERR_SIG_EN R/W Data CRC Error Signal Enable 0x0

an M
22 DAT_ENDBIT_ERR_SIG_EN R/W Data End Bit Error Signal Enable 0x0

23 CURR_LIMIT_ERR_SIG_EN R/W Current Limit Error Signal Enable 0x0
n by
24 AUTO_CMD_ERR_SIG_EN R/W Auto Command Error Signal Enable 0x0

25 ADMA_ERR_SIG_EN R/W ADMA Error Signal Enable 0x0
26 TUNE_ERR_SIG_EN R/W Tuning Error Signal Enable 0x0
tio lic
27 Reserved
ca ub
28 BOOT_ACK_ERR_SIG_EN R/W Boot Ack Error Signal Enable 0x0

31:29 Reserved
ifi p
od de
AUTO_CMD_ERR_AND_HOST_CTL2
Auto CMD Error Status Register and Host Control 2 register
M a

M

0 AUTO_CMD12_NO_EXE RO Auto CMD12 Not Executed
1 AUTO_CMD_TOUT_ERR RO Auto CMD Timeout Error
2 AUTO_CMD_CRC_ERR RO Auto CMD CRC Error
3 AUTO_CMD_ENDBIT_ERR RO Auto CMD End Bit Error
4 AUTO_CMD_IDX_ERR RO Auto CMD Index Error
6:5 Reserved
7 CMD_NOT_ISSUE_BY_CMD12 RO Command Not Issued By Auto CMD12
Error
15:8 Reserved
529
CV1835

18:16 UHS_MODE_SEL R/W USH Speed Mode Select ( for SD) 0x0
0x0 : SDR12
0x1 : SDR25
0x2 : SDR50
0x3 : SDR104
0x4 : DDR50
0x5 : Reserved
0x6 : Reserved
0x7 : Reserved
ed
eMMC Speed Mode Select ( for eMMC)
0x0 : Default speed
w
0x1 : High speed
0x2 : Reserved
lo
0x3 : HS200
al
0x4 : DDR52
0x5 : Reserved
t
0x6 : Reserved
no
0x7 : Reserved
19 EN_18_SIG R/W 1.8V Signaling Enable 0x0
e
21:20 DRV_SEL R/W Driver Strength Select 0x0
ar
0x0 : Driver Type B
0x1 : Driver Type A
n
0x2 : Driver Type C
tio
0x3 : Driver Type D
22 EXECUTE_TUNE R/W Execute Tuning 0x0
u
1 : Execute Tuning
ib
0 : Not Tuned or Tuning Completed

23 SAMPLE_CLK_SEL R/W Sampling Clock Select 0x0
r
di V
st
1 : Tuned clock is used to sample data

re k-
0 : Fixed clock is used to sample data

29:24 Reserved
d il
an M
30 ASYNC_INT_EN R/W Asynchronous Interrupt Enable. 0x0

1 : Enable
n by
0 : Disable
31 PRESET_VAL_ENABLE R/W Preset Value Enable 0x0
1 : Automatic Selection by Preset Value
tio lic
are Enabled
0 : SDLCK and Driver Strength are
ca ub
controlled by Host Driver

ifi p
CAPABILITIES1
od de
Capabilities 1 Register
M a

M
5:0 TOUT_CLK_FREQ RO Timeout Clock Frequency

Not 0 : 1KHz~ 63KHz or 1Mhz~ 63Mhz
6 Reserved
7 TOUT_CLK_UNIT RO Timeout Clock Unit
1 : 1MHz
0 : 1KHz
15:8 BASE_CLK_FREQ RO Base Clock Frequency for SD clock
0x0 : Get information through another
method
0x1 : 1MHz
0x2 : 2MHz
.........
530
CV1835

0xFF : 255Mhz
17:16 MAX_BLK_LEN RO Max Block Length
0x0 : 512 (byte)
0x1 : 1024
0x2 : 2048
0x3 : Reserverd
18 EMBEDDED_8BIT RO 8-bit Support for Embedded Device
19 ADMA2_SUPPORT RO ADMA2 Support
ed
20 Reserved
21 HS_SUPPORT RO High Speed Support
w
22 SDMA_SUPPORT RO SDMA Support
lo
23 SUSP_RES_SUPPORT RO Suspend/Resume Support
al
24 V33_SUPPORT RO 3.3V Support
t
no
27 Reserved
e
ar
28 BUS64_SUPPORT RO 64-bit System Bus Support
29 ASYNC_INT_SUPPORT RO Asynchronous Interrupt Support
n
31:30 SLOT_TYPE RO Slot Type
tio
0x0 : Removable Card

0x1 : Embedded Slot
u
0x2 : Shared Bus Slot

r ib
CAPABILITIES2
di V
st
Capabilities 2 Register
re k-

d il

an M
0 SDR50_SUPPORT RO SDR50 Support

1 SDR104_SUPPORT RO SDR104 Support
n by
2 DDR50_SUPPORT RO DDR50 Support

tio lic
3 Reserved
4 DRV_A_SUPPORT RO Driver Type A Support
ca ub
5 DRV_C_SUPPORT RO Driver Type C Support

ifi p
6 DRV_D_SUPPORT RO Driver Type D Support

od de
7 Reserved
11:8 RETUNE_TIMER RO Timer Count for Re-Tuning
M a
M
0x0 : Disable
n : 2^(n-1) seconds
0xB : 1024 seconds
0xC ~ 0xE : Reserved
0xF : Get Information from other source
12 Reserved
13 TUNE_SDR50 RO Use Tuning for SDR50
15:14 RETUNE_MODE RO Re-Tuning Modes
23:16 CLK_MULTIPLIER RO Clock Multiplier
31:24 Reserved
531
CV1835
FORCE_EVENT_ERR
Force Event Register for Auto CMD Error Status
0 FORCE_AUTO_CMD12_NOT_EXE R/W Force Event for Auto CMD12 Not 0x0
Executed
1 FORCE_AUTO_CMD_TOUT_ERR R/W Force Event for Auto CMD Timeout 0x0
Error
2 FORCE_AUTO_CMD_CRC_ERR R/W Force Event for Auto CMD CRC Error 0x0
3 FORCE_AUTO_CMD_EBIT_ERR R/W Force Event for Auto CMD End Bit Error 0x0
ed
4 FORCE_AUTO_CMD_IDX_ERR R/W Force Event for Auto CMD Index Error 0x0
w
6:5 Reserved
7 FORCE_AUTO_CMD_NOT_ISSUE R/W Force Event for Command Not Issued By 0x0
lo
Auto CMD12 Error
al
15:8 Reserved
t
16 FORCE_CMD_TOUT_ERR R/W Force Event for Auto CMD12 Not 0x0
no
Executed
17 FORCE_CMD_CRC_ERR R/W Force Event for CMD Timeout Error 0x0
18 FORCE_CMD_EBIT_ERR R/W Force Event for CMD End Bit Error 0x0
e
19 FORCE_CMD_IDX_ERR R/W Force Event for CMD Index Error 0x0
ar
20 FORCE_DAT_TOUT_ERR R/W Force Event for DATA Timeout Error 0x0
21 FORCE_DAT_CRC_ERR R/W Force Event for DATA End Bit Error 0x0
n
22 FORCE_DAT_EBIT_ERR R/W Force Event for DATA Index Error 0x0
tio
23 FORCE_CURR_LIMIT_ERR R/W Force Event for current limit error 0x0

24 FORCE_AUTO_CMD_ERR R/W Force Event for Auto CMD Error 0x0
u
25 FORCE_ADMA_ERR R/W Force Event for ADMA Error 0x0

ib
26 FORCE_TUNING_ERR R/W Force Event for Tuning Error 0x0

r
27 Reserved
di V
st
re k-
28 FORCE_BOOT_ACK_ERR R/W Force Event for Response Error 0x0

31:29 Reserved
d il
an M
ADMA_ERR_STS
n by
ADMA Error Status Register

tio lic

1:0 ADMA_ERR_STS RO ADMA Error Status
ca ub
0x0 : ST_STOP ( Stop DMA)

0x1 : ST_FDS ( Fetch Descriptor)
ifi p
0x2 : Never set this state

0x3 : ST_TFR ( transfer data)
od de
2 ADMA_LEN_MISMATCH RO ADMA Length Mismatch Error

M a
31:3 Reserved
M
ADMA_SADDR_L
ADMA System Address Register for low 32-bit
31:0 ADMA_SA_L R/W ADMA System Address for low 32-bit 0x0
ADMA_SADDR_H
ADMA System Address Register for high 32-bit
532
CV1835

31:0 ADMA_SA_H R/W ADMA System Address for high 32-bit 0x0
PRESENT_VUL_INIT_DS
Present Value Register for Initialization and Default Speed
31:0 PRESENT_VUL_INIT_DS RO Present Value Register for Initialization
and Default Speed
ed
PRESENT_VUL_HS_SDR12
w
Present Value Register for High-speed and SDR12
lo
al
31:0 PRESENT_VUL_HS_SDR12 RO Present Value Register for High-speed
and SDR12
t
no
PRESENT_VUL_SDR25_SDR50
Present Value Register for SDR25 and SDR50
e
ar
31:0 PRESENT_VUL_SDR25_SDR50 RO Present Value Register for SDR25 and
n
SDR50
tio
PRESENT_VUL_SDR104_DDR50
u
Present Value Register for SDR104 and DDR50

ib

r
di V

st
re k-
31:0 PRESENT_VUL_SDR104_DDR50 RO Present Value Register for SDR104 and

DDR50
d il
an M
SLOT_INT_AND_HOST_VER
n by
Slot Interrupt Status and Host Controller Version Register

tio lic
7:0 INT_SLOT RO Interrupt Signal for Each Slot

ca ub
15:8 Reserved
23:16 SPEC_VER RO Specification Version Number
ifi p
00h : SD Host 1.00

od de
01h : SD Host 2.00

02h : SD Host 3.00
M a
03h : SD Host 4.00

M
04h : SD Host 4.10

05h : SD Host 4.20
31:24 VENDOR_VER RO Verdor Version Number
EMMC_CTRL
MSHC Control register
0 EMMC_FUNC_EN R/W eMMC Card present 0x0
1 LATANCY_1T R/W Latancy 1t for cmd in 0x1
2 CLK_FREE_EN R/W Internal clock gating disable control 0x0
3 DISABLE_DATA_CRC_CHK R/W Disable Data CRC Check 0x0
533
CV1835

7:4 Reserved
8 EMMC_RSTN R/W EMMC Device Reset Signal control 0x1
9 EMMC_RSTN_OEN R/W Output Enable control for EMMC Device 0x1
Reset Signal PAD
11:10 Reserved
12 CQE_ALGO_SEL R/W Scheduler algorithm selected for 0x0
execution
1 : First come First serve ( FCFS_ONLY)
ed
0 : Priority based reordering with FCFS
(PRI_REORDER_PLUS_FCFS)
w
13 CQE_PREFETCH_DISABLE R/W Enable or Disable CQE's PREFETCH 0x0
Feature
lo
1 : Disable
al
0 : Enable
15:14 Reserved
t
no
16 timer_clk_sel R/W timer clock source selection 0x0
1 : 32K
0 : 100K
e
31:17 Reserved
CDET_TOUT_CTL ar
n
tio
Card Detect Control Register
u

ib
15:0 CDET_DEBUUNCE_CNT R/W card detect debounce counter 0x000F

31:16 Reserved
r
di V
st
re k-
MBIU_CTRL
d il
MBIU Control register

an M

n by
0 UNDEFL_INCR_EN R/W Undefined INCR Burst 0x1

1 BURST_INCR4_EN R/W INCR4 Burst 0x1
tio lic

ca ub
31:4 Reserved
ifi p
PHY_TX_RX_DLY
od de
PHY tx and rx delay line register

M a
M

6:0 PHY_TX_DLY R/W PHY tx delay line phase selection 0x0
7 Reserved
9:8 PHY_TX_SRC R/W PHY tx delay line clock source selection 0x0
2'b00 : clk_tx
2'b01 : inverse of clk_tx
2'b1x : reserved
10 PHY_TX_EVEN_ODD R/W PHY tx delay line clock source selection 0x0
15:11 Reserved
22:16 PHY_RX_DLY R/W PHY rx delay line phase selection 0x0
2'b00 : clk_tx
2'b01 : inverse of clk_tx
534
CV1835

2'b1x : reserved
23 Reserved
25:24 PHY_RX_SRC R/W PHY rx delay line clock source selection 0x0
26 PHY_RX_EVEN_ODD R/W PHY rx delay line clock source selection 0x0
31:27 Reserved
PHY_DS_DLY
PHY DS delay line register
ed
w
6:0 PHY_DS_DLY R/W PHY DS delay line phase selection 0x0
lo
7 Reserved
al
9:8 PHY_DS_SRC R/W PHY DS delay line clock source selection 0x0
10 PHY_DS_EVEN_ODD R/W PHY DS delay line clock source selection 0x0
t
31:11 Reserved
no
PHY_DLY_STS
e
PHY delay line status register
ar
n
0 PHY_TX_LEAD_LAG RO PHY tx delay line lead or lag flag
tio
1 PHY_RX_LEAD_LAG RO PHY rx delay line lead or lag flag

u
2 PHY_DS_LEAD_LAG RO PHY ds delay line lead or lag flag

ib
31:3 Reserved
r
di V
st
re k-
PHY_CONFIG
d il
PHY Configuration register

an M

n by
0 PHY_TX_BPS R/W PHY tx data path bypass enable 0x1

0 : Pipe enable
1 : Bypass
tio lic
1 ADJ_TIMING_EN R/W Adjust bus timing enable 0x0

ca ub
7:2 Reserved
9:8 ADJ_NCR R/W Adjust NCR counter 0x0
ifi p
11:10 ADJ_NCRC R/W Adjust NCRC counter 0x0

od de
31:12 Reserved
M a
M
535
CV1835
12.5GPIO
12.5.1 Overview
The system is equipped with four groups of GPIO (General Purpose Input/Output),
namely GPIO0, GPIO1, GPIO2, and GPIO3. Each group of GPIO provides 32
ed
programmable Input / Output pins.
w
The direction of each pin can be arbitrarily set as input or output to generate the output
lo
al
signal of a specific application or collect the input signal of a specific application. When
set to input pin, GPIO can be used as interrupt source; when set to output pin, each
t
no
GPIO can output 0 or 1 independently.
e
GPIO can generate maskable interrupt according to the level or value change of input
ar
signal(level or edge sensitive). GPIOx_INTR_FLAG（x=0~3） signal gives an indication
n
to the interrupt controller, indicating that an interrupt has occurred.
u tio
r ib
di V
st
The direction of each pin can be set as input or output.

re k-
When set to input pin, GPIO can be used as interrupt source.

d il
an M
When set to output pin, each GPIO can output 0 or 1 independently.

n by
12.5.3 Working Mode

tio lic
ca ub
12.5.3.1 Interface Reset

ifi p
od de
When the chip is powered on or the system is reset, the four GPIO modules are reset at
the same time, and the GPIO pins are in the input state by default after reset.
M a
M
12.5.3.2 General Input and Output
Each pin can be set as input or output at will. The steps are as follows.
Step 1 Configure register GPIO_SWPORTA_DDR and set GPIO as input or output.

Step 2 When the input pin is configured, read GPIO_EXT_PORTA register in order to
check the value of the input signal; when the output pin is configured, write the
536
CV1835
output value to the GPIO_SWPORTA_DR register to control the GPIO output

level.
12.5.3.3 Interrupt Operation
Each GPIO can be used as an interrupt source through the control of nine registers
including GPIO_INTEN and so on. By these registers, the user can select the interrupt
ed
source, interrupt level polarity and edge trigger characteristics.
w
When multiple GPIO interrupts occur at the same time, one interrupt will be aggregated
lo
al
for reporting (each of the four groups of GPIO will have a collective flag broken
reporting).
t
no
The characteristics of interrupt source and the type of interrupt trigger are determined
by the following five registers: GPIO_INTTYPE_LEVEL, GPIO_INT_POLARITY,
e
ar
GPIO_INTMASK, GPIO_DEBOUNCE, and GPIO_LS_SYNC. n
The original state and masked state of the interrupt are read through
tio
GPIO_RAW_INTSTATUS and GPIO_INTSTATUS. By setting GPIO_PORTA_EOI, that can

u
control the interrupt state clearing.

ib
Each GPIO can support interrupt. The setting steps are as follows.
r
di V
st
re k-
Step 1 Configure register GPIO_INTTYPE_LEVEL and select level trigger or edge

d il
trigger.
an M
Step 2 Configure register GPIO_INT_POLARITY and select low level / high level trigger
n by
as well as falling edge / rising edge trigger.

Step 3 Write 0xFFFFFFFF to register GPIO_PORTA_EOI to clear the interrupt.
tio lic
步骤 4 Configure GPIO_INTEN register; enable GPIO pin interrupt function.

ca ub
ifi p
12.5.4 GPIORegister Overview

od de
M a
The base addresses of the four GPIO modules are shown in Table 12-7.
M
Table 12- 3 Four GPIO Module Base Addresses of the Chip

GPIO0 0x03020000
GPIO1 0x03021000
GPIO2 0x03022000
GPIO3 0x03023000
RTCSYS_GPIO 0x05021000
537
CV1835
Table 12-8 shows the offset addresses and definitions of the first group of GPIO module
(GPIO0) registers. GPIO0 to GPIO3 have the same register definitions.
Table 12- 9 GPIO Register Overview

ed
Offset
w
GPIO_SWPORTA_DR 0x000 Port A data register
GPIO_SWPORTA_DDR 0x004 Port A data direction register
lo
GPIO_INTEN 0x030 Interrupt enable register
al
GPIO_INTMASK 0x034 Interrupt mask register
GPIO_INTTYPE_LEVEL 0x038 Interrupt level register
t
GPIO_INT_POLARITY 0x03c Interrupt polarity register
no
GPIO_INTSTATUS 0x040 Interrupt status of Port A
GPIO_RAW_INTSTATUS 0x044 Raw interrupt status of Port A (pre-masking)
e
GPIO_DEBOUNCE 0x048 Debounce enable register
ar
GPIO_PORTA_EOI 0x04c Port A clear interrupt register
GPIO_EXT_PORTA 0x050 Port A external port register
n
GPIO_LS_SYNC 0x060 Level-sensitive synchronization enable register
u tio
ib
12.5.5 GPIO Register Description

r
di V
st
re k-
d il
an M
GPIO_SWPORTA_DR
n by

tio lic
31:0 GPIO_SWPORTA_DR R/W Values written to this register are 0x0

output on the I/O signals for Port A if
ca ub
the corresponding data direction bits for

Port A are set to Output mode and the
ifi p
corresponding control bit for Port A is

od de
set to Software mode. The value read

back is equal to the last value written to
M a
this register.
M
GPIO_SWPORTA_DDR
31:0 GPIO_SWPORTA_DDR R/W Values written to this register 0x0
independently control the direction of
the corresponding data bit in Port A.
The default direction can be configured
as input or output after system reset
through the GPIO_DFLT_DIR_A
parameter.
0 – Input (default)
538
CV1835

1 – Output
GPIO_INTEN
31:0 GPIO_INTEN R/W Allows each bit of Port A to be 0x0
configured for interrupts. By default the
generation of interrupts is disabled.
ed
Whenever a 1 is written to a bit of this
register, it configures the corresponding
w
bit on Port A to become an interrupt;
lo
otherwise, Port A operates as a normal
GPIO signal. Interrupts are disabled on
al
the corresponding bits of Port A if the
t
corresponding data direction register is
no
set to Output or if Port A mode is set to
Hardware.
0 – Configure Port A bit as normal GPIO
e
signal (default)
ar
1 – Configure Port A bit as interrupt
n
GPIO_INTMASK
tio

u

ib
31:0 GPIO_INTMASK R/W Controls whether an interrupt on Port A 0x0

r
can create an interrupt for the interrupt

di V
st
controller by not masking it. By default,

re k-
all interrupts bits are unmasked.

d il
Whenever a 1 is written to a bit in this

an M
register, it masks the interrupt

generation capability for this signal;
n by
otherwise interrupts are allowed

through. The unmasked status can be
read as well as the resultant status after
tio lic
masking.
ca ub
0 – Interrupt bits are unmasked

(default)
ifi p
1 – Mask interrupt
od de
GPIO_INTTYPE_LEVEL
M a

M

31:0 GPIO_INTTYPE_LEVEL R/W Controls the type of interrupt that can 0x0
occur on Port A.
Whenever a 0 is written to a bit of this
register, it configures the interrupt type
to be level-sensitive; otherwise, it is
edge-sensitive.
0 – Level-sensitive (default)
1 – Edge-sensitive
GPIO_INT_POLARITY
539
CV1835

31:0 GPIO_INT_POLARITY R/W Controls the polarity of edge or level 0x0
sensitivity that can occur on input of
Port A. Whenever a 0 is written to a bit
of this register, it configures the
interrupt type to falling-edge or active-
low sensitive; otherwise, it is rising-edge
or active-high sensitive.
0 – Active-low (default)
ed
1 – Active-high
w
GPIO_INTSTATUS
lo
al
t
31:0 GPIO_INTSTATUS RO Interrupt status of Port A
no
GPIO_RAW_INTSTATUS
e
ar
n
31:0 GPIO_RAW_INTSTATUS RO Raw interrupt of status of Port A
tio
(premasking bits)
u
GPIO_DEBOUNCE
ib

r
di V
st

re k-
31:0 GPIO_DEBOUNCE R/W Controls whether an external signal that 0x0

d il
is the source of an interrupt needs to be

an M
debounced to remove any spurious

glitches. Writing a 1 to a bit in this
n by
register enables the debouncing

circuitry. A signal must be valid for two
periods of an external clock before it is
tio lic
internally processed.
ca ub
0 – No debounce (default)
1 – Enable debounce
ifi p
GPIO_PORTA_EOI
od de

M a

M
31:0 GPIO_PORTA_EOI R/W Controls the clearing of edge type 0x0

interrupts from Port A.
When a 1 is written into a
corresponding bit of this register, the
interrupt is cleared. All interrupts are
cleared when Port A is not configured
for interrupts.
0 – No interrupt clear (default)
1 – Clear interrupt
GPIO_EXT_PORTA
540
CV1835

31:0 GPIO_EXT_PORTA RO When Port A is configured as Input,
then reading this location reads the
values on the signal. When the data
direction of Port A is set as Output,
reading this location reads the data
register for Port A.
ed
GPIO_LS_SYNC
w
lo
0 GPIO_LS_SYNC R/W [0] Synchronization level 0x0
al
Writing a 1 to this register results in all
level-sensitive interrupts being
t
synchronized to pclk_intr.
no
0 – No synchronization to pclk_intr
(default)
e
1 – Synchronize to pclk_intr
ar
31:1 Reserved
n
u tio
r ib
di V
st
12.6USB DRD (Dual Role Device)

re k-
d il
an M
12.6.1 Overview
n by
tio lic
The function of USB DRD is to play the role of Hostor Device respectively, which can be changed
ca ub
by software setting. The transfer protocol conforms to USB 2.0 specification, and the maximum
ifi p
transfer rate can reach more than 40 MB/s. The software interface of Host conforms to xHCI
od de
specification, and the main operation mode of Device is scatter/gather DMA. Details will be
M a
described in the following sections. The functions of USB DRD are as follows.
M
． Control Transfer
． Bulk Transfer
． Isochronous Transfer
．Host can connect USB Hub and support Interrupt Transfer)
．USB DRD passed the USB electrical characteristic test (USBET), showing
that the signal quality and compatibility are good
541
CV1835
12.6.2.1 System Block Diagram
The picture below shows the internal system block diagram of USB DRD.
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
542
CV1835
12.6.2.2 Function Characteristics
The functions of USB DRD are as follows.

． Comply with USB2.0 transmission protocol
． Compatible with USB1.1 transmission protocol
． Support HS / FS / LS three speed modes
ed
． Support Host or Device functions
w
． Support four kinds of USB transmission modes: control transfer, bulk transfer, isochronous
lo
transfer and interrupt transfer
al
． It can connect USB Hub and expand single interface to multiple USB interfaces
t
． Up to 127 device devices can be connected through USB hub extension
no
． Support USB2.0 suspend / resume power saving mode
． Support keyboard, mouse and other HID devices
e
ar
． Device mode is mainly used for downloading and updating internal software. It can also be
used for other functions, such as data transmission
n
tio
． The maximum transmission rate is more than 40 MB/s

u
r ib
12.6.3 USBC Function and Register Description

di V
st
re k-
d il
12.6.3.1 USBC Function Description

an M
n by
USB DRD can switch between Host and Device functions, and can choose between one of them,
However, it can't work at the same time. Its function selection and management are controlled
tio lic
by the USB block. In addition, there are some events and interrupt triggers on the serial bus
ca ub
between the host and device that also place buffers in this block.
ifi p
12.6.3.2 USBC Register Abstract

od de
M a
M

Offset
GOTGCTL 0x000 Control and Status Register
GOTGINT 0x004 Interrupt Register
GAHBCFG 0x008 AHB Configuration Register
GUSBCFG 0x00c USB Configuration Register
GRSTCTL 0x010 Reset Register
GINTSTS 0x014 Interrupt Status Register
GINTMSK 0x018 Interrupt Mask Register
GUID 0x03c User ID Register
GLPMCFG 0x054 Core LPM Configuration Register
GPWRDN 0x058 Power Down Register
543
CV1835
12.6.3.3 The Detailed List of USBC Registers
The memory address of USBC is 0x0434_0000, represented as USBC_BASE_ADDR in the

document. To read and write to it, the real memory address in the memory space is represented
as USBC_BASE_ADDR + Offset. Each register has its corresponding relative address (Offset),
which is described in detail below.
ed
GOTGCTL
w
Control and Status Register
lo
al
Bits Name Acces Description Reset
s
t
0 SesReqScs RO Mode: Device only
no
Session Request Success (SesReqScs)
The core sets this bit when a session request initiation is
e
successful.
ar
■ 1'b0: Session request failure
■ 1'b1: Session request successn
Shadow: Yes
tio
Shadow Ctrl: vs_1t
One-Way: Enabled
u
ib
1 SesReq R/W Mode: SRP-capable device 0x0

Session Request (SesReq)
r
di V
The application sets this bit to initiate a session request on

st
re k-
the USB. The application can clear this bit by writing a 0

when the Host Negotiation
d il
Success Status Change bit in the OTG Interrupt register

an M
(GOTGINT.HstNegSucStsChng) is SET. The core clears this bit

when the HstNegSucStsChng bit is cleared.
n by
If you use the USB 1.1 Full-Speed Serial Transceiver interface

to initiate the session request, the application must wait
tio lic
until the VBUS discharges to 0.2 V, after the B-Session Valid

bit in this register (GOTGCTL.BSesVld) is cleared. This
ca ub
discharge time varies between

different PHYs and can be obtained from the PHY vendor.
ifi p
■ 1'b0: No session request

■ 1'b1: Session request
od de
Shadow: Yes
M a
Shadow Ctrl: vs_1t

M

2 VbvalidOvEn R/W Mode: Host only 0x0
VBUS Valid Override Enable (VbvalidOvEn)
This bit is used to enable/disable the software to override
the Bvalid
signal using the GOTGCTL.VbvalidOvVal.
■ 1'b1: Internally Bvalid received from the PHY is
overridden with
GOTGCTL.VbvalidOvVal.
■ 1'b0: Override is disabled and bvalid signal from the
respective PHY
selected is used internally by the core.
Shadow: Yes
544
CV1835

s
Shadow Ctrl: vs_1t
One-Way: Enabled
3 VbvalidOvVal R/W Mode: Host only 0x0
VBUS Valid Override Value (VbvalidOvVal)
This bit is used to set Override value for vbusvalid signal
when
GOTGCTL.VbvalidOvEn is set.
ed
■ 1'b0: vbusvalid value is 1'b0 when GOTGCTL.VbvalidOvEn
=1
w
■ 1'b1: vbusvalid value is 1'b1 when GOTGCTL.VbvalidOvEn
lo
=1
4 AvalidOvEn R/W Mode: Host only 0x0
al
A-Peripheral Session Valid Override Enable (AvalidOvEn)
t
no
the Avalid
signal using the GOTGCTL.AvalidOvVal.
■ 1'b1: Internally Avalid received from the PHY is
e
overridden with
ar
GOTGCTL.AvalidOvVal.
■ 1'b0: Override is disabled and avalid signal from the
n
respective PHY
tio
selected is used internally by the core.

5 AvalidOvVal R/W Mode: Host only 0x0
u
A-Peripheral Session Valid Override Value (AvalidOvVal)

ib
This bit is used to set Override value for Avalid signal when
r
GOTGCTL.AvalidOvEn is set.
di V
st
■ 1'b0: Avalid value is 1'b0 when GOTGCTL.AvalidOvEn =1

re k-
■ 1'b1: Avalid value is 1'b1 when GOTGCTL.AvalidOvEn =1

d il
6 BvalidOvEn R/W Mode: Device only 0x0

an M
B-Peripheral Session Valid Override Enable (BvalidOvEn)

n by
the Bvalid
signal using the GOTGCTL.BvalidOvVal.
■ 1'b1: Internally Bvalid received from the PHY is
tio lic
overridden with
ca ub
GOTGCTL.BvalidOvVal.
■ 1'b0: Override is disabled and bvalid signal from the
ifi p
respective PHY
selected is used internally by the force
od de
7 BvalidOvVal R/W Mode: Device only 0x0

B-Peripheral Session Valid Override Value (BvalidOvVal)
M a
This bit is used to set Override value for Bvalid signal when
M
GOTGCTL.BvalidOvEn is set.
■ 1'b0: Bvalid value is 1'b0 when GOTGCTL.BvalidOvEn =1
■ 1'b1: Bvalid value is 1'b1 when GOTGCTL.BvalidOvEn =1
8 HstNegScs RO Mode: HNP-capable device
Host Negotiation Success (HstNegScs)
The core sets this bit when host negotiation is successful.
The core
clears this bit when the HNP Request (HNPReq) bit in this
register is
set.
■ 1'b0: Host negotiation failure
■ 1'b1: Host negotiation success
545
CV1835

s
9 HNPReq R/W Mode: HNP Capable OTG Device 0x0
HNP Request (HNPReq)
The application sets this bit to initiate an HNP request to the
connected
USB host. The application can clear this bit by writing a 0
when the Host
Negotiation Success Status Change bit in the OTG Interrupt
register
ed
(GOTGINT.HstNegSucStsChng) is set. The core clears this bit
when the
w
HstNegSucStsChng bit is cleared.
■ 1'b0: No HNP request
lo
■ 1'b1: HNP request
al
10 HstSetHNPEn R/W Mode: HNP Capable OTG Host 0x0
Host Set HNP Enable (HstSetHNPEn)
t
no
The application sets this bit when it has successfully enabled
HNP
(using the SetFeature.SetHNPEnable command) on the
e
connected
ar
device.
■ 1'b0: Host Set HNP is not enabled
n
■ 1'b1: Host Set HNP is enabled
tio
11 DevHNPEn R/W Mode: HNP Capable OTG Device 0x0

Device HNP Enabled (DevHNPEn)
u
The application sets this bit when it successfully receives

ib
aSetFeature.SetHNPEnable command from the connected

r
USB host.
di V
st
■ 1'b0: HNP is not enabled in the application

re k-
■ 1'b1: HNP is enabled in the application

d il
12 EHEn R/W Embedded Host Enable 0x0

an M
It is used to select between OTG A Device state Machine

andEmbedded Host state machine.
n by
■ 1'b1: Embedded Host State Machine is selected

■ 1'b0: OTG A Device state machine is selected
tio lic
Note: This field is valid only in SRP-Capable OTG Mode

(OTG_MODE=0,1)
ca ub
14:13 Reserved_00_14_1 RO Reserved for future use.

3
ifi p
15 DbnceFltrBypass R/W Mode: Host and Device 0x0

Debounce Filter Bypass
od de
Bypass Debounce filters for avalid, bvalid, vbusvalid,

sessend, and iddig
M a
signals when enabled.

M
■ 1'b0: Disabled
■ 1'b1: Enabled
16 ConIDSts RO Mode: Host and Device
Connector ID Status (ConIDSts)
Indicates the connector ID status on a connect event.
■ 1'b0: The DWC_otg core is in A-Device mode
■ 1'b1: The DWC_otg core is in B-Device mode
17 DbncTime RO Mode: Host only
Long/Short Debounce Time (DbncTime)
Indicates the debounce time of a detected connection.
■ 1'b0: Long debounce time, used for physical connections
(100 ms +
546
CV1835

s
2.5 μs)
■ 1'b1: Short debounce time, used for soft connections (2.5
μs)
18 ASesVld RO Mode: Host only
A-Session Valid (ASesVld)
Indicates the Host mode transceiver status.
■ 1'b0: A-session is not valid
■ 1'b1: A-session is valid
ed
19 BSesVld RO Mode: Device only
B-Session Valid (BSesVld)
w
Indicates the Device mode transceiver status.
lo
■ 1'b0: B-session is not valid.
al
■ 1'b1: B-session is valid.
In OTG mode, you can use this bit to determine if the device
t
is connected or disconnected.
no
20 OTGVer R/W OTG Version (OTGVer) 0x0
Indicates the OTG revision.
■ 1'b0: OTG Version 1.3. In this version the core supports
e
ar
Data line
pulsing and VBus pulsing for SRP.
■ 1'b1: OTG Version 2.0. In this version the core supports
n
only Data
tio
line pulsing for SRP.

21 CurMod_operation RO Current Mode of Operation (CurMod)
u
Mode: Host and Device

ib
Indicates the current mode.

r
■ 1'b0: Device mode

di V
st
re k-
■ 1'b1: Host mode

26:22 MultValIdBC_opera RO Multi Valued ID pin (MultValIdBC)
d il
tion Mode: Host and Device

an M
Battery Charger ACA inputs in the following order:

■ Bit 26 - rid_float
n by
■ Bit 25 - rid_gnd
■ Bit 24 - rid_a
tio lic
■ Bit 23 - rid_b
■ Bit 22 - rid_c
ca ub
27 ChirpEn RO Chirp On Enable (ChirpEn)

ifi p
Mode: Device Only

This bit when programmed to 1'b1 results in the core
od de
asserting chirp_on
before sending an actual Chirp "K" signal on USB. This bit is
M a
present
M
only if OTG_BC_SUPPORT = 1. If OTG_BC_SUPPORT!=1, this

bit is a
reserved bit.
8
GOTGINT
Interrupt Register
Shadow: Yes
547
CV1835

Shadow Ctrl: vs_1t
2 SesEndDet RWC Write Behavior: One to clear
Session End Detected (SesEndDet)
The core sets this bit when the utmiotg_bvalid signal
is
deasserted.This bit can be set only by the core and
the application
ed
should write 1 to clear it.
w
8 SesReqSucStsChng RWC Write Behavior: One to clear
lo
al
Session Request Success Status Change
(SesReqSucStsChng)
t
The core sets this bit on the success or failure of a
no
session request.
The application must read the Session Request
Success bit in the
e
OTG Control and Status register
ar
(GOTGCTL.SesReqScs) to check
for success or failure.This bit can be set only by the
n
core and the
tio
application should write 1 to clear it.

9 HstNegSucStsChng RWC Write Behavior: One to clear
u

ib
Host Negotiation Success Status Change

r
(HstNegSucStsChng)
di V
st
The core sets this bit on the success or failure of a

re k-
USB host
d il
negotiation request. The application must read the

an M
Host Negotiation
Success bit of the OTG Control and Status register
n by
(GOTGCTL.HstNegScs) to check for success or

failure.This bit can
be set only by the core and the application should
tio lic
write 1 to clear it.

ca ub
17 HstNegDet RWC Write Behavior: One to clear

ifi p

Host Negotiation Detected (HstNegDet)
od de
The core sets this bit when it detects a host

negotiation request on
M a
the USB.This bit can be set only by the core and the
M
application
should write 1 to clear it.
18 ADevTOUTChg RWC Write Behavior: One to clear
A-Device Timeout Change (ADevTOUTChg)
The core sets this bit to indicate that the A-device
has timed out
while waiting for the B-device to connect.This bit can
be set only by
the core and the application should write 1 to clear
it.
19 DbnceDone RWC Write Behavior: One to clear
548
CV1835

Mode: Host only
Debounce Done (DbnceDone)
The core sets this bit when the debounce is
completed after the
device connect. The application can start driving USB
reset after
seeing this interrupt. This bit is only valid when the
HNP Capable or
SRP Capable bit is set in the Core USB Configuration
ed
register
(GUSBCFG.HNPCap or GUSBCFG.SRPCap,
w
respectively).This bit
can be set only by the core and the application
lo
should write 1 to
al
clear it.
20 MultValIpChng RWC Write Behavior: One to clear
t
This bit when set indicates that there is a change in
no
the value of at
least one ACA pin value.
e
This bit is present only if OTG_BC_SUPPORT=1,
ar
otherwise it is
reserved. n
tio
Shadow: Yes
Shadow Ctrl: vs_1t
u
ib
GAHBCFG
r
di V
st
AHB Configuration Register

re k-

d il
an M
0 GlblIntrMsk R/W Mode: Host and device 0x0

Global Interrupt Mask (GlblIntrMsk)
n by
The application uses this bit to mask or unmask the interrupt

line assertion
to itself. Irrespective of this bit's setting, the interrupt status
tio lic
registers are
updated by the core.
ca ub
■ 1'b0: Mask the interrupt assertion to the application.

■ 1'b1: Unmask the interrupt assertion to the application.
ifi p
Shadow: Yes
od de
Shadow Ctrl: vs_1t

M a
4:1 HBstLen R/W Mode: Host and device 0x0

M
Burst Length/Type (HBstLen)

This field is used in both External and Internal DMA modes.
In External
DMA mode, these bits appear on dma_burst[3:0] ports,
which can be used
by an external wrapper to interface the External DMA
Controller interface to
Synopsys DW_ahb_dmac or ARM PrimeCell.
External DMA Mode defines the DMA burst length in terms
of 32-bit words:
■ 4'b0000: 1 word
■ 4'b0001: 4 words
549
CV1835

■ 4'b0010: 8 words
■ 4'b0011: 16 words
■ 4'b0100: 32 words
■ 4'b0101: 64 words
■ 4'b0110: 128 words
■ 4'b0111: 256 words
■ Others: Reserved
Internal DMA Mode-AHB Master burst type:
ed
■ 4'b0000 Single
■ 4'b0001 INCR 4'b0011
w
■ INCR4 4'b0101
lo
■ INCR8 4'b0111
■ INCR16
al
t
5 DMAEn R/W Mode: Host and device 0x0
no
DMA Enable (DMAEn)
■ 1'b0: Core operates in Slave mode
■ 1'b1: Core operates in a DMA mode
e
This bit is always 0 when Slave-Only mode has been
ar
selected.
6 Reserved_08_6 RO Reserved for future use.
n
Shadow: Yes
tio
Shadow Ctrl: vs_1t

u
7 NPTxFEmpLvl R/W Mode: Host and device 0x0

ib
Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)

r
This bit is used only in Slave mode. In host mode and with
di V
st
Shared FIFO
re k-
with device mode, this bit indicates when the Non-Periodic

d il
TxFIFO Empty
an M
Interrupt bit in the Core Interrupt register

(GINTSTS.NPTxFEmp) is
n by
triggered.
With dedicated FIFO in device mode, this bit indicates when
IN endpoint
tio lic
Transmit FIFO empty interrupt (DIEPINTn.TxFEmp) is

triggered.
ca ub
Host mode and with Shared FIFO with device mode:

ifi p
■ 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the

Non- Periodic
od de
TxFIFO is half empty

■ 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the
M a
Non- Periodic
M
TxFIFO is completely empty

Dedicated FIFO in device mode:
■ 1'b0: DIEPINTn.TxFEmp interrupt indicates that the IN
Endpoint
TxFIFO is half empty
■ 1'b1: DIEPINTn.TxFEmp interrupt indicates that the IN
Endpoint
TxFIFO is completely empty
8 PTxFEmpLvl R/W Mode: Host only 0x0
Periodic TxFIFO Empty Level (PTxFEmpLvl)
Indicates when the Periodic TxFIFO Empty Interrupt bit in
the Core
550
CV1835

Interrupt register (GINTSTS.PTxFEmp) is triggered. This bit is
used only in
Slave mode.
■ 1'b0: GINTSTS.PTxFEmp interrupt indicates that the
Periodic TxFIFO is
half empty
■ 1'b1: GINTSTS.PTxFEmp interrupt indicates that the
Periodic TxFIFO is
completely empty
ed
20:9 Reserved_08_20_ RO Reserved for future use.
9 Shadow: Yes
w
Shadow Ctrl: vs_1t
lo
21 RemMemSupp R/W Mode: Host and Device 0x0
al
Remote Memory Support (RemMemSupp)
This bit is programmed to enable the functionality to wait
t
no
for the system
DMA Done Signal for the DMA Write Transfers.
■ GAHBCFG.RemMemSupp=1
e
The int_dma_req output signal is asserted when HSOTG
ar
DMA starts
write transfer to the external memory. When the core is
n
done with the
tio
Transfers it asserts int_dma_done signal to flag the

completion of DMA
u
writes from HSOTG. The core then waits for sys_dma_done

ib
signal from
the system to proceed further and complete the Data
r
di V
st
Transfer
re k-
corresponding to a particular Channel/Endpoint.

■ GAHBCFG.RemMemSupp=0
d il
an M
The int_dma_req and int_dma_done signals are not asserted

and the
core proceeds with the assertion of the XferComp interrupt
n by
as soon as
the DMA write transfer is done at the HSOTG Core Boundary
tio lic
and it
doesn't wait for the sys_dma_done signal to complete the
ca ub
DATA
transfers.
ifi p
22 NotiAllDmaWrit R/W Mode: Host and Device 0x0

od de
Notify all DMA Write Transactions (NotiAllDmaWrit)

This bit is programmed to enable the System DMA Done
M a
functionality for all

M
the DMA write Transactions corresponding to the

Channel/Endpoint. This
bit is valid only when GAHBCFG.RemMemSupp is set to 1.
■ GAHBCFG.NotiAllDmaWrit = 1
DWC_otg core asserts int_dma_req for all the DMA write
transactions
on the AHB interface along with int_dma_done,
chep_last_transact and
chep_number signal informations. The core waits for
sys_dma_done
signal for all the DMA write transactions in order to
complete the
transfer of a particular Channel/Endpoint.
551
CV1835

■ GAHBCFG.NotiAllDmaWrit = 0
DWC_otg core asserts int_dma_req signal only for the last
transaction
of DMA write transfer corresponding to a particular
Channel/Endpoint.
Similarly, the core waits for sys_dma_done signal only for
that
transaction of DMA write to complete the transfer of a
particular
ed
Channel/Endpoint.
23 AHBSingle R/W Mode: Host and Device 0x0
w
AHBSingleSupport (AHBSingle)
lo
This bit when programmed supports Single transfers for the
remaining data
al
in a transfer when the DWC_otg core is operating in DMA
mode.
t
■ 1’b0: This is the default mode. When this bit is set to
no
1’b0, the remaining
data in the transfer is sent using INCR burst size.
e
■ 1’b1: When set to 1’b1, the remaining data in a transfer is
ar
sent using
Single burst size.
n
Note: If this feature is enabled, the AHB RETRY and SPLIT
tio
transfers still
have INCR burst type. Enable this feature when the AHB
u
Slave connected
ib
to the DWC_otg core does not support INCR burst (and

when Split, and
r
di V
st
Retry transactions are not being used in the bus.)

re k-
24 InvDescEndiannes R/W Mode: Host and Device 0x0

s Inverse Descriptor Endianness
d il
an M
■ 1'b0: Descriptor endianness is similar to the AHB Master

endianness
■ 1'b1:
n by
- If the AHB Master endianness is Big Endian, the Descriptor

Endianness is Little Endian.
tio lic
- If the AHB Master endianness is Little Endian, the

Descriptor
ca ub
Endianness is Big Endian.

ifi p
25 Shadow: Yes
od de
Shadow Ctrl: vs_1t

M a
M
GUSBCFG
USB Configuration Register
2:0 TOutCal R/W Mode: Host and Device 0x0
HS/FS Timeout Calibration (TOutCal)
The number of PHY clocks that the application programs in this
field
is added to the high-speed/full-speed interpacket timeout
duration in
the core to account for any additional delays introduced by the
PHY.
552
CV1835

This can be required, because the delay introduced by the PHY
in
generating the linestate condition can vary from one PHY to
another.
The USB standard timeout value for high-speed operation is
736 to
816 (inclusive) bit times. The USB standard timeout value for
fullspeed
operation is 16 to 18 (inclusive) bit times. The application
ed
must program this field based on the speed of enumeration.
The
w
number of bit times added per PHY clock are:
High-speed operation:
lo
■ One 30-MHz PHY clock = 16 bit times
al
■ One 60-MHz PHY clock = 8 bit times
Full-speed operation:
t
no
■ One 30-MHz PHY clock = 0.4 bit times
e
Using the HS as an example, if you set ToutCal to '001' you add
ar
one
30MHz PHY clock or 16 bit times. If you set ToutCal to '010'
n
you add
tio
two 30MHz PHY clocks or 32 bit times, and so on. The 3 bits
allow
u
you to add up to 7 PHY clocks, and the number of bit times

ib
depend
r
on the speed, and the PHY clock you are using.

di V
st
Shadow: Yes
re k-
Shadow Ctrl: vs_1t

d il

an M
One-Way: Enabled
3 PHYIf RO Mode: Host and Device
n by
PHY Interface (PHYIf)

The application uses this bit to configure the core to support a
UTMI+ PHY with an 8- or 16-bit interface. When a ULPI PHY is
tio lic
chosen, this must be set to 8-bit mode.

■ 1'b0: 8 bits
ca ub
■ 1'b1: 16 bits
ifi p
This bit is writable only If UTMI+ and ULPI were selected.

Otherwise, this bit returns the value for the power-on
od de
interface
selected during configuration.
M a
Shadow: Yes
M
Shadow Ctrl: vs_1t

4 ULPI_UTMI_Sel R/W Mode: Host and Device 0x0
ULPI or UTMI+ Select (ULPI_UTMI_Sel)
The application uses this bit to select either a UTMI+ interface
or
ULPI Interface.
■ 1'b0: UTMI+ Interface
■ 1'b1: ULPI Interface
This bit is writable only If UTMI+ and ULPI was specified for
High-
Speed PHY Interface(s).
553
CV1835

Shadow: Yes
Shadow Ctrl: vs_1t
One-Way: Enabled
5 FSIntf R/W Mode: Host and Device 0x0
Full-Speed Serial Interface Select (FSIntf)
The application uses this bit to select either a unidirectional or
bidirectional USB 1.1 full-speed serial transceiver interface.
■ 1'b0: 6-pin unidirectional full-speed serial interface
ed
■ 1'b1: 3-pin bidirectional full-speed serial interface
If a USB 1.1 Full-Speed Serial Transceiver interface was not
w
selected, this bit is always 0, with Read Only access.
lo
If a USB 1.1 FS interface was selected, then the application can
set
al
this bit to select between the 3- and 6-pin interfaces, and
access is
t
no
Read and Write.
6 PHYSel R/W Mode: Host and Device 0x0
USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial
e
Transceiver
ar
Select (PHYSel)
The application uses this bit to select either a high-speed
n
UTMI+ or
tio
ULPI PHY, or a full-speed transceiver.

■ 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY
u
■ 1'b1: USB 1.1 full-speed serial transceiver

ib
If a USB 1.1 Full-Speed Serial Transceiver interface was not

r
selected, this bit is always 0, with Read Only access.

di V
st
If a high-speed PHY interface was not selected, this bit is

re k-
always 1,
with Read Only access.
d il
an M
If both interface types were selected (parameters have non-

zero
values), the application uses this bit to select which interface is
n by
active, and access is Read and Write.

7 DDRSel R/W Mode: Host and Device 0x0
tio lic
ULPI DDR Select (DDRSel)

The application uses this bit to select a Single Data Rate (SDR)
ca ub
or
Double Data Rate (DDR) or ULPI interface.
ifi p
■ 1'b0: Single Data Rate ULPI Interface, with 8-bit-wide data

od de
bus
■ 1'b1: Double Data Rate ULPI Interface, with 4-bit-wide data
M a
bus
M
This bit is valid only when OTG_HSPHY_INTERFACE = 2 or 3.

8 SRPCap R/W Mode: Host and Device 0x0
SRP-Capable (SRPCap)
The application uses this bit to control the DWC_otg core SRP
capabilities. If the core operates as a non-SRP-capable B-
device, it
cannot request the connected A-device (host) to activate VBUS
and
start a session.
■ 1'b0: SRP capability is not enabled.
■ 1'b1: SRP capability is enabled.
This bit is writable only if an SRP mode was specified for Mode
554
CV1835

of
Operation in coreConsultant (parameter OTG_MODE).
Otherwise,
reads return 0.
If SRP functionality is disabled by the software, the OTG signals
on
the PHY domain must be tied to the appropriate values.
9 HNPCap R/W Mode: Host and Device 0x0
HNP-Capable (HNPCap)
ed
The application uses this bit to control the DWC_otg core's
HNP
w
capabilities.
■ 1'b0: HNP capability is not enabled.
lo
■ 1'b1: HNP capability is enabled.
al
This bit is writable only if an HNP mode was specified for
Mode of
t
no
Operation in coreConsultant (parameter OTG_MODE).
Otherwise,
reads return 0.
e
If HNP functionality is disabled by the software, the OTG
ar
signals on
the PHY domain must be tied to the appropriate values.
n
13:10 USBTrdTim R/W Mode: Device only 0x5
tio
USB Turnaround Time (USBTrdTim)

Sets the turnaround time in PHY clocks. Specifies the response
u
time
ib
for a MAC request to the Packet FIFO Controller (PFC) to fetch

data
r
di V
st
from the DFIFO (SPRAM). This must be programmed to

re k-
■ 4'h5: When the MAC interface is 16-bit UTMI+.

■ 4'h9: When the MAC interface is 8-bit UTMI+.
d il
an M
Note: The values above are calculated for the minimum AHB
frequency of 30 MHz. USB turnaround time is critical for
certification
n by
where long cables and 5-Hubs are used, so If you need the
AHB to
tio lic
run at less than 30 MHz, and If USB turnaround time is not

critical,
ca ub
these bits can be programmed to a larger value.

14 Reserved_0C_1 RO Reserved for future use.
ifi p
4
od de
15 PhyLPwrClkSel R/W Mode: Host and Device 0x0

PHY Low-Power Clock Select (PhyLPwrClkSel)
M a
Selects either 480-MHz or 48-MHz (low-power) PHY mode. In

M
FS
and LS modes, the PHY can usually operate on a 48-MHz clock
to
save power.
■ 1'b0: 480-MHz Internal PLL clock
■ 1'b1: 48-MHz External Clock
In 480 MHz mode, the UTMI interface operates at either 60 or
30-
MHz, depending upon whether 8- or 16-bit data width is
selected. In
48-MHz mode, the UTMI interface operates at 48 MHz in FS
mode
and at either 48 or 6 MHz in LS mode (depending on the PHY
555
CV1835

vendor). This bit drives the utmi_fsls_low_power core output
signal,
and is valid only For UTMI+ PHYs.
16 OtgI2CSel R/W Mode: Host and Device 0x0
UTMIFS or I2C Interface Select (OtgI2CSel)
The application uses this bit to select the I2C interface.
■ 1’b0: UTMI USB 1.1 Full-Speed interface for OTG signals
■ 1’b1: I2C interface for OTG signals
This bit is writable only if I2C and UTMIFS were specified for
ed
Enable
I2C Interface? in coreConsultant (parameter
w
OTG_I2C_INTERFACE
lo
= 2). Otherwise, reads return 0.
17 ULPIFsLs R/W Mode: Host and Device 0x0
al
ULPI FS/LS Select (ULPIFsLs)
The application uses this bit to select the FS/LS serial interface
t
no
for
the ULPI PHY. This bit is valid only when the FS serial
transceiver is
e
selected on the ULPI PHY.
ar
■ 1'b0: ULPI interface
■ 1'b1: ULPI FS/LS serial interface
n
(Valid only when RTL parameters OTG_HSPHY_INTERFACE = 2
tio
or
3 and OTG_FSPHY_INTERFACE = 1, 2, or 3)
u
Before setting this bit, the application needs to ensure that

ib
GUSBCFG.ULPI_UTMI_SEL = 1'b1.
r
18 ULPIAutoRes R/W Mode: Host and Device 0x0

di V
st
ULPI Auto Resume (ULPIAutoRes)

re k-
This bit sets the AutoResume bit in the Interface Control

d il
register on
an M
the ULPI PHY.

■ 1'b0: PHY does not use AutoResume feature.
n by
■ 1'b1: PHY uses AutoResume feature.

(Valid only when RTL parameter OTG_HSPHY_INTERFACE = 2
or 3)
tio lic
19 ULPIClkSusM R/W Mode: Host and Device 0x0

ca ub
ULPI Clock SuspendM (ULPIClkSusM)

This bit sets the ClockSuspendM bit in the Interface Control
ifi p
register
on the ULPI PHY. This bit applies only in serial or carkit modes.
od de
■ 1'b0: PHY powers down internal clock during suspend.

■ 1'b1: PHY does not power down internal clock.
M a

M
or 3)
20 ULPIExtVbusDrv R/W Mode: Host only 0x0
ULPI External VBUS Drive (ULPIExtVbusDrv)
This bit selects between internal or external supply to drive 5V
on
VBUS, in ULPI PHY.
■ 1'b0: PHY drives VBUS using internal charge pump
(Default).
■ 1'b1: PHY drives VBUS using external supply.
or 3)
21 ULPIExtVbusInd R/W Mode: Host only 0x0
556
CV1835

icator ULPI External VBUS Indicator (ULPIExtVbusIndicator)
This bit indicates to the ULPI PHY to use an external VBUS
overcurrent indicator.
■ 1'b0: PHY uses internal VBUS valid comparator.
■ 1'b1: PHY uses external VBUS valid comparator.
or 3)
22 TermSelDLPulse R/W Mode: Device only 0x0
TermSel DLine Pulsing Selection (TermSelDLPulse)
ed
This bit selects utmi_termselect to drive data line pulse during
SRP.
w
■ 1'b0: Data line pulsing using utmi_txvalid (Default).
lo
■ 1'b1: Data line pulsing using utmi_termsel.
al
23 Complement R/W Mode: Host only 0x0
Indicator Complement
t
Controls the PHY to invert the ExternalVbusIndicator input
no
signal,
generating the Complement Output. For more information,
refer to
e
the ULPI Specification.
ar
■ 1'b0: PHY does not invert ExternalVbusIndicator signal
■ 1'b1: PHY does invert ExternalVbusIndicator signal
n
This bit is reserved and read-only when
tio
OTG_HSPHY_INTERFACE
is set to 0 or 1.
u
24 Indicator R/W Mode: Host only 0x0

ib
Indicator Pass Through

r
Controls whether the Complement Output is qualified with the

di V
st
Internal Vbus Valid comparator before being used in the Vbus

re k-
State
d il
in the RX CMD. For more information, refer to the ULPI

an M
Specification.
■ 1'b0: Complement Output signal is qualified with the
n by
Internal
VbusValid comparator.
■ 1'b1: Complement Output signal is not qualified with the
tio lic
Internal
ca ub
VbusValid comparator.
ifi p
OTG_HSPHY_INTERFACE
is set to 0 or 1.
od de
25 ULPI R/W Mode: Host only 0x0

ULPI Interface Protect Disable
M a
Controls circuitry built into the PHY For protecting the ULPI
M
interface
when the link tri-states STP and data. Any pull-ups or pull-
downs
employed by this feature can be disabled. For more
information,
refer to the ULPI Specification.
■ 1'b0: Enables the interface protect circuit
■ 1'b1: Disables the interface protect circuit
OTG_HSPHY_INTERFACE
is set to 0 or 1.
26 IC_USBCap RO Mode: Host and Device
557
CV1835

IC_USB-Capable (IC_USBCap)
The application uses this bit to control the DWC_otg core's
IC_USB
capabilities.
■ 1'b0: IC_USB PHY Interface is not selected.
■ 1'b1: IC_USB PHY Interface is selected.
This bit is writable only if OTG_ENABLE_IC_USB=1 and
OTG_FSPHY_INTERFACE!=0.
The reset value depends on the configuration parameter
ed
OTG_SELECT_IC_USB when OTG_ENABLE_IC_USB = 1. In all
other cases, this bit is set to 1'b0 and the bit is read only.
w
27 IC_USBTrafCtl R/W Mode: Device only 0x0
lo
IC_USB TrafficPullRemove Control (IC_USBTrafCtl)
When this bit is set, pullup/pulldown resistors are detached
al
from the
USB during traffic signaling, per section 6.3.4 of the IC_USB
t
no
specification. This bit is valid only when configuration
parameter
OTG_ENABLE_IC_USB = 1 and register field
e
USBCFG.IC_USBCap is set to 1.
ar
28 TxEndDelay R/W Mode: Device only 0x0
Tx End Delay (TxEndDelay)
n
Writing 1'b1 to this bit enables the core to follow the
tio
TxEndDelay
timings as per UTMI+ specification 1.05 section 4.1.5 for
u
opmode
ib
signal during remote wakeup.

■ 1'b0: Normal Mode.
r
di V
st
■ 1'b1: Tx End delay.

re k-
29 ForceHstMode R/W Mode: Host and device 0x0

d il
Force Host Mode (ForceHstMode)

an M
Writing a 1 to this bit forces the core to host mode irrespective

of
utmiotg_iddig input pin.
n by

■ 1'b1: Force Host Mode.
tio lic
After setting the force bit, the application must wait at least 25
ms
ca ub
before the change to take effect. When the simulation is in

ifi p
scale
down mode, waiting for 500 μs is sufficient. This bit is valid
od de
only
when OTG_MODE = 0, 1 or 2. In all other cases, this bit reads
M a
0.
M
30 ForceDevMode R/W Mode: Host and device 0x0

Force Device Mode (ForceDevMode)
Writing a 1 to this bit forces the core to device mode
irrespective of
utmiotg_iddig input pin.
■ 1'b1: Force Device Mode.
After setting the force bit, the application must wait at least 25
ms
before the change to take effect. When the simulation is in
scale
down mode, waiting for 500 μs is sufficient. This bit is valid
558
CV1835

only
when OTG_MODE = 0, 1 or 2. In all other cases, this bit reads
0.
31 CorruptTxPkt R/W Mode: Host and device 0x0
Corrupt Tx packet (CorruptTxPkt)
This bit is for debug purposes only. Never set this bit to 1.The
application should always write 1'b0 to this bit.
GRSTCTL
ed
Reset Register
w
lo
0 CSftRst RO Write Behavior: One to set
al
Core Soft Reset (CSftRst)
t
Resets the hclk and phy_clock domains as follows:
no
■ Clears the interrupts and all the CSR registers except the
following register
bits:
e
- PCGCCTL.RstPdwnModule
ar
- PCGCCTL.GateHclk
- PCGCCTL.PwrClmp
n
- PCGCCTL.StopPPhyLPwrClkSelclk
tio
- GUSBCFG.PhyLPwrClkSel
- GUSBCFG.DDRSel
u
- GUSBCFG.PHYSel
ib
- GUSBCFG.FSIntf
r
- GUSBCFG.ULPI_UTMI_Sel
di V
st
- GUSBCFG.PHYIf
re k-
- GUSBCFG.TxEndDelay
d il
- GUSBCFG.TermSelDLPulse
an M
- GUSBCFG.ULPIClkSusM
- GUSBCFG.ULPIAutoRes
n by
- GUSBCFG.ULPIFsLs
- GGPIO
- GPWRDN
tio lic
- GADPCTL
- HCFG.FSLSPclkSel
ca ub
- DCFG.DevSpd
- DCTL.SftDiscon
ifi p
■ All module state machines (except the AHB Slave Unit) are
od de
reset to the
IDLE state, and all the transmit FIFOs and the receive FIFO are
M a
flushed.
M
■ Any transactions on the AHB Master are terminated as

soon as possible,
after gracefully completing the last data phase of an AHB
transfer. Any
transactions on the USB are terminated immediately.
■ When Hibernation or ADP feature is enabled, the PMU
module is not reset
by the Core Soft Reset.
The application can write to this bit any time it wants to reset
the core. This is a
self-clearing bit and the core clears this bit after all the
necessary logic is reset
559
CV1835

in the core, which can take several clocks, depending on the
current state of
the core. After this bit is cleared, the application must wait at
least 3 PHY
clocks before doing any access to the PHY domain
(synchronization delay).
The application must also must check that bit 31 of this
register is 1 (AHB
Master is IDLE) before starting any operation.
ed
Typically, software reset is used during software development
and also when
w
you dynamically change the PHY selection bits in the USB
configuration
lo
registers listed above. When you change the PHY, the
al
corresponding clock for
the PHY is selected and used in the PHY domain. After a new
t
clock is
no
selected, the PHY domain has to be reset for proper operation.
Shadow: Yes
e
Shadow Ctrl: vs_1t
ar
One-Way: Enabled n
1 PIUFSSftRst RO Write Behavior: One to set
tio
PIU FS Dedicated Controller Soft Reset (PIUFSSftRst)
u
Resets the PIU FS Dedicated Controller

ib
All module state machines in FS Dedicated Controller of PIU

are reset to the
r
di V
IDLE state. Used to reset the FS Dedicated controller in PIU in

st
re k-
case of any
PHY Errors like Loss of activity or Babble Error resulting in the
d il
PHY remaining
an M
in RX state for more than one frame boundary.

This is a self clearing bit and core clears this bit after all the
n by
necessary logic is
reset in the core.
tio lic
Shadow: Yes
Shadow Ctrl: vs_1t
ca ub

2 FrmCntrRst RO Write Behavior: One to set
ifi p
Mode: Host only

Host Frame Counter Reset (FrmCntrRst)
od de
The application writes this bit to reset the (micro)frame

number counter inside
M a
the core. When the (micro)frame counter is reset, the

M
subsequent SOF sent

out by the core has a (micro)frame number of 0.
If the application writes 1 to the bit, it may not be able to read
back the value as
it gets cleared by the core in a few clock cycles.
Shadow: Yes
Shadow Ctrl: vs_1t
One-Way: Enabled
3 INTknQFlsh RWS Mode: Device only
IN Token Sequence Learning Queue Flush (INTknQFlsh)
This bit is valid only if OTG_EN_DED_TX_FIFO = 0.
560
CV1835

The application writes this bit to flush the IN Token Sequence
Learning
Queue.
4 RxFFlsh RO Write Behavior: One to set
RxFIFO Flush (RxFFlsh)
The application can flush the entire RxFIFO using this bit, but
must first ensure
that the core is not in the middle of a transaction. The
ed
application must only
write to this bit after checking that the core is neither reading
w
from the RxFIFO
nor writing to the RxFIFO.
lo
The application must wait until the bit is cleared before
al
performing any other
operations. This bit requires 8 clocks (slowest of PHY or AHB
t
clock) to clear.
no
5 TxFFlsh RWS Write Behavior: One to set
e
TxFIFO Flush (TxFFlsh)
ar
This bit selectively flushes a single or all transmit FIFOs, but
cannot do so if n
the core is in the midst of a transaction.
tio
The application must write this bit only after checking that the
core is neither
writing to the TxFIFO nor reading from the TxFIFO.
u
Verify using these registers:

ib
■ Read - NAK Effective Interrupt ensures the core is not

r
di V
st
reading from the

re k-
FIFO
■ Write - GRSTCTL.AHBIdle ensures the core is not writing
d il
anything to the
an M
FIFO.
Flushing is normally recommended when FIFOs are
n by
reconfigured or when
switching between Shared FIFO and Dedicated Transmit FIFO
tio lic
operation.
FIFO flushing is also recommended during device endpoint
ca ub
disable. The
application must wait until the core clears this bit before
ifi p
performing any
operations. This bit takes eight clocks to clear, using the slower
od de
clock of
M a
phy_clk or hclk.
M
10:6 TxFNum R/W Mode: Host and Device 0x0

TxFIFO Number (TxFNum)
This is the FIFO number that must be flushed using the TxFIFO
Flush bit. This
field must not be changed until the core clears the TxFIFO
Flush bit.
■ 5'h0:
- Non-periodic TxFIFO flush in Host mode
- Non-periodic TxFIFO flush in device mode when in shared
FIFO
operation
- Tx FIFO 0 flush in device mode when in dedicated FIFO mode
■ 5'h1:
561
CV1835

- Periodic TxFIFO flush in Host mode
- Periodic TxFIFO 1 flush in Device mode when in shared FIFO
operation
- TXFIFO 1 flush in device mode when in dedicated FIFO mode
■ 5'h2:
operation
- TXFIFO 2 flush in device mode when in dedicated FIFO mode
...
ed
■ 5'hF:
w
operation
lo
- TXFIFO 15 flush in device mode when in dedicated FIFO
mode
al
■ 5'h10:
- Flush all the transmit FIFOs in device or host mode.
t
no
29:11 Reserved_10_2 RO Reserved for future use.
9_11
30 DMAReq RO Mode: Host and Device
e
DMA Request Signal (DMAReq)
ar
Indicates that the DMA request is in progress. Used for debug.
31 AHBIdle RO Mode: Host and Device
n
AHB Master Idle (AHBIdle)
tio
Indicates that the AHB Master State Machine is in the IDLE

condition.
u
ib
GINTSTS
r
Interrupt Status Register

di V
st

re k-

d il
0 CurMod RO Mode: Host and Device

an M
Current Mode of Operation (CurMod)

n by

■ 1'b1: Host mode
tio lic
Shadow: Yes
Shadow Ctrl: vs_1t
ca ub

One-Way: Enabled
ifi p
1 ModeMis RWC Write Behavior: One to clear

od de
Mode Mismatch Interrupt (ModeMis)

The core sets this bit when the application is trying to access:
M a
M
■ A Host mode register, when the core is operating in Device

mode
■ A Device mode register, when the core is operating in Host
mode
The register access is completed on the AHB with an OKAY
response,
but is ignored by the core internally and does not affect the
operation
of the core.
This bit can be set only by the core and the application should
write 1
to clear it.
Shadow: Yes
562
CV1835

Shadow Ctrl: vs_1t
2 OTGInt RO Mode: Host and Device
OTG Interrupt (OTGInt)
The core sets this bit to indicate an OTG protocol event. The
application must read the OTG Interrupt Status (GOTGINT)
register to
determine the exact event that caused this interrupt. The
application
ed
must clear the appropriate status bit in the GOTGINT register
to clear
w
this bit.
Shadow: Yes
lo
Shadow Ctrl: vs_1t
al
One-Way: Enabled
t
3 Sof RWC Write Behavior: One to clear
no
Start of (micro)Frame (Sof)
e
In Host mode, the core sets this bit to indicate that an SOF
ar
(FS),
micro-SOF (HS), or Keep-Alive (LS) is transmitted on the USB.
n
The
tio
application must write a 1 to this bit to clear the interrupt.
In Device mode, in the core sets this bit to indicate that an SOF
token
u
has been received on the USB. The application can read the
ib
Device
r
di V
Status register to get the current (micro)Frame number. This

st
re k-
interrupt
is seen only when the core is operating at either HS or FS.This
d il
bit can
an M
be set only by the core and the application must write 1 to

clear it.
n by
Note: The register may return 1’b1 if read immediately after

power on
tio lic
reset. If the register bit reads 1’b1 immediately after power on

reset, it
ca ub
does not indicate that an SOF has been sent (in host mode), or
SOF
ifi p
has been received (in device mode). The read value of this
interrupt is
od de
valid only after a valid connection between host and device is

established. If the bit is set after power on reset, the
M a
application can
M
clear the bit.

4 RxFLvl RO Mode: Host and Device
RxFIFO Non-Empty (RxFLvl)
Indicates that there is at least one packet pending to be read
from the
RxFIFO.
5 NPTxFEmp RO Mode: Host and Device
Non-periodic TxFIFO Empty (NPTxFEmp)
This interrupt is asserted when the Non-periodic TxFIFO is
either half
or completely empty, and there is space for at least one entry
to be
563
CV1835

written to the Non-periodic Transmit Request Queue. The half
or
completely empty status is determined by the Non-periodic
TxFIFO
Empty Level bit in the Core AHB Configuration register
(GAHBCFG.NPTxFEmpLvl).
In host mode, the application can use GINTSTS.NPTxFEmp with
the
OTG_EN_DED_TX_FIFO parameter set to either 1 or 0.
ed
In device mode, the application uses GINTSTS.NPTxFEmp when
OTG_EN_DED_TX_FIFO=0. When OTG_EN_DED_TX_FIFO=1,
w
the
application uses DIEPINTn.TxFEmp.
lo
6 GINNakEff RO Mode: Device only
al
Global IN Non-periodic NAK Effective (GINNakEff)
Indicates that the Set Global Non-periodic IN NAK bit in the
t
Device
no
Control register (DCTL.SGNPInNak) set by the application has
taken
e
effect in the core. That is, the core has sampled the Global IN
ar
NAK bit
set by the application. This bit can be cleared by clearing the
n
Clear
tio
Global Non-periodic IN NAK bit in the Device Control register
(DCTL.CGNPInNak). This interrupt does not necessarily mean
that a
u
NAK handshake is sent out on the USB. The STALL bit takes
ib
precedence over the NAK bit.

r
di V
7 GOUTNakEff RO Mode: Device only

st
re k-
Global OUT NAK Effective (GOUTNakEff)

Indicates that the Set Global OUT NAK bit in the Device Control
d il
register (DCTL.SGOUTNak) set by the application has taken

an M
effect in
the core. This bit can be cleared by writing the Clear Global
n by
OUT NAK
bit in the Device Control register (DCTL.CGOUTNak).
tio lic
8 ULPICKINT_I2C RWC Write Behavior: One to clear

CKINT Mode: Host and Device
ca ub
ULPI Carkit Interrupt (ULPICKINT)

The core sets this interrupt when a ULPI Carkit interrupt is
ifi p
received.
The core's PHY sets ULPI Carkit interrupt in UART or Audio
od de
mode.
This field is used only if the Carkit interface was enabled in
M a
coreConsultant (parameter OTG_ULPI_CARKIT = 1). Otherwise,

M
reads return 0.
I2C Carkit Interrupt (I2CCKINT)

The core sets this interrupt when a Carkit interrupt is received.
The
core's PHY sets the I2C Carkit interrupt in Audio mode.
This field is used only if the I2C interface was enabled in
coreConsultant (parameter OTG_I2C_INTERFACE = 1).
Otherwise,
reads return 0.
9 I2CINT RWC Write Behavior: One to clear
564
CV1835

I2C Interrupt (I2CINT)
The core sets this interrupt when I2C access is completed on
the I2C
interface.
This field is used only if the I2C interface was enabled in
coreConsultant (parameter OTG_I2C_INTERFACE = 1).
Otherwise,
reads return 0.
10 ErlySusp RWC Write Behavior: One to clear
ed
Mode: Device only
Early Suspend (ErlySusp)
w
The core sets this bit to indicate that an Idle state has been
detected
lo
on the USB For 3 ms.
al
11 USBSusp RWC Write Behavior: One to clear
Mode: Device only
t
USB Suspend (USBSusp)
no
The core sets this bit to indicate that a suspend was detected
on the
e
USB. The core enters the Suspend state when there is no
ar
activity on
the linestate signal for an extended period of time.
n
12 USBRst RWC Write Behavior: One to clear
tio
Mode: Device only
USB Reset (USBRst)
u
The core sets this bit to indicate that a reset is detected on the
ib
USB.
13 EnumDone RWC Write Behavior: One to clear
r
di V
Mode: Device only

st
re k-
Enumeration Done (EnumDone)

The core sets this bit to indicate that speed enumeration is
d il
complete.
an M
The application must read the Device Status (DSTS) register to

obtain
n by
the enumerated speed.

14 ISOOutDrop RWC Write Behavior: One to clear
tio lic
Mode: Device only

Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)
ca ub
The core sets this bit when it fails to write an isochronous OUT
packet
ifi p
into the RxFIFO because the RxFIFO does not have enough
space to
od de
accommodate a maximum packet size packet for the

isochronous
M a
M
OUT endpoint.
15 EOPF RWC Write Behavior: One to clear
Mode: Device only
End of Periodic Frame Interrupt (EOPF)
Indicates that the period specified in the Periodic Frame
Interval field
of the Device Configuration register (DCFG.PerFrInt) has been
reached in the current microframe.
16 RstrDoneInt RWC Mode: Host and Device
Restore Done Interrupt (RstrDoneInt)
The core sets this bit to indicate that the Restore command
after
Hibernation was completed by the core.
565
CV1835

The core continues from Suspend state into the mode dictated
by the
PCGCCTL.RestoreMode field.
This bit is valid only when Hibernation feature is enabled
(OTG_EN_PWRPOPT=2).
17 EPMis RO Write Behavior: One to clear
Mode: Device only
Endpoint Mismatch Interrupt (EPMis)
Note: This interrupt is valid only in shared FIFO operation.
ed
Indicates that an IN token has been received for a non-periodic
endpoint, but the data for another endpoint is present in the
w
top of the
Non-periodic Transmit FIFO and the IN endpoint mismatch
lo
count
al
programmed by the application has expired.
18 IEPInt RO Mode: Device only
t
IN Endpoints Interrupt (IEPInt)
no
The core sets this bit to indicate that an interrupt is pending
on one of
e
the IN endpoints of the core (in Device mode). The application
ar
must
read the Device All Endpoints Interrupt (DAINT) register to
n
determine
tio
the exact number of the IN endpoint on Device IN Endpoint-n
Interrupt
(DIEPINTn) register to determine the exact cause of the
u
interrupt. The
ib
application must clear the appropriate status bit in the

r
di V
corresponding
st
re k-
DIEPINTn register to clear this bit.

19 OEPInt RO Mode: Device only
d il
OUT Endpoints Interrupt (OEPInt)

an M

on one of
n by
the OUT endpoints of the core (in Device mode). The

application must
tio lic
read the Device All Endpoints Interrupt (DAINT) register to

determine
ca ub
the exact number of the OUT endpoint on which the interrupt

occurred, and Then read the corresponding Device OUT
ifi p
Endpoint-n
Interrupt (DOEPINTn) register to determine the exact cause of
od de
the
interrupt. The application must clear the appropriate status bit
M a
in the
M
corresponding DOEPINTn register to clear this bit.

20 incompISOIN RWC Write Behavior: One to clear
Mode: Device only
Incomplete Isochronous IN Transfer (incompISOIN)
The core sets this interrupt to indicate that there is at least
one
isochronous IN endpoint on which the transfer is not
completed in the
current microframe. This interrupt is asserted along with the
End of
Periodic Frame Interrupt (EOPF) bit in this register.
Note: This interrupt is not asserted in Scatter/Gather DMA
566
CV1835

mode.
21 incomplP_inco RWC Write Behavior: One to clear
mpISOOUT Incomplete Periodic Transfer (incomplP)
Mode: Host only
In Host mode, the core sets this interrupt bit when there are
incomplete periodic transactions still pending which are
scheduled for
the current microframe.
ed
Incomplete Isochronous OUT Transfer (incompISOOUT)
Mode: Device only
w
In Device mode, the core sets this interrupt to indicate that
there is at
lo
least one isochronous OUT endpoint on which the transfer is
al
not
completed in the current microframe. This interrupt is
t
asserted along
no
with the End of Periodic Frame Interrupt (EOPF) bit in this
register.
e
22 FetSusp RWC Write Behavior: One to clear
ar
Mode: Device only
Data Fetch Suspended (FetSusp) n
This interrupt is valid only in DMA mode. This interrupt
tio
indicates that
the core has stopped fetching data For IN endpoints due to the
unavailability of TxFIFO space or Request Queue space. This
u
interrupt is used by the application For an endpoint mismatch

ib
algorithm.
r
di V
For example, after detecting an endpoint mismatch, the

st
re k-
application:
■ Sets a Global non-periodic IN NAK handshake
d il
■ Disables In endpoints
an M
■ Flushes the FIFO

■ Determines the token sequence from the IN Token
n by
Sequence
Learning Queue
tio lic
■ Re-enables the endpoints

■ Clears the Global non-periodic IN NAK handshake
ca ub
If the Global non-periodic IN NAK is cleared, the core has not

yet
ifi p
fetched data for the IN endpoint, and the IN token is received.

od de
The
core generates an 'IN token received when FIFO empty'
M a
interrupt.
M
DWC_otg then sends the host a NAK response. To avoid this

scenario,
the application can check the GINTSTS.FetSusp interrupt,
which
ensures that the FIFO is full before clearing a Global NAK
handshake.
Alternatively, the application can mask the “IN token received
when
FIFO empty” interrupt when clearing a Global IN NAK
handshake.
23 ResetDet RWC Write Behavior: One to clear
Mode: Device only
Reset detected Interrupt (ResetDet)
567
CV1835

In Device mode, this interrupt is asserted when a reset is
detected on
the USB in partial power-down mode when the device is in
Suspend.
In Host mode, this interrupt is not asserted.
24 PrtInt RO Mode: Host only
Host Port Interrupt (PrtInt)
The core sets this bit to indicate a change in port status of one
of the
ed
DWC_otg core ports in Host mode. The application must read
the
w
Host Port Control and Status (HPRT) register to determine the
exact
lo
event that caused this interrupt. The application must clear
al
the
appropriate status bit in the Host Port Control and Status
t
register to
no
clear this bit.
25 HChInt RO Mode: Host only
e
Host Channels Interrupt (HChInt)
ar
on one of n
the channels of the core (in Host mode). The application must
tio
read the
Host All Channels Interrupt (HAINT) register to determine the
exact
u
number of the channel on which the interrupt occurred and

ib
then read
r
di V
the corresponding Host Channel-n Interrupt (HCINTn) register

st
re k-
to
determine the exact cause of the interrupt. The application
d il
must clear
an M
the appropriate status bit in the HCINTn register to clear this

bit.
n by
26 PTxFEmp RO Mode: Host only

Periodic TxFIFO Empty (PTxFEmp)
tio lic
This interrupt is asserted when the Periodic Transmit FIFO is

either
ca ub
half or completely empty and there is space for at least one

entry to be
ifi p
written in the Periodic Request Queue. The half or completely

empty
od de
status is determined by the Periodic TxFIFO Empty Level bit in

the
M a
Core AHB Configuration register (GAHBCFG.PTxFEmpLvl).

M
27 LPM_Int RWC Write Behavior: One to clear

LPM Transaction Received Interrupt (LPM_Int)
■ Device Mode - This interrupt is asserted when the device
receives
an LPM transaction and responds with a non-ERRORed
response.
■ Host Mode - This interrupt is asserted when the device
responds to
an LPM transaction with a non-ERRORed response or when
the
host core has completed LPM transactions for the
568
CV1835

programmed
number of times (GLPMCFG.RetryCnt).
28 ConIDStsChng RWC Write Behavior: One to clear
Connector ID Status Change (ConIDStsChng)
The core sets this bit when there is a change in connector ID
status.
29 DisconnInt RWC Write Behavior: One to clear
Mode: Host only
ed
Disconnect Detected Interrupt (DisconnInt)
Asserted when a device disconnect is detected.
w
30 SessReqInt RWC Write Behavior: One to clear
lo
Session Request/New Session Detected Interrupt (SessReqInt)
al
In Host mode, this interrupt is asserted when a session request
is
t
detected from the device.
no
In Device mode, this interrupt is asserted when the
utmisrp_bvalid
e
signal goes high.
ar
31 WkUpInt RWC Write Behavior: One to clear
n
Resume/Remote Wakeup Detected Interrupt (WkUpInt)
tio
Wakeup Interrupt during Suspend(L2) or LPM(L1) state.
■ During Suspend (L2):
u
- Device Mode - This interrupt is asserted only when Host

ib
Initiated Resume is detected on USB.

- Host Mode - This interrupt is asserted only when Device
r
di V
st
Initiated Remote Wakeup is detected on USB.

re k-
■ During LPM (L1):

- Device Mode - This interrupt is asserted for either Host
d il
an M
Initiated
Resume or Device Initiated Remote Wakeup on USB.
- Host Mode - This interrupt is asserted for either Host
n by
Initiated
Resume or Device Initiated Remote Wakeup on USB.
tio lic
GINTMSK
ca ub
Interrupt Mask Register

ifi p

od de

Shadow: Yes
M a
Shadow Ctrl: vs_1t

M

One-Way: Enabled
1 ModeMisMsk R/W Mode: Host and Device 0x0
Mode Mismatch Interrupt Mask (ModeMisMsk)
Shadow: Yes
Shadow Ctrl: vs_1t
2 OTGIntMsk R/W Mode: Host and Device 0x0
OTG Interrupt Mask (OTGIntMsk)
Shadow: Yes
Shadow Ctrl: vs_1t
569
CV1835

One-Way: Enabled
3 SofMsk R/W Mode: Host and Device 0x0
Start of (micro)Frame Mask (SofMsk)
4 RxFLvlMsk R/W Mode: Host and Device 0x0
Receive FIFO Non-Empty Mask (RxFLvlMsk)
5 NPTxFEmpMsk R/W Mode: Host and Device 0x0
Non-periodic TxFIFO Empty Mask (NPTxFEmpMsk)
6 GINNakEffMsk R/W Mode: Device only 0x0
Global Non-periodic IN NAK Effective Mask
ed
(GINNakEffMsk)
7 GOUTNakEffMsk R/W Mode: Device only 0x0
w
Global OUT NAK Effective Mask (GOUTNakEffMsk)
lo
8 ULPICKINTMsk_I2C R/W ULPI Carkit Interrupt Mask (ULPICKINTMsk) 0x0
CKINTMsk Mode: Host and Device
al
I2C Carkit Interrupt Mask (I2CCKINTMsk)
t
no
9 I2CIntMsk R/W Mode: Host and Device 0x0
I2C Interrupt Mask (I2CIntMsk)
e
10 ErlySuspMsk R/W Mode: Device only 0x0
ar
Early Suspend Mask (ErlySuspMsk)
11 USBSuspMsk R/W Mode: Device only 0x0
n
USB Suspend Mask (USBSuspMsk)
tio
12 USBRstMsk R/W Mode: Device only 0x0

USB Reset Mask (USBRstMsk)
u
13 EnumDoneMsk R/W Mode: Device only 0x0

ib
Enumeration Done Mask (EnumDoneMsk)

r
14 ISOOutDropMsk R/W Mode: Device only Isochronous OUT Packet Dropped 0x0
di V
st
Interrupt
re k-
Mask (ISOOutDropMsk)
d il
15 EOPFMsk R/W Mode: Device only 0x0

an M
End of Periodic Frame Interrupt Mask (EOPFMsk)

16 RstrDoneIntMsk R/W Mode: Host and Device 0x0
n by
Restore Done Interrupt Mask (RstrDoneIntMsk)

This field is valid only when Hibernation feature is enabled
(OTG_EN_PWROPT=2).
tio lic
17 EPMisMsk R/W Mode: Device only 0x0

Endpoint Mismatch Interrupt Mask (EPMisMsk)
ca ub
18 IEPIntMsk R/W Mode: Device only 0x0

IN Endpoints Interrupt Mask (IEPIntMsk)
ifi p
19 OEPIntMsk R/W Mode: Device only 0x0

od de
OUT Endpoints Interrupt Mask (OEPIntMsk)

20 incompISOINMsk R/W Mode: Device only 0x0
M a
Incomplete Isochronous IN Transfer Mask

M
(incompISOINMsk)
This bit is enabled only when device periodic endpoints
are enabled
in Dedicated TxFIFO mode.
21 incomplPMsk_inco R/W Incomplete Periodic Transfer Mask (incomplPMsk) 0x0
mpISOOUTMsk Mode: Host only
Incomplete Isochronous OUT Transfer Mask

(incompISOOUTMsk)
Mode: Device only
22 FetSuspMsk R/W Mode: Device only 0x0
Data Fetch Suspended Mask (FetSuspMsk)
23 ResetDetMsk R/W Mode: Device only 0x0
570
CV1835

Reset detected Interrupt Mask (ResetDetMsk)
24 PrtIntMsk R/W Mode: Host only 0x0
Host Port Interrupt Mask (PrtIntMsk)
25 HChIntMsk R/W Mode: Host only 0x0
Host Channels Interrupt Mask (HChIntMsk)
26 PTxFEmpMsk R/W Mode: Host only 0x0
Periodic TxFIFO Empty Mask (PTxFEmpMsk)
27 LPM_IntMsk R/W Mode: Host and Device 0x0
LPM Transaction received interrupt Mask (LPM_IntMsk)
ed
28 ConIDStsChngMsk R/W Mode: Host and Device 0x0
Connector ID Status Change Mask (ConIDStsChngMsk)
w
29 DisconnIntMsk R/W Mode: Host and Device 0x0
lo
Disconnect Detected Interrupt Mask (DisconnIntMsk)
30 SessReqIntMsk R/W Mode: Host and Device 0x0
al
Session Request/New Session Detected Interrupt Mask
(SessReqIntMsk)
t
no
31 WkUpIntMsk R/W Mode: Host and Device 0x0
Resume/Remote Wakeup Detected Interrupt Mask
(WkUpIntMsk)
e
The WakeUp bit is used for LPM state wake up in a way
ar
similar to
that of wake up in suspend state.
n
tio
GUID
User ID Register
u

ib

r
31:0 UserID R/W User ID (UserID) 0x0

di V
st
Application-programmable ID field.
re k-
Reset: Configurable
d il
an M
GLPMCFG
Core LPM Configuration Register
n by

tio lic
0 LPMCap R/W Mode: Host and Device 0x0

LPM-Capable (LPMCap)
ca ub
The application uses this bit to control the DWC_otg core

LPM capabilities.
ifi p
If the core operates as a non-LPM-capable host, it cannot

od de
request the connected

device or hub to activate LPM mode.
M a
If the core operates as a non-LPM-capable device, it cannot

M
respond to any LPM

transactions.
■ 1b0: LPM capability is not enabled
■ 1b1: LPM capability is enabled
This bit is writable only if an LPM mode was specified for
Mode of Operation in
coreConsultant (parameter OTG_ENABLE_LPM). Otherwise,
reads return 0.
Shadow: Yes
Shadow Ctrl: vs_1t
One-Way: Enabled
1 AppL1Res R/W Mode: Device only 0x0
571
CV1835

LPM response programmed by application (AppL1Res)
Handshake response to LPM token pre-programmed by
device application
software. The response depends on GLPMCFG.LPMCap. If
GLPMCFG.LPMCap
is 1’b0, then the core always responds with NYET response.
If
GLPMCFG.LPMCap is 1’b1, the core response is as follows.
■ 1: ACK
ed
Even though ACK is pre-programmed, the core Device
responds with ACK
w
only on successful LPM transaction. The LPM transaction is
lo
successful if:
- No PID/CRC5 Errors in either EXT token or LPM token (else
al
ERROR)
- Valid bLinkState = 0001B (L1) received in LPM transaction
t
(else STALL)
no
- No data pending in transmit queue (else NYET).
■ 0: NYET
e
The pre-programmed software bit is over-ridden for
ar
response to LPM token
when:
n
- The received bLinkState is not L1 (STALL response), or
tio
- An error is detected in either of the LPM token packets
because of
u
corruption (ERROR response).

ib
Shadow: Yes
Shadow Ctrl: vs_1t
r
di V
st

re k-
5:2 HIRD R/W Mode: Host and Device 0x0

■ EnBESL = 1’b0
d il
an M
Host-Initiated Resume Duration (HIRD)

Host Mode: The value of HIRD to be sent in an LPM
transaction. This value is
n by
also used to initiate resume for a duration

TL1HubDrvResume1 for host initiated
tio lic
resume.
Device Mode (Read-Only): This field is updated with the
ca ub
Received LPM
Token HIRD bmAttribute when an ACK, NYET, or STALL
ifi p
response is sent to
an LPM transaction.
od de
Sl. No HIRD[3:0] THIRD (μs)

M a
1 4’b0000 50
M
2 4’b0001 125
3 4’b0010 200
4 4’b0011 275
5 4’b0100 350
6 4’b0101 425
7 4’b0110 500
8 4’b0111 575
9 4’b1000 650
10 4’b1001 725
11 4’b1010 800
12 4’b1011 875
13 4’b1100 950
14 4’b1101 1025
572
CV1835

15 4’b1110 1100
16 4’b1111 1175
Reset: 4’b0000
■ EnBESL = 1’b1
Best Effort Service Latency (BESL)
Host Mode: The value of BESL to be sent in an LPM
transaction. This value is
also used to initiate resume for a duration
TL1HubDrvResume1 for host initiated
ed
resume.
w
Received LPM
lo
Token BESL bmAttribute when an ACK, NYET, or STALL
response is sent to
al
an LPM transaction.
Sl. No BESL[3:0] TBESL (μs)
t
1 4’b0000 125
no
2 4’b0001 150
3 4’b0010 200
e
4 4’b0011 300
ar
5 4’b0100 400
6 4’b0101 500 n
7 4’b0110 1000
tio
8 4’b0111 2000
9 4’b1000 3000
10 4’b1001 4000
u
11 4’b1010 5000
ib
12 4’b1011 6000
r
di V
13 4’b1100 7000
st
re k-
14 4’b1101 8000
15 4’b1110 9000
d il
16 4’b1111 10000
an M
Shadow: Yes
Shadow Ctrl: vs_1t
n by

One-Way: Enabled
tio lic
6 bRemoteWake R/W Mode: Host and Device 0x0

RemoteWakeEnable (bRemoteWake)
ca ub
Host Mode: The value of remote wake up to be sent in the

wIndex field of LPM
ifi p
transaction.
od de
Received LPM Token

bRemoteWake bmAttribute when an ACK, NYET, or STALL
M a
response is sent to an
M
LPM transaction.
7 EnblSlpM R/W Mode: Host and Device 0x0
Enable utmi_sleep_n (EnblSlpM)
ULPI Interface: The application uses this bit to control the
utmi_sleep_n
assertion to the PHY when in L1 state. For the host, this bit is
valid only in “local
device” mode.
■ 1b0: utmi_sleep_n assertion from the core is not
transferred to the external
PHY.
■ 1b1: utmi_sleep_n assertion from the core is transferred
573
CV1835

to the external PHY.
Note: When a ULPI interface is configured, enabling this bit
results in a write to Bit
7 of the ULPI Function Control register. The Synopsys ULPI
PHY supports writing
to this bit, and in the L1 state asserts SleepM when
utmi_l1_suspend_n cannot be
asserted.
Other Interfaces: The application uses this bit to control
ed
utmi_sleep_n assertion
to the PHY in the L1 state. For the host, this bit is valid only
w
in Local Device mode.
■ 1’b0: utmi_sleep_n assertion from the core is not
lo
transferred to the external
al
PHY.
■ 1’b1: utmi_sleep_n assertion from the core is transferred
t
no
to the external PHY
when utmi_l1_suspend_n cannot be asserted.
12:8 HIRD_Thres R/W Mode: Host and Device 0x0
e
BESL or HIRD Threshold (HIRD_Thres)
ar
Device Mode:
■ EnBESL = 1’b0: The core puts the PHY into deep low
n
power mode in L1 (by
tio
core asserting L1SuspendM) when HIRD value is greater than

or equal to the
u
value defined in this field HIRD_Thres[3:0] and

ib
HIRD_Thres[4] is set to 1’b1.

■ EnBESL = 1’b1: The core puts the PHY into deep low
r
di V
st
power mode in L1 (by

re k-
core asserting L1SuspendM) when BESL value is greater than

or equal to the
d il
an M
value defined in this field BESL_Thres[3:0] and BESL_Thres[4]

is set to 1’b1.
■ DCTL.DeepSleepBESLReject = 1'b1: In device initiated
n by
resume, the core

expects the Host to resume service to the device within the
tio lic
BESL value
corresponding to L1 exit time specified in HIRD_Thresh[3:0].
ca ub
The Device
sends a NYET response when the received HIRD in LPM
ifi p
token is greater than

od de
HIRD threshold.
■ Note: To differentiate between Deep Sleep and Shallow
M a
sleep HIRD greater

M
than or equal to HIRD threshold comparison is done. For

differentiating
between NYET or ACK response for LPM token HIRD greater
than HIRD
Threshold comparison is used.
Host Mode: The core puts the PHY into deep low power
mode in L1 (by core
asserting L1SuspendM) when HIRD_Thres[4] is set to 1b1.
HIRD_Thres[3:0]
specifies the time for which resume signaling is to be
reflected by host
(TL1HubDrvResume2) on the USB bus when it detects device
initiated resume.
574
CV1835

HIRD_Thres must not be programmed with a value greater
than 4’b1100 in Host
mode, because this exceeds maximum TL1HubDrvResume2.
Sl. No ----Thres[3:0] --- -Host Mode Resume Signaling Time
(μs)
--- - --- - --- - --- - --------- - --- - EnBESL = 1'b0 - -EnBESL = 1'b1
1 4’b0000 60 75
2 4’b0001 135 100
3 4’b0010 -210 150
ed
4 4’b0011 285 250
5 4’b0100 360 350
w
6 4’b0101 435 450
7 4’b0110 510 950
lo
8 4’b0111 585 Invalid
al
9 4’b1000 660 Invalid
10 4’b1001 735 Invalid
t
11 4’b1010 810 Invalid
no
12 4’b1011 885 Invalid
13 4’b1100 960 Invalid
e
14 4’b1101 Invalid Invalid
ar
15 4’b1110 Invalid Invalid
16 4’b1111 Invalid Invalid n
The following truth table explains the difference in behavior
tio
between the UTMI
and ULPI interface in different modes of operation:
Bit 7 --Bit 6 --sleep_n ---l1_suspend_n --suspend_n ---Mode
u
of Operation
ib
0 --- -----1- --- ----1--- --- --1--- --- ------- --- --1--- --- ------- --
r
di V
Normal Operation
st
re k-
0 --- -----0- --- ----1--- --- --1--- --- ------- --- --0--- --- ------- --L2
Suspend
d il
1 --- -----0- --- ----1--- --- --0--- --- ------- --- --1--- --- ------- --L1
an M
Deep Sleep
1 --- -----1- --- ----0--- --- --1--- --- ------- --- --1--- --- ------- --L1
n by
Shallow Sleep
14:13 CoreL1Res RO Mode: Host and Device
LPM Response (CoreL1Res)
tio lic
Device Mode: The response of the core to LPM transaction

ca ub
received is reflected
in these two bits.
ifi p
Host Mode: Handshake response received from local device

for LPM transaction
od de
■ 11 - ACK
■ 10 - NYET
M a
M
■ 01 - STALL
■ 00 - ERROR (No handshake response)
15 SlpSts RO Mode: Device only
Port Sleep Status (SlpSts)
This bit is set as long as a Sleep condition is present on the
USB bus. The core
enters the Sleep state when an ACK response is sent to an
LPM transaction and
the TL1TokenRetry timer has expired. To stop the PHY clock,
the application must
set the Port Clock Stop bit, which asserts the PHY Suspend
input signal.
The application must rely on SlpSts and not ACK in
575
CV1835

CoreL1Res to confirm
transition into sleep.
The core comes out of sleep:
■ When there is any activity on the USB linestate
■ When the application writes to the Remote Wakeup
Signaling bit in the Device
Control register (DCTL.RmtWkUpSig) or when the application
resets or softdisconnects
the device.
ed
Host Mode: The host transitions to Sleep (L1) state as a side-
effect of a
w
successful LPM transaction by the core to the local port with
lo
ACK response from
the device. The read value of this bit reflects the current
al
Sleep status of the port.
The core clears this bit after:
t
no
■ The core detects a remote L1 Wakeup signal,
■ The application sets the Port Reset bit or the Port
L1Resume bit in the HPRT
e
register, or
ar
■ The application sets the L1Resume/ Remote Wakeup
Detected Interrupt bit or
n
Disconnect Detected Interrupt bit in the Core Interrupt
tio
register
(GINTSTS.L1WkUpInt or GINTSTS.DisconnInt, respectively).
u
Values:
ib
■ 1b0: Core not in L1

r
■ 1b1: Core in L1
di V
st
16 L1ResumeOK RO Mode: Host and device

re k-
Sleep State Resume OK (L1ResumeOK)

d il
Indicates that the application or host can start resume from

an M
Sleep state. This bit is

valid in LPM sleep (L1) state. It is set in sleep mode after a
n by
delay of 50 μs
(TL1Residency).
This bit is reset when SlpSts is 0.
tio lic
■ 1b1: The application or core can start Resume from Sleep

ca ub
state
■ 1b0: The application or core cannot start Resume from
ifi p
Sleep state
20:17 LPM_Chnl_Indx R/W Mode: Host only 0x0
od de
LPM Channel Index (LPM_Chnl_Indx)

The channel number on which the LPM transaction has to be
M a
applied while
M
sending an LPM transaction to the local device. Based on the

LPM channel index,
the core automatically inserts the device address and end
point number
programmed in the corresponding channel into the LPM
transaction.
23:21 LPM_Retry_Cnt R/W Mode: Host only 0x0
LPM Retry Count (LPM_Retry_Cnt)
When the device gives an ERROR response, this is the
number of additional LPM
retries that the host performs until a valid device response
(STALL, NYET, or ACK)
576
CV1835

is received.
24 SndLPM RWS Write Behavior: One to set
Mode: Host only
Send LPM Transaction (SndLPM)
When the application software sets this bit, an LPM
transaction containing two
tokens, EXT and LPM is sent. The hardware clears this bit
once a valid response
(STALL, NYET, or ACK) is received from the Device or the core
ed
has finished
transmitting the programmed number of LPM retries.
w
Note: This bit must be set only when the host is connected
to a local port.
lo
27:25 LPM_RetryCnt_St RO Mode: Host only
al
s LPM Retry Count Status (LPM_RetryCnt_Sts)
Number of LPM Host Retries still remaining to be
t
transmitted for the current LPM
no
sequence.
28 EnBESL R/W Mode: Host and device 0x0
e
Enable Best Effort Service Latency (BESL)
ar
This bit enables the BESL feature as defined in the LPM
errata:
n
■ 1’b0: The core works as described in the following
tio
document:
USB 2.0 Link Power Management Addendum Engineering
u
Change Notice to
ib
the USB 2.0 specification, July 16, 2007

■ 1’b1: The core works as per the LPM Errata
r
di V
st
29 RstrSlpSts R/W Mode: Device only 0x0

re k-
Restore SlpSts (RstrSlpSts)

When the application power-gates the core (partial power-
d il
an M
down or hibernation),
the application needs to program this bit to restore the LPM
status in the core.
n by
Based on the BESL value received from the Host, the

application needs to
tio lic
program this bit during restore process. The application

should program this bit
ca ub
depending on whether it decided to put the core in Shallow

Sleep (Clock Gating
ifi p
Only) or Deep Sleep (Power Gating) mode:

od de
■ 1'b0: The application puts the core in Shallow Sleep mode

based on the BESL
M a
value from the Host.

M
■ 1'b1: The application puts the core in Deep Sleep mode

based on the BESL
value from the Host.
30 HSICCon R/W Mode: Host and device 0x0
HSIC-Connect (HSICCon)
The application must use this bit to initiate the HSIC Attach
sequence.
Host Mode: Once this bit is set, the Host Core configures to
drive HSIC Idle state
(STROBE=1&DATA=0) on the bus. It then waits for device to
initiate the HSIC
Connect sequence.
Device Mode: Once this bit is set, the Device Core waits for
577
CV1835

HSIC Idle linestate
on the bus. After receiving the Idle linestate it then initiates
the HSIC Connect.
This bit is valid only if OTG_ENABLE_HSIC = 1, if_sel_hsic = 1,
and InvSelHSIC
= 0. Otherwise, it is read-only.
31 InvSelHsic R/W Mode: Host and device 0x0
HSIC-Invert Select HSIC (InvSelHsic)
The application uses this bit to control the DWC_otg core
ed
HSIC enable/disable.
This bit overrides and functionally inverts the if_sel_hsic
w
input port signal.
If the core is non-HSIC-capable, it can connect to only PHYs
lo
that are not HSIC
al
capable.
If the core is HSIC-capable, it can connect only to PHYs that
t
are HSIC capable.
no
■ If if_sel_hsic input signal is 1:
- InvSelHsic = 1b1: HSIC capability is not enabled
e
- InvSelHsic = 1b0: HSIC capability is enabled
ar
■ If if_sel_hsic input signal is 0:
- InvSelHsic = 1b1: HSIC capability is enabled
n
- InvSelHsic = 1b0: HSIC capability is not enabled
tio
This bit is writable only if HSIC mode is specified for Mode of
Operation in
u
coreConsultant (parameter OTG_ENABLE_HSIC). This bit is

ib
valid only if
OTG_ENABLE_HSIC is enabled. Otherwise, reads return 0.
r
di V
st
re k-
GPWRDN
Power Down Register
d il
an M

n by
0 PMUIntSel R/W Mode: Host and Device 0x0

PMU Interrupt Select (PMUIntSel)
When the hibernation functionality is selected
tio lic
(OTG_EN_PWROPT =
ca ub
2), a write to this bit with 1'b1 enables the PMU to generate
interrupts
ifi p
to the application. During this state, all interrupts from the

DWC_otg_core module are blocked to the application.
od de
Note: This bit must be set to 1'b1 before the core is put into
hibernation
M a
■ 1'b0: Internal DWC_otg_core interrupt is selected

M
■ 1'b1: External DWC_otg_pmu interrupt is selected

Note: This bit must not be written to during normal mode of
operation.
Shadow: Yes
Shadow Ctrl: vs_1t
One-Way: Enabled
1 PMUActv R/W Mode: Host and Device 0x0
PMU Active (PMUActv)
This bit enables or disables the PMU logic.
■ 1'b0: Disable PMU module
■ 1'b1: Enable PMU module
578
CV1835

operation.
Shadow: Yes
Shadow Ctrl: vs_1t
2 Restore R/W Mode: Host and Device 0x0
Restore
The application must program this bit to enable or disable
restore
ed
mode from the PMU module.
■ 1’b0: DWC_otg in normal mode of operation
w
■ 1’b1: DWC_otg in restore mode
lo
operation.
al
This bit is valid only when OTG_EN_PWROPT = 2.
Shadow: Yes
t
no
Shadow Ctrl: vs_1t
One-Way: Enabled
e
3 PwrDnClmp R/W Mode: Host and Device 0x0
ar
Power Down Clamp (PwrDnClmp)
The application must program this bit to enable or disable
n
the clamps
tio
to all the outputs of the DWC_otg core module to prevent

the
u
corruption of other active logic.

ib
■ 1'b0: Disable PMU power clamp

■ 1'b1: Enable PMU power clamp
r
di V
st
4 PwrDnRst_n R/W Mode: Host and Device 0x1

re k-
Power Down ResetN (PwrDnRst_n)

d il
The application must program this bit to reset the DWC_otg

an M
core
during the Hibernation exit process or during ADP when
powering up
n by
the core (if the DWC_otg core was powered off during ADP
process).
tio lic
■ 1'b1: DWC_otg is in normal operation

■ 1'b0: Reset DWC_otg
ca ub

ifi p
operation.
5 PwrDnSwtch R/W Mode: Host and Device 0x0
od de
Power Down Switch (PwrDnSwtch)

This bit indicates to the DWC_otg core whether the VDD
M a
switch is in
M
ON or OFF state.
■ 1'b0: DWC_otg is in ON state
■ 1'b1: DWC_otg is in OFF state
operation.
6 DisableVBUS R/W Mode: Host and Device 0x0
DisableVBUS
Host Mode:
The application must program this bit if HPRT0.PrtPwr was
programmed to 0 before switching off the Core. This
indicates to the
PMU whether session was ended before entering
579
CV1835

Hibernation.
■ 1'b0: HPRT0.PrtPwr was not programed to 0.
■ 1'b1: HPRT0.PrtPwr was programmed to 0.
Device Mode:
The application must program this bit to inform the PMU
whether the
bvalid valid signal is high (session valid) or low (session end)
whenever the core is switched off.
■ 1'b0: bvalid signal is High (Session Valid)
ed
■ 1'b1: bvalid signal is Low (Session End)
This bit is valid only when GPWRDN.PMUActv is 1.
w
7 LnStsChng RWC Write Behavior: One to clear
lo
al
Line State Change (LnStsChng)
This interrupt is asserted when there is a linestate change
t
detected by
no
the PMU. The application must read GPWRDN.Linestate to
determine
the current linestate on USB.
e
■ 1'b0: No LineState change on USB
ar
■ 1'b1: LineState change on USB
This bit is valid only when GPWRDN.PMUActv is 1 and
n
OTG_EN_PWROPT = 2.
tio
8 LineStageChange R/W Mode: Host and Device 0x0

Msk Mask For LineStateChange interrupt (LineStageChangeMsk)
u

ib
9 ResetDetected RWC Write Behavior: One to clear

r
Mode: Device only

di V
st
ResetDetected
re k-
This field indicates that Reset has been detected by the PMU
d il
module.
an M
This field generates an interrupt.

■ 1'b0: Reset Not Detected
n by
■ 1'b1: Reset Detected

10 Mask_ResetDetM R/W Mode: Device only 0x0
tio lic
sk Mask For ResetDetected interrupt (ResetDetMsk)

ca ub

11 DisconnectDetect RWC Write Behavior: One to clear
ifi p
Mode: Host only

DisconnectDetect
od de
This field indicates that Disconnect has been detected by the

PMU.
M a
This field generates an interrupt. After detecting disconnect

M
during
hibernation the application must not restore the core, but
instead start
the initialization process.
■ 1'b0: Disconnect not detected
■ 1'b1: Disconnect detected
12 DisconnectDetect R/W Mode: Host only 0x0
Msk Mask For DisconnectDetect Interrupt
(DisconnectDetectMsk)
13 ConnectDet RO Mode: Host and Device
580
CV1835

Write Behavior: One to clear
ConnectDet
This field indicates that a new connect has been detected
■ 1'b0: Connect not detected
■ 1'b1: Connect detected
14 ConnDetMsk R/W Mode: Host and Device 0x0
ConnDetMsk
Mask for ConnectDet interrupt
ed
15 SRPDetect RWC Mode: Host only
w
SRPDetect
lo
This field indicates that SRP has been detected by the PMU.
This field
al
generates an interrupt. After detecting SRP during
hibernation the
t
no
application must not restore the core. The application must
get into
the initialization process.
e
■ 1'b0: SRP not detected
ar
■ 1'b1: SRP detected
16 SRPDetectMsk R/W Mode: Host only 0x0
n
Mask For SRPDetect Interrupt (SRPDetectMsk)
tio
17 StsChngInt RWC Write Behavior: One to clear

Status Change Interrupt (StsChngInt)
u
This field indicates a status change in either the IDDIG or

ib
BSessVld
r
signal.
di V
st
■ 1'b0: No Status change

re k-
■ 1'b1: status change detected

d il
After receiving this interrupt the application must read the

an M
GPWRDN
register and interpret the change in IDDIG or BSesVld with
n by
respect to
the previous value stored by the application.
Note: When Battery Charger is Enabled and the ULPI
tio lic
interface is
ca ub
used, if StsChngInt is received and the application reads

GPWRDN
ifi p
register and determines that it is due to a change in the

value of
od de
IDDIG, then StsChngInt may be generated once again within

the next
M a
few clock cycles.

M
This occurs because of an ambiguity in the implementation

of Battery
Charger Support over the ULPI interface. After receiving the
StsChngInt for the second time the application can once
again read
the GPWRDN register. However, this time the value IDDIG (or
BSesVld) will not have changed. The application then
processes the
second interrupt but no further action will be required as a
result.
18 StsChngIntMsk R/W Mode: Host and Device 0x0
Mask For StsChng Interrupt (StsChngIntMsk)
581
CV1835

20:19 LineState RO Mode: Host and Device
LineState
This field indicates the current linestate on USB as seen by
the PMU
module.
■ 2'b00: DM = 0, DP = 0
■ 2'b01: DM = 0, DP = 1
■ 2'b10: DM = 1, DP = 0
■ 2'b11: Not-defined
ed
21 IDDIG RO Mode: Host and Device
w
IDDIG
lo
This bit indicates the status of the IDDIG signal. The
al
application must
read this bit after receiving GPWRDN.StsChngInt and decode
t
based
no
on the previous value stored by the application.
e
■ 1'b0: Host mode
ar
22 BSessVld RO Mode: Device only
n
B Session Valid (BSessVld)
tio
This field reflects the B session valid status signal from the
PHY.
u
■ 1'b0: B-Valid is 0
ib
■ 1'b1: B-Valid is 1
r
di V

st
re k-
23 ADPInt RWC Write Behavior: One to clear

d il
ADP Interrupt (ADPInt)

an M
This bit is set whenever there is a ADP event

28:24 MultValIdBC RO Mode: Host and Device
n by
MultValIdBC (MultValIdBC)
Battery Charger ACA inputs in the following order:
tio lic
■ Bit 28 - rid_float
■ Bit 27 - rid_gnd
ca ub
■ Bit 26 - rid_a
■ Bit 25 - rid_b
ifi p
■ Bit 24 - rid_c
od de
These bits are present only if BC_SUPPORT = 1. Otherwise,

these
M a
bits are reserved and will read 5'h0.

M
Reset: As per ACA input

29
12.6.4 The Illustration of Host Initialization Program
582
CV1835
After completing the [clock startup procedure] and [mode switching and initialization
procedure], the XHCI initialization procedure needs to be executed. As listed below, four
standard types of transmission can be started according to the requirements. For details of the
method of starting standard transmission, please refer to the XHCI specification, which will not
be repeated here.
1. Set the GINTMSK.PrtInt register to the unmask state.
2. Set the HCFG register to configure the FS or HS device.
ed
3. Set the HPRT.PrtPwr register to 1, which turns on the VBUS on the USB bus.
w
4. Wait for the HPRT0.PrtConnDet interrupt to occur, indicating that a device is connected to
lo
the USB downstream port.
al
5. Set the HPRT.PrtRst register to 1 to begin the USB port reset process.
t
no
6. Wait at least 10ms to allow enough time for the USB port reset to complete the handshake.
7. Set the HPRT.PrtRst to 0 to complete the USB port reset process.
e
8. Wait for the HPRT.PrtEnChng interrupt to occur.
9.
ar
Read the HPRT.PrtSpd register to obtain the enumeration speed value.
n
10. Set the HFIR register to configure the corresponding PHY Clock.
tio
11. Set the RXFSIZE register to configure the size of the RXFIFO.
u
12. Set the GNPTXFSIZ register to configure the size of the non-periodic transmission TXFIFO.
ib
13. Set the HPTXFSIZ register to configure the size of the periodic transmission TXFIFO.
r
di V
st
re k-
12.6.5 Host Register Description

d il
an M
The base address of the Host register in the whole memory space is 0x0434_0000, indicating as
n by
HOST_BASE_ADDR in this article. Therefore, the real address of each register of the host
tio lic
controller in the memory space will be [HOST_BASE_ADDR+ relative address].

ca ub
12.6.5.1 Register Overview

ifi p

od de
Offset
M a
HCFG 0x400 Host Configuration Register

M
HFIR 0x404 Host Frame Interval Register

HFNUM 0x408 Host Frame Number/Frame Time Remaining Register
HPTXSTS 0x410 Host Periodic Transmit FIFO/Queue Status Register
HAINT 0x414 Host All Channels Interrupt Register
HAINTMSK 0x418 Host All Channels Interrupt Mask Register
HFLBAddr 0x41c Host Frame List Base Address Register
HCCHARn 0x500 Host Channel-n Characteristics Register
HCDMAn 0x514 Host Channel-n DMA Address Register
HCDMABn 0x51c Host Channel-n DMA Buffer Address Register
583
CV1835
12.6.5.2 Detailed List of Registers
HCFG
Host Configuration Register
ed
1:0 FSLSPclkSel R/W FS/LS PHY Clock Select (FSLSPclkSel) 0x0
w
When the core is in FS Host mode:
■ 2'b00: PHY clock is running at 30/60 MHz
lo
■ 2'b01: PHY clock is running at 48 MHz
al
When the core is in LS Host mode:
t
no
■ 2'b00: PHY clock is running at 30/60 MHz. When the
UTMI+/ULPI
PHY Low Power mode is not selected, use 30/60 MHz.
e
■ 2'b01: PHY clock is running at 48 MHz. When the UTMI+
ar
PHY Low
Power mode is selected, use 48MHz If the PHY supplies a 48
n
MHz
tio
clock during LS mode.

■ 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode,
u
use 6
ib
MHz when the UTMI+ PHY Low Power mode is selected and
r
the
di V
st
PHY supplies a 6 MHz clock during LS mode. If you select a 6

re k-
MHz
d il
clock during LS mode, you must do a soft reset.

an M
■ 2'b11: Reserved
Notes:
n by
■ When Core in FS mode, the internal and external clocks

have the
same frequency.
tio lic
■ When Core in LS mode,

ca ub
- If FSLSPclkSel = 2’b00: Internal and external clocks have the

same frequency
ifi p
- If FSLSPclkSel = 2’b10: Internal clock is divided by eight

version
od de
of external 48 MHz clock (utmifs_clk).

Shadow: Yes
M a
Shadow Ctrl: vs_1t

M

One-Way: Enabled
2 FSLSSupp R/W FS- and LS-Only Support (FSLSSupp) 0x0
The application uses this bit to control the core's
enumeration speed.
Using this bit, the application can make the core enumerate
as a FS
host, even If the connected device supports HS traffic. Do
not make
changes to this field after initial programming.
■ 1'b0: HS/FS/LS, based on the maximum speed supported
by the
584
CV1835

connected device
■ 1'b1: FS/LS-only, even If the connected device can
support HS
Shadow: Yes
Shadow Ctrl: vs_1t
3 Shadow: Yes
Shadow Ctrl: vs_1t
ed
One-Way: Enabled
w
7 Ena32KHzS R/W Enable 32 KHz Suspend mode (Ena32KHzS) 0x0
lo
This bit can be set only if FS PHY interface is selected.
Otherwise, this
al
bit needs to be set to zero. When FS PHY interface is chosen
and this bit
t
is set, the core expects that the PHY clock is switched from
no
48 MHz to
32 KHz during Suspend.
e
15:8 ResValid R/W Resume Validation Period (ResValid) 0x2
ar
This field is effective only when HCFG.Ena32KHzS is set. It
controls the
n
Resume period when the core resumes from Suspend. The
tio
core counts
the ResValid number of clock cycles to detect a valid resume
u
when this
ib
is set.
r
di V
st
_16
re k-
23 DescDMA R/W Enable Scatter/gather DMA in Host mode (DescDMA) 0x0

When the Scatter/Gather DMA option is selected during
d il
configuration of
an M
the RTL, the application can set this bit during initialization
to enable the
n by
Scatter/Gather DMA operation.

Note: This bit must be modified only once after a reset. The
tio lic
following
combinations are available for programming:
ca ub
■ GAHBCFG.DMAEn=0,HCFG.DescDMA=0 => Slave mode

■ GAHBCFG.DMAEn=0,HCFG.DescDMA=1 => Invalid
ifi p
■ GAHBCFG.DMAEn=1,HCFG.DescDMA=0 => Buffered DMA

od de
mode
■ GAHBCFG.DMAEn=1,HCFG.DescDMA=1 =>
M a
Scatter/Gather DMA
M
mode
In non-Scatter/Gather DMA mode, this bit is reserved.
25:24 FrListEn R/W Frame List Entries (FrListEn) 0x0
The value in the register specifies the number of entries in
the Frame
list. This field is valid only in Scatter/Gather DMA mode.
■ 2'b00: Reserved
■ 2'b01: 8 Entries
In non-Scatter/Gather DMA mode, these bits are reserved.
26 PerSchedEna R/W Enable Periodic Scheduling (PerSchedEna) 0x0
585
CV1835

Applicable in Host Scatter/Gather DMA mode only. Enables
periodic
scheduling within the core. Initially, the bit is res and the
core does not
process any periodic channels. As soon as this bit is set, the
core gets
ready to start scheduling periodic channels and sets
HCFG.PerSchedStat.
The setting of HCFG.PerSchedStat indicates the core has
ed
enabled
periodic scheduling. Once HCFG.PerSchedEna is set, the
w
application is
not supposed to reset the bit unless HCFG.PerSchedStat is
lo
set. As soon
al
as this bit is reset, the core gets ready to stop scheduling
periodic
t
channels and resets HCFG.PerSchedStat.
no
In non-Scatter/Gather DMA mode, this bit is reserved.
e
_27
ar
31 ModeChTimEn R/W Mode Change Ready Timer Enable (ModeChTimEn) 0x0
This bit is used to enable/disable the Host core to wait 200
n
PHY clock
tio
cycles at the end of Resume to change the opmode signal to
the PHY to
00 after Suspend or LPM.
u
■ 1'b0: The Host core waits for either 200 PHY clock cycles
ib
or a
r
di V
st
linestate of SE0 at the end of resume to the change the

re k-
opmode from
2'b10 to 2'b00
d il
■ 1'b1: The Host core waits only for a linestate of SE0 at the
an M
end of
resume to change the opmode from 2'b10 to 2'b00.
n by
HFIR
tio lic
Host Frame Interval Register

ca ub

ifi p

15:0 FrInt R/W Frame Interval (FrInt) 0xEA60
od de
The value that the application programs to this field specifies

the interval
M a
between two consecutive SOFs (FS) or micro- SOFs (HS) or

M
Keep-Alive
tokens (HS). This field contains the number of PHY clocks
that constitute the
required frame interval. The default value set in this field for
an FS operation
when the PHY clock frequency is 60 MHz. The application
can write a value to
this register only after the Port Enable bit of the Host Port
Control and Status
register (HPRT.PrtEnaPort) has been set. If no value is
programmed, the core
calculates the value based on the PHY clock specified in the
586
CV1835

FS/LS PHY Clock
Select field of the Host Configuration register
(HCFG.FSLSPclkSel). Do not
change the value of this field after the initial configuration.
■ 125 μs * (PHY clock frequency for HS)
■ 1 ms * (PHY clock frequency for FS/LS)
Shadow: Yes
Shadow Ctrl: vs_1t
ed
16 HFIRRldCtrl R/W Reload Control (HFIRRldCtrl) 0x0
This bit allows dynamic reloading of the HFIR register during
w
run time.
lo
■ 1'b0: The HFIR cannot be reloaded dynamically
■ 1'b1: The HFIR can be dynamically reloaded during
al
runtime.
t
This bit needs to be programmed during initial configuration
no
and its value must
not be changed during runtime.
e
_17 Shadow: Yes
ar
Shadow Ctrl: vs_1t
n
tio
HFNUM
u
Host Frame Number/Frame Time Remaining Register

ib

r
di V
st

re k-
15:0 FrNum RO Frame Number (FrNum)

This field increments when a new SOF is transmitted on the
d il
an M
USB, and is
reset to 0 when it reaches 16'h3FFF.
This field is writable only if Remove Optional Features? was
n by
not selected in
coreConsultant (OTG_RM_OTG_FEATURES = 0). Otherwise,
tio lic
reads return
the frame number value.
ca ub
Shadow: Yes
Shadow Ctrl: vs_1t
ifi p

od de
31:16 FrRem RO Frame Time Remaining (FrRem)

Indicates the amount of time remaining in the current
M a
microframe (HS) or
M
Frame (FS/LS), in terms of PHY clocks. This field decrements

on each PHY
clock. When it reaches zero, this field is reloaded with the
value in the Frame
Interval register and a new SOF is transmitted on the USB.
Shadow: Yes
Shadow Ctrl: vs_1t
HPTXSTS
Host Periodic Transmit FIFO/Queue Status Register
587
CV1835

15:0 PTxFSpcAvail RO Periodic Transmit Data FIFO Space Available (PTxFSpcAvail)
Indicates the number of free locations available to be written
to in the Periodic
TxFIFO. Values are in terms of 32-bit words
■ 16'h0: Periodic TxFIFO is full
■ 16'h1: 1 word available
■ 16'h2: 2 words available
■ 16'hn: n words available (n: 0 ~ 32,768)
■ 16’h8000: 32,768 words available
ed
w
Shadow: Yes
Shadow Ctrl: vs_1t
lo
al
One-Way: Enabled
23:16 PTxQSpcAvail RO Periodic Transmit Request Queue Space Available
t
(PTxQSpcAvail)
no
Indicates the number of free locations available to be written
in the Periodic
Transmit Request Queue. This queue holds both IN and OUT
e
ar
requests.
■ 8'h0: Periodic Transmit Request Queue is full
■ 8'h1: 1 location available
n
tio
■ 8'h2: 2 locations available
■ n: n locations available (n: 0~16)
u
ib
Shadow: Yes
Shadow Ctrl: vs_1t
r
di V
st

re k-
31:24 PTxQTop RO Top of the Periodic Transmit Request Queue (PTxQTop)

This indicates the entry in the Periodic Tx Request Queue
d il
an M
that is currently
being processes by the MAC. This register is used for
debugging.
n by
■ Bit [31]: Odd/Even (micro)Frame

- 1'b0: send in even (micro)Frame
tio lic
- 1'b1: send in odd (micro)Frame

■ Bits [30:27]: Channel/endpoint number
ca ub
■ Bits [26:25]: Type

- 2'b00: IN/OUT
ifi p
- 2'b01: Zero-length packet

od de
- 2'b10: CSPLIT
- 2'b11: Disable channel command
M a
■ Bit [24]: Terminate (last entry for the selected channel or

M
endpoint)
HAINT
Host All Channels Interrupt Register
15:0 HAINT RO Channel Interrupts (HAINT)
One bit per channel: Bit 0 for Channel 0, bit 15 for Channel
15
Shadow: Yes
Shadow Ctrl: vs_1t
588
CV1835

One-Way: Enabled
31:16 Reserved_414_31 RO Reserved for future use
_16
HAINTMSK
Host All Channels Interrupt Mask Register
ed
w
15:0 HAINTMsk R/W Channel Interrupt Mask (HAINTMsk) 0x0
One bit per channel: Bit 0 for channel 0, bit 15 for channel
lo
15
al
Shadow: Yes
Shadow Ctrl: vs_1t
t
no
One-Way: Enabled
31:16 Reserved_418_31 RO Reserved for future use
e
_16
HFLBAddr
ar
n
Host Frame List Base Address Register
tio

u

ib
31:0 HFLBAddr R/W The starting address of the Frame list. This register is 0x0
r
used only for Isochronous and Interrupt Channels.

di V
st
Shadow: Yes
re k-
Shadow Ctrl: vs_1t

d il

an M
One-Way: Enabled
n by
HCCHARn
Host Channel-n Characteristics Register
tio lic

ca ub

10:0 MPS R/W Maximum Packet Size (MPS) 0x0
ifi p
Indicates the maximum packet size of the associated

od de
endpoint.
Shadow: Yes
M a
Shadow Ctrl: vs_1t

M

One-Way: Enabled
14:11 EPNum R/W Endpoint Number (EPNum) 0x0
Indicates the endpoint number on the device serving as the
data source
or sink.
Shadow: Yes
Shadow Ctrl: vs_1t
15 EPDir R/W Endpoint Direction (EPDir) 0x0
Indicates whether the transaction is IN or OUT.
■ 1'b0: OUT
■ 1'b1: IN
589
CV1835

Shadow: Yes
Shadow Ctrl: vs_1t
One-Way: Enabled
17 LSpdDev R/W Low-Speed Device (LSpdDev) 0x0
This field is set by the application to indicate that this
channel is
communicating to a low-speed device.
ed
The application must program this bit when a low speed
device is
w
connected to the host through an FS HUB. The DWC_otg
lo
Host core
uses this field to drive the XCVR_SELECT signal to 2’b11 while
al
communicating to the LS Device through the FS hub.
Note: In a peer to peer setup, the DWC_otg Host core
t
no
ignores this bit
even if it is set by the application software.
19:18 EPType R/W Endpoint Type (EPType) 0x0
e
Indicates the transfer type selected.
ar
■ 2'b00: Control
■ 2'b01: Isochronous
n
■ 2'b10: Bulk
tio
■ 2'b11: Interrupt
21:20 EC R/W Multi Count (MC) / Error Count (EC) 0x0
u
When the Split Enable bit of the Host Channel-n Split Control
ib
register
r
(HCSPLTn.SpltEna) is reset (1'b0), this field indicates to the

di V
st
host the
re k-
number of transactions that must be executed per

d il
microframe for this

an M
periodic endpoint. For non-periodic transfers, this field is

used only in
n by
DMA mode, and specifies the number packets to be fetched

for this
channel before the internal DMA engine changes arbitration.
tio lic
■ 2'b00: Reserved. This field yields undefined results.

ca ub
■ 2'b01: 1 transaction
■ 2'b10: 2 transactions to be issued for this endpoint per
ifi p
microframe
■ 2'b11: 3 transactions to be issued for this endpoint per
od de
microframe
When HCSPLTn.SpltEna is set (1'b1), this field indicates the
M a
M
number of
immediate retries to be performed for a periodic split
transaction on
transaction errors. This field must be set to at least 2'b01.
28:22 DevAddr R/W Device Address (DevAddr) 0x0
This field selects the specific device serving as the data
source or sink.
29 OddFrm R/W Odd Frame (OddFrm) 0x0
This field is set (reset) by the application to indicate that the
OTG host
must perform a transfer in an odd (micro)frame. This field is
applicable
for only periodic (isochronous and interrupt) transactions.
590
CV1835

■ 1'b0: Even (micro)frame
■ 1'b1: Odd (micro)frame
This field is not applicable for Scatter/Gather DMA mode and
need not
be programmed by the application and is ignored by the
core.
30 ChDis RWS Write Behavior: One to set
Channel Disable (ChDis)
The application sets this bit to stop transmitting/receiving
ed
data on a
channel, even before the transfer for that channel is
w
complete. The
lo
application must wait for the Channel Disabled interrupt
before treating
al
the channel as disabled.
31 ChEna RWS Write Behavior: One to set
t
no
Channel Enable (ChEna)
When Scatter/Gather mode is enabled:
■ 1'b0: Indicates that the descriptor structure is not yet
e
ready.
ar
■ 1'b1: Indicates that the descriptor structure and data
buffer with data
n
is setup and this channel can access the descriptor.
tio
When Scatter/Gather mode is disabled:

This field is set by the application and cleared by the OTG
u
host.
ib
■ 1'b0: Channel disabled

r
■ 1'b1: Channel enabled

di V
st
re k-
HCDMAn
d il
an M
Host Channel-n DMA Address Register

n by

31:0 DMAAddr R/W DMA Address (DMAAddr) 0x0
tio lic
This field holds the start address in the external memory

from which the data
ca ub
for the endpoint must be fetched or to which it must be

stored. This register is
ifi p
incremented on every AHB transaction.

od de
Shadow: Yes
Shadow Ctrl: vs_1t
M a

M
One-Way: Enabled
HCDMABn
Host Channel-n DMA Buffer Address Register
31:0 DMABufAddr R/W DMA Address (DMAAddr) 0x0
Holds the current buffer address. This register is updated as
and when the data
transfer for the corresponding end point is in progress. This
register is present only
591
CV1835

in Scatter/Gather DMA mode. Otherwise this field is
reserved.
Shadow: Yes
Shadow Ctrl: vs_1t
One-Way: Enabled
ed
w
lo
12.6.6 Device Initialization Program
al
t
Be sure to complete the [clock start procedure] in 13.8.6.1 before starting and switching to the
no
device function. Please keep to the following steps.
e
1. Set DescDMA to 1 to start descriptor DMA mode.
ar
2. Set the device speed to HS or FS. n
3. Set the non-zero transfer status bit.
tio
4. Set the interval value for periodic transfers.

u
5. Set the FIFO threshold size for DMA transfer.

ib
6. Clear the DCTL.SftDiscon bit to allow the device to initiate the Connection action with the
r
di V
st
host.
re k-
7. Clear the following bits in GINTMSK:

d il
an M
8. USB Port Reset mask

9. Enumeration done mask
n by
10. Early suspend mask

tio lic
11. USB suspend mask

12. SOF mask
ca ub
13. Wait for the GINTSTS.USBReset interrupt to occur and start the USB reset initialization
ifi p
process.
od de
14. Wait for the GINTSTS.EnumerationDone interrupt to occur, indicating that the USB reset
M a
program has been completed. Then read the DSTS register to obtain the enumeration
M
speed and start the enumeration initialization process.
592
CV1835
12.6.7 Device Register Description

The address of the device register in the whole memory space is 0x0434_0000, indicating as
DEV_BASE_ADDR in this article. Therefore, the real address of each register in the memory space
will be [DEV_BASE_ADDR+ relative address].
12.6.7.1 Register Overview
ed
w
Offset
lo
DCFG 0x800 Device Configuration Register
al
DCTL 0x804 Device Control Register
DSTS 0x808 Device Status Register
t
DIEPMSK 0x810 Device IN Endpoint Common Interrupt Mask Register
no
DOEPMSK 0x814 Device OUT Endpoint Common Interrupt Mask Register
DAINT 0x818 Device All Endpoints Interrupt Register
DAINTMSK 0x81c Device Endpoints Interrupt Mask Register
e
ar
DIEPEMPMSK 0x834 Device IN Endpoint FIFO Empty Interrupt Mask Register
DEACHINT 0x838 Device Each Endpoint Interrupt Register
DEACHINTMSK 0x83c Device Each Endpoint Interrupt Register Mask
n
u tio
12.6.7.2 Detailed List of Registers

r ib
di V
st
re k-
d il
DCFG
an M
Device Configuration Register

n by

tio lic
1:0 DevSpd R/W Device Speed (DevSpd) 0x0

ca ub
Indicates the speed at which the application requires the core

to enumerate,
ifi p
or the maximum speed the application can support. However,

the actual bus
od de
speed is determined only after the chirp sequence is

completed, and is
M a
based on the speed of the USB host to which the core is

M
connected.
■ 2'b00: High speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
■ 2'b01: Full speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
■ 2'b10: Low speed (USB 1.1 transceiver clock is 6 MHz). If
you select
6MHz LS mode, you must do a soft reset.
■ 2'b11: Full speed (USB 1.1 transceiver clock is 48 MHz)
Shadow: Yes
Shadow Ctrl: vs_1t
One-Way: Enabled
2 NZStsOUTHShk R/W Non-Zero-Length Status OUT Handshake (NZStsOUTHShk) 0x0
593
CV1835

The application can use this field to select the handshake the
core sends on
receiving a non zero-length data packet during the OUT
transaction of a
control transfer's Status stage.
■ 1'b1: Send a STALL handshake on a non zero-length status
OUT
transaction and do not send the received OUT packet to the
application.
ed
■ 1'b0: Send the received OUT packet to the application
(zero-length or
w
non zero-length) and send a handshake based on the NAK and
lo
STALL
bits for the endpoint in the Device Endpoint Control register.
al
Shadow: Yes
Shadow Ctrl: vs_1t
t
no
3 Ena32KHzSusp R/W Enable 32 KHz Suspend mode (Ena32KHzSusp) 0x0
This bit can be set only if FS PHY interface is selected.
e
Otherwise, this bit
ar
needs to be set to zero. If FS PHY interface is chosen and this
bit is set, the
n
PHY clock during Suspend must be switched from 48 MHz to
tio
32 KHz.
Shadow: Yes
u
Shadow Ctrl: vs_1t

ib

One-Way: Enabled
r
di V
st
10:4 DevAddr R/W Device Address (DevAddr) 0x0

re k-
The application must program this field after every SetAddress

control
d il
command.
an M
12:11 PerFrInt R/W Periodic Frame Interval (PerFrInt) 0x0

Indicates the time within a (micro)frame at which the
n by
application must be
notified using the End Of Periodic Frame Interrupt. This can be
tio lic
used to
determine if all the isochronous traffic for that (micro)frame is
ca ub
complete.
■ 2'b00: 80% of the (micro)frame interval
ifi p
■ 2'b01: 85%
od de
■ 2'b10: 90%
■ 2'b11: 95%
M a
13 EnDevOutNak R/W Enable Device OUT NAK (EnDevOutNak) 0x0

M
This bit enables setting NAK for Bulk OUT endpoints after the
transfer is
completed for Device mode Descriptor DMA mode.
■ 1'b0: The core does not set NAK after Bulk OUT transfer
complete
■ 1'b1: The core sets NAK after Bulk OUT transfer complete
This is a one time programmable bit after reset like any other
DCFG register
bits.
This bit is valid only when OTG_EN_DESC_DMA == 1’b1.
14 XCVRDLY R/W Enables or disables delay between xcvr_sel and txvalid during 0x0
device chirp
594
CV1835

■ 1'b1: Enable delay between xcvr_sel and txvalid during
Device chirp
■ 1'b0: No delay between xcvr_sel and txvalid during Device
chirp
15 ErraticIntMsk R/W Mode: Device 0x0
Erratic Error Interrupt Mask
■ 1'b1: Mask early suspend interrupt on erratic error
■ 1'b0: Early suspend interrupt is generated on erratic error
17:16 Reserved_800_ RO Reserved for future use.
ed
17_16
22:18 EPMisCnt R/W IN Endpoint Mismatch Count (EPMisCnt) 0x8
w
This field is valid only in shared FIFO operation.
lo
The application programs this field with a count that
al
determines when the
core generates an Endpoint Mismatch interrupt
t
(GINTSTS.EPMis). The core
no
loads this value into an internal counter and decrements it.
The counter is
reloaded whenever there is a match or when the counter
e
expires. The width
ar
of this counter depends on the depth of the Token Queue.
23 DescDMA R/W Enable Scatter/Gather DMA in Device mode (DescDMA). 0x0
n
When the Scatter/Gather DMA option is selected during
tio
configuration of the
RTL, the application can set this bit during initialization to
u
enable the
ib
Scatter/Gather DMA operation.

r
Note: This bit must be modified only once after a reset.

di V
st
The following combinations are available for programming:

re k-
■ GAHBCFG.DMAEn=0,DCFG.DescDMA=0 => Slave mode

d il
■ GAHBCFG.DMAEn=0,DCFG.DescDMA=1 => Invalid

an M
■ GAHBCFG.DMAEn=1,DCFG.DescDMA=0 => Buffer DMA

mode
n by
■ GAHBCFG.DMAEn=1,DCFG.DescDMA=1 => Scatter/Gather

DMA mode
tio lic
25:24 PerSchIntvl R/W Periodic Scheduling Interval (PerSchIntvl) 0x0

PerSchIntvl must be programmed only for Scatter/Gather DMA
ca ub
mode.
This field specifies the amount of time the Internal DMA
ifi p
engine must
allocate For fetching periodic IN endpoint data. Based on the
od de
number of
periodic endpoints, this value must be specified as 25,50 or
M a
75% of
M
(micro)frame.
When any periodic endpoints are active, the internal DMA
engine allocates
the specified amount of time in fetching periodic IN endpoint
data.
When no periodic endpoints are active, the internal DMA
engine services
non-periodic endpoints, ignoring this field.
After the specified time within a (micro)frame, the DMA
switches to fetching
for non-periodic endpoints.
■ 2'b00: 25% of (micro)frame.
595
CV1835

■ 2'b11: Reserved.
31:26 ResValid R/W Resume Validation Period (ResValid) 0x2
This field is effective only when DCFG.Ena32KHzSusp is set. It
controls the
resume period when the core resumes from suspend. The core
counts for
“ResValid” number of clock cycles to detect a valid resume
ed
when this bit is
set.
w
lo
DCTL
al
Device Control Register
t
no
0 RmtWkUpSig R/W Remote Wakeup Signaling (RmtWkUpSig) 0x0
e
When the application sets this bit, the core initiates remote
ar
signaling to wake the USB host. The application must set this
bit to instruct the core to exit the Suspend state. As specified
n
in
tio
the USB 2.0 specification, the application must clear this bit 1–
15 ms after setting it.If LPM is enabled and the core is in the L1
u
(Sleep) state, when the application sets this bit, the core
ib
initiates L1 remote signaling to wake up the USB host. The

application must set this bit to instruct the core to exit the
r
di V
Sleep
st
re k-
state. As specified in the LPM specification, the hardware

automatically clears this bit 50 μs (TL1DevDrvResume) after
d il
being
an M
set by the application. The application must not set this bit
when GLPMCFG bRemoteWake from the previous LPM
n by
transaction is zero.
Shadow: Yes
tio lic
Shadow Ctrl: vs_1t

ca ub
One-Way: Enabled
1 SftDiscon R/W Soft Disconnect (SftDiscon) 0x1
ifi p
The application uses this bit to signal the DWC_otg core to do

a soft disconnect. As long as this bit is set, the host does not
od de
see that the device is connected, and the device does not
receive signals on the USB. The core stays in the disconnected
M a
M
state until the application clears this bit.

■ 1’b0: Normal operation. When this bit is cleared after a soft
disconnect, the core drives the phy_opmode_o signal on
the UTMI+ to 2’b00, which generates a device connect
event to the USB host. When the device is reconnected, the
USB host restarts device enumeration.
■ 1’b1: The core drives the phy_opmode_o signal on the
UTMI+ to 2’b01, which generates a device disconnect event
to the USB host.
Note: This bit can be also used for ULPI/FS Serial interfaces.
Note: This bit is not impacted by a soft reset.
Shadow: Yes
Shadow Ctrl: vs_1t
596
CV1835

2 GNPINNakSts RO Global Non-periodic IN NAK Status (GNPINNakSts)
■ 1'b0: A handshake is sent out based on the data availability
in the transmit FIFO.
■ 1'b1: A NAK handshake is sent out on all non-periodic IN
endpoints, irrespective of the data availability in the transmit
FIFO.
Shadow: Yes
Shadow Ctrl: vs_1t
ed
One-Way: Enabled
w
3 GOUTNakSts RO Global OUT NAK Status (GOUTNakSts)
lo
■ 1'b0: A handshake is sent based on the FIFO Status and
the NAK and STALL bit settings.
al
■ 1'b1: No data is written to the RxFIFO, irrespective of space
t
availability. Sends a NAK handshake on all packets, except
no
on SETUP transactions. All isochronous OUT packets are
dropped.
6:4 TstCtl R/W Test Control (TstCtl) 0x0
e
■ 3'b000: Test mode disabled
ar
■ 3'b001: Test_J mode
■ 3'b010: Test_K mode
n
■ 3'b011: Test_SE0_NAK mode
tio
■ 3'b100: Test_Packet mode

u
■ 3'b101: Test_Force_Enable
ib
7 SGNPInNak RWC Set Global Non-periodic IN NAK (SGNPInNak)
r
di V
st
A write to this field sets the Global Non-periodic IN NAK.The

re k-
application uses this bit to send a NAK handshake on all

nonperiodic
d il
an M
IN endpoints. The core can also set this bit when a

timeout condition is detected on a non-periodic endpoint in
shared FIFO operation.
n by
The application must set this bit only after making sure that
the
tio lic
Global IN NAK Effective bit in the Core Interrupt Register

(GINTSTS.GINNakEff) is cleared.
ca ub
8 CGNPInNak RWC Clear Global Non-periodic IN NAK (CGNPInNak)

A write to this field clears the Global Non-periodic IN NAK.
ifi p
9 SGOUTNak RWC Set Global OUT NAK (SGOUTNak)

od de
A write to this field sets the Global OUT NAK.

The application uses this bit to send a NAK handshake on all
M a
OUT endpoints. The application must set the this bit only after
M
making sure that the Global OUT NAK Effective bit in the Core
Interrupt Register (GINTSTS.GOUTNakEff) is cleared.
10 CGOUTNak RWC Clear Global OUT NAK (CGOUTNak)
A write to this field clears the Global OUT NAK.
11 PWROnPrgDon R/W Power-On Programming Done (PWROnPrgDone) 0x0
e The application uses this bit to indicate that register
programming is complete after a wake-up from Power Down
mode.
12 Reserved_804_ RO Reserved for future use.
12
14:13 GMC R/W Global Multi Count (GMC) 0x0
GMC must be programmed only once after initialization.
Applicable only for Scatter/Gather DMA mode. This indicates
597
CV1835

the number of packets to be serviced for that end point before
moving to the next end point. It is only for non-periodic end
points.
■ 2’b00: Invalid.
■ 2’b01: 1 packet.
■ 2’b10: 2 packets.
■ 2’b11: 3 packets.
The value of this field automatically changes to 2'h1 when
DCFG.DescDMA is set to 1. When Scatter/Gather DMA mode
ed
is disabled, this field is reserved and reads 2’b00.
15 IgnrFrmNum R/W Ignore frame number for isochronous endpoints (IgnrFrmNum) 0x0
w
Slave Mode (GAHBCFG.DMAEn=0):
lo
This bit is not valid in Slave mode and should not be
al
programmed to 1.Non-Scatter/Gather DMA mode
(GAHBCFG.DMAEn=1,DCFG.DescDMA=0):
t
This bit is not used when Threshold mode is enabled and
no
should not be programmed to 1.
In non-Scatter/Gather DMA mode, the application receives
transfer complete interrupt after transfers for multiple
e
(micro)frames are completed.
ar
■ When Scatter/Gather DMA mode is disabled, this field is
used by the application to enable periodic transfer interrupt.
n
The application can program periodic endpoint transfers for
tio
multiple (micro)frames.
- 0: Periodic transfer interrupt feature is disabled; the
u
application must program transfers for periodic

ib
endpoints every (micro)frame

r
- 1: Packets are not flushed when an ISOC IN token is

di V
st
received for an elapsed frame. The core ignores the

re k-
frame number, sending packets as soon as the packets

d il
are ready, and the corresponding token is received. This

an M
field is also used by the application to enable periodic

transfer interrupts.
Scatter/Gather DMA Mode
n by
(GAHBCFG.DMAEn=1,DCFG.DescDMA=1):
This bit is not applicable to high-speed, high-bandwidth
tio lic
transfers and should not be programmed to 1.

In addition, this bit is not used when Threshold mode is
ca ub
enabled and should not be programmed to 1.

■ 0: The core transmits the packets only in the frame number
ifi p
in which they are intended to be transmitted.

od de
■ 1: Packets are not flushed when an ISOC IN token is

received for an elapsed frame. The core ignores the frame
M a
number, sending packets as soon as the packets are ready,

M
and the corresponding token is received. When this bit is

set, there must be only one packet per descriptor.
16 NakOnBble R/W NAK on Babble Error (NakOnBble) 0x0
Set NAK automatically on babble (NakOnBble). The core sets
NAK automatically for the endpoint on which babble is
received.
17 EnContOnBNA R/W Enable Continue on BNA (EnContOnBNA) 0x0
This bit enables the DWC_otg core to continue on BNA for Bulk
OUT and INTR OUT endpoints. With this feature enabled,
when a Bulk OUT or INTR OUT endpoint receives a BNA
interrupt the core starts processing the descriptor that caused
the BNA interrupt after the endpoint re-enables the endpoint.
598
CV1835

■ 1'b0: After receiving BNA interrupt, the core disables the
endpoint. When the endpoint is re-enabled by the
application, the core starts processing from the DOEPDMA
descriptor.
■ 1'b1: After receiving BNA interrupt, the core disables the
endpoint. When the endpoint is re-enabled by the
application, the core starts processing from the descriptor
that received the BNA interrupt.
This bit is valid only when OTG_EN_DESC_DMA == 1'b1. It is
ed
a one-time programmable after reset bit like any other DCTL
register bits.
w
18 DeepSleepBESL R/W Deep Sleep BESL Reject 0x0
lo
Reject Core rejects LPM request with HIRD value greater than HIRD
threshold programmed. NYET response is sent for LPM tokens
al
with HIRD value greater than HIRD threshold. By default, the
Deep Sleep BESL Reject feature is disabled.
t
no
31_19
e
DSTS
Device Status Register
ar
n
tio

0 SuspSts RO Suspend Status (SuspSts)
u
In Device mode, this bit is set as long as a Suspend condition is

ib
detected on
r
di V
the USB. The core enters the Suspend state when there is no
st
re k-
activity on the
phy_line_state_i signal for an extended period of time.
d il
The core comes out of the suspend under the following

an M
conditions:
■ If there is any activity on the phy_line_state_i signal
n by
■ If the application writes to the Remote Wakeup Signaling

bit in the Device
tio lic
Control register (DCTL.RmtWkUpSig).

Shadow: Yes
ca ub
Shadow Ctrl: vs_1t

ifi p
2:1 EnumSpd RO Enumerated Speed (EnumSpd)

Indicates the speed at which the DWC_otg core has come up
od de
after speed
M a
detection through a chirp sequence.

M
■ 2'b00: High speed (PHY clock is running at 30 or 60 MHz)

■ 2'b01: Full speed (PHY clock is running at 30 or 60 MHz)
■ 2'b10: Low speed (PHY clock is running at 6 MHz)
■ 2'b11: Full speed (PHY clock is running at 48 MHz)
Low speed is not supported for devices using a UTMI+ PHY.
3 ErrticErr RO Erratic Error (ErrticErr)
The core sets this bit to report any erratic errors
(phy_rxvalid_i/phy_rxvldh_i
or phy_rxactive_i is asserted For at least 2 ms, due to PHY
error) seen on
the UTMI+. Due to erratic errors, the DWC_otg core goes into
Suspend state
and an interrupt is generated to the application with Early
599
CV1835

Suspend bit of the
Core Interrupt register (GINTSTS.ErlySusp). If the early suspend
is asserted
because of an erratic error, the application can only perform a
soft
disconnect recover.
7_4
21:8 SOFFN RO Frame or Microframe Number of the Received SOF (SOFFN)
ed
When the core is operating at high speed, this field contains a
microframe
w
number. When the core is operating at full or low speed, this
field contains a
lo
Frame number.
al
Note: This register may return a non zero value if read
immediately after
t
power on reset. In case the register bit reads non zero
no
immediately after
power on reset it does not indicate that SOF has been received
e
from the
ar
host. The read value of this interrupt is valid only after a valid
connection n
between host and device is established.
tio
23:22 DevLnSts RO Device Line Status (DevLnSts)
Indicates the current logic level USB data lines
u
■ Bit [23]: Logic level of D+

ib
■ Bit [22]: Logic level of D–

r
di V
st
31_24 Shadow: Yes

re k-
Shadow Ctrl: vs_1t

d il
an M
DIEPMSK
n by
Device IN Endpoint Common Interrupt Mask Register

tio lic

ca ub
0 DiXferComplMsk R/W Transfer Completed Interrupt Mask (XferComplMsk) 0x0

Shadow: Yes
ifi p
Shadow Ctrl: vs_1t

od de
One-Way: Enabled
1 DiEPDisbldMsk R/W Endpoint Disabled Interrupt Mask (EPDisbldMsk) 0x0
M a
M
2 DiAHBErrMsk R/W AHB Error Mask (AHBErrMsk) 0x0

3 TimeOUTMsk R/W Timeout Condition Mask (TimeOUTMsk) (Non- 0x0
isochronous endpoints)
4 INTknTXFEmpMsk R/W IN Token Received When TxFIFO Empty Mask 0x0
(INTknTXFEmpMsk)
5 INTknEPMisMsk R/W IN Token received with EP Mismatch Mask 0x0
(INTknEPMisMsk)
6 INEPNakEffMsk R/W IN Endpoint NAK Effective Mask (INEPNakEffMsk) 0x0
8 TxfifoUndrnMsk R/W Fifo Underrun Mask (TxfifoUndrnMsk) 0x0
9 BNAInIntrMsk R/W BNA Interrupt Mask (BNAInIntrMsk) 0x0
This bit is valid only when Device Descriptor DMA is
enabled.
600
CV1835

13 DiNAKMsk R/W NAK interrupt Mask (NAKMsk) 0x0
Shadow: Yes
Shadow Ctrl: vs_1t
DOEPMSK
ed
Device OUT Endpoint Common Interrupt Mask Register
w
lo
0 XferComplMsk R/W Transfer Completed Interrupt Mask (XferComplMsk) 0x0
al
Shadow: Yes
Shadow Ctrl: vs_1t
t
no
One-Way: Enabled
1 EPDisbldMsk R/W Endpoint Disabled Interrupt Mask (EPDisbldMsk) 0x0
e
2 AHBErrMsk R/W AHB Error (AHBErrMsk) 0x0
ar
3 SetUPMsk R/W SETUP Phase Done Mask (SetUPMsk) 0x0
Applies to control endpoints only.
n
4 OUTTknEPdisMsk R/W OUT Token Received when Endpoint Disabled Mask 0x0
tio
(OUTTknEPdisMsk)
Applies to control OUT endpoints only.
u
5 StsPhseRcvdMsk R/W Status Phase Received Mask (StsPhseRcvdMsk) 0x0

ib
6 Back2BackSETup R/W Back-to-Back SETUP Packets Received Mask 0x0

r
Msk (Back2BackSETupMsk)
di V
st
Applies to control OUT endpoints only.

re k-

d il
8 OutPktErrMsk R/W OUT Packet Error Mask (OutPktErrMsk) 0x0

an M
9 BnaOutIntrMsk R/W BNA interrupt Mask (BnaOutIntrMsk) 0x0

n by
_10
12 BbleErrMsk R/W Babble Error interrupt Mask (BbleErrMsk) 0x0
tio lic
13 NAKMsk R/W NAK interrupt Mask (NAKMsk) 0x0

14 NYETMsk R/W NYET interrupt Mask (NYETMsk) 0x0
ca ub
Shadow: Yes
Shadow Ctrl: vs_1t
ifi p

od de
_15
M a
M
DAINT
Device All Endpoints Interrupt Register
15:0 InEpInt RO OUT Endpoint Interrupt Bits (OutEPInt)
One bit per OUT endpoint:
Bit 16 for OUT endpoint 0, bit 31 for OUT endpoint 15
Shadow: Yes
Shadow Ctrl: vs_1t
One-Way: Enabled
601
CV1835

31:16 OutEPInt RO OUT Endpoint Interrupt Bits (OutEPInt)
Bit 16 for OUT endpoint 0, bit 31 for OUT endpoint 15
DAINTMSK
Device Endpoints Interrupt Mask Register
ed
15:0 InEpMsk R/W IN EP Interrupt Mask Bits (InEpMsk) 0x0
w
One bit per IN Endpoint:
Bit 0 for IN EP 0, bit 15 for IN EP 15
lo
The value of this field depends on the number of IN
al
endpoints that are configured.
Shadow: Yes
t
Shadow Ctrl: vs_1t
no
One-Way: Enabled
e
31:16 OutEpMsk R/W OUT EP Interrupt Mask Bits (OutEpMsk) 0x0
ar
One per OUT endpoint:
Bit 16 for OUT EP 0, bit 31 for OUT EP 15
The value of this field depends on the number of OUT
n
endpoints that are configured.
u tio
DIEPEMPMSK
ib
Device IN Endpoint FIFO Empty Interrupt Mask Register

r
di V
st

re k-

d il
15:0 InEpTxfEmpMsk R/W IN EP Tx FIFO Empty Interrupt Mask Bits 0x0

an M
(InEpTxfEmpMsk)
These bits acts as mask bits for DIEPINTn.
n by
TxFEmp interrupt One bit per IN Endpoint:

■ Bit 0 for IN endpoint 0
...
tio lic
■ Bit 15 for endpoint 15

ca ub
Shadow: Yes
Shadow Ctrl: vs_1t
ifi p

One-Way: Enabled
od de

M a
M
DEACHINT
Device Each Endpoint Interrupt Register
15:0 EchInEpInt RO IN Endpoint Interrupt Bits (EchInEpInt)
...
Shadow: Yes
Shadow Ctrl: vs_1t
602
CV1835

One-Way: Enabled
31:16 EchOutEPInt RO OUT Endpoint Interrupt Bits (EchOutEPInt)
■ Bit 16 for OUT endpoint 0
...
■ Bit 31 for OUT endpoint 15
DEACHINTMSK
ed
Device Each Endpoint Interrupt Register Mask
w
lo
al
15:0 EchInEpMsk R/W IN EP Interrupt Mask Bits (EchInEpMsk) 0x0
t
no
...
e
Shadow: Yes
ar
Shadow Ctrl: vs_1t
n
One-Way: Enabled
tio
31:16 EchOutEpMsk R/W OUT EP Interrupt Mask Bits (EchOutEpMsk) 0x0

One per OUT Endpoint:
u

ib
...
r

di V
st
re k-
d il
an M
n by
12.7SARADC
tio lic
ca ub
12.7.1 Overview
ifi p
od de
The SARADC is an analog signal to digital conversion controller. There is a SARADC

M a
M
controller in this chip and 3 ADC channels on it .
12.7.2 Features
 Controller operating frequency 12.5MHz

 Samplig frequency can not be higher than 320K/S
 12bit sampling accuracy, 3 independent channels
 Three channels can be triggered at once
603
CV1835
 With sampling complete interrupt
12.7.3 Working method
The CPU configures the scanning channels, 3 channels can be configured at the same
time, and then starts SARADC for channel sampling. After finishing all the enabled
ed
channels sampling, the system is notified of the completion of sampling through
interrupts, and the CPU can obtain the conversion results.
w
lo
12.7.4 SARADC register overview
al
t
no
SARADC Base address 0x030F0000
RTCSYS_SARADC Base address 0x0502C000
e
ar
Offset n
saradc_ctrl 0x004 control register
tio
saradc_status 0x008 staus register
saradc_cyc_set 0x00c saradc waveform setting register
saradc_ch1_result
u
0x014 channel 1 result register

ib
saradc_ch2_result 0x018 channel 2 result register

saradc_ch3_result 0x01c channel 3 result register
r
di V
st
saradc_intr_en 0x020 interrupt enable register

re k-
saradc_intr_clr 0x024 interrupt clear register

saradc_intr_sta 0x028 interrupt status register
d il
an M
saradc_intr_raw 0x02c interrupt raw status register

n by
12.7.5 SARADC register description

tio lic
ca ub
ifi p
od de
saradc_ctrl
M a
M

0 reg_saradc_en RWS when re_saradc_en is set , saradc start
to measure the channels enabled in
reg_saradc_sel
3:1 Reserved
7:4 reg_saradc_sel R/W select channel (1~3) 0x0
31:8 Reserved
saradc_status
604
CV1835

0 sta_saradc_busy RO busy rise when re_saradc_en is set
3:1 Reserved
7:4 sta_saradc_ch_busy RO per channel busy status
15:8 Reserved
19:16 sta_saradc_st RO fsm status for debug
24:20 sta_saradc_cycle RO sample cycle for debug
31:25 Reserved
ed
saradc_cyc_set
w
lo
al
4:0 reg_saradc_cyc_settling R/W saradc startup cycle = 1 + 0xF
reg_saradc_cyc_settling , default is 16
t
no
cycle
7:5 Reserved
11:8 reg_saradc_cyc_samp R/W saradc sample window = 1 + 0x3
e
reg_saradc_cyc_samp , default is 4 cycle
ar
15:12 reg_saradc_cyc_clkdiv R/W saradc clock divider , freq = 0x1
ip_clk/(1+clk_div) , default is 25M/2 =
n
12.5M = 80ns
tio
19:16 reg_saradc_cyc_comp R/W saradc compare cycle = 1+ 0xB

reg_saradc_cyc_comp , default is 12
u
cycle
ib
31:20 Reserved
r
di V
st
re k-
saradc_ch1_result
d il

an M

11:0 sta_saradc_ch1_result RO ch1 measure result
n by
14:12 Reserved
15 sta_saradc_ch1_valid RO ch1 measure result is valid.
tio lic
The valid status will be cleared when

ca ub
this channel is re-triggered to

remeasure,
ifi p
31:16 Reserved
od de
saradc_ch2_result
M a

M

14:12 Reserved
remeasure,
31:16 Reserved
saradc_ch3_result
605
CV1835

14:12 Reserved
remeasure,
31:16 Reserved
ed
saradc_intr_en
w
lo
al
0 sta_saradc_intr_en R/W interrupt enable (mask) 0x0
t
31:1 Reserved
no
saradc_intr_clr
e
ar
n
0 sta_saradc_intr_clr RWC interrupt clear
tio
31:1 Reserved
u
saradc_intr_sta
r ib

di V
st
re k-

0 sta_saradc_intr_sta RO interrup masked status
d il
[0]: all channels measurenment in this

an M
time is finished
31:1 Reserved
n by
saradc_intr_raw
tio lic

ca ub

ifi p
0 sta_saradc_intr_raw RO interrupt raw status

[0]: all channels measurenment in this
od de
time is finished
31:1 Reserved
M a
M
606
CV1835
12.8Temperature sensor
12.8.1 Overview
The chip has two built-in temperature sensors to monitor the chip temperature
periodically. The power management module can be triggered to reset the system
ed
when the chip is overheated and the CPU cannot respond to the overheating interrupt
w
to avoid the risk of overheating.
lo
al
t
no
 Single measurement time:
e
ar
If setting reg_tempsen_accsel to 1 (1024T), the sampling time will be
(1/(25M/12))*(1024+2+64) ~ 523.2us
n
tio
 Period measurement time:

default value of reg_tempsen_auto_prediv is 24, it make timing unit of
u
ib
reg_tempsen_auto_cycle to be 1us. The period time between two samples should

r
di V
st
be configured larger than the single measurement time. Configure

re k-
reg_tempsen_auto_cycle = 1000000 if measured once per second.

d il
an M
 Configure measurement channnel:

Configure reg_tempsen_sel[1:0] = 0x3 to make two temperature sensors will be
n by
measured simultaneously。
tio lic
 Configure high and low temperature monitoring thresholds:

ca ub
Configure the temperature threshold that triggers high temperature alarm and low
ifi p
temperature recovery to the register tempsen_chx_temp_th.

od de
 Configure interrupt setting

M a
 Enable temperature sensor for measurement:

M
Configure reg_tempsen_en to 1 to trigger measurement then wait for interruption.
Table 12- 9 Tempsensor Interrupt vector description
中斷位信號描述
[0] Irq_Temp0_measure Tempsens0 量測完成
[1] Irq_Temp1_measure Tempsens1 量測完成
[2] reserved 保留
607
CV1835
中斷位信號描述
[3] reserved 保留
[4] Irq_Temp0_over_high_level Tempsens0 溫度大於、等於高溫臨界值
[5] Irq_Temp1_over_high_level Tempsens1 溫度大於、等於高溫臨界值
[6] reserved 保留
[7] reserved 保留
ed
[8] Irq_Temp0_under_low_level Tempsens0 溫度小於、等於低溫臨界值
w
[9] Irq_Temp1_under_low_level Tempsens1 溫度小於、等於低溫臨界值
lo
[10] reserved 保留
al
t
[12] Irq_Temp0_over_high_cont Tempsens0 溫度大於、等於高溫臨界值已達
no
reg_tempsen_ovhl_cnt_to_irq 次數
[13] Irq_Temp1_over_high_cont Tempsens1 溫度大於、等於高溫臨界值已達
e
ar
reg_tempsen_ovhl_cnt_to_irq 次數
n
tio
u
[16] Irq_Temp0_under_low_cont Tempsens0 溫度小於、等於低溫臨界值已達

ib
reg_tempsen_udll_cnt_to_irq 次數
r
di V
st
[17] Irq_Temp1_under_low_cont Tempsens1 溫度小於、等於低溫臨界值已達

re k-
reg_tempsen_udll_cnt_to_irq 次數
d il
an M
n by
[20] Irq_Temp0_overheat Tempsens0 溫度大於、等於過熱臨界值

tio lic
[21] Irq_Temp1_overheat Tempsens1 溫度大於、等於過熱臨界值

ca ub
ifi p
od de
M a
M
608
CV1835
ed
w
lo
al
t
no
e
ar
 Figure 12- 40 Relationship between temperature measurement time, count and
interruption
n
tio
 Check the temperature measurement results: sta_tempsen_chX_result record the

u
temperature measurement results of the previous time ,

r ib
sta_tempsen_chX_max_result records the maximum temperature measured, and

di V
st
re k-
tempsen_chX_temp_th_cnt records the times of continuous high temperature and

d il
low temperature.
an M
 Configures overheating protection reg_tempsen_overheat_th、Overtemperature

n by
reset request countdown time reg_tempsen_overheat_cycleand enables

tio lic
reg_overheat_reset_en.
ca ub
Please refer to register chapter of RTC, it configures hw_thm_shdn_en,

RTC_EN_THM_SHDN and RTC_THM_SHDN_AUTO_REBOOT Enable overheating to
ifi p
od de
trigger power down or restart. In the case of overheating, the temp sensor
controller will first issue an interrupt and start counting down. When
M a
M
sta_tempsen_overheat_countdown equals to 1, it triggers power down protection

request of RTC. If the software has been involved before and controlled the
temperature, it can clear the overheat countdownreg_overheat_reset_clr. However,
when the next measurement result is still overheated, the overheat protection
interrupt will trigger and countdown again.
609
CV1835
12.8.3 Temperature sensor register overview
BassAddress: 0x030A0000
Offset
tempsen_version 0x000 ip version number
ed
tempsen_ctrl 0x004 control register
tempsen_status 0x008 staus register
w
tempsen_set 0x00c temperature sensor macro setting
tempsen_intr_en 0x010 interrupt enable
lo
tempsen_intr_clr 0x014 interrupt clear
al
tempsen_intr_sta 0x018 interupt status
tempsen_intr_raw 0x01c interrupt raw status
t
no
tempsen_ch0_result 0x020 temperature sensor channel 0 result
tempsen_ch1_result 0x024 temperature sensor channel 1 result
tempsen_ch0_temp_th 0x040 temperature sensor channel 0 threshold
e
tempsen_ch1_temp_th 0x044 temperature sensor channel 1 threshold
ar
Overheat_th 0x060 overheat threshold register
tempsen_auto_period 0x064 auto sample setting register
n
tempsen_overheat_ctrl 0x068 overheat control register
tio
tempsen_overheat_countdown 0x06c overheat status register

tempsen_ch0_temp_th_cnt 0x070 counter of channel 0 over/under threshold event
u
tempsen_ch1_temp_th_cnt 0x074 counter of channel 1 over/under threshold event

r ib
di V
st
re k-
d il
an M
12.8.4 Temperature sensor register description

n by
tio lic
ca ub
tempsen_version
ifi p

od de

M a
31:0 reg_ip_version RO verision 1.0

M
tempsen_ctrl
0 reg_tempsen_en R/W when re_tempsen_en is set , tempsen 0x0
start to measure the channel set in
reg_tempsen_sel
3:1 Reserved
7:4 reg_tempsen_sel R/W temperature sense channel selection 0x0
15:8 Reserved
23:16 reg_tempsen_ovhl_cnt_to_irq R/W counting threshold of high temperature 0x8
610
CV1835

31:24 reg_tempsen_udll_cnt_to_irq R/W counting threshold of low temperature 0x8
tempsen_status
0 sta_tempsen_busy RO busy status rise when re_tempsen_en is
set
31:1 Reserved
ed
w
tempsen_set
lo
al
0 reg_tempsen_bgen R/W sensor macro bandgap enable 0x0
t
1 reg_tempsen_chopen R/W sensor macro chopper function enable 0x1
no
2 reg_tempsen_choppol R/W sensor macro chopper polarity when 0x1
CHOPEN=0
e
3 reg_tempsen_clkpol R/W sensor macro clock polarity when 0x1
ar
DA_TEMPSEN_EN=0
5:4 reg_tempsen_chopsel R/W sensor macro chop period, 0:128T, 0x2
n
1:256T, 2:512T, 3:1024T
tio
7:6 reg_tempsen_accsel R/W sensor macro accumulate period, 0x1

0:512T, 1:1024T, 2:2048T, 3:4096T
u
15:8 reg_tempsen_cyc_clkdiv R/W clock divider for sensor macro, freq = 0xB
ib
ip_clk/(1+clk_div) , default is 25M/12

=2.083M , T = 0.48us
r
di V
st
17:16 reg_tempsen_tsel R/W sensor macro test selection, please keep 0x0
re k-
0
18 reg_tempsen_en_bjt_test R/W sensor macro test selection, please keep 0x0
d il
an M
0
31:19 Reserved
n by
tempsen_intr_en
tio lic

ca ub

31:0 sta_tempsen_intr_en R/W interrupt enable 0x0
ifi p
od de
tempsen_intr_clr
M a
M

31:0 sta_tempsen_intr_clr RWC interrupt clear
tempsen_intr_sta
31:0 sta_tempsen_intr_sta RO interrupt masked status
tempsen_intr_raw
611
CV1835

31:0 sta_tempsen_intr_raw RO interrupt raw status:
[3:0] ch3~ch0 measurement finish
[7:4] ch3~ch0 measurement result is
higher than high temperature threshold
lower than low temperature threshold
[15:12] ch3~ch0's high temperature
event count is more than threshold
[19:16] ch3~ch0's low temperature
ed
event count is more than threshold
w
higher than overheat temperature
lo
tempsen_ch0_result
al
t
no
12:0 sta_tempsen_ch0_result RO channel 0 current temperature
measurement result
e
15:13 Reserved
ar
28:16 sta_tempsen_ch0_max_result RO channel 0 max temperature
measurement result
n
30:29 Reserved
tio
31 clr_tempsen_ch0_max_result RWC write 1 to clear channel 0 max

temperature measurement result
u
ib
tempsen_ch1_result
r
di V
st
re k-

d il
an M
12:0 sta_tempsen_ch1_result RO channel 1 current temperature

measurement result
15:13 Reserved
n by
28:16 sta_tempsen_ch1_max_result RO channel 1 max temperature

measurement result
tio lic
30:29 Reserved
ca ub
31 clr_tempsen_ch1_max_result RWC write 1 to clear channel 1 max

temperature measurement result
ifi p
od de
tempsen_ch0_temp_th
M a
M

12:0 reg_tempsen_ch0_hi_th R/W channel 0 high temperature threshold 0x0
to trigger interrupt
15:13 Reserved
28:16 reg_tempsen_ch0_lo_th R/W channel 0 low temperature threshold to 0x0
trigger interrupt
31:29 Reserved
tempsen_ch1_temp_th
612
CV1835

12:0 reg_tempsen_ch1_hi_th R/W channel 1 high temperature threshold 0x0
to trigger interrupt
15:13 Reserved
28:16 reg_tempsen_ch1_lo_th R/W channel 1 low temperature threshold to 0x0
trigger interrupt
31:29 Reserved
Overheat_th
ed
w
12:0 reg_tempsen_overheat_th R/W overheat temperature threshold 0x0
lo
31:13 Reserved
al
t
tempsen_auto_period
no
e
23:0 reg_tempsen_auto_cycle R/W auto measure period. T_measure = 0x0
ar
reg_tempsen_auto_cycle*T_prediv
31:24 reg_tempsen_auto_prediv R/W a predivider setting for auto measure 0x18
n
period. T_prediv =
tio
(25M/( reg_tempsen_auto_prediv+1))
u
tempsen_overheat_ctrl
r ib

di V
st

re k-
29:0 reg_tempsen_overheat_cycle R/W After overheat event happens, the cycle 0x10000
d il
count will be load to a counter and 0

an M
trigger counting down. when counting

down to 1, a reset signal will be issue to
n by
power control unit.

30 reg_overheat_reset_clr RWC write 1 to stop overheat reset counting.
tio lic
31 reg_overheat_reset_en R/W enable overheat reset counting down. 0x0

ca ub
tempsen_overheat_countdown
ifi p

od de

29:0 sta_tempsen_overheat_countdown RO overheat reset counter
M a
30 Reserved
M
31 sta_overheat_reset RO overheat reset signal status
tempsen_ch0_temp_th_cnt
7:0 sta_ch0_over_hi_temp_th_cnt RO channel 0 high temperature event count
status
15:8 sta_ch0_under_lo_temp_th_cnt RO channel 0 low temperature event count
status
16 reg_ch0_temp_th_cnt_clr RWC write 1 to clear channel 0 temperature
613
CV1835

event count
31:17 Reserved
tempsen_ch1_temp_th_cnt
7:0 sta_ch1_over_hi_temp_th_cnt RO channel 1 high temperature event count
status
ed
15:8 sta_ch1_under_lo_temp_th_cnt RO channel 1 low temperature event count
w
status
16 reg_ch1_temp_th_cnt_clr RWC write 1 to clear channel 1 temperature
lo
event count
al
31:17 Reserved
t
no
12.9PWM
e
ar
n
12.9.1 Overview
u tio
The chip provides a set of four independent PWM channel outputs.

r ib
di V
st
re k-
12.9.2 Features
d il
an M
n by
The clock source for PWM is either 100MHz or 148.5MHz (default is 100MHz). Each
PWM channel can operate independently:
tio lic
ca ub
 Support 30-bit period counter and high/low level counter for PWM waveform
ifi p
 Maximum PWM frequency up to 50MHz (100MHz/2) or 74.25MHz

od de
(148.5MHz/2), and minimum PWM frequency down to 0.093Hz

M a
(100MHz/(2^30-1)) or 0.138Hz (148.5MHz/(2^32-1))

M
 Support continuous mode (PWMMODE = 0) and fixed pulse count mode

(PWMMODE = 1)
 Support 4-channel PWM synchronous output mode (SHIFT MODE= 1) where
the phase difference between each channel are configurable
614
CV1835
12.9.3 Operation
The basic programming flow is described as follows (takes PWM0 as an example):
1. Calculates the clock cycle counts for PWM waveform high/low-level period
according to the selected clock source
ed
2. Write the period counter value into registers HLPERIOD0、PERIOD0
w
3. Set register bit PWMMODE to 0 to operate at continuous mode. The PWM0 will
lo
start generating after register bit PWMSTART[0] is set to 1 and will stop until
al
PWMSTART[0] is set to 0.
t
no
4. Set register bit PWMMODE to 1 to operate at fixed pulse count mode. Specify
the required PWM waveform to be generated to register PCOUNT0. The PWM0
e
ar
will start generating after PWMSTART[0] is set to 1 and will stop automatically
when the number of pulse is met. The status register PWMDONE turns from 0 to
n
tio
1.
u
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
Figure 12- 41 PWM Continuous mode

ifi p
od de
M a
M
615
CV1835
Figure 12- 42 PWM Pulse count mode
For example: to generate an 1MHz frequency square waveform which low level period
percentage is 75%, and totally 16 pulses:
1. Use 100MHz clock source, the period count (PERIOD0) is 100MHz / 1MHz = 100,
ed
and the low-level count (HLPERIOD0) is 100 x 75% = 75. The pulse count
w
(PCOUNT0) is 16.
lo
al
2. Set PWMSTART[0] to 1 to start PWM.
3. Read register bit PWMDONE[0] until changes from 0 to 1.
t
no
4. The generated number of PWM pulses is stored in register PULSECOUNT0 and
its value should equal to 16.
e
ar
n
To enable PWM again, set PWMSTART[0] to 0 and then 1 to reset the counters and
tio
status registers.
u
ib
Set SHIFTMODE to 1 can make 4-channel PWM operate at synchronous mode. The
r
di V
st
re k-
programming flow is described as follows:

d il
an M
1. Specify the four register pairs HLPERIOD0/PERIOD0, HLPERIOD1/PERIOD1,

n by
HLPERIOD2/PERIOD2, HLPERIOD3/PERIOD3 to the same value

2. Specify the phase shift cycle counts for the four waveform to registers
tio lic
SHIFTCOUNT0 to SHIFTCOUNT3.
ca ub
3. Set PWMSTART[3:0] to 4'hF and then set register bit SHIFTSTART to 1. The period
ifi p
counters of four PWM will start counting at the same time, and the first rising
od de
edge of nth PWM channel depends on the value of SHIFTCOUNTn.

M a
M
616
CV1835
ed
w
lo
al
t
no
e
Figure 12- 43 PWM Continuous Shift Mode
ar
n
For example: to simultaneously generate four channels 1KHz frequency square
tio
waveform which low level period percentage is 75% and each waveform is shifted by
u
ib
1/4 cycle period sequencially:

r
di V
st
re k-
1. Use 100MHz clock source, the period count is 100MHz / 1KHz = 100000, and the
d il
an M
low-level count is 100000 x 75% = 75000.

2. Specify SHIFTCOUNT0 = 0; SHIFTCOUNT1= 100,000 x 1/4 = 25,000;
n by
SHIFTCOUNT2 = 100,000 x 2/4 = 50,000; SHIFTCOUNT3 = 100,000 x 3/4 =

tio lic
75,000.
ca ub
3. Set PWMSTART[3:0] to 4'hf and set SHIFTSTART to 1.

ifi p
od de
Set SHIFTSTART to 0 to stop PWM. Read register bits PWMDONE[3:0] until 4'hf
M a
indicates that four channels waveform are completed.

M
12.9.4 PWM Register Overview
PWM register overview is shown as ：
617
CV1835
错误!未找到引用源。.
12.9.5 PWM Register Description
ed
HLPERIOD0
w
lo
al
29:0 HLPERIOD0 R/W PWM0 low level period counter value 0x1
(unit is clk_pwm, value must > 0)
t
no
PERIOD0
e
ar
29:0 PERIOD0 R/W PWM0 period counter value (unit is
n 0x2
clk_pwm, PERIOD must > 1 and must >
tio
HLPERIOD)
u
HLPERIOD1
ib

r
di V
st

re k-
d il
an M
PERIOD1
n by

tio lic
29:0 PERIOD1 R/W PWM1 period counter value (unit is 0x2

ca ub

HLPERIOD)
ifi p
HLPERIOD2
od de

M a

M
PERIOD2
HLPERIOD)
618
CV1835
HLPERIOD3
PERIOD3
ed
w
lo
HLPERIOD)
al
POLARITY
t
no
e
3:0 POLARITY R/W Polarity of PWM0~3 0x0
ar
[n] = 0: PWMn default low
[n] = 1: PWMn default high
n
7:4 Reserved
tio
11:8 PWMMODE R/W PWM mode of PWM0~3 0x0

[n+8] = 0: PWMn is continuous mode
u
[n+8] = 1: PWMn is pulse count mode

ib
15:12 Reserved
r
16 SHIFTMODE R/W PWM Phase shift mode 0x0

di V
st
0 = PWM0~3 operate at normal mode

re k-
1 = PWM0~3 operate at Phase shift

d il
mode
an M
19:17 Reserved
20 pclk_force_en R/W pclk clock always enable 0x0
n by
0 = enable clock auto gating while not

access APB
1 = pclk keep on
tio lic
31:21 Reserved
ca ub
PWMSTART
ifi p

od de

M a
3:0 PWMSTART R/W Enable PWM0~3 0x0

M
[n] = 0: disable PWMn

[n] = 1: enable PWMn
If SHIFTMODE = 1, PWMSTART[3:0] used
as the output enable of PWM0~3. The
PWM is triggered by SHIFTSTART.
31:4 Reserved
PWMDONE
3:0 PWMDONE RO PWM output done status for PWM0~3
619
CV1835

[n] = 1: PWMn finish output
This bit will be cleared to 0 after
PWMSTART[n] set to 0 then to 1.
31:4 Reserved
PWMUPDATE
ed
3:0 PWMUPDATE R/W Dynamic Update PWM counter value 0x0
w
When PWMSTART set to 1, the register
value (HLPERIODn, PERIODn) will be
lo
latched. In order to dynamic update
al
PWM period, set this bit to 1 then to 0
to upload the new values of HLPERIODn
t
and PERIOD.
no
31:4 Reserved
e
PCOUNT0
ar
tio
23:0 PCOUNT0 R/W PWM0 pulse count (value must > 0) 0x1
Only valid when PWMMODE[0] = 1.
u
31:24 Reserved
r ib
PCOUNT1
di V
st
re k-

d il

an M
n by
31:24 Reserved
tio lic
PCOUNT2
ca ub

ifi p
od de
31:24 Reserved
M a
M
PCOUNT3
31:24
PULSECOUNT0
620
CV1835

23:0 PULSECOUNT0 RO PWM0 output pulse counter status
31:24 Reserved
PULSECOUNT1
ed
31:24 Reserved
w
PULSECOUNT2
lo
al
t
no
31:24 Reserved
e
PULSECOUNT3
ar
n
tio
31:24 Reserved
u
ib
SHIFTCOUNT0
r
di V
st

re k-

d il
23:0 SHIFTCOUNT0 R/W PWM0 first pulse shift count 0x0

an M
Only valid when SHIFTMODE = 1

31:24 Reserved
n by
SHIFTCOUNT1
tio lic

ca ub

ifi p

31:24 Reserved
od de
M a
SHIFTCOUNT2
M

31:24 Reserved
SHIFTCOUNT3
621
CV1835

31:24 Reserved
SHIFTSTART
0 SHIFTSTART R/W PWM start in Phase shift mode 0x0
ed
When SHIFTMODE = 1, set this bit to 1
to simultaneously start outputting
w
PWM0~3.
31:1 Reserved
lo
al
PWM_OE
t
no
3:0 PWM_OE R/W PWM0~3 IO output enable 0xF
e
1 = output, 0 = input
ar
31:4 Reserved n
u tio
ib
12.10 Key scan

r
di V
st
re k-
d il
12.10.1 Overview
an M
n by
Keyscan supports a matrix of up to 8x8 = 64 keys. If you don't need so many keys, you
can freely decide which rows or columns to mask or keep. You can select snapshot
tio lic
mode and FIFO mode to obtain key information according to software needs.
ca ub
ifi p
12.10.2 Working Method

od de
M a
M
622
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
Figure 12- 44 Keyscan Architecture Block

tio lic
ca ub
ifi p
When the state machine (FSM) is in the rest mode (no key is pressed), all rows output 0,
od de
while col is in the input mode and the weak pull-up is turned on (the weak pull-up is set
M a
in the register mapped to IOBLK, not in the keyscan module). When any key is pressed,
M
col will see the value of not all 1 after debounce. It indicates that a key is pressed. At this
time, FSM will start a scan to let row [0] - > row [7] have only one bit output 0 at a time
(the rest are in HiZ high resistance state). Each result will be updated into an array
FSM will scan repeatedly until the col returned by all rows are all 1, indicating no key
was pressed, and then it will go to rest mode (all rows output 0)
623
CV1835
12.10.3 Basic Setting
The reg_row_mask, reg_col_mask and reg_enable in KEYSCAN0 means that when

the matrix of 8x8 is not used, some IO can be selectively deleted without output or
reference. Sine the default are all off, it neets to be turned on.
The reg_db_col in KEYSCAN_CONFIG2 determines how long debounce it takes
ed
for column input to be used.
w
The reg_slow_div in KEYSCAN_CONFIG1 determines the time of each stage in
lo
FSM of IP. Remember that this number must be larger than the debounce time.
al
Otherwise, it will be wrongly interpret the IO state before debounce completion.
t
no
The reg_wait_cntr in KEYSCAN_CONFIG3 can be used to reduce the scanning
speed. As long as the key is pressed, the keyscan module will scan continuously. This
e
ar
counter can control to wait for a certain time before starting a new round of scanning.
Which result in lower scanning frequency.
n
u tio
r ib
12.10.4 Using FIFO mode

di V
st
re k-
d il
an M
When FIFO mode is used, the 64 key values scanned by IP will be stored in the array. As
n by
long as the status of any key is different from that of the last scan, it will push the index
tio lic
of the key and the current value (0 / 1) into the FIFO. Therefore, the number in [5:0]
ca ub
specifies which key state change. [6] indicates whether it is pressed (0) or released (1).
When the FIFO is not empty, IRQ will be issued. The advantage of this mode is to offload
ifi p
od de
the software bit by bit to check which bit is changed. On the other hand, the
disadvantage is that KEY_SCAN_FIFO is a register where read will pop FIFO
M a
M
automatically. Be careful when operating it.

.
12.10.5 Using snapshot array mode
624
CV1835
When using snapshot array, the value of 64 keys currently scanned in IP will be stored in
an array. If the content of the array is not consistent with KEYSCAN_SNAPSHOT_ARRAY ,
it will send IRQ. And the software can trigger KEYSCAN_SNAPSHOT_TRIG to capture the
current array content to snapshot array, and then slowly compare what content has
changed with the previous cognition.
ed
Open the reg_irq_snapshot_change_enable in KEYSCAN_IRQ_ENABLE.
w
After receiving IRQ, read trigger KEYSCAN_SNAPSHOT_TRIG, interpret the content of
lo
KEYSCAN_SNAPSHOT_ARRAY, then clear KEY_SCAN_IRQ_CLEAR, and then finish IRQ
al
return.
t
no
e
12.10.6 Key scan Register Overview
ar
n
tio

Offset
u
ib
KEYSCAN_CONFIG0 0x000
r
di V
st
re k-
KEYSCAN_CONFIG3 0x00c
d il
an M
KEYSCAN_SNAPSHOT_ARRAY 0x014
KEYSCAN_SNAPSHOT_TRIG 0x01c
n by
KEYSCAN_FIFO_STATUS 0x020
KEYSCAN_FIFO 0x024
tio lic
KEYSCAN_IRQ_ENABLE 0x028
ca ub
KEYSCAN_IRQ_FLAG 0x02c
ifi p
KEYSCAN_IRQ_CLEAR 0x030
od de
M a
M
12.10.7 Key scan Register Description
KEYSCAN_CONFIG0
7:0 reg_row_mask R/W ROW[7:0] Mask 0xff
0 = enable
1 = disable
625
CV1835

15:8 reg_col_mask R/W COL[7:0] Mask 0xff
0 = enable
1 = disable
16 reg_enable R/W keyscan enable 0x0
0 = disable
1 = enable
31:17 Reserved
KEYSCAN_CONFIG1
ed
w
lo
23:0 reg_slow_div R/W slow divider (MUST BE BIGGER THAN 0xff
al
reg_db_col)
Each step is IP clock frequency divide by
t
reg_slow_div
no
Scan frequency = IP clock freq /
e
( (reg_slow_div+1) *
ar
(9+reg_wait_count+1))
IDLE -> ROW0 -> ROW1 -> ROW2-
n
>ROW3->ROW4->ROW5->ROW6-
tio
>ROW7->UPDATE->WAIT->IDLE
31:24 Reserved
u
ib
KEYSCAN_CONFIG2
r
di V
st

re k-

d il
15:0 reg_db_col R/W column input debounce counter (IP 0x64

an M
clock cycle)
31:16 Reserved
n by
KEYSCAN_CONFIG3
tio lic

ca ub

7:0 reg_wait_cntr R/W wait interval between each scan (unit is 0x10
ifi p
reg_slow_div count)
31:8 Reserved
od de
M a
KEYSCAN_SNAPSHOT_ARRAY
M

63:0 reg_cpu_snapshot_array RO CPU snapshot array result (0 = press, 1 =
not press)
[0] = Row 0 , Col 0
[1] = Row 0 , Col 1
…
[7] = Row 0, Col 7
[8] = Row 1, Col 0
[63] = Row 7, Col 7
[N] = Row Y, Col X (N = Y*8 + X)
626
CV1835
KEYSCAN_SNAPSHOT_TRIG
0 reg_cpu_snapshot_toggle W1T Write 1 to Trigger snapshot array to
update
When current result is different from
snapshot result, irq happen
To solve the IRQ, write 1 to trigger the
snapshot array to copy from current
ed
array and start checking which bit is
different from previous state
w
31:1 Reserved
lo
al
KEYSCAN_FIFO_STATUS
t
no
3:0 reg_fifo_count RO FIFO content count
e
0 = Empty
ar
1 = one content in FIFO
N = N content in FIFO
4 reg_fifo_not_empty RO FIFO not empty flag
n
0 = Empty
tio
1 = Not empty
31:5 Reserved
u
ib
KEYSCAN_FIFO
r
di V
st
re k-

d il
an M
6:0 reg_fifo_rdata ROC read data from FIFO (Auto POP) - check
FIFO empty-ness before read
[6] 0 = press, 1 = not-press
n by
[5:0] = index
Row = INT(index/8)
tio lic
Col = mod(index,8)
63 = Row 7 , Column 7
ca ub
13 = Row 1 , Clumne 5
31:7 Reserved
ifi p
od de
KEYSCAN_IRQ_ENABLE
M a

M

0 reg_irq_fifo_not_empty_enable R/W FIFO mode IRQ Enable 0x0
0 = Disable
1 = Enable
3:1 Reserved
4 reg_irq_snapshot_change_enable R/W Snapshot mode IRQ Enable 0x0
0 = Disable
1 = Enable
31:5 Reserved
KEYSCAN_IRQ_FLAG
627
CV1835

0 reg_irq_fifo_not_empty RO FIFO not empty IRQ flag
0 = Empty
1 = Not empty
3:1 Reserved
4 reg_irq_snapshot_change RO Snapshot change IRQ flag
0 = No change
1 = Change
ed
31:5 Reserved
w
KEYSCAN_IRQ_CLEAR
lo
al
t
0 reg_irq_fifo_not_empty_clear_w1t W1T FIFO not empty IRQ Clear (Write 1 clear)
no
3:1 Reserved
4 reg_irq_snapshot_change_clear_w1 W1T Snapshot Change IRQ Clear (Write 1
e
t clear)
ar
31:5 Reserved
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
628
CV1835
12.11 Wiegand
12.11.1 Overview
ed
w
lo
al
t
no
e
Figure 12- 45 the way wiegand signal bus transmits 0 / 1
ar
n
tio
The Wiegand interface uses two single ended signals, d0 / D1. When the bus idle both
are high, a low pulse appears on D0, indicating that a "0" is transmitted. When a low
u
ib
pulse is found on D1, it means that a "1" is transmitted.

r
di V
st
re k-
Wiegand is commonly used in access control system. There are two common formats,
d il
an M
Wiegand 26 / 34, which represent the bit number of packets respectively. The brief
n by
introduction of these two formats is as follows.

tio lic
ca ub
12.11.1.1 Wiegand 26
ifi p
od de
M a
M
Figure 12- 9 Wiegand 26 Format
629
CV1835
12.11.1.2 Wiegand 34
ed
w
lo
al
t
no
Figure 12- 47 Wiegand 34 format
e
ar
F = Facility Code n
U = User code
u tio
Some access card has a series of numbers on the back. After converting them to hex,
ib
Dec 0002262506 Hex : 22_85_EA

r
di V
st
0x22 is its Facility code (Dec = 34)

re k-
d il
0x85EA is itsuser code (Dec = 34282)

an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 12- 48 Common access card, the meaning those number
34, 34282 are facility code & user code in decimal system
PS. this IP TX RX does not handle the insertion or checking of parity. It is handled by
software.
630
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
Figure 12- 49 wiegand architecture block

od de
M a
M
The Wiegand module contains TX and Rx, which can be used for single direction or bi-
diretion used. During Transmitting, the RX will stop monitoring the bus to avoid
received the message of its own tramission. Transmitter support push pull mode or
open drain mode
631
CV1835
12.11.2.1 TX
Before Transmit, set the high time and low time of TX, and transmit sequence is MSB 1st
or LSB 1st. Then put the data in TX_BUFFER register, use TX_Trig, to start the transfer of
the data.
ed
After the transmission is complete, one can use TX_FINISH interrupt or by polling
w
TX_BUSY status to determine when can transfer another packet.
lo
al
t
no
12.11.2.2 RX
e
ar
Before received, set the debounce time and the number of bits expected to receive in a
packet. When low pulse appears in D0 D1, RX will start to push data into the temp
n
tio
buffer. When the number of received bits reaches the expected number of bits of a
packet, it will push the temp buffer to RX_ BUFFER and sent out interrupt for software
u
ib
processing, while temp buffer continues to receive the next data.

r
di V
st
re k-
If idle timeout occurs on D0 D1, even if the number of bits is not reached, it will be
d il
an M
forced to be regarded as a packet

n by
The high bit element of RX BUFFER will record the total number of bits received by this
tio lic
packet, whether it is caused by timeout or overflow before the software reads it

ca ub
ifi p
Every packet received can rely on rx_ buffer_ reciveived interrupt, or RX_ BUFFER_ VALID
od de
to determine is there any valid data in RX_BUFFER. After taking RX Data, trigger RX_
M a
BUFFER_ CLEAR to clear RX_ BUFFER to receive the next packet.

M
12.11.3 Wiegand Register Overview

Offset
TX_CONFIG0 0x000
632
CV1835

Offset
TX_CONFIG1 0x004
TX_CONFIG2 0x008
TX_BUFFER 0x00c
TX_TRIG 0x014
TX_BUSY 0x018
TX_DEBUG 0x01c
ed
RX_CONFIG0 0x020
w
RX_CONFIG1 0x024
lo
RX_CONFIG2 0x028
al
RX_BUFFER 0x02c
RX_BUFFER_VALID 0x038
t
no
RX_BUFFER_CLEAR 0x03c
RX_DEBUG 0x040
e
IRQ_ENABLE 0x044
ar
IRQ_FLAG 0x048
IRQ_CLEAR 0x04c
n
u tio
ib
12.11.4 Wiegand Register Description

r
di V
st
re k-
d il
an M
TX_CONFIG0
n by

tio lic
23:0 reg_tx_lowtime R/W TX Low width , unit = cycle 0xff

31:24 Reserved
ca ub
ifi p
TX_CONFIG1
od de

M a
23:0 reg_tx_hightime R/W TX High width , unit = cycle 0xff

M
31:24 Reserved
TX_CONFIG2
6:0 reg_tx_bitcount R/W TX Frame bit count per transmit , unit = 0x18
bit
7 Reserved
8 reg_tx_msb1st R/W TX Transmit from MSB or LSB 0x0
0 : LSB 1st , from tx_buffer[0] -->
tx_buffer[reg_tx_bitcount]
633
CV1835

1 : MSB 1st , from
tx_buffer[reg_tx_bitcount] -->
tx_buffer[0]
15:9 Reserved
16 reg_tx_opendrain R/W TX using push-pull mode or opendrain 0x0
mode
0 : push-pull mode
1 : opendrain mode
31:17 Reserved
ed
w
TX_BUFFER
lo
al
63:0 reg_tx_buffer R/W TX buffer content 0x00
t
no
TX_TRIG
e
ar
0 reg_tx_trig_w1t W1T Trigger transmittion
n
Write 1 trigger (please check
tio
reg_tx_busy before transmit)

31:1 Reserved
u
ib
TX_BUSY
r
di V
st

re k-

d il
0 reg_tx_busy RO 0 = idle, allow to trigger transmission

an M
1 = busy, do not trigger any more

tranmission or it will be ignore.
n by
31:1 Reserved
tio lic
TX_DEBUG
ca ub

ifi p
2:0 reg_tx_fsm RO TX Finite State Machine current state

od de
0 : idle
1 : wait bus idle
M a
2 : tx_start
M
3 : transmit low
4 : transmit high
5 : tx_stop
7:3 Reserved
14:8 reg_tx_pointer RO TX pointer current position
indicate how many bit is still not yet
send
31:15 Reserved
RX_CONFIG0
634
CV1835

15:0 reg_rx_debounce R/W RX input debounce time (unit is cycle) 0xff
31:16 Reserved
RX_CONFIG1
31:0 reg_idle_timeout R/W Bus timeout cycle count 0xfff
ed
When bus is idle for idle_timeout cycle,
bus is expected to be back to idle
w
If some bit has received but not yet
accumulate to rx_bitcount, it will also
lo
treat as a complete packet.
al
RX_CONFIG2
t
no
e
6:0 reg_rx_bitcount R/W RX Expected Frame bit count , unit = bit 0x18
ar
7 Reserved
8 reg_rx_msb1st R/W RX Received sequence 0x0
n
0 : LSB 1st, 1st data is put in
tio
reg_rx_buffer[0]->[1]->[2]….
1 : MSB 1st, 1st data is put in
u
reg_rx_buffer[reg_rx_bitcount]->[0]
ib
11:9 Reserved
r
12 reg_rx_enable R/W RX Enable 0x0

di V
st
0 : disable
re k-
1 : Enable
d il
31:13 Reserved
an M
RX_BUFFER
n by

tio lic

72:0 reg_rx_buffer RO RX Buffer
ca ub
[63:0] = fifo = Indicate received content

[70:64] = fifo_bit_count = How many
ifi p
effective bit is in rx_buffer[63:0]

od de
[71] = idle_reach = This RX is terminate

by bus idle timeout
M a
[72] = overflow = This RX just overwrite

M
an un-read message
95:73 Reserved
RX_BUFFER_VALID
0 reg_rx_buffer_valid RO reg_rx_buffer validness
0 : not valid
1 : valid
31:1 Reserved
635
CV1835
RX_BUFFER_CLEAR
0 reg_rx_buffer_clear_w1t W1T reg_rx_buffer clear (write 1 clear)
31:1 Reserved
RX_DEBUG
ed
w
0 reg_businidle RO bus in idle indication
lo
0 : bus is not in idle
1 : bus is in idle more than
al
reg_rx_idle_timeout cycle
31:1 Reserved
t
no
IRQ_ENABLE
e
ar
0 reg_irq_tx_finish_enable R/W TX Finish IRQ Enable (to inform all data 0x0
n
has being transmit, ready for next)
tio
0 : Disable
1 : Enable
u
3:1 Reserved
ib
4 reg_irq_rx_overflow_enable R/W RX Overflow IRQ Enable 0x0

r
di V
0 : Disable
st
re k-
1 : Enable
7:5 Reserved
d il
an M
8 reg_irq_rx_received_enable R/W RX Received IRQ Enable 0x0

0 : Disable
1 : Enable
n by
31:9 Reserved
tio lic
IRQ_FLAG
ca ub

ifi p

0 reg_irq_tx_finish RO TX Finish IRQ Flag
od de
0 : no IRQ
1 : IRQ (one tranmission has being
M a
completed)
M
3:1 Reserved
4 reg_irq_rx_overflow RO RX overflow IRQ Flag
0 : no IRQ
1 : IRQ (rx buffer is not pop and new
data has overwrited)
7:5 Reserved
8 reg_irq_rx_received RO RX received IRQ Flag
0 : no IRQ
1 : RX buffer has new data
31:9 Reserved
636
CV1835
IRQ_CLEAR
0 reg_irq_tx_finish_clear_w1t W1T TX Finish IRQ Clear , Write 1 to clear
reg_irq_tx_finish flag
3:1 Reserved
4 reg_irq_rx_overflow_clear_w1t W1T RX Overflow IRQ Clear . Write 1 to clear
reg_irq_rx_overflow flag
7:5 Reserved
ed
8 reg_irq_rx_received_clear_w1t W1T RX Received IRQ Clear . Write 1 to clear
w
reg_irq_rx_received flag
31:9 Reserved
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
637
CV1835
12.12 IRRX Infrared Interface
12.12.1 Overview
Receive external infrared data through IRRX Unit.
ed
w
1. Support NEC encoding mode (including repeat code).
lo
2. Support Philips RC5/RC6 encoding mode.
al
3. Support Sony encoding mode.
t
4. Support infrared wake-up function.
no
e
ar
12.12.3 Working Mode n
u tio
r ib
di V
st
re k-
The software predefines the format of the received infrared data. When the IRRX module
d il
an M
receives the infrared signal, it decodes it, and the encoded data that conforms to the
predefined format is transmitted to the CPU via an interrupt. The CPU then performs
n by
corresponding operations based on the encoding.

tio lic
12.12.4 IRRX Register Overview

ca ub
ifi p

od de
Offset
M a
IR_EN 0x000
M
IR_MODE 0x004
IR_CFG 0x008
IR_FRAME 0x00c
int_en 0x010
int_clr 0x014
int_msk 0x018
int 0x01c
638
CV1835

Offset
int_raw 0x020
IR_SYMBOL_CFG0 0x030
ed
IR_SYMBOL_CFG3 0x03c
w
lo
al
t
no
IR_SYMBOL_CFG7 0x04c
IR_CLOCK_CTRL 0x050
e
ar
IR_DATA0 0x080
IR_DATA1 0x084
n
tio
IR_DATA2 0x088
u
IR_DATA3 0x08c
ib
IR_DATA4 0x090
r
di V
st
IR_NEC_DATA0 0x0a8
re k-
IR_SONY_DATA0 0x0ac
d il
an M
IR_SONY_DATA1 0x0b0
n by
IR_PHILIPS_DATA0 0x0b4
IR_PHILIPS_DATA1 0x0b8
tio lic
IR_PRD_REC0 0x0e0
ca ub
IR_PRD_REC1 0x0e4
ifi p
IR_PRD_REC2 0x0e8
od de
IR_PRD_REC3 0x0ec
M a
M
IR_PRD_REC4 0x0f0
IR_PRD_REC5 0x0f4
SPARE_0 0xff0
SPARE_1 0xff4
SPARE_RO 0xff8
DATA_CODE 0xffc
639
CV1835
12.12.5 IRRX Register Description
0 reg_ir_rx_en R/W ir receiver enable 0x0
ed
1 reg_ir_rx_rst R/W ir receiver reset 0x0
w
15:2 Reserved
lo
al
16 reg_ir_init_done RO ir receiver ready
31:17 Reserved
t
no
IR_MODE
e
ar
Bits Name Access n Description Reset
1:0 reg_ir_mode R/W ir receiver mode 0x0

tio
0x0: pulse distance coding

u
0x2: bi-phase coding, RC5

ib
0x3: bi-phase coding, RC6

r
di V
st
7:2 Reserved
re k-
8 reg_periodic_mode R/W periodic sample mode 0x0

d il
an M
0x1: periodic sample, reg_ic_mode

n by
is ignored
31:9 Reserved
tio lic
IR_CFG
ca ub

ifi p

od de
7:0 reg_tick_prd R/W tick period 0x18

M a
11:8 reg_sample_prd R/W sample period 0x9

M
14:12 reg_debounce R/W input signal debounce control 0x4
15 Reserved
16 reg_import_inv R/W input signal polarity control 0x1
17 reg_export_inv R/W output data polarity control 0x0
18 reg_sony_format R/W tx transmit stop burst at frame end 0x0

0x1: SONY formate
0x0: NEC formate
640
CV1835
19 reg_repeat_support R/W support simplfied repeat code 0x1
20 reg_bit_edge_sel R/W data bit selection used in pulse 0x0

distance coding
0x1: SONY formate
0x0: NEC formate
ed
31:21 Reserved
w
IR_FRAME
lo
al
t
no
7:0 reg_length R/W ir receiver data length 0x20
8 reg_slength R/W ir receiver repeate code length 0x0
e
0x1: TC9012
ar 0x0: others
n
15:9 Reserved
tio
18:16 reg_lead_p_ratio R/W ratio of leading symbol period and 0x4

u
ib
strobe period, used in periodic

r
sample mode
di V
st
re k-
31:19 Reserved
d il
int_en
an M

n by

tio lic
0 reg_rx_done_int_en R/W rx_done interrupt enable 0x1

ca ub
1 reg_frame_err_int_en R/W frame_err interrupt enable 0x1

ifi p
2 reg_frame_ovf_int_en R/W frame_ovf interrupt enable 0x1

od de
3 reg_release_int_en R/W release interrupt enable 0x1

M a
4 reg_repeat_int_en R/W repeat interrupt enable 0x1

M
31:5 Reserved
int_clr
0 reg_rx_done_int_clr W1T rx_done interrupt clear
1 reg_frame_err_int_clr W1T frame_err interrupt clear
2 reg_frame_ovf_int_clr W1T frame_ovf interrupt clear
641
CV1835
3 reg_release_int_clr W1T release interrupt clear
4 reg_repeat_int_clr W1T repeat interrupt clear
31:5 Reserved
int_msk
ed
w
0 reg_rx_done_int_msk R/W rx_done interrupt mask 0x0
lo
1 reg_frame_err_int_msk R/W frame_err interrupt mask 0x0
al
2 reg_frame_ovf_int_msk R/W frame_ovf interrupt mask 0x0
t
no
3 reg_release_int_msk R/W release interrupt mask 0x0
4 reg_repeat_int_msk R/W repeat interrupt mask 0x0
e
ar
31:5 Reserved
int
n
tio

u
ib
0 reg_rx_done_int RO rx_done interrpt

r
di V
st
1 reg_frame_err_int RO frame_err interrpt

re k-
2 reg_frame_ovf_int RO frame_ovf interrpt

d il
an M
3 reg_release_int RO release interrpt
4 reg_repeat_int RO repeat interrpt

n by
31:5 Reserved
tio lic
int_raw
ca ub

ifi p

od de
0 reg_rx_done_int_raw RO rx_done interrupt raw value

M a
1 reg_frame_err_int_raw RO frame_err interrupt raw value

M
2 reg_frame_ovf_int_raw RO frame_ovf interrupt raw value
3 reg_release_int_raw RO release interrupt raw value
4 reg_repeat_int_raw RO repeat interrupt raw value
31:5 Reserved
IR_SYMBOL_CFG0
642
CV1835
11:0 reg_ir_rx_lead_p R/W lead symbol postive interval 0x383
15:12 Reserved
23:16 reg_ir_rx_lead_p_tol R/W lead symbol postive interval 0x48

tolerance
reg_ir_rx_lead_p +
ed
reg_ir_rx_lead_p_tol <= 12'FFF
w
reg_ir_rx_lead_p -
lo
reg_ir_rx_lead_p_tol >= 12'000
al
31:24 Reserved
t
IR_SYMBOL_CFG1
no
e
11:0 reg_ir_rx_lead_n R/W

ar
lead symbol negtive interval 0x1c1
n
15:12 Reserved
tio
23:16 reg_ir_rx_lead_n_tol R/W lead symbol negtive interval 0x24

u
ib
tolerance
r
reg_ir_rx_lead_n +
di V
st
re k-
reg_ir_rx_lead_n_tol <= 12'FFF

d il
reg_ir_rx_lead_n -
an M
reg_ir_rx_lead_n_tol >= 12'000

n by
31:24 Reserved
tio lic
IR_SYMBOL_CFG2
ca ub

ifi p
7:0 reg_ir_rx_stop R/W stop symbol postive interval 0x37

od de
11:8 reg_ir_rx_stop_tol R/W stop symbol postive interval 0x3

M a
M
tolerance
reg_ir_rx_stop + reg_ir_rx_stop_tol
<= 8'FF
reg_ir_rx_stop -
reg_ir_rx_stop_tol >= 8'00
15:12 Reserved
23:16 reg_ir_rx_bit_p R/W data symbol postive interval 0x37
31:24 reg_ir_rx_bit_p_tol R/W data symbol postive interval 0x3
643
CV1835
tolerance
reg_ir_rx_bit_p +
reg_ir_rx_bit_p_tol <= 8'FF
reg_ir_rx_bit_p -
reg_ir_rx_bit_p_tol >= 8'00
ed
IR_SYMBOL_CFG3
w
lo
al
11:0 reg_ir_rx_bit_one R/W data one totol interval 0xe0
t
15:12 Reserved
no
23:16 reg_ir_rx_bit_one_tol R/W data one total interval tolerance 0x18
e
reg_ir_rx_bit_one +
ar
reg_ir_rx_bit_one_tol <= 12'FFF
n
reg_ir_rx_bit_one -
tio
reg_ir_rx_bit_one_tol >= 12'000

u
ib
31:24 Reserved
r
IR_SYMBOL_CFG4
di V
st
re k-

d il

an M
11:0 reg_ir_rx_bit_zero R/W data zero totol interval 0x6f

n by
15:12 Reserved
tio lic
23:16 reg_ir_rx_bit_zero_tol R/W data zero total interval tolerance 0x09

ca ub
reg_ir_rx_bit_zero +
reg_ir_rx_bit_zero_tol <= 12'FFF
ifi p
reg_ir_rx_bit_zero -
od de
reg_ir_rx_bit_zero_tol >= 12'000

M a
M
31:24 Reserved
IR_SYMBOL_CFG5
15:0 reg_ir_rx_release_time R/W time for wait repeat code, >108ms. 0x27de
31:16 Reserved
IR_SYMBOL_CFG6
644
CV1835
11:0 reg_ir_rx_slead_p R/W repeate code lead symbol postive 0x383

interval
15:12 Reserved
23:16 reg_ir_rx_slead_p_tol R/W repeate code lead symbol postive 0x48

interval tolerance
ed
reg_ir_rx_slead_p +
w
reg_ir_rx_slead_p_tol <= 12'FFF
lo
reg_ir_rx_slead_p -
al
reg_ir_rx_slead_p_tol >= 12'000
t
31:24 Reserved
no
IR_SYMBOL_CFG7
e
ar
Bits Name Access n Description Reset
11:0 reg_ir_rx_slead_n R/W repeate code lead symbol negtive 0x1c1

tio
interval
u
ib
15:12 Reserved
r
23:16 reg_ir_rx_slead_n_tol R/W repeate code lead symbol negtive 0x24

di V
st
re k-
interval tolerance
d il
reg_ir_rx_slead_n +
an M
reg_ir_rx_slead_n_tol <= 12'FFF

n by
reg_ir_rx_slead_n -
tio lic
reg_ir_rx_slead_n_tol >= 12'000

ca ub
31:24 Reserved
IR_CLOCK_CTRL
ifi p

od de

M a
M
0 reg_pclock_auto_ctrl R/W pclk auto-gating control 0x0
1 reg_lpclock_switch_en R/W ip clock could be switch to 32KHz 0x0
7:2 Reserved
8 reg_skip_lead_p R/W skip lead pulse check 0x0
31:9 Reserved
IR_DATA0
645
CV1835
31:0 reg_ir_rx_data0 RO recevier data[31:0]
IR_DATA1
ed
IR_DATA2
w
lo
al
t
IR_DATA3
no
e
31:0 reg_ir_rx_data3 RO
ar
recevier data[127:96]
n
IR_DATA4
tio

u
ib

r

di V
st
re k-
IR_NEC_DATA0
d il

an M

n by
31:0 reg_ir_rx_nec_32bit RO receiver data, nec format

tio lic
IR_SONY_DATA0
ca ub

ifi p
11:0 reg_ir_rx_sony_12bit RO receiver data, sony D7C5 format

od de
15:12 Reserved
M a
M
31 Reserved
IR_SONY_DATA1
31:20 Reserved
IR_PHILIPS_DATA0
646
CV1835
11:0 reg_ir_rx_philips_rc5 RO receiver data, RC5 format
31:12 Reserved
IR_PHILIPS_DATA1
ed
w
19:0 reg_ir_rx_philips_rc6 RO receiver data, RC6 format
lo
31:20 Reserved
al
IR_PRD_REC0
t
no
e
11:0 reg_start_p0_min RO start phase0 minimul width
ar
15:12 Reserved n
27:16 reg_start_p0_max RO start phase0 maximul width
tio
31:28 Reserved
u
ib
IR_PRD_REC1
r

di V
st
re k-

d il
11:0 reg_start_p1_min RO start phase1 minimul width

an M
15:12 Reserved
n by
27:16 reg_start_p1_max RO start phase1 maximul width

tio lic
31:28 Reserved
ca ub
IR_PRD_REC2
ifi p
od de
11:0 reg_bit_p0_min RO bit phase0 minimul width

M a
M
15:12 Reserved
27:16 reg_bit_p0_max RO bit phase0 maximul width
31:28 Reserved
IR_PRD_REC3
11:0 reg_bit_p1_min RO bit phase1 minimul width
15:12 Reserved
647
CV1835
27:16 reg_bit_p1_max RO bit phase1 maximul width
31:28 Reserved
IR_PRD_REC4
ed
11:0 reg_end_min RO end phase minimuml width
w
15:12 Reserved
lo
27:16 reg_end_max RO end phase maximuml width
al
31:28 Reserved
t
no
IR_PRD_REC5
e
15:0 reg_frame_min RO
ar
frame minimul width
n
tio
31:16 reg_frame_max RO frame maximul width
SPARE_0
u
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
648
CV1835
Security Subsystem Module
The chip provides independent security subsystem module which is responsible

for providing specific security function.
ed
w
The security subsystem module includes the following security function modules:
lo
Crypto DMA
al
Secure Debug Protection
t
no
Crypto DMA provides hardware acceleration of symmetric key encryption,
e
decryption and hardware acceleration of Hash. Secure eFuse unit is responsible
ar
for providing system security settings and secure keys for security subsystem.
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
Figure 13- 1 Security Subsystem Module

M a
M
13.1CryptoDMA
13.1.1 Overview
CryptoDMA is a hardware accelerator for symmetric key algorithm, HASH

algorithm and BASE64 conversion. It supports symmetric algorithm: AES 128 /
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CV1835
192 / 256, DES / TDES, SM4 and HASH algorithm: SHA-1 / SHA256. Through the
instruction string of linked list, the function of key encryption and decryption or
hash operation of data block can be directly accessed in memory.
The symmetric algorithm is suitable for hardware encryption and
decryption of data, and supports a variety of block encryption and block
series processing methods, including ECB, CBC and CTR.
ed
The implementation of AES (Advanced Encryption Standard) algorithm
w
conforms to FIPS 197 standard. The implementation of DES (data
lo
encryption standard) / TDES algorithm conforms to ISO / IEC 18033-3.
al
Hash algorithm is suitable for data integrity checking and digital
t
no
signature operation acceleration. SHA1 and SHA256 meet FIPS180-2
standard.
e
13.1.2 Function Characteristics
ar
n
tio
The CryptoDMA module has the following features:

u
Support symmetric encryption and decryption algorithm AES and block

r ib
encryption mode ECB / CBC / CTR. The key length supports 128 bits and 256 bits,
di V
st
re k-
and the key can be configured by secure operating system or linked list
d il
instruction.
an M
Support symmetric encryption and decryption algorithm SM4 and block

n by
encryption mode ECB / CBC / CTR.

tio lic
Support symmetric encryption and decryption algorithm DES / TDES and block
ca ub
encryption mode ECB / CBC / CTR.

ifi p
Support hash algorithms SHA1 and SHA256.

od de
Support CPU configuration to input PIO data and DMA mode to read active
M a
table instruction input data.

M
Support circular linked list structure, support splicing multiple linked list data.
Provide interrupt status query, interrupt mask and interrupt clear function.
13.1.3 DMA Function Description
CryptoDMA provides DMA function of direct memory access. The application

program only needs to provide the linked list instruction to the target data block
to start the CryptoDMA function until it receives the interrupt notification to
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CV1835
complete the block encryption and decryption or hash operation, and output
the operation result to the target address.
13.1.4 Function description of symmetric key algorithm block
encryption mode
ed
w
Symmetric key algorithm AES / DES / SM4 all support ECC / CBC / CTR block
lo
encryption mode.
al
t
13.1.4.1 ECB Mode
no
e
In ECB (Electronic CodeBook) mode, encryption and decryption algorithms are
ar
directly applied to each packet data by the operation of each packet. This feature
n
enables plaintext encryption and ciphertext decryption to be carried out
tio
independently by any group of block data.

u
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
Figure 13- 2 ECB Mode
13.1.4.2 CBC Mode
CBC（Cipher Block Chaining）performs XOR operation between input plaintext

group and input vector IV(Intialization Vector) or ciphertext result of previous
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CV1835
group before encryption operation. Encryption operation in CBC mode must

start from the first block data group, and ciphertext obtained from previous
group is required for subsequent encryption operation. During decryption, the
plaintext can be obtained after decryption of the current ciphertext and XOR
operation of the previous ciphertext.
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
Figure 13- 3 CBC Mode

tio lic
13.1.4.3 CTR Mode

ca ub
ifi p
CTR（Counter）is the use of encryption or decryption of a group of different sequences

od de
to ensure the independence and security of encrypted data processing. Generally, the
M a
XOR operation is carried out between encrypted accumulated sequence and plaintext.
M
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CV1835
ed
w
lo
al
t
no
e
ar
n
Figure 13- 4 CTR Mode
u tio
r ib
di V
st
re k-
13.1.5 CryptoDMA Register Overview

d il
an M
n by

Offset
tio lic
dma_ctrl 0x000 DMA controll register

ca ub
int_mask 0x004 interrupt mask

des_base_0 0x008 descriptor base low address
ifi p
des_base_1 0x00c descriptor base high address

spacc_int_raw 0x010 interrupt
od de
secure_key_valid 0x014 key valid

des_addr_0 0x018 current descirptor low address
M a
des_addr_1 0x01c current descirptor high address

M
PIO_cmd_data_0 0x080 PIO command0

PIO_cmd_data_3 0x08c PIO command3
PIO_cmd_data_7 0x09c PIO command7
PIO_cmd_data_8 0x0a0 PIO command8
PIO_cmd_data_11 0x0ac PIO command11
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Offset
PIO_cmd_data_12 0x0b0 PIO command12
PIO_cmd_data_15 0x0bc PIO command15
PIO_cmd_data_16 0x0c0 PIO command16
PIO_cmd_data_19 0x0cc PIO command19
ed
PIO_cmd_data_20 0x0d0 PIO command20
PIO_cmd_data_21 0x0d4 PIO command21
w
key_data_0 0x100 cipher key data 0
lo
al
key_data_3 0x10c cipher key data 3
t
no
e
ar
key_data_9 0x124 cipher key data 9 n
tio
u

ib

r
di V
st

re k-

d il
an M

n by

tio lic
ini_data_0 0x180 initial vector data 0

ca ub

ini_data_3 0x18c initial vector data 3
ifi p

od de

M a
ini_data_7 0x19c initial vector data 7

M
ini_data_8 0x1a0 initial vector data 8

ini_data_11 0x1ac initial vector data 11
sha_data_0 0x1c0 SHA paramenter0
sha_data_3 0x1cc SHA paramenter3
sha_data_4 0x1d0 SHA paramenter4
sha_data_7 0x1dc SHA paramenter7
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13.1.6 CryptoDMA Register Overview
(基址 0x02060000)
ed
dma_ctrl
dma_ctrl
w
lo
al
0 dma_en R/W DMA Channel Enable Control 0x0
t
0：Channel Forbidden；
no
1：Channel Enable
1 decriptor_mode R/W Channel Command Mode 0x0
e
0: PIO Mode
ar
1:Description Key List Mode
15:2 Reserved
n
23:16 max_read_burst R/W Maximum Read Burst Value 0x0
tio
31:24 max_write_burs R/W Maximum Write Burst Value 0x0

u
int_mask
r ib
int_mask
di V
st
re k-

d il
an M
0 int_enc_mask R/W Encryption and decryption interrupt 0x0

masking
1 int_hash_mask R/W Hash interrupt masking 0x0
n by
31:2 Reserved Reserved

tio lic
des_base_0
ca ub
des_base_0
ifi p

od de

31:0 des_base_0 R/W Description key table address_ Low 0x0
M a
address
M
des_base_1
des_base_1
31:0 des_base_1 R/W Description key table address_ High 0x0
address
spacc_int_raw
spacc_int_raw
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CV1835

31:0 spacc_int_raw R/W DMA Interrupted 0x0
secure_key_valid
secure_key_valid
ed
31:0 secure_key_valid R/W Key Valid Value 0x0
One-Way: Enabled
w
lo
des_addr_0
al
des_addr_0
t
no
31:0 des_addr_0 R/W Description key table address offset_ 0x0
e
Low address
des_addr_1
ar
n
tio
des_addr_1
u

ib
31:0 des_addr_1 R/W Description key table address offset_ 0x0

r
di V
High address
st
re k-
PIO_cmd_data_0
d il
an M
PIO mode descriptor

n by

0 PIO_cmd_data_0 R/W PIO mode description key table, 0x0
tio lic
0：invalid schema description key table

ca ub
1：valid schema description key table

1 PIO_cmd_data_0_1 R/W Last descriptor of description key table 0x0
ifi p
2 PIO_cmd_data_0_2 R/W PIO mode interrupt enable 0x0

od de
0：interrupt and disable；

M a
1：Interrupt and enable

M
3 PIO_cmd_data_0_3 R/W Connection description key table 0x0

address selection
0: Use the continuation address of the
current address
1: Use the connection address register
value
7:4 PIO_cmd_data_0_4 R/W Reserved 0x0
8 PIO_cmd_data_0_8 R/W DMA use bypass 0x0
9 PIO_cmd_data_0_9 R/W Encryption and decryption using AES 0x0
10 PIO_cmd_data_0_10 R/W Encryption and decryption usingDES 0x0
11 PIO_cmd_data_0_11 R/W Reserved 0x0
12 PIO_cmd_data_0_12 R/W Encryption and decryption usingSHA 0x0
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CV1835

13 PIO_cmd_data_0_13 R/W Reserved 0x0
15:14 Reserved
19:16 PIO_cmd_data_0_16 R/W Operation Key Selection 0x0
AES / DES / SM4 is used:
1: Descriptor Key
2:Key2
4:Key1
8: Millan 0
Using sha
ed
1: Descriptors
2:Reserved
w
4:Reserved
lo
8: Using SHA parameter register
The rest areReserved
al
23:20 PIO_cmd_data_0_20 R/W First operation IV selection 0x0
t
AES / DES / SM4 is used
no
1: Descriptor IV
2:IV2
4:IV1
e
8:IV0
ar
26:24 PIO_cmd_data_0_24 R/W Continued Operation IV Selection 0x0
AES / DES / SM4 is used
n
1: Descriptor IV
tio
2:IV2
4:IV1
u
8:IV0
ib
27 PIO_cmd_data_0_27 R/W Key selection enabling 0x0

r

di V
st
re k-
PIO_cmd_data_1
d il
an M
PIO mode descriptor

n by

0 PIO_cmd_data_1_0 R/W Select 1-encryption/0-decription for 0x0
tio lic
encryption and decryption

Select 1-need parameter / 0-no need for
ca ub
hash parameter
1 PIO_cmd_data_1_1 R/W CBC Mode 0-ECB/1-CBC 0x0
ifi p
2 PIO_cmd_data_1_2 R/W CTR Mode 1-CTR 0x0

od de
5:3 PIO_cmd_data_1_3 R/W Key Mode 100-128bit/010-192bit/001- 0x0

256bit for aes 0-DES/1-TDES
M a
sha mode 0-SHA1/1-SHA256

M
PIO_cmd_data_2
PIO mode descriptor
31:0 PIO_cmd_data_2 R/W Reserved 0x0
PIO_cmd_data_3
PIO mode descriptor
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CV1835

31:0 PIO_cmd_data_3 R/W Continuous descriptor address_ Low 0x0
address
PIO_cmd_data_4
PIO mode descriptor
ed
31:0 PIO_cmd_data_4 R/W Continuous descriptor address_High 0x0
w
address
lo
al
PIO_cmd_data_5
PIO mode descriptor
t
no
e
31:0 PIO_cmd_data_5 R/W DMA source address_ Low address 0x0
PIO_cmd_data_6
ar
n
tio
PIO mode descriptor
u

ib
31:0 PIO_cmd_data_6 R/W DMA source address_ High address 0x0

r
di V
st
re k-
PIO_cmd_data_7
d il
PIO mode descriptor

an M

n by
31:0 PIO_cmd_data_7 R/W DMA target address_ Low address 0x0

tio lic
PIO_cmd_data_8
ca ub
PIO mode descriptor

ifi p

od de
31:0 PIO_cmd_data_8 R/W DMA target address_ High address 0x0

M a
M
PIO_cmd_data_9
PIO mode descriptor
31:0 PIO_cmd_data_9 R/W SHA Information size 0x0
PIO_cmd_data_10
PIO mode descriptor
658
CV1835

PIO_cmd_data_11
PIO mode descriptor
31:0 PIO_cmd_data_11 R/W BASE64 Target Information size 0x0
ed
PIO_cmd_data_12
w
PIO mode descriptor
lo
al
t
no
PIO_cmd_data_13
e
PIO mode descriptor
ar
Offset Address: 0x0b4 n
tio

u
PIO_cmd_data_14
ib
PIO mode descriptor

r
di V
st

re k-

d il

an M
PIO_cmd_data_15
n by
PIO mode descriptor

tio lic

ca ub

ifi p
PIO_cmd_data_16
od de
PIO mode descriptor

M a
M

PIO_cmd_data_17
PIO mode descriptor
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CV1835
PIO_cmd_data_18
PIO mode descriptor
PIO_cmd_data_19
PIO mode descriptor
ed
w
lo
al
PIO_cmd_data_20
t
no
PIO mode descriptor
e
ar
n
PIO_cmd_data_21
tio
PIO mode descriptor

u

ib

r
di V

st
re k-
key_data_0
d il
an M
3key
n by

31:0 key_data_0 RO Key
tio lic
ca ub
key_data_1
ifi p
key
od de

M a

M
key_data_2
key
key_data_3
key
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CV1835

key_data_4
key
ed
w
key_data_5
lo
al
key
t
no
e
ar
key_data_6
key
n
tio
u

r ib
di V
key_data_7
st
re k-
key
d il

an M

n by
key_data_8
tio lic
key
ca ub

ifi p

od de

M a
key_data_9
M
key
key_data_10
key
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CV1835

key_data_11
key
ed
key_data_12
w
lo
key
al
t
no
key_data_13
e
ar
key
n
tio
u
ib
key_data_14
r
di V
st
key
re k-

d il

an M

n by
key_data_15
tio lic
key
ca ub

ifi p

od de
key_data_16
M a
M
key
key_data_17
key
662
CV1835
key_data_18
key
key_data_19
ed
key
w
lo
al
key_data_20
t
no
key
e
ar
31:0 key_data_20 RO Key n
tio
key_data_21
key
u
ib

r

di V
st

re k-
d il
key_data_22
an M
key
n by

tio lic

ca ub
key_data_23
ifi p
key
od de

M a

M
ini_data_0
3iv
31:0 ini_data_0 RO Initial parameters
ini_data_1
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CV1835
iv
ini_data_2
iv
ed
w
lo
ini_data_3
al
iv
t
no
e
ini_data_4
ar
n
tio
iv
u

ib

r
di V
st
re k-
ini_data_5
d il
iv
an M

n by

tio lic
ini_data_6
ca ub
iv
ifi p

od de

M a
M
ini_data_7
iv
ini_data_8
iv
664
CV1835

31:2 Reserved
ini_data_9
iv
ed
w
31:2 Reserved
lo
ini_data_10
al
iv
t
no
e
ini_data_11
ar
n
iv
tio

u

ib

r
di V
st
re k-
sha_data_0
d il
sha parameter
an M

n by
31:0 sha_data_0 RO SHA Parameters

tio lic
sha_data_1
ca ub
sha parameter
ifi p

od de

M a
M
sha_data_2
sha parameter
sha_data_3
sha parameter
665
CV1835

sha_data_4
sha parameter
ed
sha_data_5
w
lo
sha parameter
al
t
no
sha_data_6
e
ar
sha parameter
n
tio
u
ib
sha_data_7
r
di V
st
sha parameter
re k-

d il

an M

n by
tio lic
ca ub
13.2Secure Debug Firewall

ifi p
od de
In order to read or control the internal functions of the chip during debugging or
M a
testing, the chip provides several debugging interfaces, such as JTAG, I2C and
M
other external interfaces. Without proper protection mechanism, these

interfaces can easily be used to attack chip security mechanism or read internal
confidential information directly or indirectly. In order to protect and control
these interfaces, the chip adopts a secure debugging firewall.
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CV1835
13.2.1 Overview
The chip supports three main debugging interfaces:

1. RISCV JTAG: RISCV processors have a built-in debug interface that allows
users to access internal registers through the JTAG interface.
2. I2C: The chip provides debug interface
ed
3. Test interface: The chip provides special debugging interface for
w
production test
lo
al
For JTAG/I2C interfaces, a secure debugging firewall provides specific protection
t
no
controls for their access.
e
ar
For the Test Interface, a secure debugging interface provides a separate class of
protection controls for its access (Test Access).
n
tio
For these debugging categories, the secure debugging firewall provides three
u
ib
connection control states:

r
di V
st
Open: allow external access without additional control

re k-
Protected: no external connection is allowed until the corresponding

d il
an M
password is input through I2C interface

n by
Closed: no external connection is allowed through this interface, and it

cannot be opened again by other methods.
tio lic
ca ub
ifi p
od de
13.2.2 Status Inquiry and Password Input Interface (I2C)

M a
M
The secure debug firewall provides an independent I2C interface for the external
chip to check the current status of the debug interface through I2C and input the
corresponding password to restart the protected interface. External users need
to specify the I2C ID of the main blockhouse to connect to the firewall interface.
The I2C interface register address is as follows:
667
CV1835
Table 13- 1 Status Query I2C Interface Register Address

byte bitwidth signal name description
address
0 32 i2c_REE_password [31:0] 128-bit debug interface password
C 32 i2c_REE_password [127:96] 128-bit debug interface password
10 32 Reserved Reserved
ed
w
1C 32 Reserved Reserved
lo
al
2C 32 Reserved Reserved
t
30 32 i2c_TST_password [31:0] 128-bit password entry field for test ports
no
34 32 i2c_TST_password [63:32] 128-bit test debug interface password
38 32 i2c_TST_password [95:64] 128-bit test debug interface password
e
3C 32 i2c_TST_password [127:96] 128-bit test debug interface password
ar
40 1 REE_PW_update Update the password compare result
n
tio
4C 1 TST_PW_update Update the compare result of test interface password
u
80 32 Chip_UID0 (LSB of ID) Chip identification number (Device ID)

ib
84 32 Chip_UID1 (MSB of ID) Chip identification number (Device ID)

88 32 MKTSEG Market segmentation number
r
di V
st
8C 32 DBG_MODE The status of the chip debugging interface protection

re k-
settings
[1:0] : Interface protection mode，
d il
an M
0:open;1:protected:2/3:closed
[3:2] : Reserved
[5:4] : Reserved
n by
[7:6] : test interface protection mode，

0:open;1:protected:2/3:closed
tio lic
[8]: Use HASH to make comparison

ca ub
90 32 reserved Reserved
94 4 DBG_PROT_STATUS The current debug protection status
ifi p
[0]: the interface ptotection status，0:open 1:closed

od de
[1]: Reserved
[2]: Reserved
M a
[3]::the test interface ptotection status，0:open 1:closed

M
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CV1835
13.2.3 Status Inquiry and Password Input Process
13.2.3.1 Status Inquiry Process
(step 1) control external I2C to send start signal
ed
(step 2) I2C sends firewall I2C ID (default 0x56)
(step 3) the I2C reads the address 0x04001A94 to obtain the current protection
w
lo
status of the debugging interface
al
t
no
13.2.3.2 Password Input Process
e
(step 1) control external I2C to send start signal
ar
(step 2) I2C sends the I2C ID of the debugging interface firewall (default: 0x56)
n
tio
(step 3) I2C reads the address of 0x04001A80 / 0x04001A84 to get the Device ID,
and reads the address of 0x04001A88 to get the market distinguishing number
u
ib
(step 4) prepare the unlocking password corresponding to each category

r
di V
st
through the equipment serial number and market distinguishing number

re k-
(step 5) I2C reads the address 0x94 to get the current protection status of the
d il
an M
debugging interface, and the blockhouse confirms whether it is locked or not

(step 6) take the non secure debug interface as an example, write the non secure
n by
password to the address of 0x04001A00 / 0x04001A04 / 0x04001A08 /

tio lic
0x04001A0c by I2C
ca ub
(step 7) I2C writes any value to the address 0x04001A10 and updates the
ifi p
password comparison value

od de
(step 5) I2C reads the address 0x94 to get the current protection status of the
M a
debugging interface, and confirms whether it is unlock

M
13.3Efuse Controller
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CV1835
13.3.1 Overview
4Kbit eFuse space is integrated in the chip, and eFuse is programmed and read
by eFuse Ctrl.
The main functions of eFuse Ctrl include：
A double bit protection mechanism is provided, which consists of two entity
ed
eFuse bits to form a single bit logical effective value. It is equivalent to providing
w
2Kbit memory space to improve the robustness of eFuse burning or data
lo
maintenance
al
t
no
After power-on-reset, the eFuse content is automatically loaded into the register
to provide the configuration settings required by the chip system, reduce the
e
ar
number of reading eFuse and improve the service life
n
tio
Provide eFuse programming, read, verify read and power on / off instructions
and content security protection mechanism.
u
r ib
di V
st
The eFuse data register is divided into two areas, one is a non secure area, and
re k-
the other is a secure area. The data in the non secure area is accessible to all
d il
an M
modules, while the secure area is accessible only to the secure module. The non
n by
secure area stores system configuration and public information, and the secure
area stores security configuration, key and password.
tio lic
ca ub
ifi p
od de
M a
M
670
CV1835
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
Figure 13- 5 eFuse CTRL Module architecture

M a
M
13.3.2 Efuse entity address translation and virtual register
address
The eFuse entity module consists of 128 lines, each line is 32bit. When reading
the entity eFuse data, one line (32bit) can be read each time. When burning, one
671
CV1835
bit can be burned each time. When reading or burning, the operation area
should be specified through the 12bit entity address interface.
The arrangement is as follows:
Fuse physical address [11:0]: {bit address [11:7], row address [6:0]}
ed
The double bit protection bar combines two adjacent different lines of entity
w
data into one line of logical data, which is automatically loaded into the register
lo
after startup. The 4KB entity space is merged into a 64 line 32bit logical space.
al
The system uses the logical space to provide corresponding functions except for
t
no
the entity address used in eFuse programming data process.
e
ar
The corresponding entity address is
Fuse physical address [11:0]: {logical address [11:7], logical row address [5:0],
n
tio
double address}
u
ib
The double bit address is 0 or 1.

r
di V
st
re k-
d il
an M
n by
Figure 13- 2 eFuse entity (row) address and logical (row) address corresponding
value
tio lic
ca ub
Logical row Macro unit

address entity row
ifi p
address
0 0 FTSN0 Production serial number
od de
1 FTSN0 Production serial number

M a
M

672
CV1835

address entity row
address
5 10 Market Segment Market Segment number
11 Market Segment Market Segment number
6 12 Analog0 Analog module calibration
13 Analog0 Analog module calibration
ed
w
lo
al
t
no
10 20 Bonding0 Configuration bonding settings
e
ar
21 Bonding0 Configuration bonding settings
11 22 SW_reserved SoftwareReserved
n
tio
23 SW_reserved SoftwareReserved
u
ib
r
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
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CV1835

address entity row
address
ed
w
lo
al
t
no
e
ar
n
tio
u
ib
r
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
35 70 DID0 Chip serial number

M
71 DID0 Chip serial number

36 72 DID1 Chip serial number
73 DID1 Chip serial number
37 74 Nvcounter Anti rollback number
75 Nvcounter Anti rollback number
38 76 eFuse_w_lock0 efuse Anti write options
77 eFuse_w_lock0 efuse Anti write options
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address entity row
address
39 78 eFuse_w_lock1 efuse Anti write options
79 eFuse_w_lock1 efuse Anti write options
40 80 SCS_config Security startup settings
81 SCS_config Security startup settings
41 82 DBG_mode Debug interface protection settings
ed
83 DBG_mode Debug interface protection settings
w
42 84 Kpub_Hash0 Public key hash value
lo
85 Kpub_Hash0 Public key hash value
al
t
no
e
ar
n
tio

u

ib

r
di V
st

re k-

d il
an M

n by

tio lic
50 100 SecReserved Security system reserved column

ca ub
101 SecReserved Security system reserved column

ifi p

od de

M a
M

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address entity row
address
ed
w
lo
al
t
no
e
ar
n
tio
u
r ib
di V
st
re k-
d il
an M
13.3.3 Efuse Ctrl Register Overview

n by
The eFuse Ctrl register provides two access interfaces, the insecure interface and the
tio lic
secure interface
ca ub
Non secure interface provides

ifi p
·Control interface of eFuse controller, read / write control field

od de
eFuse register content, which can be used to read non-secure registers

M a
M
Secure interface provides
Complete eFuse register content, only provide read function

The overview of non-secure registers of fuse Ctrl is shown in the table below:
Offset
EFUSE_MODE 0x000 EFUSE_MODE
EFUSE_ADR 0x004 EFUSE_ADR
EFUSE_DIR_CMD 0x008 EFUSE_DIR_CMD
EFUSE_RD_DATA 0x00c EFUSE_RD_DATA
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Offset
EFUSE_STATUS 0x010 EFUSE_STATUS
EFUSE_ONE_WAY 0x014 EFUSE_ONE_WAY
PGM_PLUSE_WIDTH 0x018 PGM_PLUSE_WIDTH
A_READ_WIDTH 0x01c A_READ_WIDTH
M_READ_WIDTH 0x020 M_READ_WIDTH
FTSN0 0x100 Efuse Register contents
ed
FTSN3 0x10c Efuse Register contents
w
eFuse_FT_Debug 0x114 Efuse Register contents
lo
Analog0 0x118 Efuse Register contents
al
Analog1 0x11c Efuse Register contents
t
no
Bonding0 0x128 Efuse Register contents
SW_info 0x12c Efuse Register contents
e
SW_reserved30 0x130 Efuse Register contents
ar
n
SW_reserved3c 0x13c Efuse Register contents
tio
u

ib

r
di V
st

re k-

d il
an M

n by

tio lic

ca ub

ifi p

od de

DID0 0x18c Efuse Register contents
M a
DID1 0x190 Efuse Register contents

M
MSID 0x194 Efuse Register contents

eFuse_w_lock0 0x198 Efuse Register contents
eFuse_w_lock1 0x19c Efuse Register contents
SCS_config 0x1a0 Efuse Register contents
DBG_mode 0x1a4 Efuse Register contents
Kpub_Hash0 0x1a8 Efuse Register contents
Kpub_Hash1 0x1ac Efuse Register contents
Kpub_Hash2 0x1b0 Efuse Register contents
Kpub_Hash5 0x1bc Efuse Register contents
Kpub_Hash6 0x1c0 Efuse Register contents
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Offset
Kpub_Hash7 0x1c4 Efuse Register contents
ed
13.3.4 Efuse CTRL Register Overview
w
lo
(Base Address 0x03050000)
al
t
EFUSE_MODE
no
Efuse operation mode
e
ar
3:0 EFUSE_OP_MODE R/W eFuse firewall control register built in 0x0
n
instructions:
tio
0000: standby status / module start
status
u
0001: reads eFuse instruction normally

ib
0010: test pressure reading eFuse

command
r
di V
st
0100: burn instruction

re k-
1xxx: eFuse module shutdown

4 eFuse_A_Fire W1T Start eFuse built-in instruction action
d il
an M
7:5 eFuse_REFRESH_MODE R/W 001: Start shadow register update 0x0

Others:Reserved
10:8 eFuse_DIRECT_MODE R/W Reserved 0x0
n by
11 clear_eFuse_status R/W Clear error information 0x0

1: Clear
tio lic
0: no action
31:12 EFUSE_MODE_reseved R/W Reserved 0x0
ca ub
ifi p
EFUSE_ADR
od de
Efuse address for embedded opreation

M a
M

11:0 EFUSE_ADR R/W Specifies the eFuse physical address 0x0
used by the built-in instruction
31:12 Reserved
EFUSE_DIR_CMD
direct bit-wise reg-control signals to eFuse macro IO
31:0 EFUSE_DIR_CMD R/W Reserved, Test interface 0x0
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EFUSE_RD_DATA
eFuse Macro readback data for embedded read
31:0 EFUSE_RD_DATA RO eFuse Module read value
EFUSE_STATUS
ed
eFuse_busy
w
lo
0 eFuse_busy RO eFuseController busy
al
1 EFUSE_READ_err RO Read action error indication
2 EFUSE_M_READ_err RO Pressure reading action error indication
t
no
3 EFUSE_PGM_err RO Burning action error indication
7:4 EfuseCTL_ST RO Controller status indication
0: Started
e
ar
1: Auto read
2: Waiting
3: Reading
n
4: Burning and writing
tio
5: Pressure reading
6: Test model test
u
7: Shutting down
ib
31:8 EFUSE_STATUS RO Reserved

r
di V
st
re k-
EFUSE_ONE_WAY
d il
EFUSE_ONE_WAY
an M

n by

31:0 EFUSE_ONE_WAY R/W Reserved 0x0
One-Way: Enabled
tio lic
ca ub
PGM_PLUSE_WIDTH
ifi p
PGM_PLUSE_WIDTH
od de

M a
8:0 PGM_PLUSE_WIDTH R/W Reserved 0x0

M
31:9 Reserved
A_READ_WIDTH
A_READ_WIDTH
8:0 A_READ_WIDTH R/W Reserved 0x0
31:9 Reserved
M_READ_WIDTH
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M_READ_WIDTH
8:0 M_READ_WIDTH R/W Reserved 0x0
31:9 Reserved
FTSN0
serial number for FT(function test)
ed
w
31:0 FTSN0 RO Production serial number
lo
al
FTSN1
t
no
e
ar
n
FTSN2
tio

u

ib

r
di V

st
re k-
FTSN3
d il
an M

n by

tio lic
ca ub
FTSN4
ifi p

od de

M a

M
MRK_SEG
Market Segment
31:0 MRK_SEG RO Market differentiation number
Analog0
Analog trimming data
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31:0 Analog0 RO Analog module calibration
Analog1
ed
w
Analog2
lo
al
t
no
e
ar
Analog3
n
tio
u

r ib
di V
Bonding0
st
re k-
Bonding option
d il

an M

31:0 Bonding0 RO Configuration binding settings
n by
SW_info
tio lic
reserved for SW or MBIST use

ca ub

ifi p

od de
31:0 SW_info RO SoftwareReserved

M a
M
SW_reserved30
31:0 reserved30 RO SoftwareReserved
SW_reserved34
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SW_reserved38
ed
SW_reserved3c
w
lo
al
t
31:0 reserved3c RO SoftwareReserved
no
SW_reserved40
e
ar
n
tio
u
ib
SW_reserved44
r
di V
st

re k-

d il

an M

n by
SW_reserved48
tio lic

ca ub

ifi p

od de
SW_reserved4c
M a
M

SW_reserved50
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SW_reserved54
SW_reserved58
ed
w
lo
al
SW_reserved5c
t
no
e
ar
n
tio
SW_reserved60
u
ib

r

di V
st

re k-
d il
SW_reserved64
an M

n by

tio lic

ca ub
SW_reserved68
ifi p

od de

M a

M
SW_reserved6c
SW_reserved70
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SW_reserved74
ed
w
lo
SW_reserved78
al
t
no
e
SW_reserved7c
ar
n
tio
u

ib

r
di V
st
re k-
SW_reserved80
d il

an M

n by

tio lic
SW_reserved84
ca ub

ifi p

od de

M a
M
SW_reserved88
DID0
device ID
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31:0 DID0 RO Chip serial number
DID1
device ID
31:0 DID1 RO Chip serial number
ed
MSID
w
lo
Nvcounter
al
t
31:0 MSID RO Anti rollback number
no
eFuse_w_lock0
e
ar
eFuse_w_lock0
n
tio
31:0 eFuse_w_lock0 RO efuse Anti write options
u
ib
eFuse_w_lock1
r
di V
st
eFuse_w_lock1
re k-

d il

an M
31:0 eFuse_w_lock1 RO efuse Anti write options

n by
SCS_config
tio lic
SCS_config
ca ub

ifi p
31:0 SCS_enable RO Security startup settings

od de
DBG_mode
M a
M
DBG_mode
31:0 REE_dbg_mode RO Debug interface protection settings
Kpub_Hash0
Hash value of boot loader authentication public key
31:0 Kpub_Hash0 RO Public key hash value
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Kpub_Hash1
Kpub_Hash2
ed
w
lo
al
Kpub_Hash3
t
no
e
ar
n
tio
Kpub_Hash4
u
ib

r

di V
st

re k-
d il
Kpub_Hash5
an M

n by

tio lic

ca ub
Kpub_Hash6
ifi p

od de

M a

M
Kpub_Hash7
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CV1835
13.3.5 eFuse CTRL Operation Process
The contents of eFuse will automatically load the eFuse contents into the internal
ed
registers during the boot process, and set the eFuse to a closed state after loading is
completed.
w
lo
13.3.5.1 eFuse Start Process
al
t
EFuse Ctrl will enter the closed state after the startup procedure is completed.
no
Before further action, the controller must be started.
e
Step 1: Read eFuse_ Status [0], until the read back value is 0, indicating that the
ar
eFuse controller is idle and can initiate the next operation.
n
tio
Step 2: Set eFuse Ctrl to write 0x40 to start the commandeFuse CTRL
u
13.3.5.2 eFuse Burning Process

r ib
di V
st
eFuse CTRL has built-in burn command to do the burning of single bit eFuse.
re k-
d il
Step 1: Read EFUSE_STATUS [0], until the read back value is 0, indicating that the
an M

n by
Step 2: Convert the value to be burned into the entity address of eFuse and fill in
EFUSE_ADR
tio lic
Step 3: Set eFuse CTRL to write 0x14 and start the burning command
ca ub
ifi p
eFuse controller has completed the burning and writing, and can initiate the next
od de
operation.
M a
M
Step 5: Set eFuse Ctrl to write 0x12 and start the read command.
Step 6: Check EFUSE_RD_DATA whether the burned address in data can be read
back to the previously burned value.
13.3.5.3 eFuse Closing Process
After the eFuse is started manually, it can still control the eFuse to go back to the
off state, which can save power consumption and avoid the eFuse's invalid action.
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Step 2: Set eFuse Ctrl to write to 0xf0 to close the command
ed
w
lo
al
t
no
e
ar
n
u tio
r ib
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st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
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Intelligent Secure Operation Environment
In order to keep the operation environment of the blockhouse security system reliable
and the security of intelligent programs and data not threatened, the operation system
ed
must establish a perfect intelligent security operation environment to provide
w
comprehensive and complete protection for valuable assets. In particular, the intelligent
lo
program library and personal identification data must provide confidentiality, credibility
al
and integrity to ensure the asset security of manufacturers and users.
t
no
According to the requirements of intelligent secure operation environment, the security
e
system provides complete hardware and software protection functions from startup,
ar
n
It includes: 1. The establishment of trust chain: providing the foundation of security
tio
environment, which is the foundation of trusted environment, such as hardware security

u
ib
setting, trust root, security startup; 2. Data encryption security: data encryption
r
di V
program, operation core encryption; 3. Execution isolation: Hardware isolation, software

st
re k-
isolation; 4. Software and firmware verification: verifying the credibility and integrity of
d il
an M
software, including Boot and load verification procedures, 5. Secure storage and
transmission: protect external data storage and exchange, 6. Secure update: ensure a
n by
secure environment. These functions provide a systematic method and system to

tio lic
protect valuable program code and data.

ca ub
ifi p
od de
14.1Establishment of Trust Chain

M a
M
When the device is started, the hardware system will start the security mechanism
according to the security settings. Secure boot refers to the trusted platform startup
sequence for security applications. After powering on, the initial instruction is read from
the built-in read-only memory (ROM), which is the secure boot ROM of the system. This
program contains the secure boot root public key for authorization authentication,
which will verify the root signature of the underlying boot loader. Once it passes the
verification, the system will start. Then it verifies subsequent boot loaders. After
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verifying the legality of the signature, the entire boot program starts to load the driver,
detect devices, and start the system daemon. If any component fails the check, that
component will not be loaded, and the secure boot process will fail.
ed
w
lo
al
t
no
e
ar
n
u tio
ib
Figure 14- 1 Establishment of trust chain

r
di V
st
re k-
d il
an M
14.2Data Encryption Security

n by
For confidential programs or data that need to be kept secret, including loaders, secure
tio lic
and non secure system programs required for startup, secure and non secure code and
ca ub
data required for application, such as AI model, security system can provide encryption
ifi p
protection programs, and use secure key operation to complete in the trusted
od de
execution environment. After decryption, the data of highly confidential programs or

M a
data are also isolated from the system .In a secure environment, non secure program
M
access is not allowed. The system provides common public standard cryptographic
algorithms, including symmetric and asymmetric encryption and decryption and
signature verification algorithms, such as AES, des or RSA, ECC, etc. It also supports
Chinese cryptographic algorithms, including SM2, SM3 and SM4, which meet a wide
range of security standards. The key is managed by the security system, and the non
security program is not allowed to use the security key.
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14.3Software and Hardware verification
The trust chain will ensure that all system components are officially written, signed and
distributed, and can not come from other unknown organizations, such as malicious
attackers from third parties. The trust chain is also used to check the signature when the
application starts. All applications must be signed directly or indirectly by the official to
ed
ensure the credibility and integrity of the system program and prevent the program
w
from being modified or implanted with malicious programs or backdoors. In the
lo
running stage, if the system wants to load the program library dynamically, such as the
al
artificial intelligence model library, it still needs to be verified and decrypted by the
t
no
security system to ensure the credibility of the program library.
e
14.4Secure Storage and Transmission ar
n
tio
Due to the application requirements, the system must transfer the security data into or
u
ib
out of the security environment to achieve data storage or exchange. For the storage or
r
di V
st
transmission of security data, the security operation environment only allows data
re k-
transmission through the pre-defined security interface. The security interface includes
d il
an M
secure storage, secure debugging and secure connection.

n by
Secure storage requires that secure data cannot be transmitted to external storage
tio lic
media in plaintext. All secure data must be encrypted according to the device security
ca ub
key or private password corresponding to its security level before moving out of the
ifi p
security environment. The external storage data exists in ciphertext. Security debugging
od de
needs to use different security passwords to connect the debugging interface

M a
according to the security level of the running environment. Secure connection ensures
M
the security of network equipment in the transmission process.
14.5Security Update
In the face of ever-changing attacks, the security environment must maintain

continuous security updates and patches. In addition to application security updates,
the chip security environment also provides firmware updates that support secure
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startup, as well as version control and anti rollback protection. The security update
firmware needs to be verified by the authorized signature to start the security firmware
update, and the version of the chip is consistent with the firmware through eFuse.
Through the comprehensive security protection mechanism, an intelligent and secure

operation environment is established, which can effectively guarantee the data security
ed
of manufacturers and users, and meet the national security requirements.
w
lo
al
t
no
e
ar
n
u tio
r ib
di V
st
re k-
d il
an M
n by
tio lic
ca ub
ifi p
od de
M a
M
692

CV1800B CV1801B Preliminary Datasheet Full en

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CV1800B CV1801B Preliminary Datasheet Full en

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Release date: 2022-11-07

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Revision Date Description

Terms and Conditions

result based on Customer’s specification or published shandard.

Revision History .................................................................................................................................. 2

1.3.1 Overview .....................................................................................................................22

1.3.2 Processor Core .........................................................................................................23

1.3.3 TPU ............................................................................................................................... 23

1.3.4 Video Coding (CV180ZB/CV1800B/CV1801B) ........................................... 24

1.3.5 Video Interface ........................................................................................................ 24

1.3.7 CV Hardware Acceleration EngineCV .............................................................25

1.3.8 Audio Encoding and Decoding .........................................................................25

1.3.9 Network Interface...................................................................................................26

1.3.10 Security System Module ...................................................................................... 26

1.3.11 Intelligent Secure Operating Environment .................................................. 26

1.3.12 Peripheral Interfaces (CV180ZB/CV1800B/CV1801B) ............................. 26

1.3.13 External Memory Interface ................................................................................. 27

1.4.4 Secure Boot ...............................................................................................................29

2.5.3 Destructive Voltage ............................................................................................... 43

2.5.4 Power Sequencing(CV180ZB/CV1800B/CV1801B) .................................. 43

2.5.5 The DC/AC Electrical Parameters of the Power Supply ...........................46

2.5.6 1.8V I/O Electrical Parameters ........................................................................... 47

2.5.7 18OD33 IO (VDDIO=1.8V) Electrical Parameters ..................................... 47

2.5.8 18OD33 IO (VDDIO=3.0V) Electrical Parameters ..................................... 49

2.5.9 Audio GPIO Electrical Parameters ...................................................................50

2.5.11 MIPI Rx Electrical Parameters ............................................................................ 50

2.5.12 Sub-LVDS Electrical Parameters ....................................................................... 52

2.5.13 HiSPi Electrical Parameters ................................................................................. 52

2.5.14 SDIO Electrical Parameters ................................................................................. 53

2.5.15 2.5.15 VI RAW/BT.656/BT.1120Electrical

2.6.4 AIAO (I2S/PCM) Timing ........................................................................................58

3.2.2 Function Block Diagram .......................................................................................79

3.2.3 Clock Resource and Frequency Division Structure................................... 79

3.2.4 PLL Configuration ...................................................................................................80

3.2.5 CLK_DIV Clock Frequency Division Configuration ....................................82

3.2.6 PLL CRG Register Overview ................................................................................ 84

3.2.7 PLL CRG Register Overview ................................................................................ 86

3.2.8 CLK_DIV CRG Register Overview ......................................................................95

3.3 Processor Subsystem ............................................................................................................114

3.4 Interrupt System .....................................................................................................................115

3.5 System Controller .................................................................................................................. 116

3.5.1 Overview ..................................................................................................................116

3.5.2 Function Description .......................................................................................... 116

3.6.5 DMAC Register ......................................................................................................131

3.8.6 WDT register description ..................................................................................190

3.9.1 Overview ..................................................................................................................192

3.9.2 Features ....................................................................................................................193

3.9.3 Function description...........................................................................................193

3.9.4 Operation................................................................................................................ 195

3.9.5 RTC register overview .........................................................................................199

3.10.1 Overview ..................................................................................................................228

3.10.2 Clock control..........................................................................................................229

3.10.3 DDR low power consumption control .........................................................229

3.10.4 Voltage regulation...............................................................................................230

3.11 Chip internal temperature detection............................................................................. 232

3.12.6 8051 Subsystem Registers ............................................................................... 237

4.2.5 Register overview .................................................................................................301